1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. 3 */ 4 5 #include <linux/kernel.h> 6 #include <linux/init.h> 7 #include <linux/err.h> 8 #include <linux/ctype.h> 9 #include <linux/io.h> 10 #include <linux/of.h> 11 #include <linux/of_device.h> 12 #include <linux/platform_device.h> 13 #include <linux/module.h> 14 #include <linux/regmap.h> 15 16 #include <dt-bindings/clock/qcom,gcc-msm8994.h> 17 18 #include "common.h" 19 #include "clk-regmap.h" 20 #include "clk-alpha-pll.h" 21 #include "clk-rcg.h" 22 #include "clk-branch.h" 23 #include "reset.h" 24 #include "gdsc.h" 25 26 enum { 27 P_XO, 28 P_GPLL0, 29 P_GPLL4, 30 }; 31 32 static struct clk_alpha_pll gpll0_early = { 33 .offset = 0, 34 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 35 .clkr = { 36 .enable_reg = 0x1480, 37 .enable_mask = BIT(0), 38 .hw.init = &(struct clk_init_data){ 39 .name = "gpll0_early", 40 .parent_data = &(const struct clk_parent_data){ 41 .fw_name = "xo", 42 }, 43 .num_parents = 1, 44 .ops = &clk_alpha_pll_ops, 45 }, 46 }, 47 }; 48 49 static struct clk_alpha_pll_postdiv gpll0 = { 50 .offset = 0, 51 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 52 .clkr.hw.init = &(struct clk_init_data){ 53 .name = "gpll0", 54 .parent_names = (const char *[]) { "gpll0_early" }, 55 .num_parents = 1, 56 .ops = &clk_alpha_pll_postdiv_ops, 57 }, 58 }; 59 60 static struct clk_alpha_pll gpll4_early = { 61 .offset = 0x1dc0, 62 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 63 .clkr = { 64 .enable_reg = 0x1480, 65 .enable_mask = BIT(4), 66 .hw.init = &(struct clk_init_data){ 67 .name = "gpll4_early", 68 .parent_data = &(const struct clk_parent_data){ 69 .fw_name = "xo", 70 }, 71 .num_parents = 1, 72 .ops = &clk_alpha_pll_ops, 73 }, 74 }, 75 }; 76 77 static struct clk_alpha_pll_postdiv gpll4 = { 78 .offset = 0x1dc0, 79 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 80 .clkr.hw.init = &(struct clk_init_data){ 81 .name = "gpll4", 82 .parent_names = (const char *[]) { "gpll4_early" }, 83 .num_parents = 1, 84 .ops = &clk_alpha_pll_postdiv_ops, 85 }, 86 }; 87 88 static const struct parent_map gcc_xo_gpll0_map[] = { 89 { P_XO, 0 }, 90 { P_GPLL0, 1 }, 91 }; 92 93 static const struct clk_parent_data gcc_xo_gpll0[] = { 94 { .fw_name = "xo" }, 95 { .hw = &gpll0.clkr.hw }, 96 }; 97 98 static const struct parent_map gcc_xo_gpll0_gpll4_map[] = { 99 { P_XO, 0 }, 100 { P_GPLL0, 1 }, 101 { P_GPLL4, 5 }, 102 }; 103 104 static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = { 105 { .fw_name = "xo" }, 106 { .hw = &gpll0.clkr.hw }, 107 { .hw = &gpll4.clkr.hw }, 108 }; 109 110 static struct clk_rcg2 system_noc_clk_src = { 111 .cmd_rcgr = 0x0120, 112 .hid_width = 5, 113 .parent_map = gcc_xo_gpll0_map, 114 .clkr.hw.init = &(struct clk_init_data){ 115 .name = "system_noc_clk_src", 116 .parent_data = gcc_xo_gpll0, 117 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 118 .ops = &clk_rcg2_ops, 119 }, 120 }; 121 122 static struct clk_rcg2 config_noc_clk_src = { 123 .cmd_rcgr = 0x0150, 124 .hid_width = 5, 125 .parent_map = gcc_xo_gpll0_map, 126 .clkr.hw.init = &(struct clk_init_data){ 127 .name = "config_noc_clk_src", 128 .parent_data = gcc_xo_gpll0, 129 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 130 .ops = &clk_rcg2_ops, 131 }, 132 }; 133 134 static struct clk_rcg2 periph_noc_clk_src = { 135 .cmd_rcgr = 0x0190, 136 .hid_width = 5, 137 .parent_map = gcc_xo_gpll0_map, 138 .clkr.hw.init = &(struct clk_init_data){ 139 .name = "periph_noc_clk_src", 140 .parent_data = gcc_xo_gpll0, 141 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 142 .ops = &clk_rcg2_ops, 143 }, 144 }; 145 146 static struct freq_tbl ftbl_ufs_axi_clk_src[] = { 147 F(50000000, P_GPLL0, 12, 0, 0), 148 F(100000000, P_GPLL0, 6, 0, 0), 149 F(150000000, P_GPLL0, 4, 0, 0), 150 F(171430000, P_GPLL0, 3.5, 0, 0), 151 F(200000000, P_GPLL0, 3, 0, 0), 152 F(240000000, P_GPLL0, 2.5, 0, 0), 153 { } 154 }; 155 156 static struct clk_rcg2 ufs_axi_clk_src = { 157 .cmd_rcgr = 0x1d68, 158 .mnd_width = 8, 159 .hid_width = 5, 160 .parent_map = gcc_xo_gpll0_map, 161 .freq_tbl = ftbl_ufs_axi_clk_src, 162 .clkr.hw.init = &(struct clk_init_data){ 163 .name = "ufs_axi_clk_src", 164 .parent_data = gcc_xo_gpll0, 165 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 166 .ops = &clk_rcg2_ops, 167 }, 168 }; 169 170 static struct freq_tbl ftbl_usb30_master_clk_src[] = { 171 F(19200000, P_XO, 1, 0, 0), 172 F(125000000, P_GPLL0, 1, 5, 24), 173 { } 174 }; 175 176 static struct clk_rcg2 usb30_master_clk_src = { 177 .cmd_rcgr = 0x03d4, 178 .mnd_width = 8, 179 .hid_width = 5, 180 .parent_map = gcc_xo_gpll0_map, 181 .freq_tbl = ftbl_usb30_master_clk_src, 182 .clkr.hw.init = &(struct clk_init_data){ 183 .name = "usb30_master_clk_src", 184 .parent_data = gcc_xo_gpll0, 185 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 186 .ops = &clk_rcg2_ops, 187 }, 188 }; 189 190 static struct freq_tbl ftbl_blsp_i2c_apps_clk_src[] = { 191 F(19200000, P_XO, 1, 0, 0), 192 F(50000000, P_GPLL0, 12, 0, 0), 193 { } 194 }; 195 196 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { 197 .cmd_rcgr = 0x0660, 198 .hid_width = 5, 199 .parent_map = gcc_xo_gpll0_map, 200 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 201 .clkr.hw.init = &(struct clk_init_data){ 202 .name = "blsp1_qup1_i2c_apps_clk_src", 203 .parent_data = gcc_xo_gpll0, 204 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 205 .ops = &clk_rcg2_ops, 206 }, 207 }; 208 209 static struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = { 210 F(960000, P_XO, 10, 1, 2), 211 F(4800000, P_XO, 4, 0, 0), 212 F(9600000, P_XO, 2, 0, 0), 213 F(15000000, P_GPLL0, 10, 1, 4), 214 F(19200000, P_XO, 1, 0, 0), 215 F(24000000, P_GPLL0, 12.5, 1, 2), 216 F(25000000, P_GPLL0, 12, 1, 2), 217 F(48000000, P_GPLL0, 12.5, 0, 0), 218 F(50000000, P_GPLL0, 12, 0, 0), 219 { } 220 }; 221 222 static struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src_8992[] = { 223 F(960000, P_XO, 10, 1, 2), 224 F(4800000, P_XO, 4, 0, 0), 225 F(9600000, P_XO, 2, 0, 0), 226 F(15000000, P_GPLL0, 10, 1, 4), 227 F(19200000, P_XO, 1, 0, 0), 228 F(25000000, P_GPLL0, 12, 1, 2), 229 F(50000000, P_GPLL0, 12, 0, 0), 230 { } 231 }; 232 233 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { 234 .cmd_rcgr = 0x064c, 235 .mnd_width = 8, 236 .hid_width = 5, 237 .parent_map = gcc_xo_gpll0_map, 238 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 239 .clkr.hw.init = &(struct clk_init_data){ 240 .name = "blsp1_qup1_spi_apps_clk_src", 241 .parent_data = gcc_xo_gpll0, 242 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 243 .ops = &clk_rcg2_ops, 244 }, 245 }; 246 247 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { 248 .cmd_rcgr = 0x06e0, 249 .hid_width = 5, 250 .parent_map = gcc_xo_gpll0_map, 251 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 252 .clkr.hw.init = &(struct clk_init_data){ 253 .name = "blsp1_qup2_i2c_apps_clk_src", 254 .parent_data = gcc_xo_gpll0, 255 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 256 .ops = &clk_rcg2_ops, 257 }, 258 }; 259 260 static struct freq_tbl ftbl_blsp1_qup2_spi_apps_clk_src[] = { 261 F(960000, P_XO, 10, 1, 2), 262 F(4800000, P_XO, 4, 0, 0), 263 F(9600000, P_XO, 2, 0, 0), 264 F(15000000, P_GPLL0, 10, 1, 4), 265 F(19200000, P_XO, 1, 0, 0), 266 F(24000000, P_GPLL0, 12.5, 1, 2), 267 F(25000000, P_GPLL0, 12, 1, 2), 268 F(42860000, P_GPLL0, 14, 0, 0), 269 F(46150000, P_GPLL0, 13, 0, 0), 270 { } 271 }; 272 273 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { 274 .cmd_rcgr = 0x06cc, 275 .mnd_width = 8, 276 .hid_width = 5, 277 .parent_map = gcc_xo_gpll0_map, 278 .freq_tbl = ftbl_blsp1_qup2_spi_apps_clk_src, 279 .clkr.hw.init = &(struct clk_init_data){ 280 .name = "blsp1_qup2_spi_apps_clk_src", 281 .parent_data = gcc_xo_gpll0, 282 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 283 .ops = &clk_rcg2_ops, 284 }, 285 }; 286 287 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { 288 .cmd_rcgr = 0x0760, 289 .hid_width = 5, 290 .parent_map = gcc_xo_gpll0_map, 291 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 292 .clkr.hw.init = &(struct clk_init_data){ 293 .name = "blsp1_qup3_i2c_apps_clk_src", 294 .parent_data = gcc_xo_gpll0, 295 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 296 .ops = &clk_rcg2_ops, 297 }, 298 }; 299 300 static struct freq_tbl ftbl_blsp1_qup3_4_spi_apps_clk_src[] = { 301 F(960000, P_XO, 10, 1, 2), 302 F(4800000, P_XO, 4, 0, 0), 303 F(9600000, P_XO, 2, 0, 0), 304 F(15000000, P_GPLL0, 10, 1, 4), 305 F(19200000, P_XO, 1, 0, 0), 306 F(24000000, P_GPLL0, 12.5, 1, 2), 307 F(25000000, P_GPLL0, 12, 1, 2), 308 F(42860000, P_GPLL0, 14, 0, 0), 309 F(44440000, P_GPLL0, 13.5, 0, 0), 310 { } 311 }; 312 313 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { 314 .cmd_rcgr = 0x074c, 315 .mnd_width = 8, 316 .hid_width = 5, 317 .parent_map = gcc_xo_gpll0_map, 318 .freq_tbl = ftbl_blsp1_qup3_4_spi_apps_clk_src, 319 .clkr.hw.init = &(struct clk_init_data){ 320 .name = "blsp1_qup3_spi_apps_clk_src", 321 .parent_data = gcc_xo_gpll0, 322 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 323 .ops = &clk_rcg2_ops, 324 }, 325 }; 326 327 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { 328 .cmd_rcgr = 0x07e0, 329 .hid_width = 5, 330 .parent_map = gcc_xo_gpll0_map, 331 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 332 .clkr.hw.init = &(struct clk_init_data){ 333 .name = "blsp1_qup4_i2c_apps_clk_src", 334 .parent_data = gcc_xo_gpll0, 335 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 336 .ops = &clk_rcg2_ops, 337 }, 338 }; 339 340 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { 341 .cmd_rcgr = 0x07cc, 342 .mnd_width = 8, 343 .hid_width = 5, 344 .parent_map = gcc_xo_gpll0_map, 345 .freq_tbl = ftbl_blsp1_qup3_4_spi_apps_clk_src, 346 .clkr.hw.init = &(struct clk_init_data){ 347 .name = "blsp1_qup4_spi_apps_clk_src", 348 .parent_data = gcc_xo_gpll0, 349 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 350 .ops = &clk_rcg2_ops, 351 }, 352 }; 353 354 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = { 355 .cmd_rcgr = 0x0860, 356 .hid_width = 5, 357 .parent_map = gcc_xo_gpll0_map, 358 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 359 .clkr.hw.init = &(struct clk_init_data){ 360 .name = "blsp1_qup5_i2c_apps_clk_src", 361 .parent_data = gcc_xo_gpll0, 362 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 363 .ops = &clk_rcg2_ops, 364 }, 365 }; 366 367 static struct freq_tbl ftbl_blsp1_qup5_spi_apps_clk_src[] = { 368 F(960000, P_XO, 10, 1, 2), 369 F(4800000, P_XO, 4, 0, 0), 370 F(9600000, P_XO, 2, 0, 0), 371 F(15000000, P_GPLL0, 10, 1, 4), 372 F(19200000, P_XO, 1, 0, 0), 373 F(24000000, P_GPLL0, 12.5, 1, 2), 374 F(25000000, P_GPLL0, 12, 1, 2), 375 F(40000000, P_GPLL0, 15, 0, 0), 376 F(42860000, P_GPLL0, 14, 0, 0), 377 { } 378 }; 379 380 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = { 381 .cmd_rcgr = 0x084c, 382 .mnd_width = 8, 383 .hid_width = 5, 384 .parent_map = gcc_xo_gpll0_map, 385 .freq_tbl = ftbl_blsp1_qup5_spi_apps_clk_src, 386 .clkr.hw.init = &(struct clk_init_data){ 387 .name = "blsp1_qup5_spi_apps_clk_src", 388 .parent_data = gcc_xo_gpll0, 389 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 390 .ops = &clk_rcg2_ops, 391 }, 392 }; 393 394 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = { 395 .cmd_rcgr = 0x08e0, 396 .hid_width = 5, 397 .parent_map = gcc_xo_gpll0_map, 398 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 399 .clkr.hw.init = &(struct clk_init_data){ 400 .name = "blsp1_qup6_i2c_apps_clk_src", 401 .parent_data = gcc_xo_gpll0, 402 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 403 .ops = &clk_rcg2_ops, 404 }, 405 }; 406 407 static struct freq_tbl ftbl_blsp1_qup6_spi_apps_clk_src[] = { 408 F(960000, P_XO, 10, 1, 2), 409 F(4800000, P_XO, 4, 0, 0), 410 F(9600000, P_XO, 2, 0, 0), 411 F(15000000, P_GPLL0, 10, 1, 4), 412 F(19200000, P_XO, 1, 0, 0), 413 F(24000000, P_GPLL0, 12.5, 1, 2), 414 F(27906976, P_GPLL0, 1, 2, 43), 415 F(41380000, P_GPLL0, 15, 0, 0), 416 F(42860000, P_GPLL0, 14, 0, 0), 417 { } 418 }; 419 420 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = { 421 .cmd_rcgr = 0x08cc, 422 .mnd_width = 8, 423 .hid_width = 5, 424 .parent_map = gcc_xo_gpll0_map, 425 .freq_tbl = ftbl_blsp1_qup6_spi_apps_clk_src, 426 .clkr.hw.init = &(struct clk_init_data){ 427 .name = "blsp1_qup6_spi_apps_clk_src", 428 .parent_data = gcc_xo_gpll0, 429 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 430 .ops = &clk_rcg2_ops, 431 }, 432 }; 433 434 static struct freq_tbl ftbl_blsp_uart_apps_clk_src[] = { 435 F(3686400, P_GPLL0, 1, 96, 15625), 436 F(7372800, P_GPLL0, 1, 192, 15625), 437 F(14745600, P_GPLL0, 1, 384, 15625), 438 F(16000000, P_GPLL0, 5, 2, 15), 439 F(19200000, P_XO, 1, 0, 0), 440 F(24000000, P_GPLL0, 5, 1, 5), 441 F(32000000, P_GPLL0, 1, 4, 75), 442 F(40000000, P_GPLL0, 15, 0, 0), 443 F(46400000, P_GPLL0, 1, 29, 375), 444 F(48000000, P_GPLL0, 12.5, 0, 0), 445 F(51200000, P_GPLL0, 1, 32, 375), 446 F(56000000, P_GPLL0, 1, 7, 75), 447 F(58982400, P_GPLL0, 1, 1536, 15625), 448 F(60000000, P_GPLL0, 10, 0, 0), 449 F(63160000, P_GPLL0, 9.5, 0, 0), 450 { } 451 }; 452 453 static struct clk_rcg2 blsp1_uart1_apps_clk_src = { 454 .cmd_rcgr = 0x068c, 455 .mnd_width = 16, 456 .hid_width = 5, 457 .parent_map = gcc_xo_gpll0_map, 458 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 459 .clkr.hw.init = &(struct clk_init_data){ 460 .name = "blsp1_uart1_apps_clk_src", 461 .parent_data = gcc_xo_gpll0, 462 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 463 .ops = &clk_rcg2_ops, 464 }, 465 }; 466 467 static struct clk_rcg2 blsp1_uart2_apps_clk_src = { 468 .cmd_rcgr = 0x070c, 469 .mnd_width = 16, 470 .hid_width = 5, 471 .parent_map = gcc_xo_gpll0_map, 472 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 473 .clkr.hw.init = &(struct clk_init_data){ 474 .name = "blsp1_uart2_apps_clk_src", 475 .parent_data = gcc_xo_gpll0, 476 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 477 .ops = &clk_rcg2_ops, 478 }, 479 }; 480 481 static struct clk_rcg2 blsp1_uart3_apps_clk_src = { 482 .cmd_rcgr = 0x078c, 483 .mnd_width = 16, 484 .hid_width = 5, 485 .parent_map = gcc_xo_gpll0_map, 486 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 487 .clkr.hw.init = &(struct clk_init_data){ 488 .name = "blsp1_uart3_apps_clk_src", 489 .parent_data = gcc_xo_gpll0, 490 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 491 .ops = &clk_rcg2_ops, 492 }, 493 }; 494 495 static struct clk_rcg2 blsp1_uart4_apps_clk_src = { 496 .cmd_rcgr = 0x080c, 497 .mnd_width = 16, 498 .hid_width = 5, 499 .parent_map = gcc_xo_gpll0_map, 500 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 501 .clkr.hw.init = &(struct clk_init_data){ 502 .name = "blsp1_uart4_apps_clk_src", 503 .parent_data = gcc_xo_gpll0, 504 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 505 .ops = &clk_rcg2_ops, 506 }, 507 }; 508 509 static struct clk_rcg2 blsp1_uart5_apps_clk_src = { 510 .cmd_rcgr = 0x088c, 511 .mnd_width = 16, 512 .hid_width = 5, 513 .parent_map = gcc_xo_gpll0_map, 514 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 515 .clkr.hw.init = &(struct clk_init_data){ 516 .name = "blsp1_uart5_apps_clk_src", 517 .parent_data = gcc_xo_gpll0, 518 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 519 .ops = &clk_rcg2_ops, 520 }, 521 }; 522 523 static struct clk_rcg2 blsp1_uart6_apps_clk_src = { 524 .cmd_rcgr = 0x090c, 525 .mnd_width = 16, 526 .hid_width = 5, 527 .parent_map = gcc_xo_gpll0_map, 528 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 529 .clkr.hw.init = &(struct clk_init_data){ 530 .name = "blsp1_uart6_apps_clk_src", 531 .parent_data = gcc_xo_gpll0, 532 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 533 .ops = &clk_rcg2_ops, 534 }, 535 }; 536 537 static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = { 538 .cmd_rcgr = 0x09a0, 539 .hid_width = 5, 540 .parent_map = gcc_xo_gpll0_map, 541 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 542 .clkr.hw.init = &(struct clk_init_data){ 543 .name = "blsp2_qup1_i2c_apps_clk_src", 544 .parent_data = gcc_xo_gpll0, 545 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 546 .ops = &clk_rcg2_ops, 547 }, 548 }; 549 550 static struct freq_tbl ftbl_blsp2_qup1_2_spi_apps_clk_src[] = { 551 F(960000, P_XO, 10, 1, 2), 552 F(4800000, P_XO, 4, 0, 0), 553 F(9600000, P_XO, 2, 0, 0), 554 F(15000000, P_GPLL0, 10, 1, 4), 555 F(19200000, P_XO, 1, 0, 0), 556 F(24000000, P_GPLL0, 12.5, 1, 2), 557 F(25000000, P_GPLL0, 12, 1, 2), 558 F(42860000, P_GPLL0, 14, 0, 0), 559 F(44440000, P_GPLL0, 13.5, 0, 0), 560 { } 561 }; 562 563 static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = { 564 .cmd_rcgr = 0x098c, 565 .mnd_width = 8, 566 .hid_width = 5, 567 .parent_map = gcc_xo_gpll0_map, 568 .freq_tbl = ftbl_blsp2_qup1_2_spi_apps_clk_src, 569 .clkr.hw.init = &(struct clk_init_data){ 570 .name = "blsp2_qup1_spi_apps_clk_src", 571 .parent_data = gcc_xo_gpll0, 572 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 573 .ops = &clk_rcg2_ops, 574 }, 575 }; 576 577 static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = { 578 .cmd_rcgr = 0x0a20, 579 .hid_width = 5, 580 .parent_map = gcc_xo_gpll0_map, 581 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 582 .clkr.hw.init = &(struct clk_init_data){ 583 .name = "blsp2_qup2_i2c_apps_clk_src", 584 .parent_data = gcc_xo_gpll0, 585 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 586 .ops = &clk_rcg2_ops, 587 }, 588 }; 589 590 static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = { 591 .cmd_rcgr = 0x0a0c, 592 .mnd_width = 8, 593 .hid_width = 5, 594 .parent_map = gcc_xo_gpll0_map, 595 .freq_tbl = ftbl_blsp2_qup1_2_spi_apps_clk_src, 596 .clkr.hw.init = &(struct clk_init_data){ 597 .name = "blsp2_qup2_spi_apps_clk_src", 598 .parent_data = gcc_xo_gpll0, 599 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 600 .ops = &clk_rcg2_ops, 601 }, 602 }; 603 604 static struct freq_tbl ftbl_blsp2_qup3_4_spi_apps_clk_src[] = { 605 F(960000, P_XO, 10, 1, 2), 606 F(4800000, P_XO, 4, 0, 0), 607 F(9600000, P_XO, 2, 0, 0), 608 F(15000000, P_GPLL0, 10, 1, 4), 609 F(19200000, P_XO, 1, 0, 0), 610 F(24000000, P_GPLL0, 12.5, 1, 2), 611 F(25000000, P_GPLL0, 12, 1, 2), 612 F(42860000, P_GPLL0, 14, 0, 0), 613 F(48000000, P_GPLL0, 12.5, 0, 0), 614 { } 615 }; 616 617 static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = { 618 .cmd_rcgr = 0x0aa0, 619 .hid_width = 5, 620 .parent_map = gcc_xo_gpll0_map, 621 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 622 .clkr.hw.init = &(struct clk_init_data){ 623 .name = "blsp2_qup3_i2c_apps_clk_src", 624 .parent_data = gcc_xo_gpll0, 625 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 626 .ops = &clk_rcg2_ops, 627 }, 628 }; 629 630 static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = { 631 .cmd_rcgr = 0x0a8c, 632 .mnd_width = 8, 633 .hid_width = 5, 634 .parent_map = gcc_xo_gpll0_map, 635 .freq_tbl = ftbl_blsp2_qup3_4_spi_apps_clk_src, 636 .clkr.hw.init = &(struct clk_init_data){ 637 .name = "blsp2_qup3_spi_apps_clk_src", 638 .parent_data = gcc_xo_gpll0, 639 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 640 .ops = &clk_rcg2_ops, 641 }, 642 }; 643 644 static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = { 645 .cmd_rcgr = 0x0b20, 646 .hid_width = 5, 647 .parent_map = gcc_xo_gpll0_map, 648 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 649 .clkr.hw.init = &(struct clk_init_data){ 650 .name = "blsp2_qup4_i2c_apps_clk_src", 651 .parent_data = gcc_xo_gpll0, 652 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 653 .ops = &clk_rcg2_ops, 654 }, 655 }; 656 657 static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = { 658 .cmd_rcgr = 0x0b0c, 659 .mnd_width = 8, 660 .hid_width = 5, 661 .parent_map = gcc_xo_gpll0_map, 662 .freq_tbl = ftbl_blsp2_qup3_4_spi_apps_clk_src, 663 .clkr.hw.init = &(struct clk_init_data){ 664 .name = "blsp2_qup4_spi_apps_clk_src", 665 .parent_data = gcc_xo_gpll0, 666 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 667 .ops = &clk_rcg2_ops, 668 }, 669 }; 670 671 static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = { 672 .cmd_rcgr = 0x0ba0, 673 .hid_width = 5, 674 .parent_map = gcc_xo_gpll0_map, 675 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 676 .clkr.hw.init = &(struct clk_init_data){ 677 .name = "blsp2_qup5_i2c_apps_clk_src", 678 .parent_data = gcc_xo_gpll0, 679 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 680 .ops = &clk_rcg2_ops, 681 }, 682 }; 683 684 static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = { 685 .cmd_rcgr = 0x0b8c, 686 .mnd_width = 8, 687 .hid_width = 5, 688 .parent_map = gcc_xo_gpll0_map, 689 /* BLSP1 QUP1 and BLSP2 QUP5 use the same freqs */ 690 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 691 .clkr.hw.init = &(struct clk_init_data){ 692 .name = "blsp2_qup5_spi_apps_clk_src", 693 .parent_data = gcc_xo_gpll0, 694 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 695 .ops = &clk_rcg2_ops, 696 }, 697 }; 698 699 static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = { 700 .cmd_rcgr = 0x0c20, 701 .hid_width = 5, 702 .parent_map = gcc_xo_gpll0_map, 703 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 704 .clkr.hw.init = &(struct clk_init_data){ 705 .name = "blsp2_qup6_i2c_apps_clk_src", 706 .parent_data = gcc_xo_gpll0, 707 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 708 .ops = &clk_rcg2_ops, 709 }, 710 }; 711 712 static struct freq_tbl ftbl_blsp2_qup6_spi_apps_clk_src[] = { 713 F(960000, P_XO, 10, 1, 2), 714 F(4800000, P_XO, 4, 0, 0), 715 F(9600000, P_XO, 2, 0, 0), 716 F(15000000, P_GPLL0, 10, 1, 4), 717 F(19200000, P_XO, 1, 0, 0), 718 F(24000000, P_GPLL0, 12.5, 1, 2), 719 F(25000000, P_GPLL0, 12, 1, 2), 720 F(44440000, P_GPLL0, 13.5, 0, 0), 721 F(48000000, P_GPLL0, 12.5, 0, 0), 722 { } 723 }; 724 725 static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = { 726 .cmd_rcgr = 0x0c0c, 727 .mnd_width = 8, 728 .hid_width = 5, 729 .parent_map = gcc_xo_gpll0_map, 730 .freq_tbl = ftbl_blsp2_qup6_spi_apps_clk_src, 731 .clkr.hw.init = &(struct clk_init_data){ 732 .name = "blsp2_qup6_spi_apps_clk_src", 733 .parent_data = gcc_xo_gpll0, 734 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 735 .ops = &clk_rcg2_ops, 736 }, 737 }; 738 739 static struct clk_rcg2 blsp2_uart1_apps_clk_src = { 740 .cmd_rcgr = 0x09cc, 741 .mnd_width = 16, 742 .hid_width = 5, 743 .parent_map = gcc_xo_gpll0_map, 744 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 745 .clkr.hw.init = &(struct clk_init_data){ 746 .name = "blsp2_uart1_apps_clk_src", 747 .parent_data = gcc_xo_gpll0, 748 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 749 .ops = &clk_rcg2_ops, 750 }, 751 }; 752 753 static struct clk_rcg2 blsp2_uart2_apps_clk_src = { 754 .cmd_rcgr = 0x0a4c, 755 .mnd_width = 16, 756 .hid_width = 5, 757 .parent_map = gcc_xo_gpll0_map, 758 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 759 .clkr.hw.init = &(struct clk_init_data){ 760 .name = "blsp2_uart2_apps_clk_src", 761 .parent_data = gcc_xo_gpll0, 762 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 763 .ops = &clk_rcg2_ops, 764 }, 765 }; 766 767 static struct clk_rcg2 blsp2_uart3_apps_clk_src = { 768 .cmd_rcgr = 0x0acc, 769 .mnd_width = 16, 770 .hid_width = 5, 771 .parent_map = gcc_xo_gpll0_map, 772 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 773 .clkr.hw.init = &(struct clk_init_data){ 774 .name = "blsp2_uart3_apps_clk_src", 775 .parent_data = gcc_xo_gpll0, 776 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 777 .ops = &clk_rcg2_ops, 778 }, 779 }; 780 781 static struct clk_rcg2 blsp2_uart4_apps_clk_src = { 782 .cmd_rcgr = 0x0b4c, 783 .mnd_width = 16, 784 .hid_width = 5, 785 .parent_map = gcc_xo_gpll0_map, 786 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 787 .clkr.hw.init = &(struct clk_init_data){ 788 .name = "blsp2_uart4_apps_clk_src", 789 .parent_data = gcc_xo_gpll0, 790 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 791 .ops = &clk_rcg2_ops, 792 }, 793 }; 794 795 static struct clk_rcg2 blsp2_uart5_apps_clk_src = { 796 .cmd_rcgr = 0x0bcc, 797 .mnd_width = 16, 798 .hid_width = 5, 799 .parent_map = gcc_xo_gpll0_map, 800 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 801 .clkr.hw.init = &(struct clk_init_data){ 802 .name = "blsp2_uart5_apps_clk_src", 803 .parent_data = gcc_xo_gpll0, 804 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 805 .ops = &clk_rcg2_ops, 806 }, 807 }; 808 809 static struct clk_rcg2 blsp2_uart6_apps_clk_src = { 810 .cmd_rcgr = 0x0c4c, 811 .mnd_width = 16, 812 .hid_width = 5, 813 .parent_map = gcc_xo_gpll0_map, 814 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 815 .clkr.hw.init = &(struct clk_init_data){ 816 .name = "blsp2_uart6_apps_clk_src", 817 .parent_data = gcc_xo_gpll0, 818 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 819 .ops = &clk_rcg2_ops, 820 }, 821 }; 822 823 static struct freq_tbl ftbl_gp1_clk_src[] = { 824 F(19200000, P_XO, 1, 0, 0), 825 F(100000000, P_GPLL0, 6, 0, 0), 826 F(200000000, P_GPLL0, 3, 0, 0), 827 { } 828 }; 829 830 static struct clk_rcg2 gp1_clk_src = { 831 .cmd_rcgr = 0x1904, 832 .mnd_width = 8, 833 .hid_width = 5, 834 .parent_map = gcc_xo_gpll0_map, 835 .freq_tbl = ftbl_gp1_clk_src, 836 .clkr.hw.init = &(struct clk_init_data){ 837 .name = "gp1_clk_src", 838 .parent_data = gcc_xo_gpll0, 839 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 840 .ops = &clk_rcg2_ops, 841 }, 842 }; 843 844 static struct freq_tbl ftbl_gp2_clk_src[] = { 845 F(19200000, P_XO, 1, 0, 0), 846 F(100000000, P_GPLL0, 6, 0, 0), 847 F(200000000, P_GPLL0, 3, 0, 0), 848 { } 849 }; 850 851 static struct clk_rcg2 gp2_clk_src = { 852 .cmd_rcgr = 0x1944, 853 .mnd_width = 8, 854 .hid_width = 5, 855 .parent_map = gcc_xo_gpll0_map, 856 .freq_tbl = ftbl_gp2_clk_src, 857 .clkr.hw.init = &(struct clk_init_data){ 858 .name = "gp2_clk_src", 859 .parent_data = gcc_xo_gpll0, 860 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 861 .ops = &clk_rcg2_ops, 862 }, 863 }; 864 865 static struct freq_tbl ftbl_gp3_clk_src[] = { 866 F(19200000, P_XO, 1, 0, 0), 867 F(100000000, P_GPLL0, 6, 0, 0), 868 F(200000000, P_GPLL0, 3, 0, 0), 869 { } 870 }; 871 872 static struct clk_rcg2 gp3_clk_src = { 873 .cmd_rcgr = 0x1984, 874 .mnd_width = 8, 875 .hid_width = 5, 876 .parent_map = gcc_xo_gpll0_map, 877 .freq_tbl = ftbl_gp3_clk_src, 878 .clkr.hw.init = &(struct clk_init_data){ 879 .name = "gp3_clk_src", 880 .parent_data = gcc_xo_gpll0, 881 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 882 .ops = &clk_rcg2_ops, 883 }, 884 }; 885 886 static struct freq_tbl ftbl_pcie_0_aux_clk_src[] = { 887 F(1011000, P_XO, 1, 1, 19), 888 { } 889 }; 890 891 static struct clk_rcg2 pcie_0_aux_clk_src = { 892 .cmd_rcgr = 0x1b00, 893 .mnd_width = 8, 894 .hid_width = 5, 895 .freq_tbl = ftbl_pcie_0_aux_clk_src, 896 .clkr.hw.init = &(struct clk_init_data){ 897 .name = "pcie_0_aux_clk_src", 898 .parent_data = &(const struct clk_parent_data){ 899 .fw_name = "xo", 900 }, 901 .num_parents = 1, 902 .ops = &clk_rcg2_ops, 903 }, 904 }; 905 906 static struct freq_tbl ftbl_pcie_pipe_clk_src[] = { 907 F(125000000, P_XO, 1, 0, 0), 908 { } 909 }; 910 911 static struct clk_rcg2 pcie_0_pipe_clk_src = { 912 .cmd_rcgr = 0x1adc, 913 .hid_width = 5, 914 .freq_tbl = ftbl_pcie_pipe_clk_src, 915 .clkr.hw.init = &(struct clk_init_data){ 916 .name = "pcie_0_pipe_clk_src", 917 .parent_data = &(const struct clk_parent_data){ 918 .fw_name = "xo", 919 }, 920 .num_parents = 1, 921 .ops = &clk_rcg2_ops, 922 }, 923 }; 924 925 static struct freq_tbl ftbl_pcie_1_aux_clk_src[] = { 926 F(1011000, P_XO, 1, 1, 19), 927 { } 928 }; 929 930 static struct clk_rcg2 pcie_1_aux_clk_src = { 931 .cmd_rcgr = 0x1b80, 932 .mnd_width = 8, 933 .hid_width = 5, 934 .freq_tbl = ftbl_pcie_1_aux_clk_src, 935 .clkr.hw.init = &(struct clk_init_data){ 936 .name = "pcie_1_aux_clk_src", 937 .parent_data = &(const struct clk_parent_data){ 938 .fw_name = "xo", 939 }, 940 .num_parents = 1, 941 .ops = &clk_rcg2_ops, 942 }, 943 }; 944 945 static struct clk_rcg2 pcie_1_pipe_clk_src = { 946 .cmd_rcgr = 0x1b5c, 947 .hid_width = 5, 948 .freq_tbl = ftbl_pcie_pipe_clk_src, 949 .clkr.hw.init = &(struct clk_init_data){ 950 .name = "pcie_1_pipe_clk_src", 951 .parent_data = &(const struct clk_parent_data){ 952 .fw_name = "xo", 953 }, 954 .num_parents = 1, 955 .ops = &clk_rcg2_ops, 956 }, 957 }; 958 959 static struct freq_tbl ftbl_pdm2_clk_src[] = { 960 F(60000000, P_GPLL0, 10, 0, 0), 961 { } 962 }; 963 964 static struct clk_rcg2 pdm2_clk_src = { 965 .cmd_rcgr = 0x0cd0, 966 .hid_width = 5, 967 .parent_map = gcc_xo_gpll0_map, 968 .freq_tbl = ftbl_pdm2_clk_src, 969 .clkr.hw.init = &(struct clk_init_data){ 970 .name = "pdm2_clk_src", 971 .parent_data = gcc_xo_gpll0, 972 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 973 .ops = &clk_rcg2_ops, 974 }, 975 }; 976 977 static struct freq_tbl ftbl_sdcc1_apps_clk_src[] = { 978 F(144000, P_XO, 16, 3, 25), 979 F(400000, P_XO, 12, 1, 4), 980 F(20000000, P_GPLL0, 15, 1, 2), 981 F(25000000, P_GPLL0, 12, 1, 2), 982 F(50000000, P_GPLL0, 12, 0, 0), 983 F(100000000, P_GPLL0, 6, 0, 0), 984 F(192000000, P_GPLL4, 2, 0, 0), 985 F(384000000, P_GPLL4, 1, 0, 0), 986 { } 987 }; 988 989 static struct freq_tbl ftbl_sdcc1_apps_clk_src_8992[] = { 990 F(144000, P_XO, 16, 3, 25), 991 F(400000, P_XO, 12, 1, 4), 992 F(20000000, P_GPLL0, 15, 1, 2), 993 F(25000000, P_GPLL0, 12, 1, 2), 994 F(50000000, P_GPLL0, 12, 0, 0), 995 F(100000000, P_GPLL0, 6, 0, 0), 996 F(172000000, P_GPLL4, 2, 0, 0), 997 F(344000000, P_GPLL4, 1, 0, 0), 998 { } 999 }; 1000 1001 static struct clk_rcg2 sdcc1_apps_clk_src = { 1002 .cmd_rcgr = 0x04d0, 1003 .mnd_width = 8, 1004 .hid_width = 5, 1005 .parent_map = gcc_xo_gpll0_gpll4_map, 1006 .freq_tbl = ftbl_sdcc1_apps_clk_src, 1007 .clkr.hw.init = &(struct clk_init_data){ 1008 .name = "sdcc1_apps_clk_src", 1009 .parent_data = gcc_xo_gpll0_gpll4, 1010 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4), 1011 .ops = &clk_rcg2_floor_ops, 1012 }, 1013 }; 1014 1015 static struct freq_tbl ftbl_sdcc2_4_apps_clk_src[] = { 1016 F(144000, P_XO, 16, 3, 25), 1017 F(400000, P_XO, 12, 1, 4), 1018 F(20000000, P_GPLL0, 15, 1, 2), 1019 F(25000000, P_GPLL0, 12, 1, 2), 1020 F(50000000, P_GPLL0, 12, 0, 0), 1021 F(100000000, P_GPLL0, 6, 0, 0), 1022 F(200000000, P_GPLL0, 3, 0, 0), 1023 { } 1024 }; 1025 1026 static struct clk_rcg2 sdcc2_apps_clk_src = { 1027 .cmd_rcgr = 0x0510, 1028 .mnd_width = 8, 1029 .hid_width = 5, 1030 .parent_map = gcc_xo_gpll0_map, 1031 .freq_tbl = ftbl_sdcc2_4_apps_clk_src, 1032 .clkr.hw.init = &(struct clk_init_data){ 1033 .name = "sdcc2_apps_clk_src", 1034 .parent_data = gcc_xo_gpll0, 1035 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1036 .ops = &clk_rcg2_floor_ops, 1037 }, 1038 }; 1039 1040 static struct clk_rcg2 sdcc3_apps_clk_src = { 1041 .cmd_rcgr = 0x0550, 1042 .mnd_width = 8, 1043 .hid_width = 5, 1044 .parent_map = gcc_xo_gpll0_map, 1045 .freq_tbl = ftbl_sdcc2_4_apps_clk_src, 1046 .clkr.hw.init = &(struct clk_init_data){ 1047 .name = "sdcc3_apps_clk_src", 1048 .parent_data = gcc_xo_gpll0, 1049 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1050 .ops = &clk_rcg2_floor_ops, 1051 }, 1052 }; 1053 1054 static struct clk_rcg2 sdcc4_apps_clk_src = { 1055 .cmd_rcgr = 0x0590, 1056 .mnd_width = 8, 1057 .hid_width = 5, 1058 .parent_map = gcc_xo_gpll0_map, 1059 .freq_tbl = ftbl_sdcc2_4_apps_clk_src, 1060 .clkr.hw.init = &(struct clk_init_data){ 1061 .name = "sdcc4_apps_clk_src", 1062 .parent_data = gcc_xo_gpll0, 1063 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1064 .ops = &clk_rcg2_floor_ops, 1065 }, 1066 }; 1067 1068 static struct freq_tbl ftbl_tsif_ref_clk_src[] = { 1069 F(105500, P_XO, 1, 1, 182), 1070 { } 1071 }; 1072 1073 static struct clk_rcg2 tsif_ref_clk_src = { 1074 .cmd_rcgr = 0x0d90, 1075 .mnd_width = 8, 1076 .hid_width = 5, 1077 .freq_tbl = ftbl_tsif_ref_clk_src, 1078 .clkr.hw.init = &(struct clk_init_data){ 1079 .name = "tsif_ref_clk_src", 1080 .parent_data = &(const struct clk_parent_data){ 1081 .fw_name = "xo", 1082 }, 1083 .num_parents = 1, 1084 .ops = &clk_rcg2_ops, 1085 }, 1086 }; 1087 1088 static struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = { 1089 F(19200000, P_XO, 1, 0, 0), 1090 F(60000000, P_GPLL0, 10, 0, 0), 1091 { } 1092 }; 1093 1094 static struct clk_rcg2 usb30_mock_utmi_clk_src = { 1095 .cmd_rcgr = 0x03e8, 1096 .hid_width = 5, 1097 .parent_map = gcc_xo_gpll0_map, 1098 .freq_tbl = ftbl_usb30_mock_utmi_clk_src, 1099 .clkr.hw.init = &(struct clk_init_data){ 1100 .name = "usb30_mock_utmi_clk_src", 1101 .parent_data = gcc_xo_gpll0, 1102 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1103 .ops = &clk_rcg2_ops, 1104 }, 1105 }; 1106 1107 static struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = { 1108 F(1200000, P_XO, 16, 0, 0), 1109 { } 1110 }; 1111 1112 static struct clk_rcg2 usb3_phy_aux_clk_src = { 1113 .cmd_rcgr = 0x1414, 1114 .hid_width = 5, 1115 .freq_tbl = ftbl_usb3_phy_aux_clk_src, 1116 .clkr.hw.init = &(struct clk_init_data){ 1117 .name = "usb3_phy_aux_clk_src", 1118 .parent_data = &(const struct clk_parent_data){ 1119 .fw_name = "xo", 1120 }, 1121 .num_parents = 1, 1122 .ops = &clk_rcg2_ops, 1123 }, 1124 }; 1125 1126 static struct freq_tbl ftbl_usb_hs_system_clk_src[] = { 1127 F(75000000, P_GPLL0, 8, 0, 0), 1128 { } 1129 }; 1130 1131 static struct clk_rcg2 usb_hs_system_clk_src = { 1132 .cmd_rcgr = 0x0490, 1133 .hid_width = 5, 1134 .parent_map = gcc_xo_gpll0_map, 1135 .freq_tbl = ftbl_usb_hs_system_clk_src, 1136 .clkr.hw.init = &(struct clk_init_data){ 1137 .name = "usb_hs_system_clk_src", 1138 .parent_data = gcc_xo_gpll0, 1139 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1140 .ops = &clk_rcg2_ops, 1141 }, 1142 }; 1143 1144 static struct clk_branch gcc_blsp1_ahb_clk = { 1145 .halt_reg = 0x05c4, 1146 .halt_check = BRANCH_HALT_VOTED, 1147 .clkr = { 1148 .enable_reg = 0x1484, 1149 .enable_mask = BIT(17), 1150 .hw.init = &(struct clk_init_data){ 1151 .name = "gcc_blsp1_ahb_clk", 1152 .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw }, 1153 .num_parents = 1, 1154 .ops = &clk_branch2_ops, 1155 }, 1156 }, 1157 }; 1158 1159 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { 1160 .halt_reg = 0x0648, 1161 .clkr = { 1162 .enable_reg = 0x0648, 1163 .enable_mask = BIT(0), 1164 .hw.init = &(struct clk_init_data){ 1165 .name = "gcc_blsp1_qup1_i2c_apps_clk", 1166 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup1_i2c_apps_clk_src.clkr.hw }, 1167 .num_parents = 1, 1168 .flags = CLK_SET_RATE_PARENT, 1169 .ops = &clk_branch2_ops, 1170 }, 1171 }, 1172 }; 1173 1174 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { 1175 .halt_reg = 0x0644, 1176 .clkr = { 1177 .enable_reg = 0x0644, 1178 .enable_mask = BIT(0), 1179 .hw.init = &(struct clk_init_data){ 1180 .name = "gcc_blsp1_qup1_spi_apps_clk", 1181 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup1_spi_apps_clk_src.clkr.hw }, 1182 .num_parents = 1, 1183 .flags = CLK_SET_RATE_PARENT, 1184 .ops = &clk_branch2_ops, 1185 }, 1186 }, 1187 }; 1188 1189 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { 1190 .halt_reg = 0x06c8, 1191 .clkr = { 1192 .enable_reg = 0x06c8, 1193 .enable_mask = BIT(0), 1194 .hw.init = &(struct clk_init_data){ 1195 .name = "gcc_blsp1_qup2_i2c_apps_clk", 1196 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup2_i2c_apps_clk_src.clkr.hw }, 1197 .num_parents = 1, 1198 .flags = CLK_SET_RATE_PARENT, 1199 .ops = &clk_branch2_ops, 1200 }, 1201 }, 1202 }; 1203 1204 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { 1205 .halt_reg = 0x06c4, 1206 .clkr = { 1207 .enable_reg = 0x06c4, 1208 .enable_mask = BIT(0), 1209 .hw.init = &(struct clk_init_data){ 1210 .name = "gcc_blsp1_qup2_spi_apps_clk", 1211 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup2_spi_apps_clk_src.clkr.hw }, 1212 .num_parents = 1, 1213 .flags = CLK_SET_RATE_PARENT, 1214 .ops = &clk_branch2_ops, 1215 }, 1216 }, 1217 }; 1218 1219 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = { 1220 .halt_reg = 0x0748, 1221 .clkr = { 1222 .enable_reg = 0x0748, 1223 .enable_mask = BIT(0), 1224 .hw.init = &(struct clk_init_data){ 1225 .name = "gcc_blsp1_qup3_i2c_apps_clk", 1226 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup3_i2c_apps_clk_src.clkr.hw }, 1227 .num_parents = 1, 1228 .flags = CLK_SET_RATE_PARENT, 1229 .ops = &clk_branch2_ops, 1230 }, 1231 }, 1232 }; 1233 1234 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = { 1235 .halt_reg = 0x0744, 1236 .clkr = { 1237 .enable_reg = 0x0744, 1238 .enable_mask = BIT(0), 1239 .hw.init = &(struct clk_init_data){ 1240 .name = "gcc_blsp1_qup3_spi_apps_clk", 1241 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup3_spi_apps_clk_src.clkr.hw }, 1242 .num_parents = 1, 1243 .flags = CLK_SET_RATE_PARENT, 1244 .ops = &clk_branch2_ops, 1245 }, 1246 }, 1247 }; 1248 1249 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = { 1250 .halt_reg = 0x07c8, 1251 .clkr = { 1252 .enable_reg = 0x07c8, 1253 .enable_mask = BIT(0), 1254 .hw.init = &(struct clk_init_data){ 1255 .name = "gcc_blsp1_qup4_i2c_apps_clk", 1256 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup4_i2c_apps_clk_src.clkr.hw }, 1257 .num_parents = 1, 1258 .flags = CLK_SET_RATE_PARENT, 1259 .ops = &clk_branch2_ops, 1260 }, 1261 }, 1262 }; 1263 1264 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = { 1265 .halt_reg = 0x07c4, 1266 .clkr = { 1267 .enable_reg = 0x07c4, 1268 .enable_mask = BIT(0), 1269 .hw.init = &(struct clk_init_data){ 1270 .name = "gcc_blsp1_qup4_spi_apps_clk", 1271 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup4_spi_apps_clk_src.clkr.hw }, 1272 .num_parents = 1, 1273 .flags = CLK_SET_RATE_PARENT, 1274 .ops = &clk_branch2_ops, 1275 }, 1276 }, 1277 }; 1278 1279 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = { 1280 .halt_reg = 0x0848, 1281 .clkr = { 1282 .enable_reg = 0x0848, 1283 .enable_mask = BIT(0), 1284 .hw.init = &(struct clk_init_data){ 1285 .name = "gcc_blsp1_qup5_i2c_apps_clk", 1286 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup5_i2c_apps_clk_src.clkr.hw }, 1287 .num_parents = 1, 1288 .flags = CLK_SET_RATE_PARENT, 1289 .ops = &clk_branch2_ops, 1290 }, 1291 }, 1292 }; 1293 1294 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = { 1295 .halt_reg = 0x0844, 1296 .clkr = { 1297 .enable_reg = 0x0844, 1298 .enable_mask = BIT(0), 1299 .hw.init = &(struct clk_init_data){ 1300 .name = "gcc_blsp1_qup5_spi_apps_clk", 1301 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup5_spi_apps_clk_src.clkr.hw }, 1302 .num_parents = 1, 1303 .flags = CLK_SET_RATE_PARENT, 1304 .ops = &clk_branch2_ops, 1305 }, 1306 }, 1307 }; 1308 1309 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = { 1310 .halt_reg = 0x08c8, 1311 .clkr = { 1312 .enable_reg = 0x08c8, 1313 .enable_mask = BIT(0), 1314 .hw.init = &(struct clk_init_data){ 1315 .name = "gcc_blsp1_qup6_i2c_apps_clk", 1316 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup6_i2c_apps_clk_src.clkr.hw }, 1317 .num_parents = 1, 1318 .flags = CLK_SET_RATE_PARENT, 1319 .ops = &clk_branch2_ops, 1320 }, 1321 }, 1322 }; 1323 1324 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = { 1325 .halt_reg = 0x08c4, 1326 .clkr = { 1327 .enable_reg = 0x08c4, 1328 .enable_mask = BIT(0), 1329 .hw.init = &(struct clk_init_data){ 1330 .name = "gcc_blsp1_qup6_spi_apps_clk", 1331 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup6_spi_apps_clk_src.clkr.hw }, 1332 .num_parents = 1, 1333 .flags = CLK_SET_RATE_PARENT, 1334 .ops = &clk_branch2_ops, 1335 }, 1336 }, 1337 }; 1338 1339 static struct clk_branch gcc_blsp1_uart1_apps_clk = { 1340 .halt_reg = 0x0684, 1341 .clkr = { 1342 .enable_reg = 0x0684, 1343 .enable_mask = BIT(0), 1344 .hw.init = &(struct clk_init_data){ 1345 .name = "gcc_blsp1_uart1_apps_clk", 1346 .parent_hws = (const struct clk_hw *[]){ &blsp1_uart1_apps_clk_src.clkr.hw }, 1347 .num_parents = 1, 1348 .flags = CLK_SET_RATE_PARENT, 1349 .ops = &clk_branch2_ops, 1350 }, 1351 }, 1352 }; 1353 1354 static struct clk_branch gcc_blsp1_uart2_apps_clk = { 1355 .halt_reg = 0x0704, 1356 .clkr = { 1357 .enable_reg = 0x0704, 1358 .enable_mask = BIT(0), 1359 .hw.init = &(struct clk_init_data){ 1360 .name = "gcc_blsp1_uart2_apps_clk", 1361 .parent_hws = (const struct clk_hw *[]){ &blsp1_uart2_apps_clk_src.clkr.hw }, 1362 .num_parents = 1, 1363 .flags = CLK_SET_RATE_PARENT, 1364 .ops = &clk_branch2_ops, 1365 }, 1366 }, 1367 }; 1368 1369 static struct clk_branch gcc_blsp1_uart3_apps_clk = { 1370 .halt_reg = 0x0784, 1371 .clkr = { 1372 .enable_reg = 0x0784, 1373 .enable_mask = BIT(0), 1374 .hw.init = &(struct clk_init_data){ 1375 .name = "gcc_blsp1_uart3_apps_clk", 1376 .parent_hws = (const struct clk_hw *[]){ &blsp1_uart3_apps_clk_src.clkr.hw }, 1377 .num_parents = 1, 1378 .flags = CLK_SET_RATE_PARENT, 1379 .ops = &clk_branch2_ops, 1380 }, 1381 }, 1382 }; 1383 1384 static struct clk_branch gcc_blsp1_uart4_apps_clk = { 1385 .halt_reg = 0x0804, 1386 .clkr = { 1387 .enable_reg = 0x0804, 1388 .enable_mask = BIT(0), 1389 .hw.init = &(struct clk_init_data){ 1390 .name = "gcc_blsp1_uart4_apps_clk", 1391 .parent_hws = (const struct clk_hw *[]){ &blsp1_uart4_apps_clk_src.clkr.hw }, 1392 .num_parents = 1, 1393 .flags = CLK_SET_RATE_PARENT, 1394 .ops = &clk_branch2_ops, 1395 }, 1396 }, 1397 }; 1398 1399 static struct clk_branch gcc_blsp1_uart5_apps_clk = { 1400 .halt_reg = 0x0884, 1401 .clkr = { 1402 .enable_reg = 0x0884, 1403 .enable_mask = BIT(0), 1404 .hw.init = &(struct clk_init_data){ 1405 .name = "gcc_blsp1_uart5_apps_clk", 1406 .parent_hws = (const struct clk_hw *[]){ &blsp1_uart5_apps_clk_src.clkr.hw }, 1407 .num_parents = 1, 1408 .flags = CLK_SET_RATE_PARENT, 1409 .ops = &clk_branch2_ops, 1410 }, 1411 }, 1412 }; 1413 1414 static struct clk_branch gcc_blsp1_uart6_apps_clk = { 1415 .halt_reg = 0x0904, 1416 .clkr = { 1417 .enable_reg = 0x0904, 1418 .enable_mask = BIT(0), 1419 .hw.init = &(struct clk_init_data){ 1420 .name = "gcc_blsp1_uart6_apps_clk", 1421 .parent_hws = (const struct clk_hw *[]){ &blsp1_uart6_apps_clk_src.clkr.hw }, 1422 .num_parents = 1, 1423 .flags = CLK_SET_RATE_PARENT, 1424 .ops = &clk_branch2_ops, 1425 }, 1426 }, 1427 }; 1428 1429 static struct clk_branch gcc_blsp2_ahb_clk = { 1430 .halt_reg = 0x0944, 1431 .halt_check = BRANCH_HALT_VOTED, 1432 .clkr = { 1433 .enable_reg = 0x1484, 1434 .enable_mask = BIT(15), 1435 .hw.init = &(struct clk_init_data){ 1436 .name = "gcc_blsp2_ahb_clk", 1437 .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw }, 1438 .num_parents = 1, 1439 .ops = &clk_branch2_ops, 1440 }, 1441 }, 1442 }; 1443 1444 static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = { 1445 .halt_reg = 0x0988, 1446 .clkr = { 1447 .enable_reg = 0x0988, 1448 .enable_mask = BIT(0), 1449 .hw.init = &(struct clk_init_data){ 1450 .name = "gcc_blsp2_qup1_i2c_apps_clk", 1451 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup1_i2c_apps_clk_src.clkr.hw }, 1452 .num_parents = 1, 1453 .flags = CLK_SET_RATE_PARENT, 1454 .ops = &clk_branch2_ops, 1455 }, 1456 }, 1457 }; 1458 1459 static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = { 1460 .halt_reg = 0x0984, 1461 .clkr = { 1462 .enable_reg = 0x0984, 1463 .enable_mask = BIT(0), 1464 .hw.init = &(struct clk_init_data){ 1465 .name = "gcc_blsp2_qup1_spi_apps_clk", 1466 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup1_spi_apps_clk_src.clkr.hw }, 1467 .num_parents = 1, 1468 .flags = CLK_SET_RATE_PARENT, 1469 .ops = &clk_branch2_ops, 1470 }, 1471 }, 1472 }; 1473 1474 static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = { 1475 .halt_reg = 0x0a08, 1476 .clkr = { 1477 .enable_reg = 0x0a08, 1478 .enable_mask = BIT(0), 1479 .hw.init = &(struct clk_init_data){ 1480 .name = "gcc_blsp2_qup2_i2c_apps_clk", 1481 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup2_i2c_apps_clk_src.clkr.hw }, 1482 .num_parents = 1, 1483 .flags = CLK_SET_RATE_PARENT, 1484 .ops = &clk_branch2_ops, 1485 }, 1486 }, 1487 }; 1488 1489 static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = { 1490 .halt_reg = 0x0a04, 1491 .clkr = { 1492 .enable_reg = 0x0a04, 1493 .enable_mask = BIT(0), 1494 .hw.init = &(struct clk_init_data){ 1495 .name = "gcc_blsp2_qup2_spi_apps_clk", 1496 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup2_spi_apps_clk_src.clkr.hw }, 1497 .num_parents = 1, 1498 .flags = CLK_SET_RATE_PARENT, 1499 .ops = &clk_branch2_ops, 1500 }, 1501 }, 1502 }; 1503 1504 static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = { 1505 .halt_reg = 0x0a88, 1506 .clkr = { 1507 .enable_reg = 0x0a88, 1508 .enable_mask = BIT(0), 1509 .hw.init = &(struct clk_init_data){ 1510 .name = "gcc_blsp2_qup3_i2c_apps_clk", 1511 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup3_i2c_apps_clk_src.clkr.hw }, 1512 .num_parents = 1, 1513 .flags = CLK_SET_RATE_PARENT, 1514 .ops = &clk_branch2_ops, 1515 }, 1516 }, 1517 }; 1518 1519 static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = { 1520 .halt_reg = 0x0a84, 1521 .clkr = { 1522 .enable_reg = 0x0a84, 1523 .enable_mask = BIT(0), 1524 .hw.init = &(struct clk_init_data){ 1525 .name = "gcc_blsp2_qup3_spi_apps_clk", 1526 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup3_spi_apps_clk_src.clkr.hw }, 1527 .num_parents = 1, 1528 .flags = CLK_SET_RATE_PARENT, 1529 .ops = &clk_branch2_ops, 1530 }, 1531 }, 1532 }; 1533 1534 static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = { 1535 .halt_reg = 0x0b08, 1536 .clkr = { 1537 .enable_reg = 0x0b08, 1538 .enable_mask = BIT(0), 1539 .hw.init = &(struct clk_init_data){ 1540 .name = "gcc_blsp2_qup4_i2c_apps_clk", 1541 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup4_i2c_apps_clk_src.clkr.hw }, 1542 .num_parents = 1, 1543 .flags = CLK_SET_RATE_PARENT, 1544 .ops = &clk_branch2_ops, 1545 }, 1546 }, 1547 }; 1548 1549 static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = { 1550 .halt_reg = 0x0b04, 1551 .clkr = { 1552 .enable_reg = 0x0b04, 1553 .enable_mask = BIT(0), 1554 .hw.init = &(struct clk_init_data){ 1555 .name = "gcc_blsp2_qup4_spi_apps_clk", 1556 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup4_spi_apps_clk_src.clkr.hw }, 1557 .num_parents = 1, 1558 .flags = CLK_SET_RATE_PARENT, 1559 .ops = &clk_branch2_ops, 1560 }, 1561 }, 1562 }; 1563 1564 static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = { 1565 .halt_reg = 0x0b88, 1566 .clkr = { 1567 .enable_reg = 0x0b88, 1568 .enable_mask = BIT(0), 1569 .hw.init = &(struct clk_init_data){ 1570 .name = "gcc_blsp2_qup5_i2c_apps_clk", 1571 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup5_i2c_apps_clk_src.clkr.hw }, 1572 .num_parents = 1, 1573 .flags = CLK_SET_RATE_PARENT, 1574 .ops = &clk_branch2_ops, 1575 }, 1576 }, 1577 }; 1578 1579 static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = { 1580 .halt_reg = 0x0b84, 1581 .clkr = { 1582 .enable_reg = 0x0b84, 1583 .enable_mask = BIT(0), 1584 .hw.init = &(struct clk_init_data){ 1585 .name = "gcc_blsp2_qup5_spi_apps_clk", 1586 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup5_spi_apps_clk_src.clkr.hw }, 1587 .num_parents = 1, 1588 .flags = CLK_SET_RATE_PARENT, 1589 .ops = &clk_branch2_ops, 1590 }, 1591 }, 1592 }; 1593 1594 static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = { 1595 .halt_reg = 0x0c08, 1596 .clkr = { 1597 .enable_reg = 0x0c08, 1598 .enable_mask = BIT(0), 1599 .hw.init = &(struct clk_init_data){ 1600 .name = "gcc_blsp2_qup6_i2c_apps_clk", 1601 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup6_i2c_apps_clk_src.clkr.hw }, 1602 .num_parents = 1, 1603 .flags = CLK_SET_RATE_PARENT, 1604 .ops = &clk_branch2_ops, 1605 }, 1606 }, 1607 }; 1608 1609 static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = { 1610 .halt_reg = 0x0c04, 1611 .clkr = { 1612 .enable_reg = 0x0c04, 1613 .enable_mask = BIT(0), 1614 .hw.init = &(struct clk_init_data){ 1615 .name = "gcc_blsp2_qup6_spi_apps_clk", 1616 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup6_spi_apps_clk_src.clkr.hw }, 1617 .num_parents = 1, 1618 .flags = CLK_SET_RATE_PARENT, 1619 .ops = &clk_branch2_ops, 1620 }, 1621 }, 1622 }; 1623 1624 static struct clk_branch gcc_blsp2_uart1_apps_clk = { 1625 .halt_reg = 0x09c4, 1626 .clkr = { 1627 .enable_reg = 0x09c4, 1628 .enable_mask = BIT(0), 1629 .hw.init = &(struct clk_init_data){ 1630 .name = "gcc_blsp2_uart1_apps_clk", 1631 .parent_hws = (const struct clk_hw *[]){ &blsp2_uart1_apps_clk_src.clkr.hw }, 1632 .num_parents = 1, 1633 .flags = CLK_SET_RATE_PARENT, 1634 .ops = &clk_branch2_ops, 1635 }, 1636 }, 1637 }; 1638 1639 static struct clk_branch gcc_blsp2_uart2_apps_clk = { 1640 .halt_reg = 0x0a44, 1641 .clkr = { 1642 .enable_reg = 0x0a44, 1643 .enable_mask = BIT(0), 1644 .hw.init = &(struct clk_init_data){ 1645 .name = "gcc_blsp2_uart2_apps_clk", 1646 .parent_hws = (const struct clk_hw *[]){ &blsp2_uart2_apps_clk_src.clkr.hw }, 1647 .num_parents = 1, 1648 .flags = CLK_SET_RATE_PARENT, 1649 .ops = &clk_branch2_ops, 1650 }, 1651 }, 1652 }; 1653 1654 static struct clk_branch gcc_blsp2_uart3_apps_clk = { 1655 .halt_reg = 0x0ac4, 1656 .clkr = { 1657 .enable_reg = 0x0ac4, 1658 .enable_mask = BIT(0), 1659 .hw.init = &(struct clk_init_data){ 1660 .name = "gcc_blsp2_uart3_apps_clk", 1661 .parent_hws = (const struct clk_hw *[]){ &blsp2_uart3_apps_clk_src.clkr.hw }, 1662 .num_parents = 1, 1663 .flags = CLK_SET_RATE_PARENT, 1664 .ops = &clk_branch2_ops, 1665 }, 1666 }, 1667 }; 1668 1669 static struct clk_branch gcc_blsp2_uart4_apps_clk = { 1670 .halt_reg = 0x0b44, 1671 .clkr = { 1672 .enable_reg = 0x0b44, 1673 .enable_mask = BIT(0), 1674 .hw.init = &(struct clk_init_data){ 1675 .name = "gcc_blsp2_uart4_apps_clk", 1676 .parent_hws = (const struct clk_hw *[]){ &blsp2_uart4_apps_clk_src.clkr.hw }, 1677 .num_parents = 1, 1678 .flags = CLK_SET_RATE_PARENT, 1679 .ops = &clk_branch2_ops, 1680 }, 1681 }, 1682 }; 1683 1684 static struct clk_branch gcc_blsp2_uart5_apps_clk = { 1685 .halt_reg = 0x0bc4, 1686 .clkr = { 1687 .enable_reg = 0x0bc4, 1688 .enable_mask = BIT(0), 1689 .hw.init = &(struct clk_init_data){ 1690 .name = "gcc_blsp2_uart5_apps_clk", 1691 .parent_hws = (const struct clk_hw *[]){ &blsp2_uart5_apps_clk_src.clkr.hw }, 1692 .num_parents = 1, 1693 .flags = CLK_SET_RATE_PARENT, 1694 .ops = &clk_branch2_ops, 1695 }, 1696 }, 1697 }; 1698 1699 static struct clk_branch gcc_blsp2_uart6_apps_clk = { 1700 .halt_reg = 0x0c44, 1701 .clkr = { 1702 .enable_reg = 0x0c44, 1703 .enable_mask = BIT(0), 1704 .hw.init = &(struct clk_init_data){ 1705 .name = "gcc_blsp2_uart6_apps_clk", 1706 .parent_hws = (const struct clk_hw *[]){ &blsp2_uart6_apps_clk_src.clkr.hw }, 1707 .num_parents = 1, 1708 .flags = CLK_SET_RATE_PARENT, 1709 .ops = &clk_branch2_ops, 1710 }, 1711 }, 1712 }; 1713 1714 static struct clk_branch gcc_gp1_clk = { 1715 .halt_reg = 0x1900, 1716 .clkr = { 1717 .enable_reg = 0x1900, 1718 .enable_mask = BIT(0), 1719 .hw.init = &(struct clk_init_data){ 1720 .name = "gcc_gp1_clk", 1721 .parent_hws = (const struct clk_hw *[]){ &gp1_clk_src.clkr.hw }, 1722 .num_parents = 1, 1723 .flags = CLK_SET_RATE_PARENT, 1724 .ops = &clk_branch2_ops, 1725 }, 1726 }, 1727 }; 1728 1729 static struct clk_branch gcc_gp2_clk = { 1730 .halt_reg = 0x1940, 1731 .clkr = { 1732 .enable_reg = 0x1940, 1733 .enable_mask = BIT(0), 1734 .hw.init = &(struct clk_init_data){ 1735 .name = "gcc_gp2_clk", 1736 .parent_hws = (const struct clk_hw *[]){ &gp2_clk_src.clkr.hw }, 1737 .num_parents = 1, 1738 .flags = CLK_SET_RATE_PARENT, 1739 .ops = &clk_branch2_ops, 1740 }, 1741 }, 1742 }; 1743 1744 static struct clk_branch gcc_gp3_clk = { 1745 .halt_reg = 0x1980, 1746 .clkr = { 1747 .enable_reg = 0x1980, 1748 .enable_mask = BIT(0), 1749 .hw.init = &(struct clk_init_data){ 1750 .name = "gcc_gp3_clk", 1751 .parent_hws = (const struct clk_hw *[]){ &gp3_clk_src.clkr.hw }, 1752 .num_parents = 1, 1753 .flags = CLK_SET_RATE_PARENT, 1754 .ops = &clk_branch2_ops, 1755 }, 1756 }, 1757 }; 1758 1759 static struct clk_branch gcc_lpass_q6_axi_clk = { 1760 .halt_reg = 0x0280, 1761 .clkr = { 1762 .enable_reg = 0x0280, 1763 .enable_mask = BIT(0), 1764 .hw.init = &(struct clk_init_data){ 1765 .name = "gcc_lpass_q6_axi_clk", 1766 .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw }, 1767 .num_parents = 1, 1768 .ops = &clk_branch2_ops, 1769 }, 1770 }, 1771 }; 1772 1773 static struct clk_branch gcc_mss_q6_bimc_axi_clk = { 1774 .halt_reg = 0x0284, 1775 .clkr = { 1776 .enable_reg = 0x0284, 1777 .enable_mask = BIT(0), 1778 .hw.init = &(struct clk_init_data){ 1779 .name = "gcc_mss_q6_bimc_axi_clk", 1780 .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw }, 1781 .num_parents = 1, 1782 .ops = &clk_branch2_ops, 1783 }, 1784 }, 1785 }; 1786 1787 static struct clk_branch gcc_pcie_0_aux_clk = { 1788 .halt_reg = 0x1ad4, 1789 .clkr = { 1790 .enable_reg = 0x1ad4, 1791 .enable_mask = BIT(0), 1792 .hw.init = &(struct clk_init_data){ 1793 .name = "gcc_pcie_0_aux_clk", 1794 .parent_hws = (const struct clk_hw *[]){ &pcie_0_aux_clk_src.clkr.hw }, 1795 .num_parents = 1, 1796 .flags = CLK_SET_RATE_PARENT, 1797 .ops = &clk_branch2_ops, 1798 }, 1799 }, 1800 }; 1801 1802 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { 1803 .halt_reg = 0x1ad0, 1804 .clkr = { 1805 .enable_reg = 0x1ad0, 1806 .enable_mask = BIT(0), 1807 .hw.init = &(struct clk_init_data){ 1808 .name = "gcc_pcie_0_cfg_ahb_clk", 1809 .parent_hws = (const struct clk_hw *[]){ &config_noc_clk_src.clkr.hw }, 1810 .num_parents = 1, 1811 .flags = CLK_SET_RATE_PARENT, 1812 .ops = &clk_branch2_ops, 1813 }, 1814 }, 1815 }; 1816 1817 static struct clk_branch gcc_pcie_0_mstr_axi_clk = { 1818 .halt_reg = 0x1acc, 1819 .clkr = { 1820 .enable_reg = 0x1acc, 1821 .enable_mask = BIT(0), 1822 .hw.init = &(struct clk_init_data){ 1823 .name = "gcc_pcie_0_mstr_axi_clk", 1824 .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw }, 1825 .num_parents = 1, 1826 .flags = CLK_SET_RATE_PARENT, 1827 .ops = &clk_branch2_ops, 1828 }, 1829 }, 1830 }; 1831 1832 static struct clk_branch gcc_pcie_0_pipe_clk = { 1833 .halt_reg = 0x1ad8, 1834 .halt_check = BRANCH_HALT_DELAY, 1835 .clkr = { 1836 .enable_reg = 0x1ad8, 1837 .enable_mask = BIT(0), 1838 .hw.init = &(struct clk_init_data){ 1839 .name = "gcc_pcie_0_pipe_clk", 1840 .parent_hws = (const struct clk_hw *[]){ &pcie_0_pipe_clk_src.clkr.hw }, 1841 .num_parents = 1, 1842 .flags = CLK_SET_RATE_PARENT, 1843 .ops = &clk_branch2_ops, 1844 }, 1845 }, 1846 }; 1847 1848 static struct clk_branch gcc_pcie_0_slv_axi_clk = { 1849 .halt_reg = 0x1ac8, 1850 .halt_check = BRANCH_HALT_DELAY, 1851 .clkr = { 1852 .enable_reg = 0x1ac8, 1853 .enable_mask = BIT(0), 1854 .hw.init = &(struct clk_init_data){ 1855 .name = "gcc_pcie_0_slv_axi_clk", 1856 .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw }, 1857 .num_parents = 1, 1858 .flags = CLK_SET_RATE_PARENT, 1859 .ops = &clk_branch2_ops, 1860 }, 1861 }, 1862 }; 1863 1864 static struct clk_branch gcc_pcie_1_aux_clk = { 1865 .halt_reg = 0x1b54, 1866 .clkr = { 1867 .enable_reg = 0x1b54, 1868 .enable_mask = BIT(0), 1869 .hw.init = &(struct clk_init_data){ 1870 .name = "gcc_pcie_1_aux_clk", 1871 .parent_hws = (const struct clk_hw *[]){ &pcie_1_aux_clk_src.clkr.hw }, 1872 .num_parents = 1, 1873 .flags = CLK_SET_RATE_PARENT, 1874 .ops = &clk_branch2_ops, 1875 }, 1876 }, 1877 }; 1878 1879 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { 1880 .halt_reg = 0x1b54, 1881 .clkr = { 1882 .enable_reg = 0x1b54, 1883 .enable_mask = BIT(0), 1884 .hw.init = &(struct clk_init_data){ 1885 .name = "gcc_pcie_1_cfg_ahb_clk", 1886 .parent_hws = (const struct clk_hw *[]){ &config_noc_clk_src.clkr.hw }, 1887 .num_parents = 1, 1888 .flags = CLK_SET_RATE_PARENT, 1889 .ops = &clk_branch2_ops, 1890 }, 1891 }, 1892 }; 1893 1894 static struct clk_branch gcc_pcie_1_mstr_axi_clk = { 1895 .halt_reg = 0x1b50, 1896 .clkr = { 1897 .enable_reg = 0x1b50, 1898 .enable_mask = BIT(0), 1899 .hw.init = &(struct clk_init_data){ 1900 .name = "gcc_pcie_1_mstr_axi_clk", 1901 .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw }, 1902 .num_parents = 1, 1903 .flags = CLK_SET_RATE_PARENT, 1904 .ops = &clk_branch2_ops, 1905 }, 1906 }, 1907 }; 1908 1909 static struct clk_branch gcc_pcie_1_pipe_clk = { 1910 .halt_reg = 0x1b58, 1911 .halt_check = BRANCH_HALT_DELAY, 1912 .clkr = { 1913 .enable_reg = 0x1b58, 1914 .enable_mask = BIT(0), 1915 .hw.init = &(struct clk_init_data){ 1916 .name = "gcc_pcie_1_pipe_clk", 1917 .parent_hws = (const struct clk_hw *[]){ &pcie_1_pipe_clk_src.clkr.hw }, 1918 .num_parents = 1, 1919 .flags = CLK_SET_RATE_PARENT, 1920 .ops = &clk_branch2_ops, 1921 }, 1922 }, 1923 }; 1924 1925 static struct clk_branch gcc_pcie_1_slv_axi_clk = { 1926 .halt_reg = 0x1b48, 1927 .clkr = { 1928 .enable_reg = 0x1b48, 1929 .enable_mask = BIT(0), 1930 .hw.init = &(struct clk_init_data){ 1931 .name = "gcc_pcie_1_slv_axi_clk", 1932 .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw }, 1933 .num_parents = 1, 1934 .flags = CLK_SET_RATE_PARENT, 1935 .ops = &clk_branch2_ops, 1936 }, 1937 }, 1938 }; 1939 1940 static struct clk_branch gcc_pdm2_clk = { 1941 .halt_reg = 0x0ccc, 1942 .clkr = { 1943 .enable_reg = 0x0ccc, 1944 .enable_mask = BIT(0), 1945 .hw.init = &(struct clk_init_data){ 1946 .name = "gcc_pdm2_clk", 1947 .parent_hws = (const struct clk_hw *[]){ &pdm2_clk_src.clkr.hw }, 1948 .num_parents = 1, 1949 .flags = CLK_SET_RATE_PARENT, 1950 .ops = &clk_branch2_ops, 1951 }, 1952 }, 1953 }; 1954 1955 static struct clk_branch gcc_pdm_ahb_clk = { 1956 .halt_reg = 0x0cc4, 1957 .clkr = { 1958 .enable_reg = 0x0cc4, 1959 .enable_mask = BIT(0), 1960 .hw.init = &(struct clk_init_data){ 1961 .name = "gcc_pdm_ahb_clk", 1962 .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw }, 1963 .num_parents = 1, 1964 .ops = &clk_branch2_ops, 1965 }, 1966 }, 1967 }; 1968 1969 static struct clk_branch gcc_sdcc1_apps_clk = { 1970 .halt_reg = 0x04c4, 1971 .clkr = { 1972 .enable_reg = 0x04c4, 1973 .enable_mask = BIT(0), 1974 .hw.init = &(struct clk_init_data){ 1975 .name = "gcc_sdcc1_apps_clk", 1976 .parent_hws = (const struct clk_hw *[]){ &sdcc1_apps_clk_src.clkr.hw }, 1977 .num_parents = 1, 1978 .flags = CLK_SET_RATE_PARENT, 1979 .ops = &clk_branch2_ops, 1980 }, 1981 }, 1982 }; 1983 1984 static struct clk_branch gcc_sdcc1_ahb_clk = { 1985 .halt_reg = 0x04c8, 1986 .clkr = { 1987 .enable_reg = 0x04c8, 1988 .enable_mask = BIT(0), 1989 .hw.init = &(struct clk_init_data){ 1990 .name = "gcc_sdcc1_ahb_clk", 1991 .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw }, 1992 .num_parents = 1, 1993 .flags = CLK_SET_RATE_PARENT, 1994 .ops = &clk_branch2_ops, 1995 }, 1996 }, 1997 }; 1998 1999 static struct clk_branch gcc_sdcc2_ahb_clk = { 2000 .halt_reg = 0x0508, 2001 .clkr = { 2002 .enable_reg = 0x0508, 2003 .enable_mask = BIT(0), 2004 .hw.init = &(struct clk_init_data){ 2005 .name = "gcc_sdcc2_ahb_clk", 2006 .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw }, 2007 .num_parents = 1, 2008 .flags = CLK_SET_RATE_PARENT, 2009 .ops = &clk_branch2_ops, 2010 }, 2011 }, 2012 }; 2013 2014 static struct clk_branch gcc_sdcc2_apps_clk = { 2015 .halt_reg = 0x0504, 2016 .clkr = { 2017 .enable_reg = 0x0504, 2018 .enable_mask = BIT(0), 2019 .hw.init = &(struct clk_init_data){ 2020 .name = "gcc_sdcc2_apps_clk", 2021 .parent_hws = (const struct clk_hw *[]){ &sdcc2_apps_clk_src.clkr.hw }, 2022 .num_parents = 1, 2023 .flags = CLK_SET_RATE_PARENT, 2024 .ops = &clk_branch2_ops, 2025 }, 2026 }, 2027 }; 2028 2029 static struct clk_branch gcc_sdcc3_ahb_clk = { 2030 .halt_reg = 0x0548, 2031 .clkr = { 2032 .enable_reg = 0x0548, 2033 .enable_mask = BIT(0), 2034 .hw.init = &(struct clk_init_data){ 2035 .name = "gcc_sdcc3_ahb_clk", 2036 .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw }, 2037 .num_parents = 1, 2038 .flags = CLK_SET_RATE_PARENT, 2039 .ops = &clk_branch2_ops, 2040 }, 2041 }, 2042 }; 2043 2044 static struct clk_branch gcc_sdcc3_apps_clk = { 2045 .halt_reg = 0x0544, 2046 .clkr = { 2047 .enable_reg = 0x0544, 2048 .enable_mask = BIT(0), 2049 .hw.init = &(struct clk_init_data){ 2050 .name = "gcc_sdcc3_apps_clk", 2051 .parent_hws = (const struct clk_hw *[]){ &sdcc3_apps_clk_src.clkr.hw }, 2052 .num_parents = 1, 2053 .flags = CLK_SET_RATE_PARENT, 2054 .ops = &clk_branch2_ops, 2055 }, 2056 }, 2057 }; 2058 2059 static struct clk_branch gcc_sdcc4_ahb_clk = { 2060 .halt_reg = 0x0588, 2061 .clkr = { 2062 .enable_reg = 0x0588, 2063 .enable_mask = BIT(0), 2064 .hw.init = &(struct clk_init_data){ 2065 .name = "gcc_sdcc4_ahb_clk", 2066 .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw }, 2067 .num_parents = 1, 2068 .flags = CLK_SET_RATE_PARENT, 2069 .ops = &clk_branch2_ops, 2070 }, 2071 }, 2072 }; 2073 2074 static struct clk_branch gcc_sdcc4_apps_clk = { 2075 .halt_reg = 0x0584, 2076 .clkr = { 2077 .enable_reg = 0x0584, 2078 .enable_mask = BIT(0), 2079 .hw.init = &(struct clk_init_data){ 2080 .name = "gcc_sdcc4_apps_clk", 2081 .parent_hws = (const struct clk_hw *[]){ &sdcc4_apps_clk_src.clkr.hw }, 2082 .num_parents = 1, 2083 .flags = CLK_SET_RATE_PARENT, 2084 .ops = &clk_branch2_ops, 2085 }, 2086 }, 2087 }; 2088 2089 static struct clk_branch gcc_sys_noc_ufs_axi_clk = { 2090 .halt_reg = 0x1d7c, 2091 .clkr = { 2092 .enable_reg = 0x1d7c, 2093 .enable_mask = BIT(0), 2094 .hw.init = &(struct clk_init_data){ 2095 .name = "gcc_sys_noc_ufs_axi_clk", 2096 .parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw }, 2097 .num_parents = 1, 2098 .flags = CLK_SET_RATE_PARENT, 2099 .ops = &clk_branch2_ops, 2100 }, 2101 }, 2102 }; 2103 2104 static struct clk_branch gcc_sys_noc_usb3_axi_clk = { 2105 .halt_reg = 0x03fc, 2106 .clkr = { 2107 .enable_reg = 0x03fc, 2108 .enable_mask = BIT(0), 2109 .hw.init = &(struct clk_init_data){ 2110 .name = "gcc_sys_noc_usb3_axi_clk", 2111 .parent_hws = (const struct clk_hw *[]){ &usb30_master_clk_src.clkr.hw }, 2112 .num_parents = 1, 2113 .flags = CLK_SET_RATE_PARENT, 2114 .ops = &clk_branch2_ops, 2115 }, 2116 }, 2117 }; 2118 2119 static struct clk_branch gcc_tsif_ahb_clk = { 2120 .halt_reg = 0x0d84, 2121 .clkr = { 2122 .enable_reg = 0x0d84, 2123 .enable_mask = BIT(0), 2124 .hw.init = &(struct clk_init_data){ 2125 .name = "gcc_tsif_ahb_clk", 2126 .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw }, 2127 .num_parents = 1, 2128 .ops = &clk_branch2_ops, 2129 }, 2130 }, 2131 }; 2132 2133 static struct clk_branch gcc_tsif_ref_clk = { 2134 .halt_reg = 0x0d88, 2135 .clkr = { 2136 .enable_reg = 0x0d88, 2137 .enable_mask = BIT(0), 2138 .hw.init = &(struct clk_init_data){ 2139 .name = "gcc_tsif_ref_clk", 2140 .parent_hws = (const struct clk_hw *[]){ &tsif_ref_clk_src.clkr.hw }, 2141 .num_parents = 1, 2142 .flags = CLK_SET_RATE_PARENT, 2143 .ops = &clk_branch2_ops, 2144 }, 2145 }, 2146 }; 2147 2148 static struct clk_branch gcc_ufs_ahb_clk = { 2149 .halt_reg = 0x1d4c, 2150 .clkr = { 2151 .enable_reg = 0x1d4c, 2152 .enable_mask = BIT(0), 2153 .hw.init = &(struct clk_init_data){ 2154 .name = "gcc_ufs_ahb_clk", 2155 .parent_hws = (const struct clk_hw *[]){ &config_noc_clk_src.clkr.hw }, 2156 .num_parents = 1, 2157 .ops = &clk_branch2_ops, 2158 }, 2159 }, 2160 }; 2161 2162 static struct clk_branch gcc_ufs_axi_clk = { 2163 .halt_reg = 0x1d48, 2164 .clkr = { 2165 .enable_reg = 0x1d48, 2166 .enable_mask = BIT(0), 2167 .hw.init = &(struct clk_init_data){ 2168 .name = "gcc_ufs_axi_clk", 2169 .parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw }, 2170 .num_parents = 1, 2171 .flags = CLK_SET_RATE_PARENT, 2172 .ops = &clk_branch2_ops, 2173 }, 2174 }, 2175 }; 2176 2177 static struct clk_branch gcc_ufs_rx_cfg_clk = { 2178 .halt_reg = 0x1d54, 2179 .clkr = { 2180 .enable_reg = 0x1d54, 2181 .enable_mask = BIT(0), 2182 .hw.init = &(struct clk_init_data){ 2183 .name = "gcc_ufs_rx_cfg_clk", 2184 .parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw }, 2185 .num_parents = 1, 2186 .flags = CLK_SET_RATE_PARENT, 2187 .ops = &clk_branch2_ops, 2188 }, 2189 }, 2190 }; 2191 2192 static struct clk_branch gcc_ufs_rx_symbol_0_clk = { 2193 .halt_reg = 0x1d60, 2194 .halt_check = BRANCH_HALT_DELAY, 2195 .clkr = { 2196 .enable_reg = 0x1d60, 2197 .enable_mask = BIT(0), 2198 .hw.init = &(struct clk_init_data){ 2199 .name = "gcc_ufs_rx_symbol_0_clk", 2200 .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw }, 2201 .num_parents = 1, 2202 .ops = &clk_branch2_ops, 2203 }, 2204 }, 2205 }; 2206 2207 static struct clk_branch gcc_ufs_rx_symbol_1_clk = { 2208 .halt_reg = 0x1d64, 2209 .halt_check = BRANCH_HALT_DELAY, 2210 .clkr = { 2211 .enable_reg = 0x1d64, 2212 .enable_mask = BIT(0), 2213 .hw.init = &(struct clk_init_data){ 2214 .name = "gcc_ufs_rx_symbol_1_clk", 2215 .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw }, 2216 .num_parents = 1, 2217 .ops = &clk_branch2_ops, 2218 }, 2219 }, 2220 }; 2221 2222 static struct clk_branch gcc_ufs_tx_cfg_clk = { 2223 .halt_reg = 0x1d50, 2224 .clkr = { 2225 .enable_reg = 0x1d50, 2226 .enable_mask = BIT(0), 2227 .hw.init = &(struct clk_init_data){ 2228 .name = "gcc_ufs_tx_cfg_clk", 2229 .parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw }, 2230 .num_parents = 1, 2231 .flags = CLK_SET_RATE_PARENT, 2232 .ops = &clk_branch2_ops, 2233 }, 2234 }, 2235 }; 2236 2237 static struct clk_branch gcc_ufs_tx_symbol_0_clk = { 2238 .halt_reg = 0x1d58, 2239 .halt_check = BRANCH_HALT_DELAY, 2240 .clkr = { 2241 .enable_reg = 0x1d58, 2242 .enable_mask = BIT(0), 2243 .hw.init = &(struct clk_init_data){ 2244 .name = "gcc_ufs_tx_symbol_0_clk", 2245 .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw }, 2246 .num_parents = 1, 2247 .ops = &clk_branch2_ops, 2248 }, 2249 }, 2250 }; 2251 2252 static struct clk_branch gcc_ufs_tx_symbol_1_clk = { 2253 .halt_reg = 0x1d5c, 2254 .halt_check = BRANCH_HALT_DELAY, 2255 .clkr = { 2256 .enable_reg = 0x1d5c, 2257 .enable_mask = BIT(0), 2258 .hw.init = &(struct clk_init_data){ 2259 .name = "gcc_ufs_tx_symbol_1_clk", 2260 .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw }, 2261 .num_parents = 1, 2262 .ops = &clk_branch2_ops, 2263 }, 2264 }, 2265 }; 2266 2267 static struct clk_branch gcc_usb2_hs_phy_sleep_clk = { 2268 .halt_reg = 0x04ac, 2269 .clkr = { 2270 .enable_reg = 0x04ac, 2271 .enable_mask = BIT(0), 2272 .hw.init = &(struct clk_init_data){ 2273 .name = "gcc_usb2_hs_phy_sleep_clk", 2274 .parent_data = &(const struct clk_parent_data){ 2275 .fw_name = "sleep", 2276 .name = "sleep" 2277 }, 2278 .num_parents = 1, 2279 .ops = &clk_branch2_ops, 2280 }, 2281 }, 2282 }; 2283 2284 static struct clk_branch gcc_usb30_master_clk = { 2285 .halt_reg = 0x03c8, 2286 .clkr = { 2287 .enable_reg = 0x03c8, 2288 .enable_mask = BIT(0), 2289 .hw.init = &(struct clk_init_data){ 2290 .name = "gcc_usb30_master_clk", 2291 .parent_hws = (const struct clk_hw *[]){ &usb30_master_clk_src.clkr.hw }, 2292 .num_parents = 1, 2293 .flags = CLK_SET_RATE_PARENT, 2294 .ops = &clk_branch2_ops, 2295 }, 2296 }, 2297 }; 2298 2299 static struct clk_branch gcc_usb30_mock_utmi_clk = { 2300 .halt_reg = 0x03d0, 2301 .clkr = { 2302 .enable_reg = 0x03d0, 2303 .enable_mask = BIT(0), 2304 .hw.init = &(struct clk_init_data){ 2305 .name = "gcc_usb30_mock_utmi_clk", 2306 .parent_hws = (const struct clk_hw *[]){ &usb30_mock_utmi_clk_src.clkr.hw }, 2307 .num_parents = 1, 2308 .flags = CLK_SET_RATE_PARENT, 2309 .ops = &clk_branch2_ops, 2310 }, 2311 }, 2312 }; 2313 2314 static struct clk_branch gcc_usb30_sleep_clk = { 2315 .halt_reg = 0x03cc, 2316 .clkr = { 2317 .enable_reg = 0x03cc, 2318 .enable_mask = BIT(0), 2319 .hw.init = &(struct clk_init_data){ 2320 .name = "gcc_usb30_sleep_clk", 2321 .parent_data = &(const struct clk_parent_data){ 2322 .fw_name = "sleep", 2323 .name = "sleep" 2324 }, 2325 .num_parents = 1, 2326 .ops = &clk_branch2_ops, 2327 }, 2328 }, 2329 }; 2330 2331 static struct clk_branch gcc_usb3_phy_aux_clk = { 2332 .halt_reg = 0x1408, 2333 .clkr = { 2334 .enable_reg = 0x1408, 2335 .enable_mask = BIT(0), 2336 .hw.init = &(struct clk_init_data){ 2337 .name = "gcc_usb3_phy_aux_clk", 2338 .parent_hws = (const struct clk_hw *[]){ &usb3_phy_aux_clk_src.clkr.hw }, 2339 .num_parents = 1, 2340 .flags = CLK_SET_RATE_PARENT, 2341 .ops = &clk_branch2_ops, 2342 }, 2343 }, 2344 }; 2345 2346 static struct clk_branch gcc_usb3_phy_pipe_clk = { 2347 .halt_reg = 0x140c, 2348 .halt_check = BRANCH_HALT_SKIP, 2349 .clkr = { 2350 .enable_reg = 0x140c, 2351 .enable_mask = BIT(0), 2352 .hw.init = &(struct clk_init_data){ 2353 .name = "gcc_usb3_phy_pipe_clk", 2354 .ops = &clk_branch2_ops, 2355 }, 2356 }, 2357 }; 2358 2359 static struct clk_branch gcc_usb_hs_ahb_clk = { 2360 .halt_reg = 0x0488, 2361 .clkr = { 2362 .enable_reg = 0x0488, 2363 .enable_mask = BIT(0), 2364 .hw.init = &(struct clk_init_data){ 2365 .name = "gcc_usb_hs_ahb_clk", 2366 .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw }, 2367 .num_parents = 1, 2368 .ops = &clk_branch2_ops, 2369 }, 2370 }, 2371 }; 2372 2373 static struct clk_branch gcc_usb_hs_system_clk = { 2374 .halt_reg = 0x0484, 2375 .clkr = { 2376 .enable_reg = 0x0484, 2377 .enable_mask = BIT(0), 2378 .hw.init = &(struct clk_init_data){ 2379 .name = "gcc_usb_hs_system_clk", 2380 .parent_hws = (const struct clk_hw *[]){ &usb_hs_system_clk_src.clkr.hw }, 2381 .num_parents = 1, 2382 .flags = CLK_SET_RATE_PARENT, 2383 .ops = &clk_branch2_ops, 2384 }, 2385 }, 2386 }; 2387 2388 static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = { 2389 .halt_reg = 0x1a84, 2390 .clkr = { 2391 .enable_reg = 0x1a84, 2392 .enable_mask = BIT(0), 2393 .hw.init = &(struct clk_init_data){ 2394 .name = "gcc_usb_phy_cfg_ahb2phy_clk", 2395 .ops = &clk_branch2_ops, 2396 }, 2397 }, 2398 }; 2399 2400 static struct clk_branch gpll0_out_mmsscc = { 2401 .halt_check = BRANCH_HALT_DELAY, 2402 .clkr = { 2403 .enable_reg = 0x1484, 2404 .enable_mask = BIT(26), 2405 .hw.init = &(struct clk_init_data){ 2406 .name = "gpll0_out_mmsscc", 2407 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw }, 2408 .num_parents = 1, 2409 .ops = &clk_branch2_ops, 2410 }, 2411 }, 2412 }; 2413 2414 static struct clk_branch gpll0_out_msscc = { 2415 .halt_check = BRANCH_HALT_DELAY, 2416 .clkr = { 2417 .enable_reg = 0x1484, 2418 .enable_mask = BIT(27), 2419 .hw.init = &(struct clk_init_data){ 2420 .name = "gpll0_out_msscc", 2421 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw }, 2422 .num_parents = 1, 2423 .ops = &clk_branch2_ops, 2424 }, 2425 }, 2426 }; 2427 2428 static struct clk_branch pcie_0_phy_ldo = { 2429 .halt_reg = 0x1e00, 2430 .halt_check = BRANCH_HALT_SKIP, 2431 .clkr = { 2432 .enable_reg = 0x1E00, 2433 .enable_mask = BIT(0), 2434 .hw.init = &(struct clk_init_data){ 2435 .name = "pcie_0_phy_ldo", 2436 .ops = &clk_branch2_ops, 2437 }, 2438 }, 2439 }; 2440 2441 static struct clk_branch pcie_1_phy_ldo = { 2442 .halt_reg = 0x1e04, 2443 .halt_check = BRANCH_HALT_SKIP, 2444 .clkr = { 2445 .enable_reg = 0x1E04, 2446 .enable_mask = BIT(0), 2447 .hw.init = &(struct clk_init_data){ 2448 .name = "pcie_1_phy_ldo", 2449 .ops = &clk_branch2_ops, 2450 }, 2451 }, 2452 }; 2453 2454 static struct clk_branch ufs_phy_ldo = { 2455 .halt_reg = 0x1e0c, 2456 .halt_check = BRANCH_HALT_SKIP, 2457 .clkr = { 2458 .enable_reg = 0x1E0C, 2459 .enable_mask = BIT(0), 2460 .hw.init = &(struct clk_init_data){ 2461 .name = "ufs_phy_ldo", 2462 .ops = &clk_branch2_ops, 2463 }, 2464 }, 2465 }; 2466 2467 static struct clk_branch usb_ss_phy_ldo = { 2468 .halt_reg = 0x1e08, 2469 .halt_check = BRANCH_HALT_SKIP, 2470 .clkr = { 2471 .enable_reg = 0x1E08, 2472 .enable_mask = BIT(0), 2473 .hw.init = &(struct clk_init_data){ 2474 .name = "usb_ss_phy_ldo", 2475 .ops = &clk_branch2_ops, 2476 }, 2477 }, 2478 }; 2479 2480 static struct clk_branch gcc_boot_rom_ahb_clk = { 2481 .halt_reg = 0x0e04, 2482 .halt_check = BRANCH_HALT_VOTED, 2483 .hwcg_reg = 0x0e04, 2484 .hwcg_bit = 1, 2485 .clkr = { 2486 .enable_reg = 0x1484, 2487 .enable_mask = BIT(10), 2488 .hw.init = &(struct clk_init_data){ 2489 .name = "gcc_boot_rom_ahb_clk", 2490 .parent_hws = (const struct clk_hw *[]){ &config_noc_clk_src.clkr.hw }, 2491 .num_parents = 1, 2492 .ops = &clk_branch2_ops, 2493 }, 2494 }, 2495 }; 2496 2497 static struct clk_branch gcc_prng_ahb_clk = { 2498 .halt_reg = 0x0d04, 2499 .halt_check = BRANCH_HALT_VOTED, 2500 .clkr = { 2501 .enable_reg = 0x1484, 2502 .enable_mask = BIT(13), 2503 .hw.init = &(struct clk_init_data){ 2504 .name = "gcc_prng_ahb_clk", 2505 .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw }, 2506 .num_parents = 1, 2507 .ops = &clk_branch2_ops, 2508 }, 2509 }, 2510 }; 2511 2512 static struct gdsc pcie_0_gdsc = { 2513 .gdscr = 0x1ac4, 2514 .pd = { 2515 .name = "pcie_0", 2516 }, 2517 .pwrsts = PWRSTS_OFF_ON, 2518 }; 2519 2520 static struct gdsc pcie_1_gdsc = { 2521 .gdscr = 0x1b44, 2522 .pd = { 2523 .name = "pcie_1", 2524 }, 2525 .pwrsts = PWRSTS_OFF_ON, 2526 }; 2527 2528 static struct gdsc usb30_gdsc = { 2529 .gdscr = 0x3c4, 2530 .pd = { 2531 .name = "usb30", 2532 }, 2533 .pwrsts = PWRSTS_OFF_ON, 2534 }; 2535 2536 static struct gdsc ufs_gdsc = { 2537 .gdscr = 0x1d44, 2538 .pd = { 2539 .name = "ufs", 2540 }, 2541 .pwrsts = PWRSTS_OFF_ON, 2542 }; 2543 2544 static struct clk_regmap *gcc_msm8994_clocks[] = { 2545 [GPLL0_EARLY] = &gpll0_early.clkr, 2546 [GPLL0] = &gpll0.clkr, 2547 [GPLL4_EARLY] = &gpll4_early.clkr, 2548 [GPLL4] = &gpll4.clkr, 2549 [CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr, 2550 [PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr, 2551 [SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr, 2552 [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr, 2553 [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr, 2554 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr, 2555 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr, 2556 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr, 2557 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr, 2558 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr, 2559 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr, 2560 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr, 2561 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr, 2562 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr, 2563 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr, 2564 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr, 2565 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr, 2566 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr, 2567 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr, 2568 [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr, 2569 [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr, 2570 [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr, 2571 [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr, 2572 [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr, 2573 [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr, 2574 [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr, 2575 [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr, 2576 [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr, 2577 [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr, 2578 [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr, 2579 [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr, 2580 [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr, 2581 [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr, 2582 [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr, 2583 [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr, 2584 [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr, 2585 [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr, 2586 [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr, 2587 [BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr, 2588 [BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr, 2589 [BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr, 2590 [GP1_CLK_SRC] = &gp1_clk_src.clkr, 2591 [GP2_CLK_SRC] = &gp2_clk_src.clkr, 2592 [GP3_CLK_SRC] = &gp3_clk_src.clkr, 2593 [PCIE_0_AUX_CLK_SRC] = &pcie_0_aux_clk_src.clkr, 2594 [PCIE_0_PIPE_CLK_SRC] = &pcie_0_pipe_clk_src.clkr, 2595 [PCIE_1_AUX_CLK_SRC] = &pcie_1_aux_clk_src.clkr, 2596 [PCIE_1_PIPE_CLK_SRC] = &pcie_1_pipe_clk_src.clkr, 2597 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr, 2598 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr, 2599 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr, 2600 [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr, 2601 [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr, 2602 [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr, 2603 [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr, 2604 [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr, 2605 [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr, 2606 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr, 2607 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr, 2608 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr, 2609 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr, 2610 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr, 2611 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr, 2612 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr, 2613 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr, 2614 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr, 2615 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr, 2616 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr, 2617 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr, 2618 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr, 2619 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, 2620 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr, 2621 [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr, 2622 [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr, 2623 [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr, 2624 [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr, 2625 [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr, 2626 [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr, 2627 [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr, 2628 [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr, 2629 [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr, 2630 [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr, 2631 [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr, 2632 [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr, 2633 [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr, 2634 [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr, 2635 [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr, 2636 [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr, 2637 [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr, 2638 [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr, 2639 [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr, 2640 [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr, 2641 [GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr, 2642 [GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr, 2643 [GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr, 2644 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 2645 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 2646 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 2647 [GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr, 2648 [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr, 2649 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, 2650 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, 2651 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, 2652 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, 2653 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, 2654 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr, 2655 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr, 2656 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr, 2657 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr, 2658 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr, 2659 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 2660 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 2661 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, 2662 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, 2663 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 2664 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 2665 [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr, 2666 [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr, 2667 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, 2668 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, 2669 [GCC_SYS_NOC_UFS_AXI_CLK] = &gcc_sys_noc_ufs_axi_clk.clkr, 2670 [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr, 2671 [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr, 2672 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr, 2673 [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr, 2674 [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr, 2675 [GCC_UFS_RX_CFG_CLK] = &gcc_ufs_rx_cfg_clk.clkr, 2676 [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr, 2677 [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr, 2678 [GCC_UFS_TX_CFG_CLK] = &gcc_ufs_tx_cfg_clk.clkr, 2679 [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr, 2680 [GCC_UFS_TX_SYMBOL_1_CLK] = &gcc_ufs_tx_symbol_1_clk.clkr, 2681 [GCC_USB2_HS_PHY_SLEEP_CLK] = &gcc_usb2_hs_phy_sleep_clk.clkr, 2682 [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr, 2683 [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr, 2684 [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr, 2685 [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr, 2686 [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr, 2687 [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr, 2688 [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr, 2689 [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr, 2690 [GPLL0_OUT_MMSSCC] = &gpll0_out_mmsscc.clkr, 2691 [GPLL0_OUT_MSSCC] = &gpll0_out_msscc.clkr, 2692 [PCIE_0_PHY_LDO] = &pcie_0_phy_ldo.clkr, 2693 [PCIE_1_PHY_LDO] = &pcie_1_phy_ldo.clkr, 2694 [UFS_PHY_LDO] = &ufs_phy_ldo.clkr, 2695 [USB_SS_PHY_LDO] = &usb_ss_phy_ldo.clkr, 2696 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 2697 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, 2698 }; 2699 2700 static struct gdsc *gcc_msm8994_gdscs[] = { 2701 /* This GDSC does not exist, but ABI has to remain intact */ 2702 [PCIE_GDSC] = NULL, 2703 [PCIE_0_GDSC] = &pcie_0_gdsc, 2704 [PCIE_1_GDSC] = &pcie_1_gdsc, 2705 [USB30_GDSC] = &usb30_gdsc, 2706 [UFS_GDSC] = &ufs_gdsc, 2707 }; 2708 2709 static const struct qcom_reset_map gcc_msm8994_resets[] = { 2710 [USB3_PHY_RESET] = { 0x1400 }, 2711 [USB3PHY_PHY_RESET] = { 0x1404 }, 2712 [MSS_RESET] = { 0x1680 }, 2713 [PCIE_PHY_0_RESET] = { 0x1b18 }, 2714 [PCIE_PHY_1_RESET] = { 0x1b98 }, 2715 [QUSB2_PHY_RESET] = { 0x04b8 }, 2716 }; 2717 2718 static const struct regmap_config gcc_msm8994_regmap_config = { 2719 .reg_bits = 32, 2720 .reg_stride = 4, 2721 .val_bits = 32, 2722 .max_register = 0x2000, 2723 .fast_io = true, 2724 }; 2725 2726 static const struct qcom_cc_desc gcc_msm8994_desc = { 2727 .config = &gcc_msm8994_regmap_config, 2728 .clks = gcc_msm8994_clocks, 2729 .num_clks = ARRAY_SIZE(gcc_msm8994_clocks), 2730 .resets = gcc_msm8994_resets, 2731 .num_resets = ARRAY_SIZE(gcc_msm8994_resets), 2732 .gdscs = gcc_msm8994_gdscs, 2733 .num_gdscs = ARRAY_SIZE(gcc_msm8994_gdscs), 2734 }; 2735 2736 static const struct of_device_id gcc_msm8994_match_table[] = { 2737 { .compatible = "qcom,gcc-msm8992" }, 2738 { .compatible = "qcom,gcc-msm8994" }, /* V2 and V2.1 */ 2739 {} 2740 }; 2741 MODULE_DEVICE_TABLE(of, gcc_msm8994_match_table); 2742 2743 static int gcc_msm8994_probe(struct platform_device *pdev) 2744 { 2745 if (of_device_is_compatible(pdev->dev.of_node, "qcom,gcc-msm8992")) { 2746 /* MSM8992 features less clocks and some have different freq tables */ 2747 gcc_msm8994_desc.clks[UFS_AXI_CLK_SRC] = NULL; 2748 gcc_msm8994_desc.clks[GCC_LPASS_Q6_AXI_CLK] = NULL; 2749 gcc_msm8994_desc.clks[UFS_PHY_LDO] = NULL; 2750 gcc_msm8994_desc.clks[GCC_UFS_AHB_CLK] = NULL; 2751 gcc_msm8994_desc.clks[GCC_UFS_AXI_CLK] = NULL; 2752 gcc_msm8994_desc.clks[GCC_UFS_RX_CFG_CLK] = NULL; 2753 gcc_msm8994_desc.clks[GCC_UFS_RX_SYMBOL_0_CLK] = NULL; 2754 gcc_msm8994_desc.clks[GCC_UFS_RX_SYMBOL_1_CLK] = NULL; 2755 gcc_msm8994_desc.clks[GCC_UFS_TX_CFG_CLK] = NULL; 2756 gcc_msm8994_desc.clks[GCC_UFS_TX_SYMBOL_0_CLK] = NULL; 2757 gcc_msm8994_desc.clks[GCC_UFS_TX_SYMBOL_1_CLK] = NULL; 2758 2759 sdcc1_apps_clk_src.freq_tbl = ftbl_sdcc1_apps_clk_src_8992; 2760 blsp1_qup1_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992; 2761 blsp1_qup2_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992; 2762 blsp1_qup3_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992; 2763 blsp1_qup4_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992; 2764 blsp1_qup5_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992; 2765 blsp1_qup6_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992; 2766 blsp2_qup1_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992; 2767 blsp2_qup2_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992; 2768 blsp2_qup3_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992; 2769 blsp2_qup4_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992; 2770 blsp2_qup5_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992; 2771 blsp2_qup6_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992; 2772 2773 /* 2774 * Some 8992 boards might *possibly* use 2775 * PCIe1 clocks and controller, but it's not 2776 * standard and they should be disabled otherwise. 2777 */ 2778 gcc_msm8994_desc.clks[PCIE_1_AUX_CLK_SRC] = NULL; 2779 gcc_msm8994_desc.clks[PCIE_1_PIPE_CLK_SRC] = NULL; 2780 gcc_msm8994_desc.clks[PCIE_1_PHY_LDO] = NULL; 2781 gcc_msm8994_desc.clks[GCC_PCIE_1_AUX_CLK] = NULL; 2782 gcc_msm8994_desc.clks[GCC_PCIE_1_CFG_AHB_CLK] = NULL; 2783 gcc_msm8994_desc.clks[GCC_PCIE_1_MSTR_AXI_CLK] = NULL; 2784 gcc_msm8994_desc.clks[GCC_PCIE_1_PIPE_CLK] = NULL; 2785 gcc_msm8994_desc.clks[GCC_PCIE_1_SLV_AXI_CLK] = NULL; 2786 gcc_msm8994_desc.clks[GCC_SYS_NOC_UFS_AXI_CLK] = NULL; 2787 } 2788 2789 return qcom_cc_probe(pdev, &gcc_msm8994_desc); 2790 } 2791 2792 static struct platform_driver gcc_msm8994_driver = { 2793 .probe = gcc_msm8994_probe, 2794 .driver = { 2795 .name = "gcc-msm8994", 2796 .of_match_table = gcc_msm8994_match_table, 2797 }, 2798 }; 2799 2800 static int __init gcc_msm8994_init(void) 2801 { 2802 return platform_driver_register(&gcc_msm8994_driver); 2803 } 2804 core_initcall(gcc_msm8994_init); 2805 2806 static void __exit gcc_msm8994_exit(void) 2807 { 2808 platform_driver_unregister(&gcc_msm8994_driver); 2809 } 2810 module_exit(gcc_msm8994_exit); 2811 2812 MODULE_DESCRIPTION("Qualcomm GCC MSM8994 Driver"); 2813 MODULE_LICENSE("GPL v2"); 2814 MODULE_ALIAS("platform:gcc-msm8994"); 2815