1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. 3 */ 4 5 #include <linux/kernel.h> 6 #include <linux/init.h> 7 #include <linux/err.h> 8 #include <linux/ctype.h> 9 #include <linux/io.h> 10 #include <linux/of.h> 11 #include <linux/platform_device.h> 12 #include <linux/module.h> 13 #include <linux/regmap.h> 14 15 #include <dt-bindings/clock/qcom,gcc-msm8994.h> 16 17 #include "common.h" 18 #include "clk-regmap.h" 19 #include "clk-alpha-pll.h" 20 #include "clk-rcg.h" 21 #include "clk-branch.h" 22 #include "reset.h" 23 #include "gdsc.h" 24 25 enum { 26 P_XO, 27 P_GPLL0, 28 P_GPLL4, 29 }; 30 31 static struct clk_alpha_pll gpll0_early = { 32 .offset = 0, 33 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 34 .clkr = { 35 .enable_reg = 0x1480, 36 .enable_mask = BIT(0), 37 .hw.init = &(struct clk_init_data){ 38 .name = "gpll0_early", 39 .parent_data = &(const struct clk_parent_data){ 40 .fw_name = "xo", 41 }, 42 .num_parents = 1, 43 .ops = &clk_alpha_pll_ops, 44 }, 45 }, 46 }; 47 48 static struct clk_alpha_pll_postdiv gpll0 = { 49 .offset = 0, 50 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 51 .clkr.hw.init = &(struct clk_init_data){ 52 .name = "gpll0", 53 .parent_names = (const char *[]) { "gpll0_early" }, 54 .num_parents = 1, 55 .ops = &clk_alpha_pll_postdiv_ops, 56 }, 57 }; 58 59 static struct clk_alpha_pll gpll4_early = { 60 .offset = 0x1dc0, 61 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 62 .clkr = { 63 .enable_reg = 0x1480, 64 .enable_mask = BIT(4), 65 .hw.init = &(struct clk_init_data){ 66 .name = "gpll4_early", 67 .parent_data = &(const struct clk_parent_data){ 68 .fw_name = "xo", 69 }, 70 .num_parents = 1, 71 .ops = &clk_alpha_pll_ops, 72 }, 73 }, 74 }; 75 76 static struct clk_alpha_pll_postdiv gpll4 = { 77 .offset = 0x1dc0, 78 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 79 .clkr.hw.init = &(struct clk_init_data){ 80 .name = "gpll4", 81 .parent_names = (const char *[]) { "gpll4_early" }, 82 .num_parents = 1, 83 .ops = &clk_alpha_pll_postdiv_ops, 84 }, 85 }; 86 87 static const struct parent_map gcc_xo_gpll0_map[] = { 88 { P_XO, 0 }, 89 { P_GPLL0, 1 }, 90 }; 91 92 static const struct clk_parent_data gcc_xo_gpll0[] = { 93 { .fw_name = "xo" }, 94 { .hw = &gpll0.clkr.hw }, 95 }; 96 97 static const struct parent_map gcc_xo_gpll0_gpll4_map[] = { 98 { P_XO, 0 }, 99 { P_GPLL0, 1 }, 100 { P_GPLL4, 5 }, 101 }; 102 103 static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = { 104 { .fw_name = "xo" }, 105 { .hw = &gpll0.clkr.hw }, 106 { .hw = &gpll4.clkr.hw }, 107 }; 108 109 static struct clk_rcg2 system_noc_clk_src = { 110 .cmd_rcgr = 0x0120, 111 .hid_width = 5, 112 .parent_map = gcc_xo_gpll0_map, 113 .clkr.hw.init = &(struct clk_init_data){ 114 .name = "system_noc_clk_src", 115 .parent_data = gcc_xo_gpll0, 116 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 117 .ops = &clk_rcg2_ops, 118 }, 119 }; 120 121 static struct clk_rcg2 config_noc_clk_src = { 122 .cmd_rcgr = 0x0150, 123 .hid_width = 5, 124 .parent_map = gcc_xo_gpll0_map, 125 .clkr.hw.init = &(struct clk_init_data){ 126 .name = "config_noc_clk_src", 127 .parent_data = gcc_xo_gpll0, 128 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 129 .ops = &clk_rcg2_ops, 130 }, 131 }; 132 133 static struct clk_rcg2 periph_noc_clk_src = { 134 .cmd_rcgr = 0x0190, 135 .hid_width = 5, 136 .parent_map = gcc_xo_gpll0_map, 137 .clkr.hw.init = &(struct clk_init_data){ 138 .name = "periph_noc_clk_src", 139 .parent_data = gcc_xo_gpll0, 140 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 141 .ops = &clk_rcg2_ops, 142 }, 143 }; 144 145 static struct freq_tbl ftbl_ufs_axi_clk_src[] = { 146 F(50000000, P_GPLL0, 12, 0, 0), 147 F(100000000, P_GPLL0, 6, 0, 0), 148 F(150000000, P_GPLL0, 4, 0, 0), 149 F(171430000, P_GPLL0, 3.5, 0, 0), 150 F(200000000, P_GPLL0, 3, 0, 0), 151 F(240000000, P_GPLL0, 2.5, 0, 0), 152 { } 153 }; 154 155 static struct clk_rcg2 ufs_axi_clk_src = { 156 .cmd_rcgr = 0x1d68, 157 .mnd_width = 8, 158 .hid_width = 5, 159 .parent_map = gcc_xo_gpll0_map, 160 .freq_tbl = ftbl_ufs_axi_clk_src, 161 .clkr.hw.init = &(struct clk_init_data){ 162 .name = "ufs_axi_clk_src", 163 .parent_data = gcc_xo_gpll0, 164 .num_parents = 2, 165 .ops = &clk_rcg2_ops, 166 }, 167 }; 168 169 static struct freq_tbl ftbl_usb30_master_clk_src[] = { 170 F(19200000, P_XO, 1, 0, 0), 171 F(125000000, P_GPLL0, 1, 5, 24), 172 { } 173 }; 174 175 static struct clk_rcg2 usb30_master_clk_src = { 176 .cmd_rcgr = 0x03d4, 177 .mnd_width = 8, 178 .hid_width = 5, 179 .parent_map = gcc_xo_gpll0_map, 180 .freq_tbl = ftbl_usb30_master_clk_src, 181 .clkr.hw.init = &(struct clk_init_data){ 182 .name = "usb30_master_clk_src", 183 .parent_data = gcc_xo_gpll0, 184 .num_parents = 2, 185 .ops = &clk_rcg2_ops, 186 }, 187 }; 188 189 static struct freq_tbl ftbl_blsp_i2c_apps_clk_src[] = { 190 F(19200000, P_XO, 1, 0, 0), 191 F(50000000, P_GPLL0, 12, 0, 0), 192 { } 193 }; 194 195 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { 196 .cmd_rcgr = 0x0660, 197 .hid_width = 5, 198 .parent_map = gcc_xo_gpll0_map, 199 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 200 .clkr.hw.init = &(struct clk_init_data){ 201 .name = "blsp1_qup1_i2c_apps_clk_src", 202 .parent_data = gcc_xo_gpll0, 203 .num_parents = 2, 204 .ops = &clk_rcg2_ops, 205 }, 206 }; 207 208 static struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = { 209 F(960000, P_XO, 10, 1, 2), 210 F(4800000, P_XO, 4, 0, 0), 211 F(9600000, P_XO, 2, 0, 0), 212 F(15000000, P_GPLL0, 10, 1, 4), 213 F(19200000, P_XO, 1, 0, 0), 214 F(24000000, P_GPLL0, 12.5, 1, 2), 215 F(25000000, P_GPLL0, 12, 1, 2), 216 F(48000000, P_GPLL0, 12.5, 0, 0), 217 F(50000000, P_GPLL0, 12, 0, 0), 218 { } 219 }; 220 221 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { 222 .cmd_rcgr = 0x064c, 223 .mnd_width = 8, 224 .hid_width = 5, 225 .parent_map = gcc_xo_gpll0_map, 226 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 227 .clkr.hw.init = &(struct clk_init_data){ 228 .name = "blsp1_qup1_spi_apps_clk_src", 229 .parent_data = gcc_xo_gpll0, 230 .num_parents = 2, 231 .ops = &clk_rcg2_ops, 232 }, 233 }; 234 235 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { 236 .cmd_rcgr = 0x06e0, 237 .hid_width = 5, 238 .parent_map = gcc_xo_gpll0_map, 239 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 240 .clkr.hw.init = &(struct clk_init_data){ 241 .name = "blsp1_qup2_i2c_apps_clk_src", 242 .parent_data = gcc_xo_gpll0, 243 .num_parents = 2, 244 .ops = &clk_rcg2_ops, 245 }, 246 }; 247 248 static struct freq_tbl ftbl_blsp1_qup2_spi_apps_clk_src[] = { 249 F(960000, P_XO, 10, 1, 2), 250 F(4800000, P_XO, 4, 0, 0), 251 F(9600000, P_XO, 2, 0, 0), 252 F(15000000, P_GPLL0, 10, 1, 4), 253 F(19200000, P_XO, 1, 0, 0), 254 F(24000000, P_GPLL0, 12.5, 1, 2), 255 F(25000000, P_GPLL0, 12, 1, 2), 256 F(42860000, P_GPLL0, 14, 0, 0), 257 F(46150000, P_GPLL0, 13, 0, 0), 258 { } 259 }; 260 261 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { 262 .cmd_rcgr = 0x06cc, 263 .mnd_width = 8, 264 .hid_width = 5, 265 .parent_map = gcc_xo_gpll0_map, 266 .freq_tbl = ftbl_blsp1_qup2_spi_apps_clk_src, 267 .clkr.hw.init = &(struct clk_init_data){ 268 .name = "blsp1_qup2_spi_apps_clk_src", 269 .parent_data = gcc_xo_gpll0, 270 .num_parents = 2, 271 .ops = &clk_rcg2_ops, 272 }, 273 }; 274 275 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { 276 .cmd_rcgr = 0x0760, 277 .hid_width = 5, 278 .parent_map = gcc_xo_gpll0_map, 279 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 280 .clkr.hw.init = &(struct clk_init_data){ 281 .name = "blsp1_qup3_i2c_apps_clk_src", 282 .parent_data = gcc_xo_gpll0, 283 .num_parents = 2, 284 .ops = &clk_rcg2_ops, 285 }, 286 }; 287 288 static struct freq_tbl ftbl_blsp1_qup3_4_spi_apps_clk_src[] = { 289 F(960000, P_XO, 10, 1, 2), 290 F(4800000, P_XO, 4, 0, 0), 291 F(9600000, P_XO, 2, 0, 0), 292 F(15000000, P_GPLL0, 10, 1, 4), 293 F(19200000, P_XO, 1, 0, 0), 294 F(24000000, P_GPLL0, 12.5, 1, 2), 295 F(25000000, P_GPLL0, 12, 1, 2), 296 F(42860000, P_GPLL0, 14, 0, 0), 297 F(44440000, P_GPLL0, 13.5, 0, 0), 298 { } 299 }; 300 301 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { 302 .cmd_rcgr = 0x074c, 303 .mnd_width = 8, 304 .hid_width = 5, 305 .parent_map = gcc_xo_gpll0_map, 306 .freq_tbl = ftbl_blsp1_qup3_4_spi_apps_clk_src, 307 .clkr.hw.init = &(struct clk_init_data){ 308 .name = "blsp1_qup3_spi_apps_clk_src", 309 .parent_data = gcc_xo_gpll0, 310 .num_parents = 2, 311 .ops = &clk_rcg2_ops, 312 }, 313 }; 314 315 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { 316 .cmd_rcgr = 0x07e0, 317 .hid_width = 5, 318 .parent_map = gcc_xo_gpll0_map, 319 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 320 .clkr.hw.init = &(struct clk_init_data){ 321 .name = "blsp1_qup4_i2c_apps_clk_src", 322 .parent_data = gcc_xo_gpll0, 323 .num_parents = 2, 324 .ops = &clk_rcg2_ops, 325 }, 326 }; 327 328 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { 329 .cmd_rcgr = 0x07cc, 330 .mnd_width = 8, 331 .hid_width = 5, 332 .parent_map = gcc_xo_gpll0_map, 333 .freq_tbl = ftbl_blsp1_qup3_4_spi_apps_clk_src, 334 .clkr.hw.init = &(struct clk_init_data){ 335 .name = "blsp1_qup4_spi_apps_clk_src", 336 .parent_data = gcc_xo_gpll0, 337 .num_parents = 2, 338 .ops = &clk_rcg2_ops, 339 }, 340 }; 341 342 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = { 343 .cmd_rcgr = 0x0860, 344 .hid_width = 5, 345 .parent_map = gcc_xo_gpll0_map, 346 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 347 .clkr.hw.init = &(struct clk_init_data){ 348 .name = "blsp1_qup5_i2c_apps_clk_src", 349 .parent_data = gcc_xo_gpll0, 350 .num_parents = 2, 351 .ops = &clk_rcg2_ops, 352 }, 353 }; 354 355 static struct freq_tbl ftbl_blsp1_qup5_spi_apps_clk_src[] = { 356 F(960000, P_XO, 10, 1, 2), 357 F(4800000, P_XO, 4, 0, 0), 358 F(9600000, P_XO, 2, 0, 0), 359 F(15000000, P_GPLL0, 10, 1, 4), 360 F(19200000, P_XO, 1, 0, 0), 361 F(24000000, P_GPLL0, 12.5, 1, 2), 362 F(25000000, P_GPLL0, 12, 1, 2), 363 F(40000000, P_GPLL0, 15, 0, 0), 364 F(42860000, P_GPLL0, 14, 0, 0), 365 { } 366 }; 367 368 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = { 369 .cmd_rcgr = 0x084c, 370 .mnd_width = 8, 371 .hid_width = 5, 372 .parent_map = gcc_xo_gpll0_map, 373 .freq_tbl = ftbl_blsp1_qup5_spi_apps_clk_src, 374 .clkr.hw.init = &(struct clk_init_data){ 375 .name = "blsp1_qup5_spi_apps_clk_src", 376 .parent_data = gcc_xo_gpll0, 377 .num_parents = 2, 378 .ops = &clk_rcg2_ops, 379 }, 380 }; 381 382 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = { 383 .cmd_rcgr = 0x08e0, 384 .hid_width = 5, 385 .parent_map = gcc_xo_gpll0_map, 386 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 387 .clkr.hw.init = &(struct clk_init_data){ 388 .name = "blsp1_qup6_i2c_apps_clk_src", 389 .parent_data = gcc_xo_gpll0, 390 .num_parents = 2, 391 .ops = &clk_rcg2_ops, 392 }, 393 }; 394 395 static struct freq_tbl ftbl_blsp1_qup6_spi_apps_clk_src[] = { 396 F(960000, P_XO, 10, 1, 2), 397 F(4800000, P_XO, 4, 0, 0), 398 F(9600000, P_XO, 2, 0, 0), 399 F(15000000, P_GPLL0, 10, 1, 4), 400 F(19200000, P_XO, 1, 0, 0), 401 F(24000000, P_GPLL0, 12.5, 1, 2), 402 F(27906976, P_GPLL0, 1, 2, 43), 403 F(41380000, P_GPLL0, 15, 0, 0), 404 F(42860000, P_GPLL0, 14, 0, 0), 405 { } 406 }; 407 408 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = { 409 .cmd_rcgr = 0x08cc, 410 .mnd_width = 8, 411 .hid_width = 5, 412 .parent_map = gcc_xo_gpll0_map, 413 .freq_tbl = ftbl_blsp1_qup6_spi_apps_clk_src, 414 .clkr.hw.init = &(struct clk_init_data){ 415 .name = "blsp1_qup6_spi_apps_clk_src", 416 .parent_data = gcc_xo_gpll0, 417 .num_parents = 2, 418 .ops = &clk_rcg2_ops, 419 }, 420 }; 421 422 static struct freq_tbl ftbl_blsp_uart_apps_clk_src[] = { 423 F(3686400, P_GPLL0, 1, 96, 15625), 424 F(7372800, P_GPLL0, 1, 192, 15625), 425 F(14745600, P_GPLL0, 1, 384, 15625), 426 F(16000000, P_GPLL0, 5, 2, 15), 427 F(19200000, P_XO, 1, 0, 0), 428 F(24000000, P_GPLL0, 5, 1, 5), 429 F(32000000, P_GPLL0, 1, 4, 75), 430 F(40000000, P_GPLL0, 15, 0, 0), 431 F(46400000, P_GPLL0, 1, 29, 375), 432 F(48000000, P_GPLL0, 12.5, 0, 0), 433 F(51200000, P_GPLL0, 1, 32, 375), 434 F(56000000, P_GPLL0, 1, 7, 75), 435 F(58982400, P_GPLL0, 1, 1536, 15625), 436 F(60000000, P_GPLL0, 10, 0, 0), 437 F(63160000, P_GPLL0, 9.5, 0, 0), 438 { } 439 }; 440 441 static struct clk_rcg2 blsp1_uart1_apps_clk_src = { 442 .cmd_rcgr = 0x068c, 443 .mnd_width = 16, 444 .hid_width = 5, 445 .parent_map = gcc_xo_gpll0_map, 446 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 447 .clkr.hw.init = &(struct clk_init_data){ 448 .name = "blsp1_uart1_apps_clk_src", 449 .parent_data = gcc_xo_gpll0, 450 .num_parents = 2, 451 .ops = &clk_rcg2_ops, 452 }, 453 }; 454 455 static struct clk_rcg2 blsp1_uart2_apps_clk_src = { 456 .cmd_rcgr = 0x070c, 457 .mnd_width = 16, 458 .hid_width = 5, 459 .parent_map = gcc_xo_gpll0_map, 460 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 461 .clkr.hw.init = &(struct clk_init_data){ 462 .name = "blsp1_uart2_apps_clk_src", 463 .parent_data = gcc_xo_gpll0, 464 .num_parents = 2, 465 .ops = &clk_rcg2_ops, 466 }, 467 }; 468 469 static struct clk_rcg2 blsp1_uart3_apps_clk_src = { 470 .cmd_rcgr = 0x078c, 471 .mnd_width = 16, 472 .hid_width = 5, 473 .parent_map = gcc_xo_gpll0_map, 474 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 475 .clkr.hw.init = &(struct clk_init_data){ 476 .name = "blsp1_uart3_apps_clk_src", 477 .parent_data = gcc_xo_gpll0, 478 .num_parents = 2, 479 .ops = &clk_rcg2_ops, 480 }, 481 }; 482 483 static struct clk_rcg2 blsp1_uart4_apps_clk_src = { 484 .cmd_rcgr = 0x080c, 485 .mnd_width = 16, 486 .hid_width = 5, 487 .parent_map = gcc_xo_gpll0_map, 488 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 489 .clkr.hw.init = &(struct clk_init_data){ 490 .name = "blsp1_uart4_apps_clk_src", 491 .parent_data = gcc_xo_gpll0, 492 .num_parents = 2, 493 .ops = &clk_rcg2_ops, 494 }, 495 }; 496 497 static struct clk_rcg2 blsp1_uart5_apps_clk_src = { 498 .cmd_rcgr = 0x088c, 499 .mnd_width = 16, 500 .hid_width = 5, 501 .parent_map = gcc_xo_gpll0_map, 502 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 503 .clkr.hw.init = &(struct clk_init_data){ 504 .name = "blsp1_uart5_apps_clk_src", 505 .parent_data = gcc_xo_gpll0, 506 .num_parents = 2, 507 .ops = &clk_rcg2_ops, 508 }, 509 }; 510 511 static struct clk_rcg2 blsp1_uart6_apps_clk_src = { 512 .cmd_rcgr = 0x090c, 513 .mnd_width = 16, 514 .hid_width = 5, 515 .parent_map = gcc_xo_gpll0_map, 516 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 517 .clkr.hw.init = &(struct clk_init_data){ 518 .name = "blsp1_uart6_apps_clk_src", 519 .parent_data = gcc_xo_gpll0, 520 .num_parents = 2, 521 .ops = &clk_rcg2_ops, 522 }, 523 }; 524 525 static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = { 526 .cmd_rcgr = 0x09a0, 527 .hid_width = 5, 528 .parent_map = gcc_xo_gpll0_map, 529 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 530 .clkr.hw.init = &(struct clk_init_data){ 531 .name = "blsp2_qup1_i2c_apps_clk_src", 532 .parent_data = gcc_xo_gpll0, 533 .num_parents = 2, 534 .ops = &clk_rcg2_ops, 535 }, 536 }; 537 538 static struct freq_tbl ftbl_blsp2_qup1_2_spi_apps_clk_src[] = { 539 F(960000, P_XO, 10, 1, 2), 540 F(4800000, P_XO, 4, 0, 0), 541 F(9600000, P_XO, 2, 0, 0), 542 F(15000000, P_GPLL0, 10, 1, 4), 543 F(19200000, P_XO, 1, 0, 0), 544 F(24000000, P_GPLL0, 12.5, 1, 2), 545 F(25000000, P_GPLL0, 12, 1, 2), 546 F(42860000, P_GPLL0, 14, 0, 0), 547 F(44440000, P_GPLL0, 13.5, 0, 0), 548 { } 549 }; 550 551 static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = { 552 .cmd_rcgr = 0x098c, 553 .mnd_width = 8, 554 .hid_width = 5, 555 .parent_map = gcc_xo_gpll0_map, 556 .freq_tbl = ftbl_blsp2_qup1_2_spi_apps_clk_src, 557 .clkr.hw.init = &(struct clk_init_data){ 558 .name = "blsp2_qup1_spi_apps_clk_src", 559 .parent_data = gcc_xo_gpll0, 560 .num_parents = 2, 561 .ops = &clk_rcg2_ops, 562 }, 563 }; 564 565 static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = { 566 .cmd_rcgr = 0x0a20, 567 .hid_width = 5, 568 .parent_map = gcc_xo_gpll0_map, 569 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 570 .clkr.hw.init = &(struct clk_init_data){ 571 .name = "blsp2_qup2_i2c_apps_clk_src", 572 .parent_data = gcc_xo_gpll0, 573 .num_parents = 2, 574 .ops = &clk_rcg2_ops, 575 }, 576 }; 577 578 static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = { 579 .cmd_rcgr = 0x0a0c, 580 .mnd_width = 8, 581 .hid_width = 5, 582 .parent_map = gcc_xo_gpll0_map, 583 .freq_tbl = ftbl_blsp2_qup1_2_spi_apps_clk_src, 584 .clkr.hw.init = &(struct clk_init_data){ 585 .name = "blsp2_qup2_spi_apps_clk_src", 586 .parent_data = gcc_xo_gpll0, 587 .num_parents = 2, 588 .ops = &clk_rcg2_ops, 589 }, 590 }; 591 592 static struct freq_tbl ftbl_blsp2_qup3_4_spi_apps_clk_src[] = { 593 F(960000, P_XO, 10, 1, 2), 594 F(4800000, P_XO, 4, 0, 0), 595 F(9600000, P_XO, 2, 0, 0), 596 F(15000000, P_GPLL0, 10, 1, 4), 597 F(19200000, P_XO, 1, 0, 0), 598 F(24000000, P_GPLL0, 12.5, 1, 2), 599 F(25000000, P_GPLL0, 12, 1, 2), 600 F(42860000, P_GPLL0, 14, 0, 0), 601 F(48000000, P_GPLL0, 12.5, 0, 0), 602 { } 603 }; 604 605 static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = { 606 .cmd_rcgr = 0x0aa0, 607 .hid_width = 5, 608 .parent_map = gcc_xo_gpll0_map, 609 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 610 .clkr.hw.init = &(struct clk_init_data){ 611 .name = "blsp2_qup3_i2c_apps_clk_src", 612 .parent_data = gcc_xo_gpll0, 613 .num_parents = 2, 614 .ops = &clk_rcg2_ops, 615 }, 616 }; 617 618 static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = { 619 .cmd_rcgr = 0x0a8c, 620 .mnd_width = 8, 621 .hid_width = 5, 622 .parent_map = gcc_xo_gpll0_map, 623 .freq_tbl = ftbl_blsp2_qup3_4_spi_apps_clk_src, 624 .clkr.hw.init = &(struct clk_init_data){ 625 .name = "blsp2_qup3_spi_apps_clk_src", 626 .parent_data = gcc_xo_gpll0, 627 .num_parents = 2, 628 .ops = &clk_rcg2_ops, 629 }, 630 }; 631 632 static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = { 633 .cmd_rcgr = 0x0b20, 634 .hid_width = 5, 635 .parent_map = gcc_xo_gpll0_map, 636 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 637 .clkr.hw.init = &(struct clk_init_data){ 638 .name = "blsp2_qup4_i2c_apps_clk_src", 639 .parent_data = gcc_xo_gpll0, 640 .num_parents = 2, 641 .ops = &clk_rcg2_ops, 642 }, 643 }; 644 645 static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = { 646 .cmd_rcgr = 0x0b0c, 647 .mnd_width = 8, 648 .hid_width = 5, 649 .parent_map = gcc_xo_gpll0_map, 650 .freq_tbl = ftbl_blsp2_qup3_4_spi_apps_clk_src, 651 .clkr.hw.init = &(struct clk_init_data){ 652 .name = "blsp2_qup4_spi_apps_clk_src", 653 .parent_data = gcc_xo_gpll0, 654 .num_parents = 2, 655 .ops = &clk_rcg2_ops, 656 }, 657 }; 658 659 static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = { 660 .cmd_rcgr = 0x0ba0, 661 .hid_width = 5, 662 .parent_map = gcc_xo_gpll0_map, 663 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 664 .clkr.hw.init = &(struct clk_init_data){ 665 .name = "blsp2_qup5_i2c_apps_clk_src", 666 .parent_data = gcc_xo_gpll0, 667 .num_parents = 2, 668 .ops = &clk_rcg2_ops, 669 }, 670 }; 671 672 static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = { 673 .cmd_rcgr = 0x0b8c, 674 .mnd_width = 8, 675 .hid_width = 5, 676 .parent_map = gcc_xo_gpll0_map, 677 /* BLSP1 QUP1 and BLSP2 QUP5 use the same freqs */ 678 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 679 .clkr.hw.init = &(struct clk_init_data){ 680 .name = "blsp2_qup5_spi_apps_clk_src", 681 .parent_data = gcc_xo_gpll0, 682 .num_parents = 2, 683 .ops = &clk_rcg2_ops, 684 }, 685 }; 686 687 static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = { 688 .cmd_rcgr = 0x0c20, 689 .hid_width = 5, 690 .parent_map = gcc_xo_gpll0_map, 691 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 692 .clkr.hw.init = &(struct clk_init_data){ 693 .name = "blsp2_qup6_i2c_apps_clk_src", 694 .parent_data = gcc_xo_gpll0, 695 .num_parents = 2, 696 .ops = &clk_rcg2_ops, 697 }, 698 }; 699 700 static struct freq_tbl ftbl_blsp2_qup6_spi_apps_clk_src[] = { 701 F(960000, P_XO, 10, 1, 2), 702 F(4800000, P_XO, 4, 0, 0), 703 F(9600000, P_XO, 2, 0, 0), 704 F(15000000, P_GPLL0, 10, 1, 4), 705 F(19200000, P_XO, 1, 0, 0), 706 F(24000000, P_GPLL0, 12.5, 1, 2), 707 F(25000000, P_GPLL0, 12, 1, 2), 708 F(44440000, P_GPLL0, 13.5, 0, 0), 709 F(48000000, P_GPLL0, 12.5, 0, 0), 710 { } 711 }; 712 713 static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = { 714 .cmd_rcgr = 0x0c0c, 715 .mnd_width = 8, 716 .hid_width = 5, 717 .parent_map = gcc_xo_gpll0_map, 718 .freq_tbl = ftbl_blsp2_qup6_spi_apps_clk_src, 719 .clkr.hw.init = &(struct clk_init_data){ 720 .name = "blsp2_qup6_spi_apps_clk_src", 721 .parent_data = gcc_xo_gpll0, 722 .num_parents = 2, 723 .ops = &clk_rcg2_ops, 724 }, 725 }; 726 727 static struct clk_rcg2 blsp2_uart1_apps_clk_src = { 728 .cmd_rcgr = 0x09cc, 729 .mnd_width = 16, 730 .hid_width = 5, 731 .parent_map = gcc_xo_gpll0_map, 732 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 733 .clkr.hw.init = &(struct clk_init_data){ 734 .name = "blsp2_uart1_apps_clk_src", 735 .parent_data = gcc_xo_gpll0, 736 .num_parents = 2, 737 .ops = &clk_rcg2_ops, 738 }, 739 }; 740 741 static struct clk_rcg2 blsp2_uart2_apps_clk_src = { 742 .cmd_rcgr = 0x0a4c, 743 .mnd_width = 16, 744 .hid_width = 5, 745 .parent_map = gcc_xo_gpll0_map, 746 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 747 .clkr.hw.init = &(struct clk_init_data){ 748 .name = "blsp2_uart2_apps_clk_src", 749 .parent_data = gcc_xo_gpll0, 750 .num_parents = 2, 751 .ops = &clk_rcg2_ops, 752 }, 753 }; 754 755 static struct clk_rcg2 blsp2_uart3_apps_clk_src = { 756 .cmd_rcgr = 0x0acc, 757 .mnd_width = 16, 758 .hid_width = 5, 759 .parent_map = gcc_xo_gpll0_map, 760 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 761 .clkr.hw.init = &(struct clk_init_data){ 762 .name = "blsp2_uart3_apps_clk_src", 763 .parent_data = gcc_xo_gpll0, 764 .num_parents = 2, 765 .ops = &clk_rcg2_ops, 766 }, 767 }; 768 769 static struct clk_rcg2 blsp2_uart4_apps_clk_src = { 770 .cmd_rcgr = 0x0b4c, 771 .mnd_width = 16, 772 .hid_width = 5, 773 .parent_map = gcc_xo_gpll0_map, 774 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 775 .clkr.hw.init = &(struct clk_init_data){ 776 .name = "blsp2_uart4_apps_clk_src", 777 .parent_data = gcc_xo_gpll0, 778 .num_parents = 2, 779 .ops = &clk_rcg2_ops, 780 }, 781 }; 782 783 static struct clk_rcg2 blsp2_uart5_apps_clk_src = { 784 .cmd_rcgr = 0x0bcc, 785 .mnd_width = 16, 786 .hid_width = 5, 787 .parent_map = gcc_xo_gpll0_map, 788 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 789 .clkr.hw.init = &(struct clk_init_data){ 790 .name = "blsp2_uart5_apps_clk_src", 791 .parent_data = gcc_xo_gpll0, 792 .num_parents = 2, 793 .ops = &clk_rcg2_ops, 794 }, 795 }; 796 797 static struct clk_rcg2 blsp2_uart6_apps_clk_src = { 798 .cmd_rcgr = 0x0c4c, 799 .mnd_width = 16, 800 .hid_width = 5, 801 .parent_map = gcc_xo_gpll0_map, 802 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 803 .clkr.hw.init = &(struct clk_init_data){ 804 .name = "blsp2_uart6_apps_clk_src", 805 .parent_data = gcc_xo_gpll0, 806 .num_parents = 2, 807 .ops = &clk_rcg2_ops, 808 }, 809 }; 810 811 static struct freq_tbl ftbl_gp1_clk_src[] = { 812 F(19200000, P_XO, 1, 0, 0), 813 F(100000000, P_GPLL0, 6, 0, 0), 814 F(200000000, P_GPLL0, 3, 0, 0), 815 { } 816 }; 817 818 static struct clk_rcg2 gp1_clk_src = { 819 .cmd_rcgr = 0x1904, 820 .mnd_width = 8, 821 .hid_width = 5, 822 .parent_map = gcc_xo_gpll0_map, 823 .freq_tbl = ftbl_gp1_clk_src, 824 .clkr.hw.init = &(struct clk_init_data){ 825 .name = "gp1_clk_src", 826 .parent_data = gcc_xo_gpll0, 827 .num_parents = 2, 828 .ops = &clk_rcg2_ops, 829 }, 830 }; 831 832 static struct freq_tbl ftbl_gp2_clk_src[] = { 833 F(19200000, P_XO, 1, 0, 0), 834 F(100000000, P_GPLL0, 6, 0, 0), 835 F(200000000, P_GPLL0, 3, 0, 0), 836 { } 837 }; 838 839 static struct clk_rcg2 gp2_clk_src = { 840 .cmd_rcgr = 0x1944, 841 .mnd_width = 8, 842 .hid_width = 5, 843 .parent_map = gcc_xo_gpll0_map, 844 .freq_tbl = ftbl_gp2_clk_src, 845 .clkr.hw.init = &(struct clk_init_data){ 846 .name = "gp2_clk_src", 847 .parent_data = gcc_xo_gpll0, 848 .num_parents = 2, 849 .ops = &clk_rcg2_ops, 850 }, 851 }; 852 853 static struct freq_tbl ftbl_gp3_clk_src[] = { 854 F(19200000, P_XO, 1, 0, 0), 855 F(100000000, P_GPLL0, 6, 0, 0), 856 F(200000000, P_GPLL0, 3, 0, 0), 857 { } 858 }; 859 860 static struct clk_rcg2 gp3_clk_src = { 861 .cmd_rcgr = 0x1984, 862 .mnd_width = 8, 863 .hid_width = 5, 864 .parent_map = gcc_xo_gpll0_map, 865 .freq_tbl = ftbl_gp3_clk_src, 866 .clkr.hw.init = &(struct clk_init_data){ 867 .name = "gp3_clk_src", 868 .parent_data = gcc_xo_gpll0, 869 .num_parents = 2, 870 .ops = &clk_rcg2_ops, 871 }, 872 }; 873 874 static struct freq_tbl ftbl_pcie_0_aux_clk_src[] = { 875 F(1011000, P_XO, 1, 1, 19), 876 { } 877 }; 878 879 static struct clk_rcg2 pcie_0_aux_clk_src = { 880 .cmd_rcgr = 0x1b00, 881 .mnd_width = 8, 882 .hid_width = 5, 883 .freq_tbl = ftbl_pcie_0_aux_clk_src, 884 .clkr.hw.init = &(struct clk_init_data){ 885 .name = "pcie_0_aux_clk_src", 886 .parent_data = &(const struct clk_parent_data){ 887 .fw_name = "xo", 888 }, 889 .num_parents = 1, 890 .ops = &clk_rcg2_ops, 891 }, 892 }; 893 894 static struct freq_tbl ftbl_pcie_pipe_clk_src[] = { 895 F(125000000, P_XO, 1, 0, 0), 896 { } 897 }; 898 899 static struct clk_rcg2 pcie_0_pipe_clk_src = { 900 .cmd_rcgr = 0x1adc, 901 .hid_width = 5, 902 .freq_tbl = ftbl_pcie_pipe_clk_src, 903 .clkr.hw.init = &(struct clk_init_data){ 904 .name = "pcie_0_pipe_clk_src", 905 .parent_data = &(const struct clk_parent_data){ 906 .fw_name = "xo", 907 }, 908 .num_parents = 1, 909 .ops = &clk_rcg2_ops, 910 }, 911 }; 912 913 static struct freq_tbl ftbl_pcie_1_aux_clk_src[] = { 914 F(1011000, P_XO, 1, 1, 19), 915 { } 916 }; 917 918 static struct clk_rcg2 pcie_1_aux_clk_src = { 919 .cmd_rcgr = 0x1b80, 920 .mnd_width = 8, 921 .hid_width = 5, 922 .freq_tbl = ftbl_pcie_1_aux_clk_src, 923 .clkr.hw.init = &(struct clk_init_data){ 924 .name = "pcie_1_aux_clk_src", 925 .parent_data = &(const struct clk_parent_data){ 926 .fw_name = "xo", 927 }, 928 .num_parents = 1, 929 .ops = &clk_rcg2_ops, 930 }, 931 }; 932 933 static struct clk_rcg2 pcie_1_pipe_clk_src = { 934 .cmd_rcgr = 0x1b5c, 935 .hid_width = 5, 936 .freq_tbl = ftbl_pcie_pipe_clk_src, 937 .clkr.hw.init = &(struct clk_init_data){ 938 .name = "pcie_1_pipe_clk_src", 939 .parent_data = &(const struct clk_parent_data){ 940 .fw_name = "xo", 941 }, 942 .num_parents = 1, 943 .ops = &clk_rcg2_ops, 944 }, 945 }; 946 947 static struct freq_tbl ftbl_pdm2_clk_src[] = { 948 F(60000000, P_GPLL0, 10, 0, 0), 949 { } 950 }; 951 952 static struct clk_rcg2 pdm2_clk_src = { 953 .cmd_rcgr = 0x0cd0, 954 .hid_width = 5, 955 .parent_map = gcc_xo_gpll0_map, 956 .freq_tbl = ftbl_pdm2_clk_src, 957 .clkr.hw.init = &(struct clk_init_data){ 958 .name = "pdm2_clk_src", 959 .parent_data = gcc_xo_gpll0, 960 .num_parents = 2, 961 .ops = &clk_rcg2_ops, 962 }, 963 }; 964 965 static struct freq_tbl ftbl_sdcc1_apps_clk_src[] = { 966 F(144000, P_XO, 16, 3, 25), 967 F(400000, P_XO, 12, 1, 4), 968 F(20000000, P_GPLL0, 15, 1, 2), 969 F(25000000, P_GPLL0, 12, 1, 2), 970 F(50000000, P_GPLL0, 12, 0, 0), 971 F(100000000, P_GPLL0, 6, 0, 0), 972 F(192000000, P_GPLL4, 2, 0, 0), 973 F(384000000, P_GPLL4, 1, 0, 0), 974 { } 975 }; 976 977 static struct clk_rcg2 sdcc1_apps_clk_src = { 978 .cmd_rcgr = 0x04d0, 979 .mnd_width = 8, 980 .hid_width = 5, 981 .parent_map = gcc_xo_gpll0_gpll4_map, 982 .freq_tbl = ftbl_sdcc1_apps_clk_src, 983 .clkr.hw.init = &(struct clk_init_data){ 984 .name = "sdcc1_apps_clk_src", 985 .parent_data = gcc_xo_gpll0_gpll4, 986 .num_parents = 3, 987 .ops = &clk_rcg2_floor_ops, 988 }, 989 }; 990 991 static struct freq_tbl ftbl_sdcc2_4_apps_clk_src[] = { 992 F(144000, P_XO, 16, 3, 25), 993 F(400000, P_XO, 12, 1, 4), 994 F(20000000, P_GPLL0, 15, 1, 2), 995 F(25000000, P_GPLL0, 12, 1, 2), 996 F(50000000, P_GPLL0, 12, 0, 0), 997 F(100000000, P_GPLL0, 6, 0, 0), 998 F(200000000, P_GPLL0, 3, 0, 0), 999 { } 1000 }; 1001 1002 static struct clk_rcg2 sdcc2_apps_clk_src = { 1003 .cmd_rcgr = 0x0510, 1004 .mnd_width = 8, 1005 .hid_width = 5, 1006 .parent_map = gcc_xo_gpll0_map, 1007 .freq_tbl = ftbl_sdcc2_4_apps_clk_src, 1008 .clkr.hw.init = &(struct clk_init_data){ 1009 .name = "sdcc2_apps_clk_src", 1010 .parent_data = gcc_xo_gpll0, 1011 .num_parents = 2, 1012 .ops = &clk_rcg2_floor_ops, 1013 }, 1014 }; 1015 1016 static struct clk_rcg2 sdcc3_apps_clk_src = { 1017 .cmd_rcgr = 0x0550, 1018 .mnd_width = 8, 1019 .hid_width = 5, 1020 .parent_map = gcc_xo_gpll0_map, 1021 .freq_tbl = ftbl_sdcc2_4_apps_clk_src, 1022 .clkr.hw.init = &(struct clk_init_data){ 1023 .name = "sdcc3_apps_clk_src", 1024 .parent_data = gcc_xo_gpll0, 1025 .num_parents = 2, 1026 .ops = &clk_rcg2_floor_ops, 1027 }, 1028 }; 1029 1030 static struct clk_rcg2 sdcc4_apps_clk_src = { 1031 .cmd_rcgr = 0x0590, 1032 .mnd_width = 8, 1033 .hid_width = 5, 1034 .parent_map = gcc_xo_gpll0_map, 1035 .freq_tbl = ftbl_sdcc2_4_apps_clk_src, 1036 .clkr.hw.init = &(struct clk_init_data){ 1037 .name = "sdcc4_apps_clk_src", 1038 .parent_data = gcc_xo_gpll0, 1039 .num_parents = 2, 1040 .ops = &clk_rcg2_floor_ops, 1041 }, 1042 }; 1043 1044 static struct freq_tbl ftbl_tsif_ref_clk_src[] = { 1045 F(105500, P_XO, 1, 1, 182), 1046 { } 1047 }; 1048 1049 static struct clk_rcg2 tsif_ref_clk_src = { 1050 .cmd_rcgr = 0x0d90, 1051 .mnd_width = 8, 1052 .hid_width = 5, 1053 .freq_tbl = ftbl_tsif_ref_clk_src, 1054 .clkr.hw.init = &(struct clk_init_data){ 1055 .name = "tsif_ref_clk_src", 1056 .parent_data = &(const struct clk_parent_data){ 1057 .fw_name = "xo", 1058 }, 1059 .num_parents = 1, 1060 .ops = &clk_rcg2_ops, 1061 }, 1062 }; 1063 1064 static struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = { 1065 F(19200000, P_XO, 1, 0, 0), 1066 F(60000000, P_GPLL0, 10, 0, 0), 1067 { } 1068 }; 1069 1070 static struct clk_rcg2 usb30_mock_utmi_clk_src = { 1071 .cmd_rcgr = 0x03e8, 1072 .hid_width = 5, 1073 .parent_map = gcc_xo_gpll0_map, 1074 .freq_tbl = ftbl_usb30_mock_utmi_clk_src, 1075 .clkr.hw.init = &(struct clk_init_data){ 1076 .name = "usb30_mock_utmi_clk_src", 1077 .parent_data = gcc_xo_gpll0, 1078 .num_parents = 2, 1079 .ops = &clk_rcg2_ops, 1080 }, 1081 }; 1082 1083 static struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = { 1084 F(1200000, P_XO, 16, 0, 0), 1085 { } 1086 }; 1087 1088 static struct clk_rcg2 usb3_phy_aux_clk_src = { 1089 .cmd_rcgr = 0x1414, 1090 .hid_width = 5, 1091 .freq_tbl = ftbl_usb3_phy_aux_clk_src, 1092 .clkr.hw.init = &(struct clk_init_data){ 1093 .name = "usb3_phy_aux_clk_src", 1094 .parent_data = &(const struct clk_parent_data){ 1095 .fw_name = "xo", 1096 }, 1097 .num_parents = 1, 1098 .ops = &clk_rcg2_ops, 1099 }, 1100 }; 1101 1102 static struct freq_tbl ftbl_usb_hs_system_clk_src[] = { 1103 F(75000000, P_GPLL0, 8, 0, 0), 1104 { } 1105 }; 1106 1107 static struct clk_rcg2 usb_hs_system_clk_src = { 1108 .cmd_rcgr = 0x0490, 1109 .hid_width = 5, 1110 .parent_map = gcc_xo_gpll0_map, 1111 .freq_tbl = ftbl_usb_hs_system_clk_src, 1112 .clkr.hw.init = &(struct clk_init_data){ 1113 .name = "usb_hs_system_clk_src", 1114 .parent_data = gcc_xo_gpll0, 1115 .num_parents = 2, 1116 .ops = &clk_rcg2_ops, 1117 }, 1118 }; 1119 1120 static struct clk_branch gcc_blsp1_ahb_clk = { 1121 .halt_reg = 0x05c4, 1122 .halt_check = BRANCH_HALT_VOTED, 1123 .clkr = { 1124 .enable_reg = 0x1484, 1125 .enable_mask = BIT(17), 1126 .hw.init = &(struct clk_init_data){ 1127 .name = "gcc_blsp1_ahb_clk", 1128 .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw }, 1129 .num_parents = 1, 1130 .ops = &clk_branch2_ops, 1131 }, 1132 }, 1133 }; 1134 1135 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { 1136 .halt_reg = 0x0648, 1137 .clkr = { 1138 .enable_reg = 0x0648, 1139 .enable_mask = BIT(0), 1140 .hw.init = &(struct clk_init_data){ 1141 .name = "gcc_blsp1_qup1_i2c_apps_clk", 1142 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup1_i2c_apps_clk_src.clkr.hw }, 1143 .num_parents = 1, 1144 .flags = CLK_SET_RATE_PARENT, 1145 .ops = &clk_branch2_ops, 1146 }, 1147 }, 1148 }; 1149 1150 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { 1151 .halt_reg = 0x0644, 1152 .clkr = { 1153 .enable_reg = 0x0644, 1154 .enable_mask = BIT(0), 1155 .hw.init = &(struct clk_init_data){ 1156 .name = "gcc_blsp1_qup1_spi_apps_clk", 1157 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup1_spi_apps_clk_src.clkr.hw }, 1158 .num_parents = 1, 1159 .flags = CLK_SET_RATE_PARENT, 1160 .ops = &clk_branch2_ops, 1161 }, 1162 }, 1163 }; 1164 1165 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { 1166 .halt_reg = 0x06c8, 1167 .clkr = { 1168 .enable_reg = 0x06c8, 1169 .enable_mask = BIT(0), 1170 .hw.init = &(struct clk_init_data){ 1171 .name = "gcc_blsp1_qup2_i2c_apps_clk", 1172 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup2_i2c_apps_clk_src.clkr.hw }, 1173 .num_parents = 1, 1174 .flags = CLK_SET_RATE_PARENT, 1175 .ops = &clk_branch2_ops, 1176 }, 1177 }, 1178 }; 1179 1180 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { 1181 .halt_reg = 0x06c4, 1182 .clkr = { 1183 .enable_reg = 0x06c4, 1184 .enable_mask = BIT(0), 1185 .hw.init = &(struct clk_init_data){ 1186 .name = "gcc_blsp1_qup2_spi_apps_clk", 1187 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup2_spi_apps_clk_src.clkr.hw }, 1188 .num_parents = 1, 1189 .flags = CLK_SET_RATE_PARENT, 1190 .ops = &clk_branch2_ops, 1191 }, 1192 }, 1193 }; 1194 1195 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = { 1196 .halt_reg = 0x0748, 1197 .clkr = { 1198 .enable_reg = 0x0748, 1199 .enable_mask = BIT(0), 1200 .hw.init = &(struct clk_init_data){ 1201 .name = "gcc_blsp1_qup3_i2c_apps_clk", 1202 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup3_i2c_apps_clk_src.clkr.hw }, 1203 .num_parents = 1, 1204 .flags = CLK_SET_RATE_PARENT, 1205 .ops = &clk_branch2_ops, 1206 }, 1207 }, 1208 }; 1209 1210 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = { 1211 .halt_reg = 0x0744, 1212 .clkr = { 1213 .enable_reg = 0x0744, 1214 .enable_mask = BIT(0), 1215 .hw.init = &(struct clk_init_data){ 1216 .name = "gcc_blsp1_qup3_spi_apps_clk", 1217 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup3_spi_apps_clk_src.clkr.hw }, 1218 .num_parents = 1, 1219 .flags = CLK_SET_RATE_PARENT, 1220 .ops = &clk_branch2_ops, 1221 }, 1222 }, 1223 }; 1224 1225 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = { 1226 .halt_reg = 0x07c8, 1227 .clkr = { 1228 .enable_reg = 0x07c8, 1229 .enable_mask = BIT(0), 1230 .hw.init = &(struct clk_init_data){ 1231 .name = "gcc_blsp1_qup4_i2c_apps_clk", 1232 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup4_i2c_apps_clk_src.clkr.hw }, 1233 .num_parents = 1, 1234 .flags = CLK_SET_RATE_PARENT, 1235 .ops = &clk_branch2_ops, 1236 }, 1237 }, 1238 }; 1239 1240 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = { 1241 .halt_reg = 0x07c4, 1242 .clkr = { 1243 .enable_reg = 0x07c4, 1244 .enable_mask = BIT(0), 1245 .hw.init = &(struct clk_init_data){ 1246 .name = "gcc_blsp1_qup4_spi_apps_clk", 1247 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup4_spi_apps_clk_src.clkr.hw }, 1248 .num_parents = 1, 1249 .flags = CLK_SET_RATE_PARENT, 1250 .ops = &clk_branch2_ops, 1251 }, 1252 }, 1253 }; 1254 1255 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = { 1256 .halt_reg = 0x0848, 1257 .clkr = { 1258 .enable_reg = 0x0848, 1259 .enable_mask = BIT(0), 1260 .hw.init = &(struct clk_init_data){ 1261 .name = "gcc_blsp1_qup5_i2c_apps_clk", 1262 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup5_i2c_apps_clk_src.clkr.hw }, 1263 .num_parents = 1, 1264 .flags = CLK_SET_RATE_PARENT, 1265 .ops = &clk_branch2_ops, 1266 }, 1267 }, 1268 }; 1269 1270 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = { 1271 .halt_reg = 0x0844, 1272 .clkr = { 1273 .enable_reg = 0x0844, 1274 .enable_mask = BIT(0), 1275 .hw.init = &(struct clk_init_data){ 1276 .name = "gcc_blsp1_qup5_spi_apps_clk", 1277 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup5_spi_apps_clk_src.clkr.hw }, 1278 .num_parents = 1, 1279 .flags = CLK_SET_RATE_PARENT, 1280 .ops = &clk_branch2_ops, 1281 }, 1282 }, 1283 }; 1284 1285 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = { 1286 .halt_reg = 0x08c8, 1287 .clkr = { 1288 .enable_reg = 0x08c8, 1289 .enable_mask = BIT(0), 1290 .hw.init = &(struct clk_init_data){ 1291 .name = "gcc_blsp1_qup6_i2c_apps_clk", 1292 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup6_i2c_apps_clk_src.clkr.hw }, 1293 .num_parents = 1, 1294 .flags = CLK_SET_RATE_PARENT, 1295 .ops = &clk_branch2_ops, 1296 }, 1297 }, 1298 }; 1299 1300 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = { 1301 .halt_reg = 0x08c4, 1302 .clkr = { 1303 .enable_reg = 0x08c4, 1304 .enable_mask = BIT(0), 1305 .hw.init = &(struct clk_init_data){ 1306 .name = "gcc_blsp1_qup6_spi_apps_clk", 1307 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup6_spi_apps_clk_src.clkr.hw }, 1308 .num_parents = 1, 1309 .flags = CLK_SET_RATE_PARENT, 1310 .ops = &clk_branch2_ops, 1311 }, 1312 }, 1313 }; 1314 1315 static struct clk_branch gcc_blsp1_uart1_apps_clk = { 1316 .halt_reg = 0x0684, 1317 .clkr = { 1318 .enable_reg = 0x0684, 1319 .enable_mask = BIT(0), 1320 .hw.init = &(struct clk_init_data){ 1321 .name = "gcc_blsp1_uart1_apps_clk", 1322 .parent_hws = (const struct clk_hw *[]){ &blsp1_uart1_apps_clk_src.clkr.hw }, 1323 .num_parents = 1, 1324 .flags = CLK_SET_RATE_PARENT, 1325 .ops = &clk_branch2_ops, 1326 }, 1327 }, 1328 }; 1329 1330 static struct clk_branch gcc_blsp1_uart2_apps_clk = { 1331 .halt_reg = 0x0704, 1332 .clkr = { 1333 .enable_reg = 0x0704, 1334 .enable_mask = BIT(0), 1335 .hw.init = &(struct clk_init_data){ 1336 .name = "gcc_blsp1_uart2_apps_clk", 1337 .parent_hws = (const struct clk_hw *[]){ &blsp1_uart2_apps_clk_src.clkr.hw }, 1338 .num_parents = 1, 1339 .flags = CLK_SET_RATE_PARENT, 1340 .ops = &clk_branch2_ops, 1341 }, 1342 }, 1343 }; 1344 1345 static struct clk_branch gcc_blsp1_uart3_apps_clk = { 1346 .halt_reg = 0x0784, 1347 .clkr = { 1348 .enable_reg = 0x0784, 1349 .enable_mask = BIT(0), 1350 .hw.init = &(struct clk_init_data){ 1351 .name = "gcc_blsp1_uart3_apps_clk", 1352 .parent_hws = (const struct clk_hw *[]){ &blsp1_uart3_apps_clk_src.clkr.hw }, 1353 .num_parents = 1, 1354 .flags = CLK_SET_RATE_PARENT, 1355 .ops = &clk_branch2_ops, 1356 }, 1357 }, 1358 }; 1359 1360 static struct clk_branch gcc_blsp1_uart4_apps_clk = { 1361 .halt_reg = 0x0804, 1362 .clkr = { 1363 .enable_reg = 0x0804, 1364 .enable_mask = BIT(0), 1365 .hw.init = &(struct clk_init_data){ 1366 .name = "gcc_blsp1_uart4_apps_clk", 1367 .parent_hws = (const struct clk_hw *[]){ &blsp1_uart4_apps_clk_src.clkr.hw }, 1368 .num_parents = 1, 1369 .flags = CLK_SET_RATE_PARENT, 1370 .ops = &clk_branch2_ops, 1371 }, 1372 }, 1373 }; 1374 1375 static struct clk_branch gcc_blsp1_uart5_apps_clk = { 1376 .halt_reg = 0x0884, 1377 .clkr = { 1378 .enable_reg = 0x0884, 1379 .enable_mask = BIT(0), 1380 .hw.init = &(struct clk_init_data){ 1381 .name = "gcc_blsp1_uart5_apps_clk", 1382 .parent_hws = (const struct clk_hw *[]){ &blsp1_uart5_apps_clk_src.clkr.hw }, 1383 .num_parents = 1, 1384 .flags = CLK_SET_RATE_PARENT, 1385 .ops = &clk_branch2_ops, 1386 }, 1387 }, 1388 }; 1389 1390 static struct clk_branch gcc_blsp1_uart6_apps_clk = { 1391 .halt_reg = 0x0904, 1392 .clkr = { 1393 .enable_reg = 0x0904, 1394 .enable_mask = BIT(0), 1395 .hw.init = &(struct clk_init_data){ 1396 .name = "gcc_blsp1_uart6_apps_clk", 1397 .parent_hws = (const struct clk_hw *[]){ &blsp1_uart6_apps_clk_src.clkr.hw }, 1398 .num_parents = 1, 1399 .flags = CLK_SET_RATE_PARENT, 1400 .ops = &clk_branch2_ops, 1401 }, 1402 }, 1403 }; 1404 1405 static struct clk_branch gcc_blsp2_ahb_clk = { 1406 .halt_reg = 0x0944, 1407 .halt_check = BRANCH_HALT_VOTED, 1408 .clkr = { 1409 .enable_reg = 0x1484, 1410 .enable_mask = BIT(15), 1411 .hw.init = &(struct clk_init_data){ 1412 .name = "gcc_blsp2_ahb_clk", 1413 .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw }, 1414 .num_parents = 1, 1415 .ops = &clk_branch2_ops, 1416 }, 1417 }, 1418 }; 1419 1420 static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = { 1421 .halt_reg = 0x0988, 1422 .clkr = { 1423 .enable_reg = 0x0988, 1424 .enable_mask = BIT(0), 1425 .hw.init = &(struct clk_init_data){ 1426 .name = "gcc_blsp2_qup1_i2c_apps_clk", 1427 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup1_i2c_apps_clk_src.clkr.hw }, 1428 .num_parents = 1, 1429 .flags = CLK_SET_RATE_PARENT, 1430 .ops = &clk_branch2_ops, 1431 }, 1432 }, 1433 }; 1434 1435 static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = { 1436 .halt_reg = 0x0984, 1437 .clkr = { 1438 .enable_reg = 0x0984, 1439 .enable_mask = BIT(0), 1440 .hw.init = &(struct clk_init_data){ 1441 .name = "gcc_blsp2_qup1_spi_apps_clk", 1442 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup1_spi_apps_clk_src.clkr.hw }, 1443 .num_parents = 1, 1444 .flags = CLK_SET_RATE_PARENT, 1445 .ops = &clk_branch2_ops, 1446 }, 1447 }, 1448 }; 1449 1450 static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = { 1451 .halt_reg = 0x0a08, 1452 .clkr = { 1453 .enable_reg = 0x0a08, 1454 .enable_mask = BIT(0), 1455 .hw.init = &(struct clk_init_data){ 1456 .name = "gcc_blsp2_qup2_i2c_apps_clk", 1457 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup2_i2c_apps_clk_src.clkr.hw }, 1458 .num_parents = 1, 1459 .flags = CLK_SET_RATE_PARENT, 1460 .ops = &clk_branch2_ops, 1461 }, 1462 }, 1463 }; 1464 1465 static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = { 1466 .halt_reg = 0x0a04, 1467 .clkr = { 1468 .enable_reg = 0x0a04, 1469 .enable_mask = BIT(0), 1470 .hw.init = &(struct clk_init_data){ 1471 .name = "gcc_blsp2_qup2_spi_apps_clk", 1472 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup2_spi_apps_clk_src.clkr.hw }, 1473 .num_parents = 1, 1474 .flags = CLK_SET_RATE_PARENT, 1475 .ops = &clk_branch2_ops, 1476 }, 1477 }, 1478 }; 1479 1480 static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = { 1481 .halt_reg = 0x0a88, 1482 .clkr = { 1483 .enable_reg = 0x0a88, 1484 .enable_mask = BIT(0), 1485 .hw.init = &(struct clk_init_data){ 1486 .name = "gcc_blsp2_qup3_i2c_apps_clk", 1487 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup3_i2c_apps_clk_src.clkr.hw }, 1488 .num_parents = 1, 1489 .flags = CLK_SET_RATE_PARENT, 1490 .ops = &clk_branch2_ops, 1491 }, 1492 }, 1493 }; 1494 1495 static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = { 1496 .halt_reg = 0x0a84, 1497 .clkr = { 1498 .enable_reg = 0x0a84, 1499 .enable_mask = BIT(0), 1500 .hw.init = &(struct clk_init_data){ 1501 .name = "gcc_blsp2_qup3_spi_apps_clk", 1502 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup3_spi_apps_clk_src.clkr.hw }, 1503 .num_parents = 1, 1504 .flags = CLK_SET_RATE_PARENT, 1505 .ops = &clk_branch2_ops, 1506 }, 1507 }, 1508 }; 1509 1510 static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = { 1511 .halt_reg = 0x0b08, 1512 .clkr = { 1513 .enable_reg = 0x0b08, 1514 .enable_mask = BIT(0), 1515 .hw.init = &(struct clk_init_data){ 1516 .name = "gcc_blsp2_qup4_i2c_apps_clk", 1517 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup4_i2c_apps_clk_src.clkr.hw }, 1518 .num_parents = 1, 1519 .flags = CLK_SET_RATE_PARENT, 1520 .ops = &clk_branch2_ops, 1521 }, 1522 }, 1523 }; 1524 1525 static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = { 1526 .halt_reg = 0x0b04, 1527 .clkr = { 1528 .enable_reg = 0x0b04, 1529 .enable_mask = BIT(0), 1530 .hw.init = &(struct clk_init_data){ 1531 .name = "gcc_blsp2_qup4_spi_apps_clk", 1532 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup4_spi_apps_clk_src.clkr.hw }, 1533 .num_parents = 1, 1534 .flags = CLK_SET_RATE_PARENT, 1535 .ops = &clk_branch2_ops, 1536 }, 1537 }, 1538 }; 1539 1540 static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = { 1541 .halt_reg = 0x0b88, 1542 .clkr = { 1543 .enable_reg = 0x0b88, 1544 .enable_mask = BIT(0), 1545 .hw.init = &(struct clk_init_data){ 1546 .name = "gcc_blsp2_qup5_i2c_apps_clk", 1547 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup5_i2c_apps_clk_src.clkr.hw }, 1548 .num_parents = 1, 1549 .flags = CLK_SET_RATE_PARENT, 1550 .ops = &clk_branch2_ops, 1551 }, 1552 }, 1553 }; 1554 1555 static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = { 1556 .halt_reg = 0x0b84, 1557 .clkr = { 1558 .enable_reg = 0x0b84, 1559 .enable_mask = BIT(0), 1560 .hw.init = &(struct clk_init_data){ 1561 .name = "gcc_blsp2_qup5_spi_apps_clk", 1562 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup5_spi_apps_clk_src.clkr.hw }, 1563 .num_parents = 1, 1564 .flags = CLK_SET_RATE_PARENT, 1565 .ops = &clk_branch2_ops, 1566 }, 1567 }, 1568 }; 1569 1570 static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = { 1571 .halt_reg = 0x0c08, 1572 .clkr = { 1573 .enable_reg = 0x0c08, 1574 .enable_mask = BIT(0), 1575 .hw.init = &(struct clk_init_data){ 1576 .name = "gcc_blsp2_qup6_i2c_apps_clk", 1577 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup6_i2c_apps_clk_src.clkr.hw }, 1578 .num_parents = 1, 1579 .flags = CLK_SET_RATE_PARENT, 1580 .ops = &clk_branch2_ops, 1581 }, 1582 }, 1583 }; 1584 1585 static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = { 1586 .halt_reg = 0x0c04, 1587 .clkr = { 1588 .enable_reg = 0x0c04, 1589 .enable_mask = BIT(0), 1590 .hw.init = &(struct clk_init_data){ 1591 .name = "gcc_blsp2_qup6_spi_apps_clk", 1592 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup6_spi_apps_clk_src.clkr.hw }, 1593 .num_parents = 1, 1594 .flags = CLK_SET_RATE_PARENT, 1595 .ops = &clk_branch2_ops, 1596 }, 1597 }, 1598 }; 1599 1600 static struct clk_branch gcc_blsp2_uart1_apps_clk = { 1601 .halt_reg = 0x09c4, 1602 .clkr = { 1603 .enable_reg = 0x09c4, 1604 .enable_mask = BIT(0), 1605 .hw.init = &(struct clk_init_data){ 1606 .name = "gcc_blsp2_uart1_apps_clk", 1607 .parent_hws = (const struct clk_hw *[]){ &blsp2_uart1_apps_clk_src.clkr.hw }, 1608 .num_parents = 1, 1609 .flags = CLK_SET_RATE_PARENT, 1610 .ops = &clk_branch2_ops, 1611 }, 1612 }, 1613 }; 1614 1615 static struct clk_branch gcc_blsp2_uart2_apps_clk = { 1616 .halt_reg = 0x0a44, 1617 .clkr = { 1618 .enable_reg = 0x0a44, 1619 .enable_mask = BIT(0), 1620 .hw.init = &(struct clk_init_data){ 1621 .name = "gcc_blsp2_uart2_apps_clk", 1622 .parent_hws = (const struct clk_hw *[]){ &blsp2_uart2_apps_clk_src.clkr.hw }, 1623 .num_parents = 1, 1624 .flags = CLK_SET_RATE_PARENT, 1625 .ops = &clk_branch2_ops, 1626 }, 1627 }, 1628 }; 1629 1630 static struct clk_branch gcc_blsp2_uart3_apps_clk = { 1631 .halt_reg = 0x0ac4, 1632 .clkr = { 1633 .enable_reg = 0x0ac4, 1634 .enable_mask = BIT(0), 1635 .hw.init = &(struct clk_init_data){ 1636 .name = "gcc_blsp2_uart3_apps_clk", 1637 .parent_hws = (const struct clk_hw *[]){ &blsp2_uart3_apps_clk_src.clkr.hw }, 1638 .num_parents = 1, 1639 .flags = CLK_SET_RATE_PARENT, 1640 .ops = &clk_branch2_ops, 1641 }, 1642 }, 1643 }; 1644 1645 static struct clk_branch gcc_blsp2_uart4_apps_clk = { 1646 .halt_reg = 0x0b44, 1647 .clkr = { 1648 .enable_reg = 0x0b44, 1649 .enable_mask = BIT(0), 1650 .hw.init = &(struct clk_init_data){ 1651 .name = "gcc_blsp2_uart4_apps_clk", 1652 .parent_hws = (const struct clk_hw *[]){ &blsp2_uart4_apps_clk_src.clkr.hw }, 1653 .num_parents = 1, 1654 .flags = CLK_SET_RATE_PARENT, 1655 .ops = &clk_branch2_ops, 1656 }, 1657 }, 1658 }; 1659 1660 static struct clk_branch gcc_blsp2_uart5_apps_clk = { 1661 .halt_reg = 0x0bc4, 1662 .clkr = { 1663 .enable_reg = 0x0bc4, 1664 .enable_mask = BIT(0), 1665 .hw.init = &(struct clk_init_data){ 1666 .name = "gcc_blsp2_uart5_apps_clk", 1667 .parent_hws = (const struct clk_hw *[]){ &blsp2_uart5_apps_clk_src.clkr.hw }, 1668 .num_parents = 1, 1669 .flags = CLK_SET_RATE_PARENT, 1670 .ops = &clk_branch2_ops, 1671 }, 1672 }, 1673 }; 1674 1675 static struct clk_branch gcc_blsp2_uart6_apps_clk = { 1676 .halt_reg = 0x0c44, 1677 .clkr = { 1678 .enable_reg = 0x0c44, 1679 .enable_mask = BIT(0), 1680 .hw.init = &(struct clk_init_data){ 1681 .name = "gcc_blsp2_uart6_apps_clk", 1682 .parent_hws = (const struct clk_hw *[]){ &blsp2_uart6_apps_clk_src.clkr.hw }, 1683 .num_parents = 1, 1684 .flags = CLK_SET_RATE_PARENT, 1685 .ops = &clk_branch2_ops, 1686 }, 1687 }, 1688 }; 1689 1690 static struct clk_branch gcc_gp1_clk = { 1691 .halt_reg = 0x1900, 1692 .clkr = { 1693 .enable_reg = 0x1900, 1694 .enable_mask = BIT(0), 1695 .hw.init = &(struct clk_init_data){ 1696 .name = "gcc_gp1_clk", 1697 .parent_hws = (const struct clk_hw *[]){ &gp1_clk_src.clkr.hw }, 1698 .num_parents = 1, 1699 .flags = CLK_SET_RATE_PARENT, 1700 .ops = &clk_branch2_ops, 1701 }, 1702 }, 1703 }; 1704 1705 static struct clk_branch gcc_gp2_clk = { 1706 .halt_reg = 0x1940, 1707 .clkr = { 1708 .enable_reg = 0x1940, 1709 .enable_mask = BIT(0), 1710 .hw.init = &(struct clk_init_data){ 1711 .name = "gcc_gp2_clk", 1712 .parent_hws = (const struct clk_hw *[]){ &gp2_clk_src.clkr.hw }, 1713 .num_parents = 1, 1714 .flags = CLK_SET_RATE_PARENT, 1715 .ops = &clk_branch2_ops, 1716 }, 1717 }, 1718 }; 1719 1720 static struct clk_branch gcc_gp3_clk = { 1721 .halt_reg = 0x1980, 1722 .clkr = { 1723 .enable_reg = 0x1980, 1724 .enable_mask = BIT(0), 1725 .hw.init = &(struct clk_init_data){ 1726 .name = "gcc_gp3_clk", 1727 .parent_hws = (const struct clk_hw *[]){ &gp3_clk_src.clkr.hw }, 1728 .num_parents = 1, 1729 .flags = CLK_SET_RATE_PARENT, 1730 .ops = &clk_branch2_ops, 1731 }, 1732 }, 1733 }; 1734 1735 static struct clk_branch gcc_lpass_q6_axi_clk = { 1736 .halt_reg = 0x0280, 1737 .clkr = { 1738 .enable_reg = 0x0280, 1739 .enable_mask = BIT(0), 1740 .hw.init = &(struct clk_init_data){ 1741 .name = "gcc_lpass_q6_axi_clk", 1742 .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw }, 1743 .num_parents = 1, 1744 .ops = &clk_branch2_ops, 1745 }, 1746 }, 1747 }; 1748 1749 static struct clk_branch gcc_mss_q6_bimc_axi_clk = { 1750 .halt_reg = 0x0284, 1751 .clkr = { 1752 .enable_reg = 0x0284, 1753 .enable_mask = BIT(0), 1754 .hw.init = &(struct clk_init_data){ 1755 .name = "gcc_mss_q6_bimc_axi_clk", 1756 .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw }, 1757 .num_parents = 1, 1758 .ops = &clk_branch2_ops, 1759 }, 1760 }, 1761 }; 1762 1763 static struct clk_branch gcc_pcie_0_aux_clk = { 1764 .halt_reg = 0x1ad4, 1765 .clkr = { 1766 .enable_reg = 0x1ad4, 1767 .enable_mask = BIT(0), 1768 .hw.init = &(struct clk_init_data){ 1769 .name = "gcc_pcie_0_aux_clk", 1770 .parent_hws = (const struct clk_hw *[]){ &pcie_0_aux_clk_src.clkr.hw }, 1771 .num_parents = 1, 1772 .flags = CLK_SET_RATE_PARENT, 1773 .ops = &clk_branch2_ops, 1774 }, 1775 }, 1776 }; 1777 1778 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { 1779 .halt_reg = 0x1ad0, 1780 .clkr = { 1781 .enable_reg = 0x1ad0, 1782 .enable_mask = BIT(0), 1783 .hw.init = &(struct clk_init_data){ 1784 .name = "gcc_pcie_0_cfg_ahb_clk", 1785 .parent_hws = (const struct clk_hw *[]){ &config_noc_clk_src.clkr.hw }, 1786 .num_parents = 1, 1787 .flags = CLK_SET_RATE_PARENT, 1788 .ops = &clk_branch2_ops, 1789 }, 1790 }, 1791 }; 1792 1793 static struct clk_branch gcc_pcie_0_mstr_axi_clk = { 1794 .halt_reg = 0x1acc, 1795 .clkr = { 1796 .enable_reg = 0x1acc, 1797 .enable_mask = BIT(0), 1798 .hw.init = &(struct clk_init_data){ 1799 .name = "gcc_pcie_0_mstr_axi_clk", 1800 .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw }, 1801 .num_parents = 1, 1802 .flags = CLK_SET_RATE_PARENT, 1803 .ops = &clk_branch2_ops, 1804 }, 1805 }, 1806 }; 1807 1808 static struct clk_branch gcc_pcie_0_pipe_clk = { 1809 .halt_reg = 0x1ad8, 1810 .halt_check = BRANCH_HALT_DELAY, 1811 .clkr = { 1812 .enable_reg = 0x1ad8, 1813 .enable_mask = BIT(0), 1814 .hw.init = &(struct clk_init_data){ 1815 .name = "gcc_pcie_0_pipe_clk", 1816 .parent_hws = (const struct clk_hw *[]){ &pcie_0_pipe_clk_src.clkr.hw }, 1817 .num_parents = 1, 1818 .flags = CLK_SET_RATE_PARENT, 1819 .ops = &clk_branch2_ops, 1820 }, 1821 }, 1822 }; 1823 1824 static struct clk_branch gcc_pcie_0_slv_axi_clk = { 1825 .halt_reg = 0x1ac8, 1826 .halt_check = BRANCH_HALT_DELAY, 1827 .clkr = { 1828 .enable_reg = 0x1ac8, 1829 .enable_mask = BIT(0), 1830 .hw.init = &(struct clk_init_data){ 1831 .name = "gcc_pcie_0_slv_axi_clk", 1832 .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw }, 1833 .num_parents = 1, 1834 .flags = CLK_SET_RATE_PARENT, 1835 .ops = &clk_branch2_ops, 1836 }, 1837 }, 1838 }; 1839 1840 static struct clk_branch gcc_pcie_1_aux_clk = { 1841 .halt_reg = 0x1b54, 1842 .clkr = { 1843 .enable_reg = 0x1b54, 1844 .enable_mask = BIT(0), 1845 .hw.init = &(struct clk_init_data){ 1846 .name = "gcc_pcie_1_aux_clk", 1847 .parent_hws = (const struct clk_hw *[]){ &pcie_1_aux_clk_src.clkr.hw }, 1848 .num_parents = 1, 1849 .flags = CLK_SET_RATE_PARENT, 1850 .ops = &clk_branch2_ops, 1851 }, 1852 }, 1853 }; 1854 1855 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { 1856 .halt_reg = 0x1b54, 1857 .clkr = { 1858 .enable_reg = 0x1b54, 1859 .enable_mask = BIT(0), 1860 .hw.init = &(struct clk_init_data){ 1861 .name = "gcc_pcie_1_cfg_ahb_clk", 1862 .parent_hws = (const struct clk_hw *[]){ &config_noc_clk_src.clkr.hw }, 1863 .num_parents = 1, 1864 .flags = CLK_SET_RATE_PARENT, 1865 .ops = &clk_branch2_ops, 1866 }, 1867 }, 1868 }; 1869 1870 static struct clk_branch gcc_pcie_1_mstr_axi_clk = { 1871 .halt_reg = 0x1b50, 1872 .clkr = { 1873 .enable_reg = 0x1b50, 1874 .enable_mask = BIT(0), 1875 .hw.init = &(struct clk_init_data){ 1876 .name = "gcc_pcie_1_mstr_axi_clk", 1877 .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw }, 1878 .num_parents = 1, 1879 .flags = CLK_SET_RATE_PARENT, 1880 .ops = &clk_branch2_ops, 1881 }, 1882 }, 1883 }; 1884 1885 static struct clk_branch gcc_pcie_1_pipe_clk = { 1886 .halt_reg = 0x1b58, 1887 .halt_check = BRANCH_HALT_DELAY, 1888 .clkr = { 1889 .enable_reg = 0x1b58, 1890 .enable_mask = BIT(0), 1891 .hw.init = &(struct clk_init_data){ 1892 .name = "gcc_pcie_1_pipe_clk", 1893 .parent_hws = (const struct clk_hw *[]){ &pcie_1_pipe_clk_src.clkr.hw }, 1894 .num_parents = 1, 1895 .flags = CLK_SET_RATE_PARENT, 1896 .ops = &clk_branch2_ops, 1897 }, 1898 }, 1899 }; 1900 1901 static struct clk_branch gcc_pcie_1_slv_axi_clk = { 1902 .halt_reg = 0x1b48, 1903 .clkr = { 1904 .enable_reg = 0x1b48, 1905 .enable_mask = BIT(0), 1906 .hw.init = &(struct clk_init_data){ 1907 .name = "gcc_pcie_1_slv_axi_clk", 1908 .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw }, 1909 .num_parents = 1, 1910 .flags = CLK_SET_RATE_PARENT, 1911 .ops = &clk_branch2_ops, 1912 }, 1913 }, 1914 }; 1915 1916 static struct clk_branch gcc_pdm2_clk = { 1917 .halt_reg = 0x0ccc, 1918 .clkr = { 1919 .enable_reg = 0x0ccc, 1920 .enable_mask = BIT(0), 1921 .hw.init = &(struct clk_init_data){ 1922 .name = "gcc_pdm2_clk", 1923 .parent_hws = (const struct clk_hw *[]){ &pdm2_clk_src.clkr.hw }, 1924 .num_parents = 1, 1925 .flags = CLK_SET_RATE_PARENT, 1926 .ops = &clk_branch2_ops, 1927 }, 1928 }, 1929 }; 1930 1931 static struct clk_branch gcc_pdm_ahb_clk = { 1932 .halt_reg = 0x0cc4, 1933 .clkr = { 1934 .enable_reg = 0x0cc4, 1935 .enable_mask = BIT(0), 1936 .hw.init = &(struct clk_init_data){ 1937 .name = "gcc_pdm_ahb_clk", 1938 .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw }, 1939 .num_parents = 1, 1940 .ops = &clk_branch2_ops, 1941 }, 1942 }, 1943 }; 1944 1945 static struct clk_branch gcc_sdcc1_apps_clk = { 1946 .halt_reg = 0x04c4, 1947 .clkr = { 1948 .enable_reg = 0x04c4, 1949 .enable_mask = BIT(0), 1950 .hw.init = &(struct clk_init_data){ 1951 .name = "gcc_sdcc1_apps_clk", 1952 .parent_hws = (const struct clk_hw *[]){ &sdcc1_apps_clk_src.clkr.hw }, 1953 .num_parents = 1, 1954 .flags = CLK_SET_RATE_PARENT, 1955 .ops = &clk_branch2_ops, 1956 }, 1957 }, 1958 }; 1959 1960 static struct clk_branch gcc_sdcc1_ahb_clk = { 1961 .halt_reg = 0x04c8, 1962 .clkr = { 1963 .enable_reg = 0x04c8, 1964 .enable_mask = BIT(0), 1965 .hw.init = &(struct clk_init_data){ 1966 .name = "gcc_sdcc1_ahb_clk", 1967 .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw }, 1968 .num_parents = 1, 1969 .flags = CLK_SET_RATE_PARENT, 1970 .ops = &clk_branch2_ops, 1971 }, 1972 }, 1973 }; 1974 1975 static struct clk_branch gcc_sdcc2_ahb_clk = { 1976 .halt_reg = 0x0508, 1977 .clkr = { 1978 .enable_reg = 0x0508, 1979 .enable_mask = BIT(0), 1980 .hw.init = &(struct clk_init_data){ 1981 .name = "gcc_sdcc2_ahb_clk", 1982 .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw }, 1983 .num_parents = 1, 1984 .flags = CLK_SET_RATE_PARENT, 1985 .ops = &clk_branch2_ops, 1986 }, 1987 }, 1988 }; 1989 1990 static struct clk_branch gcc_sdcc2_apps_clk = { 1991 .halt_reg = 0x0504, 1992 .clkr = { 1993 .enable_reg = 0x0504, 1994 .enable_mask = BIT(0), 1995 .hw.init = &(struct clk_init_data){ 1996 .name = "gcc_sdcc2_apps_clk", 1997 .parent_hws = (const struct clk_hw *[]){ &sdcc2_apps_clk_src.clkr.hw }, 1998 .num_parents = 1, 1999 .flags = CLK_SET_RATE_PARENT, 2000 .ops = &clk_branch2_ops, 2001 }, 2002 }, 2003 }; 2004 2005 static struct clk_branch gcc_sdcc3_ahb_clk = { 2006 .halt_reg = 0x0548, 2007 .clkr = { 2008 .enable_reg = 0x0548, 2009 .enable_mask = BIT(0), 2010 .hw.init = &(struct clk_init_data){ 2011 .name = "gcc_sdcc3_ahb_clk", 2012 .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw }, 2013 .num_parents = 1, 2014 .flags = CLK_SET_RATE_PARENT, 2015 .ops = &clk_branch2_ops, 2016 }, 2017 }, 2018 }; 2019 2020 static struct clk_branch gcc_sdcc3_apps_clk = { 2021 .halt_reg = 0x0544, 2022 .clkr = { 2023 .enable_reg = 0x0544, 2024 .enable_mask = BIT(0), 2025 .hw.init = &(struct clk_init_data){ 2026 .name = "gcc_sdcc3_apps_clk", 2027 .parent_hws = (const struct clk_hw *[]){ &sdcc3_apps_clk_src.clkr.hw }, 2028 .num_parents = 1, 2029 .flags = CLK_SET_RATE_PARENT, 2030 .ops = &clk_branch2_ops, 2031 }, 2032 }, 2033 }; 2034 2035 static struct clk_branch gcc_sdcc4_ahb_clk = { 2036 .halt_reg = 0x0588, 2037 .clkr = { 2038 .enable_reg = 0x0588, 2039 .enable_mask = BIT(0), 2040 .hw.init = &(struct clk_init_data){ 2041 .name = "gcc_sdcc4_ahb_clk", 2042 .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw }, 2043 .num_parents = 1, 2044 .flags = CLK_SET_RATE_PARENT, 2045 .ops = &clk_branch2_ops, 2046 }, 2047 }, 2048 }; 2049 2050 static struct clk_branch gcc_sdcc4_apps_clk = { 2051 .halt_reg = 0x0584, 2052 .clkr = { 2053 .enable_reg = 0x0584, 2054 .enable_mask = BIT(0), 2055 .hw.init = &(struct clk_init_data){ 2056 .name = "gcc_sdcc4_apps_clk", 2057 .parent_hws = (const struct clk_hw *[]){ &sdcc4_apps_clk_src.clkr.hw }, 2058 .num_parents = 1, 2059 .flags = CLK_SET_RATE_PARENT, 2060 .ops = &clk_branch2_ops, 2061 }, 2062 }, 2063 }; 2064 2065 static struct clk_branch gcc_sys_noc_ufs_axi_clk = { 2066 .halt_reg = 0x1d7c, 2067 .clkr = { 2068 .enable_reg = 0x1d7c, 2069 .enable_mask = BIT(0), 2070 .hw.init = &(struct clk_init_data){ 2071 .name = "gcc_sys_noc_ufs_axi_clk", 2072 .parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw }, 2073 .num_parents = 1, 2074 .flags = CLK_SET_RATE_PARENT, 2075 .ops = &clk_branch2_ops, 2076 }, 2077 }, 2078 }; 2079 2080 static struct clk_branch gcc_sys_noc_usb3_axi_clk = { 2081 .halt_reg = 0x03fc, 2082 .clkr = { 2083 .enable_reg = 0x03fc, 2084 .enable_mask = BIT(0), 2085 .hw.init = &(struct clk_init_data){ 2086 .name = "gcc_sys_noc_usb3_axi_clk", 2087 .parent_hws = (const struct clk_hw *[]){ &usb30_master_clk_src.clkr.hw }, 2088 .num_parents = 1, 2089 .flags = CLK_SET_RATE_PARENT, 2090 .ops = &clk_branch2_ops, 2091 }, 2092 }, 2093 }; 2094 2095 static struct clk_branch gcc_tsif_ahb_clk = { 2096 .halt_reg = 0x0d84, 2097 .clkr = { 2098 .enable_reg = 0x0d84, 2099 .enable_mask = BIT(0), 2100 .hw.init = &(struct clk_init_data){ 2101 .name = "gcc_tsif_ahb_clk", 2102 .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw }, 2103 .num_parents = 1, 2104 .ops = &clk_branch2_ops, 2105 }, 2106 }, 2107 }; 2108 2109 static struct clk_branch gcc_tsif_ref_clk = { 2110 .halt_reg = 0x0d88, 2111 .clkr = { 2112 .enable_reg = 0x0d88, 2113 .enable_mask = BIT(0), 2114 .hw.init = &(struct clk_init_data){ 2115 .name = "gcc_tsif_ref_clk", 2116 .parent_hws = (const struct clk_hw *[]){ &tsif_ref_clk_src.clkr.hw }, 2117 .num_parents = 1, 2118 .flags = CLK_SET_RATE_PARENT, 2119 .ops = &clk_branch2_ops, 2120 }, 2121 }, 2122 }; 2123 2124 static struct clk_branch gcc_ufs_ahb_clk = { 2125 .halt_reg = 0x1d4c, 2126 .clkr = { 2127 .enable_reg = 0x1d4c, 2128 .enable_mask = BIT(0), 2129 .hw.init = &(struct clk_init_data){ 2130 .name = "gcc_ufs_ahb_clk", 2131 .parent_hws = (const struct clk_hw *[]){ &config_noc_clk_src.clkr.hw }, 2132 .num_parents = 1, 2133 .ops = &clk_branch2_ops, 2134 }, 2135 }, 2136 }; 2137 2138 static struct clk_branch gcc_ufs_axi_clk = { 2139 .halt_reg = 0x1d48, 2140 .clkr = { 2141 .enable_reg = 0x1d48, 2142 .enable_mask = BIT(0), 2143 .hw.init = &(struct clk_init_data){ 2144 .name = "gcc_ufs_axi_clk", 2145 .parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw }, 2146 .num_parents = 1, 2147 .flags = CLK_SET_RATE_PARENT, 2148 .ops = &clk_branch2_ops, 2149 }, 2150 }, 2151 }; 2152 2153 static struct clk_branch gcc_ufs_rx_cfg_clk = { 2154 .halt_reg = 0x1d54, 2155 .clkr = { 2156 .enable_reg = 0x1d54, 2157 .enable_mask = BIT(0), 2158 .hw.init = &(struct clk_init_data){ 2159 .name = "gcc_ufs_rx_cfg_clk", 2160 .parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw }, 2161 .num_parents = 1, 2162 .flags = CLK_SET_RATE_PARENT, 2163 .ops = &clk_branch2_ops, 2164 }, 2165 }, 2166 }; 2167 2168 static struct clk_branch gcc_ufs_rx_symbol_0_clk = { 2169 .halt_reg = 0x1d60, 2170 .halt_check = BRANCH_HALT_DELAY, 2171 .clkr = { 2172 .enable_reg = 0x1d60, 2173 .enable_mask = BIT(0), 2174 .hw.init = &(struct clk_init_data){ 2175 .name = "gcc_ufs_rx_symbol_0_clk", 2176 .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw }, 2177 .num_parents = 1, 2178 .ops = &clk_branch2_ops, 2179 }, 2180 }, 2181 }; 2182 2183 static struct clk_branch gcc_ufs_rx_symbol_1_clk = { 2184 .halt_reg = 0x1d64, 2185 .halt_check = BRANCH_HALT_DELAY, 2186 .clkr = { 2187 .enable_reg = 0x1d64, 2188 .enable_mask = BIT(0), 2189 .hw.init = &(struct clk_init_data){ 2190 .name = "gcc_ufs_rx_symbol_1_clk", 2191 .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw }, 2192 .num_parents = 1, 2193 .ops = &clk_branch2_ops, 2194 }, 2195 }, 2196 }; 2197 2198 static struct clk_branch gcc_ufs_tx_cfg_clk = { 2199 .halt_reg = 0x1d50, 2200 .clkr = { 2201 .enable_reg = 0x1d50, 2202 .enable_mask = BIT(0), 2203 .hw.init = &(struct clk_init_data){ 2204 .name = "gcc_ufs_tx_cfg_clk", 2205 .parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw }, 2206 .num_parents = 1, 2207 .flags = CLK_SET_RATE_PARENT, 2208 .ops = &clk_branch2_ops, 2209 }, 2210 }, 2211 }; 2212 2213 static struct clk_branch gcc_ufs_tx_symbol_0_clk = { 2214 .halt_reg = 0x1d58, 2215 .halt_check = BRANCH_HALT_DELAY, 2216 .clkr = { 2217 .enable_reg = 0x1d58, 2218 .enable_mask = BIT(0), 2219 .hw.init = &(struct clk_init_data){ 2220 .name = "gcc_ufs_tx_symbol_0_clk", 2221 .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw }, 2222 .num_parents = 1, 2223 .ops = &clk_branch2_ops, 2224 }, 2225 }, 2226 }; 2227 2228 static struct clk_branch gcc_ufs_tx_symbol_1_clk = { 2229 .halt_reg = 0x1d5c, 2230 .halt_check = BRANCH_HALT_DELAY, 2231 .clkr = { 2232 .enable_reg = 0x1d5c, 2233 .enable_mask = BIT(0), 2234 .hw.init = &(struct clk_init_data){ 2235 .name = "gcc_ufs_tx_symbol_1_clk", 2236 .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw }, 2237 .num_parents = 1, 2238 .ops = &clk_branch2_ops, 2239 }, 2240 }, 2241 }; 2242 2243 static struct clk_branch gcc_usb2_hs_phy_sleep_clk = { 2244 .halt_reg = 0x04ac, 2245 .clkr = { 2246 .enable_reg = 0x04ac, 2247 .enable_mask = BIT(0), 2248 .hw.init = &(struct clk_init_data){ 2249 .name = "gcc_usb2_hs_phy_sleep_clk", 2250 .parent_data = &(const struct clk_parent_data){ 2251 .fw_name = "sleep", 2252 .name = "sleep" 2253 }, 2254 .num_parents = 1, 2255 .ops = &clk_branch2_ops, 2256 }, 2257 }, 2258 }; 2259 2260 static struct clk_branch gcc_usb30_master_clk = { 2261 .halt_reg = 0x03c8, 2262 .clkr = { 2263 .enable_reg = 0x03c8, 2264 .enable_mask = BIT(0), 2265 .hw.init = &(struct clk_init_data){ 2266 .name = "gcc_usb30_master_clk", 2267 .parent_hws = (const struct clk_hw *[]){ &usb30_master_clk_src.clkr.hw }, 2268 .num_parents = 1, 2269 .flags = CLK_SET_RATE_PARENT, 2270 .ops = &clk_branch2_ops, 2271 }, 2272 }, 2273 }; 2274 2275 static struct clk_branch gcc_usb30_mock_utmi_clk = { 2276 .halt_reg = 0x03d0, 2277 .clkr = { 2278 .enable_reg = 0x03d0, 2279 .enable_mask = BIT(0), 2280 .hw.init = &(struct clk_init_data){ 2281 .name = "gcc_usb30_mock_utmi_clk", 2282 .parent_hws = (const struct clk_hw *[]){ &usb30_mock_utmi_clk_src.clkr.hw }, 2283 .num_parents = 1, 2284 .flags = CLK_SET_RATE_PARENT, 2285 .ops = &clk_branch2_ops, 2286 }, 2287 }, 2288 }; 2289 2290 static struct clk_branch gcc_usb30_sleep_clk = { 2291 .halt_reg = 0x03cc, 2292 .clkr = { 2293 .enable_reg = 0x03cc, 2294 .enable_mask = BIT(0), 2295 .hw.init = &(struct clk_init_data){ 2296 .name = "gcc_usb30_sleep_clk", 2297 .parent_data = &(const struct clk_parent_data){ 2298 .fw_name = "sleep", 2299 .name = "sleep" 2300 }, 2301 .num_parents = 1, 2302 .ops = &clk_branch2_ops, 2303 }, 2304 }, 2305 }; 2306 2307 static struct clk_branch gcc_usb3_phy_aux_clk = { 2308 .halt_reg = 0x1408, 2309 .clkr = { 2310 .enable_reg = 0x1408, 2311 .enable_mask = BIT(0), 2312 .hw.init = &(struct clk_init_data){ 2313 .name = "gcc_usb3_phy_aux_clk", 2314 .parent_hws = (const struct clk_hw *[]){ &usb3_phy_aux_clk_src.clkr.hw }, 2315 .num_parents = 1, 2316 .flags = CLK_SET_RATE_PARENT, 2317 .ops = &clk_branch2_ops, 2318 }, 2319 }, 2320 }; 2321 2322 static struct clk_branch gcc_usb3_phy_pipe_clk = { 2323 .halt_reg = 0x140c, 2324 .halt_check = BRANCH_HALT_SKIP, 2325 .clkr = { 2326 .enable_reg = 0x140c, 2327 .enable_mask = BIT(0), 2328 .hw.init = &(struct clk_init_data){ 2329 .name = "gcc_usb3_phy_pipe_clk", 2330 .ops = &clk_branch2_ops, 2331 }, 2332 }, 2333 }; 2334 2335 static struct clk_branch gcc_usb_hs_ahb_clk = { 2336 .halt_reg = 0x0488, 2337 .clkr = { 2338 .enable_reg = 0x0488, 2339 .enable_mask = BIT(0), 2340 .hw.init = &(struct clk_init_data){ 2341 .name = "gcc_usb_hs_ahb_clk", 2342 .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw }, 2343 .num_parents = 1, 2344 .ops = &clk_branch2_ops, 2345 }, 2346 }, 2347 }; 2348 2349 static struct clk_branch gcc_usb_hs_system_clk = { 2350 .halt_reg = 0x0484, 2351 .clkr = { 2352 .enable_reg = 0x0484, 2353 .enable_mask = BIT(0), 2354 .hw.init = &(struct clk_init_data){ 2355 .name = "gcc_usb_hs_system_clk", 2356 .parent_hws = (const struct clk_hw *[]){ &usb_hs_system_clk_src.clkr.hw }, 2357 .num_parents = 1, 2358 .flags = CLK_SET_RATE_PARENT, 2359 .ops = &clk_branch2_ops, 2360 }, 2361 }, 2362 }; 2363 2364 static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = { 2365 .halt_reg = 0x1a84, 2366 .clkr = { 2367 .enable_reg = 0x1a84, 2368 .enable_mask = BIT(0), 2369 .hw.init = &(struct clk_init_data){ 2370 .name = "gcc_usb_phy_cfg_ahb2phy_clk", 2371 .ops = &clk_branch2_ops, 2372 }, 2373 }, 2374 }; 2375 2376 static struct clk_branch gpll0_out_mmsscc = { 2377 .halt_check = BRANCH_HALT_DELAY, 2378 .clkr = { 2379 .enable_reg = 0x1484, 2380 .enable_mask = BIT(26), 2381 .hw.init = &(struct clk_init_data){ 2382 .name = "gpll0_out_mmsscc", 2383 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw }, 2384 .num_parents = 1, 2385 .ops = &clk_branch2_ops, 2386 }, 2387 }, 2388 }; 2389 2390 static struct clk_branch gpll0_out_msscc = { 2391 .halt_check = BRANCH_HALT_DELAY, 2392 .clkr = { 2393 .enable_reg = 0x1484, 2394 .enable_mask = BIT(27), 2395 .hw.init = &(struct clk_init_data){ 2396 .name = "gpll0_out_msscc", 2397 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw }, 2398 .num_parents = 1, 2399 .ops = &clk_branch2_ops, 2400 }, 2401 }, 2402 }; 2403 2404 static struct clk_branch pcie_0_phy_ldo = { 2405 .halt_reg = 0x1e00, 2406 .halt_check = BRANCH_HALT_SKIP, 2407 .clkr = { 2408 .enable_reg = 0x1E00, 2409 .enable_mask = BIT(0), 2410 .hw.init = &(struct clk_init_data){ 2411 .name = "pcie_0_phy_ldo", 2412 .ops = &clk_branch2_ops, 2413 }, 2414 }, 2415 }; 2416 2417 static struct clk_branch pcie_1_phy_ldo = { 2418 .halt_reg = 0x1e04, 2419 .halt_check = BRANCH_HALT_SKIP, 2420 .clkr = { 2421 .enable_reg = 0x1E04, 2422 .enable_mask = BIT(0), 2423 .hw.init = &(struct clk_init_data){ 2424 .name = "pcie_1_phy_ldo", 2425 .ops = &clk_branch2_ops, 2426 }, 2427 }, 2428 }; 2429 2430 static struct clk_branch ufs_phy_ldo = { 2431 .halt_reg = 0x1e0c, 2432 .halt_check = BRANCH_HALT_SKIP, 2433 .clkr = { 2434 .enable_reg = 0x1E0C, 2435 .enable_mask = BIT(0), 2436 .hw.init = &(struct clk_init_data){ 2437 .name = "ufs_phy_ldo", 2438 .ops = &clk_branch2_ops, 2439 }, 2440 }, 2441 }; 2442 2443 static struct clk_branch usb_ss_phy_ldo = { 2444 .halt_reg = 0x1e08, 2445 .halt_check = BRANCH_HALT_SKIP, 2446 .clkr = { 2447 .enable_reg = 0x1E08, 2448 .enable_mask = BIT(0), 2449 .hw.init = &(struct clk_init_data){ 2450 .name = "usb_ss_phy_ldo", 2451 .ops = &clk_branch2_ops, 2452 }, 2453 }, 2454 }; 2455 2456 static struct clk_branch gcc_boot_rom_ahb_clk = { 2457 .halt_reg = 0x0e04, 2458 .halt_check = BRANCH_HALT_VOTED, 2459 .hwcg_reg = 0x0e04, 2460 .hwcg_bit = 1, 2461 .clkr = { 2462 .enable_reg = 0x1484, 2463 .enable_mask = BIT(10), 2464 .hw.init = &(struct clk_init_data){ 2465 .name = "gcc_boot_rom_ahb_clk", 2466 .parent_hws = (const struct clk_hw *[]){ &config_noc_clk_src.clkr.hw }, 2467 .num_parents = 1, 2468 .ops = &clk_branch2_ops, 2469 }, 2470 }, 2471 }; 2472 2473 static struct clk_branch gcc_prng_ahb_clk = { 2474 .halt_reg = 0x0d04, 2475 .halt_check = BRANCH_HALT_VOTED, 2476 .clkr = { 2477 .enable_reg = 0x1484, 2478 .enable_mask = BIT(13), 2479 .hw.init = &(struct clk_init_data){ 2480 .name = "gcc_prng_ahb_clk", 2481 .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw }, 2482 .num_parents = 1, 2483 .ops = &clk_branch2_ops, 2484 }, 2485 }, 2486 }; 2487 2488 static struct gdsc pcie_0_gdsc = { 2489 .gdscr = 0x1ac4, 2490 .pd = { 2491 .name = "pcie_0", 2492 }, 2493 .pwrsts = PWRSTS_OFF_ON, 2494 }; 2495 2496 static struct gdsc pcie_1_gdsc = { 2497 .gdscr = 0x1b44, 2498 .pd = { 2499 .name = "pcie_1", 2500 }, 2501 .pwrsts = PWRSTS_OFF_ON, 2502 }; 2503 2504 static struct gdsc usb30_gdsc = { 2505 .gdscr = 0x3c4, 2506 .pd = { 2507 .name = "usb30", 2508 }, 2509 .pwrsts = PWRSTS_OFF_ON, 2510 }; 2511 2512 static struct gdsc ufs_gdsc = { 2513 .gdscr = 0x1d44, 2514 .pd = { 2515 .name = "ufs", 2516 }, 2517 .pwrsts = PWRSTS_OFF_ON, 2518 }; 2519 2520 static struct clk_regmap *gcc_msm8994_clocks[] = { 2521 [GPLL0_EARLY] = &gpll0_early.clkr, 2522 [GPLL0] = &gpll0.clkr, 2523 [GPLL4_EARLY] = &gpll4_early.clkr, 2524 [GPLL4] = &gpll4.clkr, 2525 [CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr, 2526 [PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr, 2527 [SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr, 2528 [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr, 2529 [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr, 2530 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr, 2531 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr, 2532 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr, 2533 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr, 2534 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr, 2535 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr, 2536 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr, 2537 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr, 2538 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr, 2539 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr, 2540 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr, 2541 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr, 2542 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr, 2543 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr, 2544 [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr, 2545 [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr, 2546 [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr, 2547 [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr, 2548 [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr, 2549 [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr, 2550 [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr, 2551 [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr, 2552 [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr, 2553 [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr, 2554 [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr, 2555 [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr, 2556 [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr, 2557 [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr, 2558 [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr, 2559 [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr, 2560 [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr, 2561 [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr, 2562 [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr, 2563 [BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr, 2564 [BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr, 2565 [BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr, 2566 [GP1_CLK_SRC] = &gp1_clk_src.clkr, 2567 [GP2_CLK_SRC] = &gp2_clk_src.clkr, 2568 [GP3_CLK_SRC] = &gp3_clk_src.clkr, 2569 [PCIE_0_AUX_CLK_SRC] = &pcie_0_aux_clk_src.clkr, 2570 [PCIE_0_PIPE_CLK_SRC] = &pcie_0_pipe_clk_src.clkr, 2571 [PCIE_1_AUX_CLK_SRC] = &pcie_1_aux_clk_src.clkr, 2572 [PCIE_1_PIPE_CLK_SRC] = &pcie_1_pipe_clk_src.clkr, 2573 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr, 2574 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr, 2575 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr, 2576 [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr, 2577 [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr, 2578 [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr, 2579 [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr, 2580 [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr, 2581 [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr, 2582 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr, 2583 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr, 2584 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr, 2585 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr, 2586 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr, 2587 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr, 2588 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr, 2589 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr, 2590 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr, 2591 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr, 2592 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr, 2593 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr, 2594 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr, 2595 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, 2596 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr, 2597 [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr, 2598 [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr, 2599 [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr, 2600 [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr, 2601 [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr, 2602 [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr, 2603 [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr, 2604 [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr, 2605 [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr, 2606 [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr, 2607 [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr, 2608 [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr, 2609 [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr, 2610 [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr, 2611 [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr, 2612 [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr, 2613 [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr, 2614 [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr, 2615 [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr, 2616 [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr, 2617 [GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr, 2618 [GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr, 2619 [GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr, 2620 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 2621 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 2622 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 2623 [GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr, 2624 [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr, 2625 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, 2626 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, 2627 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, 2628 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, 2629 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, 2630 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr, 2631 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr, 2632 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr, 2633 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr, 2634 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr, 2635 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 2636 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 2637 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, 2638 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, 2639 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 2640 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 2641 [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr, 2642 [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr, 2643 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, 2644 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, 2645 [GCC_SYS_NOC_UFS_AXI_CLK] = &gcc_sys_noc_ufs_axi_clk.clkr, 2646 [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr, 2647 [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr, 2648 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr, 2649 [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr, 2650 [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr, 2651 [GCC_UFS_RX_CFG_CLK] = &gcc_ufs_rx_cfg_clk.clkr, 2652 [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr, 2653 [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr, 2654 [GCC_UFS_TX_CFG_CLK] = &gcc_ufs_tx_cfg_clk.clkr, 2655 [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr, 2656 [GCC_UFS_TX_SYMBOL_1_CLK] = &gcc_ufs_tx_symbol_1_clk.clkr, 2657 [GCC_USB2_HS_PHY_SLEEP_CLK] = &gcc_usb2_hs_phy_sleep_clk.clkr, 2658 [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr, 2659 [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr, 2660 [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr, 2661 [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr, 2662 [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr, 2663 [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr, 2664 [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr, 2665 [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr, 2666 [GPLL0_OUT_MMSSCC] = &gpll0_out_mmsscc.clkr, 2667 [GPLL0_OUT_MSSCC] = &gpll0_out_msscc.clkr, 2668 [PCIE_0_PHY_LDO] = &pcie_0_phy_ldo.clkr, 2669 [PCIE_1_PHY_LDO] = &pcie_1_phy_ldo.clkr, 2670 [UFS_PHY_LDO] = &ufs_phy_ldo.clkr, 2671 [USB_SS_PHY_LDO] = &usb_ss_phy_ldo.clkr, 2672 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 2673 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, 2674 }; 2675 2676 static struct gdsc *gcc_msm8994_gdscs[] = { 2677 /* This GDSC does not exist, but ABI has to remain intact */ 2678 [PCIE_GDSC] = NULL, 2679 [PCIE_0_GDSC] = &pcie_0_gdsc, 2680 [PCIE_1_GDSC] = &pcie_1_gdsc, 2681 [USB30_GDSC] = &usb30_gdsc, 2682 [UFS_GDSC] = &ufs_gdsc, 2683 }; 2684 2685 static const struct qcom_reset_map gcc_msm8994_resets[] = { 2686 [USB3_PHY_RESET] = { 0x1400 }, 2687 [USB3PHY_PHY_RESET] = { 0x1404 }, 2688 [MSS_RESET] = { 0x1680 }, 2689 [PCIE_PHY_0_RESET] = { 0x1b18 }, 2690 [PCIE_PHY_1_RESET] = { 0x1b98 }, 2691 [QUSB2_PHY_RESET] = { 0x04b8 }, 2692 }; 2693 2694 static const struct regmap_config gcc_msm8994_regmap_config = { 2695 .reg_bits = 32, 2696 .reg_stride = 4, 2697 .val_bits = 32, 2698 .max_register = 0x2000, 2699 .fast_io = true, 2700 }; 2701 2702 static const struct qcom_cc_desc gcc_msm8994_desc = { 2703 .config = &gcc_msm8994_regmap_config, 2704 .clks = gcc_msm8994_clocks, 2705 .num_clks = ARRAY_SIZE(gcc_msm8994_clocks), 2706 .resets = gcc_msm8994_resets, 2707 .num_resets = ARRAY_SIZE(gcc_msm8994_resets), 2708 .gdscs = gcc_msm8994_gdscs, 2709 .num_gdscs = ARRAY_SIZE(gcc_msm8994_gdscs), 2710 }; 2711 2712 static const struct of_device_id gcc_msm8994_match_table[] = { 2713 { .compatible = "qcom,gcc-msm8994" }, 2714 {} 2715 }; 2716 MODULE_DEVICE_TABLE(of, gcc_msm8994_match_table); 2717 2718 static int gcc_msm8994_probe(struct platform_device *pdev) 2719 { 2720 return qcom_cc_probe(pdev, &gcc_msm8994_desc); 2721 } 2722 2723 static struct platform_driver gcc_msm8994_driver = { 2724 .probe = gcc_msm8994_probe, 2725 .driver = { 2726 .name = "gcc-msm8994", 2727 .of_match_table = gcc_msm8994_match_table, 2728 }, 2729 }; 2730 2731 static int __init gcc_msm8994_init(void) 2732 { 2733 return platform_driver_register(&gcc_msm8994_driver); 2734 } 2735 core_initcall(gcc_msm8994_init); 2736 2737 static void __exit gcc_msm8994_exit(void) 2738 { 2739 platform_driver_unregister(&gcc_msm8994_driver); 2740 } 2741 module_exit(gcc_msm8994_exit); 2742 2743 MODULE_DESCRIPTION("Qualcomm GCC MSM8994 Driver"); 2744 MODULE_LICENSE("GPL v2"); 2745 MODULE_ALIAS("platform:gcc-msm8994"); 2746