1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. 3 */ 4 5 #include <linux/kernel.h> 6 #include <linux/init.h> 7 #include <linux/err.h> 8 #include <linux/ctype.h> 9 #include <linux/io.h> 10 #include <linux/of.h> 11 #include <linux/platform_device.h> 12 #include <linux/module.h> 13 #include <linux/regmap.h> 14 15 #include <dt-bindings/clock/qcom,gcc-msm8994.h> 16 17 #include "common.h" 18 #include "clk-regmap.h" 19 #include "clk-alpha-pll.h" 20 #include "clk-rcg.h" 21 #include "clk-branch.h" 22 #include "reset.h" 23 #include "gdsc.h" 24 25 enum { 26 P_XO, 27 P_GPLL0, 28 P_GPLL4, 29 }; 30 31 static struct clk_alpha_pll gpll0_early = { 32 .offset = 0, 33 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 34 .clkr = { 35 .enable_reg = 0x1480, 36 .enable_mask = BIT(0), 37 .hw.init = &(struct clk_init_data){ 38 .name = "gpll0_early", 39 .parent_data = &(const struct clk_parent_data){ 40 .fw_name = "xo", 41 }, 42 .num_parents = 1, 43 .ops = &clk_alpha_pll_ops, 44 }, 45 }, 46 }; 47 48 static struct clk_alpha_pll_postdiv gpll0 = { 49 .offset = 0, 50 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 51 .clkr.hw.init = &(struct clk_init_data){ 52 .name = "gpll0", 53 .parent_names = (const char *[]) { "gpll0_early" }, 54 .num_parents = 1, 55 .ops = &clk_alpha_pll_postdiv_ops, 56 }, 57 }; 58 59 static struct clk_alpha_pll gpll4_early = { 60 .offset = 0x1dc0, 61 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 62 .clkr = { 63 .enable_reg = 0x1480, 64 .enable_mask = BIT(4), 65 .hw.init = &(struct clk_init_data){ 66 .name = "gpll4_early", 67 .parent_data = &(const struct clk_parent_data){ 68 .fw_name = "xo", 69 }, 70 .num_parents = 1, 71 .ops = &clk_alpha_pll_ops, 72 }, 73 }, 74 }; 75 76 static struct clk_alpha_pll_postdiv gpll4 = { 77 .offset = 0x1dc0, 78 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 79 .clkr.hw.init = &(struct clk_init_data){ 80 .name = "gpll4", 81 .parent_names = (const char *[]) { "gpll4_early" }, 82 .num_parents = 1, 83 .ops = &clk_alpha_pll_postdiv_ops, 84 }, 85 }; 86 87 static const struct parent_map gcc_xo_gpll0_map[] = { 88 { P_XO, 0 }, 89 { P_GPLL0, 1 }, 90 }; 91 92 static const struct clk_parent_data gcc_xo_gpll0[] = { 93 { .fw_name = "xo" }, 94 { .hw = &gpll0.clkr.hw }, 95 }; 96 97 static const struct parent_map gcc_xo_gpll0_gpll4_map[] = { 98 { P_XO, 0 }, 99 { P_GPLL0, 1 }, 100 { P_GPLL4, 5 }, 101 }; 102 103 static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = { 104 { .fw_name = "xo" }, 105 { .hw = &gpll0.clkr.hw }, 106 { .hw = &gpll4.clkr.hw }, 107 }; 108 109 static struct freq_tbl ftbl_ufs_axi_clk_src[] = { 110 F(50000000, P_GPLL0, 12, 0, 0), 111 F(100000000, P_GPLL0, 6, 0, 0), 112 F(150000000, P_GPLL0, 4, 0, 0), 113 F(171430000, P_GPLL0, 3.5, 0, 0), 114 F(200000000, P_GPLL0, 3, 0, 0), 115 F(240000000, P_GPLL0, 2.5, 0, 0), 116 { } 117 }; 118 119 static struct clk_rcg2 ufs_axi_clk_src = { 120 .cmd_rcgr = 0x1d68, 121 .mnd_width = 8, 122 .hid_width = 5, 123 .parent_map = gcc_xo_gpll0_map, 124 .freq_tbl = ftbl_ufs_axi_clk_src, 125 .clkr.hw.init = &(struct clk_init_data){ 126 .name = "ufs_axi_clk_src", 127 .parent_data = gcc_xo_gpll0, 128 .num_parents = 2, 129 .ops = &clk_rcg2_ops, 130 }, 131 }; 132 133 static struct freq_tbl ftbl_usb30_master_clk_src[] = { 134 F(19200000, P_XO, 1, 0, 0), 135 F(125000000, P_GPLL0, 1, 5, 24), 136 { } 137 }; 138 139 static struct clk_rcg2 usb30_master_clk_src = { 140 .cmd_rcgr = 0x03d4, 141 .mnd_width = 8, 142 .hid_width = 5, 143 .parent_map = gcc_xo_gpll0_map, 144 .freq_tbl = ftbl_usb30_master_clk_src, 145 .clkr.hw.init = &(struct clk_init_data){ 146 .name = "usb30_master_clk_src", 147 .parent_data = gcc_xo_gpll0, 148 .num_parents = 2, 149 .ops = &clk_rcg2_ops, 150 }, 151 }; 152 153 static struct freq_tbl ftbl_blsp_i2c_apps_clk_src[] = { 154 F(19200000, P_XO, 1, 0, 0), 155 F(50000000, P_GPLL0, 12, 0, 0), 156 { } 157 }; 158 159 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { 160 .cmd_rcgr = 0x0660, 161 .hid_width = 5, 162 .parent_map = gcc_xo_gpll0_map, 163 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 164 .clkr.hw.init = &(struct clk_init_data){ 165 .name = "blsp1_qup1_i2c_apps_clk_src", 166 .parent_data = gcc_xo_gpll0, 167 .num_parents = 2, 168 .ops = &clk_rcg2_ops, 169 }, 170 }; 171 172 static struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = { 173 F(960000, P_XO, 10, 1, 2), 174 F(4800000, P_XO, 4, 0, 0), 175 F(9600000, P_XO, 2, 0, 0), 176 F(15000000, P_GPLL0, 10, 1, 4), 177 F(19200000, P_XO, 1, 0, 0), 178 F(24000000, P_GPLL0, 12.5, 1, 2), 179 F(25000000, P_GPLL0, 12, 1, 2), 180 F(48000000, P_GPLL0, 12.5, 0, 0), 181 F(50000000, P_GPLL0, 12, 0, 0), 182 { } 183 }; 184 185 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { 186 .cmd_rcgr = 0x064c, 187 .mnd_width = 8, 188 .hid_width = 5, 189 .parent_map = gcc_xo_gpll0_map, 190 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 191 .clkr.hw.init = &(struct clk_init_data){ 192 .name = "blsp1_qup1_spi_apps_clk_src", 193 .parent_data = gcc_xo_gpll0, 194 .num_parents = 2, 195 .ops = &clk_rcg2_ops, 196 }, 197 }; 198 199 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { 200 .cmd_rcgr = 0x06e0, 201 .hid_width = 5, 202 .parent_map = gcc_xo_gpll0_map, 203 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 204 .clkr.hw.init = &(struct clk_init_data){ 205 .name = "blsp1_qup2_i2c_apps_clk_src", 206 .parent_data = gcc_xo_gpll0, 207 .num_parents = 2, 208 .ops = &clk_rcg2_ops, 209 }, 210 }; 211 212 static struct freq_tbl ftbl_blsp1_qup2_spi_apps_clk_src[] = { 213 F(960000, P_XO, 10, 1, 2), 214 F(4800000, P_XO, 4, 0, 0), 215 F(9600000, P_XO, 2, 0, 0), 216 F(15000000, P_GPLL0, 10, 1, 4), 217 F(19200000, P_XO, 1, 0, 0), 218 F(24000000, P_GPLL0, 12.5, 1, 2), 219 F(25000000, P_GPLL0, 12, 1, 2), 220 F(42860000, P_GPLL0, 14, 0, 0), 221 F(46150000, P_GPLL0, 13, 0, 0), 222 { } 223 }; 224 225 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { 226 .cmd_rcgr = 0x06cc, 227 .mnd_width = 8, 228 .hid_width = 5, 229 .parent_map = gcc_xo_gpll0_map, 230 .freq_tbl = ftbl_blsp1_qup2_spi_apps_clk_src, 231 .clkr.hw.init = &(struct clk_init_data){ 232 .name = "blsp1_qup2_spi_apps_clk_src", 233 .parent_data = gcc_xo_gpll0, 234 .num_parents = 2, 235 .ops = &clk_rcg2_ops, 236 }, 237 }; 238 239 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { 240 .cmd_rcgr = 0x0760, 241 .hid_width = 5, 242 .parent_map = gcc_xo_gpll0_map, 243 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 244 .clkr.hw.init = &(struct clk_init_data){ 245 .name = "blsp1_qup3_i2c_apps_clk_src", 246 .parent_data = gcc_xo_gpll0, 247 .num_parents = 2, 248 .ops = &clk_rcg2_ops, 249 }, 250 }; 251 252 static struct freq_tbl ftbl_blsp1_qup3_4_spi_apps_clk_src[] = { 253 F(960000, P_XO, 10, 1, 2), 254 F(4800000, P_XO, 4, 0, 0), 255 F(9600000, P_XO, 2, 0, 0), 256 F(15000000, P_GPLL0, 10, 1, 4), 257 F(19200000, P_XO, 1, 0, 0), 258 F(24000000, P_GPLL0, 12.5, 1, 2), 259 F(25000000, P_GPLL0, 12, 1, 2), 260 F(42860000, P_GPLL0, 14, 0, 0), 261 F(44440000, P_GPLL0, 13.5, 0, 0), 262 { } 263 }; 264 265 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { 266 .cmd_rcgr = 0x074c, 267 .mnd_width = 8, 268 .hid_width = 5, 269 .parent_map = gcc_xo_gpll0_map, 270 .freq_tbl = ftbl_blsp1_qup3_4_spi_apps_clk_src, 271 .clkr.hw.init = &(struct clk_init_data){ 272 .name = "blsp1_qup3_spi_apps_clk_src", 273 .parent_data = gcc_xo_gpll0, 274 .num_parents = 2, 275 .ops = &clk_rcg2_ops, 276 }, 277 }; 278 279 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { 280 .cmd_rcgr = 0x07e0, 281 .hid_width = 5, 282 .parent_map = gcc_xo_gpll0_map, 283 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 284 .clkr.hw.init = &(struct clk_init_data){ 285 .name = "blsp1_qup4_i2c_apps_clk_src", 286 .parent_data = gcc_xo_gpll0, 287 .num_parents = 2, 288 .ops = &clk_rcg2_ops, 289 }, 290 }; 291 292 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { 293 .cmd_rcgr = 0x07cc, 294 .mnd_width = 8, 295 .hid_width = 5, 296 .parent_map = gcc_xo_gpll0_map, 297 .freq_tbl = ftbl_blsp1_qup3_4_spi_apps_clk_src, 298 .clkr.hw.init = &(struct clk_init_data){ 299 .name = "blsp1_qup4_spi_apps_clk_src", 300 .parent_data = gcc_xo_gpll0, 301 .num_parents = 2, 302 .ops = &clk_rcg2_ops, 303 }, 304 }; 305 306 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = { 307 .cmd_rcgr = 0x0860, 308 .hid_width = 5, 309 .parent_map = gcc_xo_gpll0_map, 310 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 311 .clkr.hw.init = &(struct clk_init_data){ 312 .name = "blsp1_qup5_i2c_apps_clk_src", 313 .parent_data = gcc_xo_gpll0, 314 .num_parents = 2, 315 .ops = &clk_rcg2_ops, 316 }, 317 }; 318 319 static struct freq_tbl ftbl_blsp1_qup5_spi_apps_clk_src[] = { 320 F(960000, P_XO, 10, 1, 2), 321 F(4800000, P_XO, 4, 0, 0), 322 F(9600000, P_XO, 2, 0, 0), 323 F(15000000, P_GPLL0, 10, 1, 4), 324 F(19200000, P_XO, 1, 0, 0), 325 F(24000000, P_GPLL0, 12.5, 1, 2), 326 F(25000000, P_GPLL0, 12, 1, 2), 327 F(40000000, P_GPLL0, 15, 0, 0), 328 F(42860000, P_GPLL0, 14, 0, 0), 329 { } 330 }; 331 332 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = { 333 .cmd_rcgr = 0x084c, 334 .mnd_width = 8, 335 .hid_width = 5, 336 .parent_map = gcc_xo_gpll0_map, 337 .freq_tbl = ftbl_blsp1_qup5_spi_apps_clk_src, 338 .clkr.hw.init = &(struct clk_init_data){ 339 .name = "blsp1_qup5_spi_apps_clk_src", 340 .parent_data = gcc_xo_gpll0, 341 .num_parents = 2, 342 .ops = &clk_rcg2_ops, 343 }, 344 }; 345 346 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = { 347 .cmd_rcgr = 0x08e0, 348 .hid_width = 5, 349 .parent_map = gcc_xo_gpll0_map, 350 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 351 .clkr.hw.init = &(struct clk_init_data){ 352 .name = "blsp1_qup6_i2c_apps_clk_src", 353 .parent_data = gcc_xo_gpll0, 354 .num_parents = 2, 355 .ops = &clk_rcg2_ops, 356 }, 357 }; 358 359 static struct freq_tbl ftbl_blsp1_qup6_spi_apps_clk_src[] = { 360 F(960000, P_XO, 10, 1, 2), 361 F(4800000, P_XO, 4, 0, 0), 362 F(9600000, P_XO, 2, 0, 0), 363 F(15000000, P_GPLL0, 10, 1, 4), 364 F(19200000, P_XO, 1, 0, 0), 365 F(24000000, P_GPLL0, 12.5, 1, 2), 366 F(27906976, P_GPLL0, 1, 2, 43), 367 F(41380000, P_GPLL0, 15, 0, 0), 368 F(42860000, P_GPLL0, 14, 0, 0), 369 { } 370 }; 371 372 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = { 373 .cmd_rcgr = 0x08cc, 374 .mnd_width = 8, 375 .hid_width = 5, 376 .parent_map = gcc_xo_gpll0_map, 377 .freq_tbl = ftbl_blsp1_qup6_spi_apps_clk_src, 378 .clkr.hw.init = &(struct clk_init_data){ 379 .name = "blsp1_qup6_spi_apps_clk_src", 380 .parent_data = gcc_xo_gpll0, 381 .num_parents = 2, 382 .ops = &clk_rcg2_ops, 383 }, 384 }; 385 386 static struct freq_tbl ftbl_blsp_uart_apps_clk_src[] = { 387 F(3686400, P_GPLL0, 1, 96, 15625), 388 F(7372800, P_GPLL0, 1, 192, 15625), 389 F(14745600, P_GPLL0, 1, 384, 15625), 390 F(16000000, P_GPLL0, 5, 2, 15), 391 F(19200000, P_XO, 1, 0, 0), 392 F(24000000, P_GPLL0, 5, 1, 5), 393 F(32000000, P_GPLL0, 1, 4, 75), 394 F(40000000, P_GPLL0, 15, 0, 0), 395 F(46400000, P_GPLL0, 1, 29, 375), 396 F(48000000, P_GPLL0, 12.5, 0, 0), 397 F(51200000, P_GPLL0, 1, 32, 375), 398 F(56000000, P_GPLL0, 1, 7, 75), 399 F(58982400, P_GPLL0, 1, 1536, 15625), 400 F(60000000, P_GPLL0, 10, 0, 0), 401 F(63160000, P_GPLL0, 9.5, 0, 0), 402 { } 403 }; 404 405 static struct clk_rcg2 blsp1_uart1_apps_clk_src = { 406 .cmd_rcgr = 0x068c, 407 .mnd_width = 16, 408 .hid_width = 5, 409 .parent_map = gcc_xo_gpll0_map, 410 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 411 .clkr.hw.init = &(struct clk_init_data){ 412 .name = "blsp1_uart1_apps_clk_src", 413 .parent_data = gcc_xo_gpll0, 414 .num_parents = 2, 415 .ops = &clk_rcg2_ops, 416 }, 417 }; 418 419 static struct clk_rcg2 blsp1_uart2_apps_clk_src = { 420 .cmd_rcgr = 0x070c, 421 .mnd_width = 16, 422 .hid_width = 5, 423 .parent_map = gcc_xo_gpll0_map, 424 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 425 .clkr.hw.init = &(struct clk_init_data){ 426 .name = "blsp1_uart2_apps_clk_src", 427 .parent_data = gcc_xo_gpll0, 428 .num_parents = 2, 429 .ops = &clk_rcg2_ops, 430 }, 431 }; 432 433 static struct clk_rcg2 blsp1_uart3_apps_clk_src = { 434 .cmd_rcgr = 0x078c, 435 .mnd_width = 16, 436 .hid_width = 5, 437 .parent_map = gcc_xo_gpll0_map, 438 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 439 .clkr.hw.init = &(struct clk_init_data){ 440 .name = "blsp1_uart3_apps_clk_src", 441 .parent_data = gcc_xo_gpll0, 442 .num_parents = 2, 443 .ops = &clk_rcg2_ops, 444 }, 445 }; 446 447 static struct clk_rcg2 blsp1_uart4_apps_clk_src = { 448 .cmd_rcgr = 0x080c, 449 .mnd_width = 16, 450 .hid_width = 5, 451 .parent_map = gcc_xo_gpll0_map, 452 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 453 .clkr.hw.init = &(struct clk_init_data){ 454 .name = "blsp1_uart4_apps_clk_src", 455 .parent_data = gcc_xo_gpll0, 456 .num_parents = 2, 457 .ops = &clk_rcg2_ops, 458 }, 459 }; 460 461 static struct clk_rcg2 blsp1_uart5_apps_clk_src = { 462 .cmd_rcgr = 0x088c, 463 .mnd_width = 16, 464 .hid_width = 5, 465 .parent_map = gcc_xo_gpll0_map, 466 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 467 .clkr.hw.init = &(struct clk_init_data){ 468 .name = "blsp1_uart5_apps_clk_src", 469 .parent_data = gcc_xo_gpll0, 470 .num_parents = 2, 471 .ops = &clk_rcg2_ops, 472 }, 473 }; 474 475 static struct clk_rcg2 blsp1_uart6_apps_clk_src = { 476 .cmd_rcgr = 0x090c, 477 .mnd_width = 16, 478 .hid_width = 5, 479 .parent_map = gcc_xo_gpll0_map, 480 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 481 .clkr.hw.init = &(struct clk_init_data){ 482 .name = "blsp1_uart6_apps_clk_src", 483 .parent_data = gcc_xo_gpll0, 484 .num_parents = 2, 485 .ops = &clk_rcg2_ops, 486 }, 487 }; 488 489 static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = { 490 .cmd_rcgr = 0x09a0, 491 .hid_width = 5, 492 .parent_map = gcc_xo_gpll0_map, 493 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 494 .clkr.hw.init = &(struct clk_init_data){ 495 .name = "blsp2_qup1_i2c_apps_clk_src", 496 .parent_data = gcc_xo_gpll0, 497 .num_parents = 2, 498 .ops = &clk_rcg2_ops, 499 }, 500 }; 501 502 static struct freq_tbl ftbl_blsp2_qup1_2_spi_apps_clk_src[] = { 503 F(960000, P_XO, 10, 1, 2), 504 F(4800000, P_XO, 4, 0, 0), 505 F(9600000, P_XO, 2, 0, 0), 506 F(15000000, P_GPLL0, 10, 1, 4), 507 F(19200000, P_XO, 1, 0, 0), 508 F(24000000, P_GPLL0, 12.5, 1, 2), 509 F(25000000, P_GPLL0, 12, 1, 2), 510 F(42860000, P_GPLL0, 14, 0, 0), 511 F(44440000, P_GPLL0, 13.5, 0, 0), 512 { } 513 }; 514 515 static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = { 516 .cmd_rcgr = 0x098c, 517 .mnd_width = 8, 518 .hid_width = 5, 519 .parent_map = gcc_xo_gpll0_map, 520 .freq_tbl = ftbl_blsp2_qup1_2_spi_apps_clk_src, 521 .clkr.hw.init = &(struct clk_init_data){ 522 .name = "blsp2_qup1_spi_apps_clk_src", 523 .parent_data = gcc_xo_gpll0, 524 .num_parents = 2, 525 .ops = &clk_rcg2_ops, 526 }, 527 }; 528 529 static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = { 530 .cmd_rcgr = 0x0a20, 531 .hid_width = 5, 532 .parent_map = gcc_xo_gpll0_map, 533 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 534 .clkr.hw.init = &(struct clk_init_data){ 535 .name = "blsp2_qup2_i2c_apps_clk_src", 536 .parent_data = gcc_xo_gpll0, 537 .num_parents = 2, 538 .ops = &clk_rcg2_ops, 539 }, 540 }; 541 542 static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = { 543 .cmd_rcgr = 0x0a0c, 544 .mnd_width = 8, 545 .hid_width = 5, 546 .parent_map = gcc_xo_gpll0_map, 547 .freq_tbl = ftbl_blsp2_qup1_2_spi_apps_clk_src, 548 .clkr.hw.init = &(struct clk_init_data){ 549 .name = "blsp2_qup2_spi_apps_clk_src", 550 .parent_data = gcc_xo_gpll0, 551 .num_parents = 2, 552 .ops = &clk_rcg2_ops, 553 }, 554 }; 555 556 static struct freq_tbl ftbl_blsp2_qup3_4_spi_apps_clk_src[] = { 557 F(960000, P_XO, 10, 1, 2), 558 F(4800000, P_XO, 4, 0, 0), 559 F(9600000, P_XO, 2, 0, 0), 560 F(15000000, P_GPLL0, 10, 1, 4), 561 F(19200000, P_XO, 1, 0, 0), 562 F(24000000, P_GPLL0, 12.5, 1, 2), 563 F(25000000, P_GPLL0, 12, 1, 2), 564 F(42860000, P_GPLL0, 14, 0, 0), 565 F(48000000, P_GPLL0, 12.5, 0, 0), 566 { } 567 }; 568 569 static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = { 570 .cmd_rcgr = 0x0aa0, 571 .hid_width = 5, 572 .parent_map = gcc_xo_gpll0_map, 573 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 574 .clkr.hw.init = &(struct clk_init_data){ 575 .name = "blsp2_qup3_i2c_apps_clk_src", 576 .parent_data = gcc_xo_gpll0, 577 .num_parents = 2, 578 .ops = &clk_rcg2_ops, 579 }, 580 }; 581 582 static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = { 583 .cmd_rcgr = 0x0a8c, 584 .mnd_width = 8, 585 .hid_width = 5, 586 .parent_map = gcc_xo_gpll0_map, 587 .freq_tbl = ftbl_blsp2_qup3_4_spi_apps_clk_src, 588 .clkr.hw.init = &(struct clk_init_data){ 589 .name = "blsp2_qup3_spi_apps_clk_src", 590 .parent_data = gcc_xo_gpll0, 591 .num_parents = 2, 592 .ops = &clk_rcg2_ops, 593 }, 594 }; 595 596 static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = { 597 .cmd_rcgr = 0x0b20, 598 .hid_width = 5, 599 .parent_map = gcc_xo_gpll0_map, 600 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 601 .clkr.hw.init = &(struct clk_init_data){ 602 .name = "blsp2_qup4_i2c_apps_clk_src", 603 .parent_data = gcc_xo_gpll0, 604 .num_parents = 2, 605 .ops = &clk_rcg2_ops, 606 }, 607 }; 608 609 static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = { 610 .cmd_rcgr = 0x0b0c, 611 .mnd_width = 8, 612 .hid_width = 5, 613 .parent_map = gcc_xo_gpll0_map, 614 .freq_tbl = ftbl_blsp2_qup3_4_spi_apps_clk_src, 615 .clkr.hw.init = &(struct clk_init_data){ 616 .name = "blsp2_qup4_spi_apps_clk_src", 617 .parent_data = gcc_xo_gpll0, 618 .num_parents = 2, 619 .ops = &clk_rcg2_ops, 620 }, 621 }; 622 623 static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = { 624 .cmd_rcgr = 0x0ba0, 625 .hid_width = 5, 626 .parent_map = gcc_xo_gpll0_map, 627 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 628 .clkr.hw.init = &(struct clk_init_data){ 629 .name = "blsp2_qup5_i2c_apps_clk_src", 630 .parent_data = gcc_xo_gpll0, 631 .num_parents = 2, 632 .ops = &clk_rcg2_ops, 633 }, 634 }; 635 636 static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = { 637 .cmd_rcgr = 0x0b8c, 638 .mnd_width = 8, 639 .hid_width = 5, 640 .parent_map = gcc_xo_gpll0_map, 641 /* BLSP1 QUP1 and BLSP2 QUP5 use the same freqs */ 642 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 643 .clkr.hw.init = &(struct clk_init_data){ 644 .name = "blsp2_qup5_spi_apps_clk_src", 645 .parent_data = gcc_xo_gpll0, 646 .num_parents = 2, 647 .ops = &clk_rcg2_ops, 648 }, 649 }; 650 651 static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = { 652 .cmd_rcgr = 0x0c20, 653 .hid_width = 5, 654 .parent_map = gcc_xo_gpll0_map, 655 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 656 .clkr.hw.init = &(struct clk_init_data){ 657 .name = "blsp2_qup6_i2c_apps_clk_src", 658 .parent_data = gcc_xo_gpll0, 659 .num_parents = 2, 660 .ops = &clk_rcg2_ops, 661 }, 662 }; 663 664 static struct freq_tbl ftbl_blsp2_qup6_spi_apps_clk_src[] = { 665 F(960000, P_XO, 10, 1, 2), 666 F(4800000, P_XO, 4, 0, 0), 667 F(9600000, P_XO, 2, 0, 0), 668 F(15000000, P_GPLL0, 10, 1, 4), 669 F(19200000, P_XO, 1, 0, 0), 670 F(24000000, P_GPLL0, 12.5, 1, 2), 671 F(25000000, P_GPLL0, 12, 1, 2), 672 F(44440000, P_GPLL0, 13.5, 0, 0), 673 F(48000000, P_GPLL0, 12.5, 0, 0), 674 { } 675 }; 676 677 static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = { 678 .cmd_rcgr = 0x0c0c, 679 .mnd_width = 8, 680 .hid_width = 5, 681 .parent_map = gcc_xo_gpll0_map, 682 .freq_tbl = ftbl_blsp2_qup6_spi_apps_clk_src, 683 .clkr.hw.init = &(struct clk_init_data){ 684 .name = "blsp2_qup6_spi_apps_clk_src", 685 .parent_data = gcc_xo_gpll0, 686 .num_parents = 2, 687 .ops = &clk_rcg2_ops, 688 }, 689 }; 690 691 static struct clk_rcg2 blsp2_uart1_apps_clk_src = { 692 .cmd_rcgr = 0x09cc, 693 .mnd_width = 16, 694 .hid_width = 5, 695 .parent_map = gcc_xo_gpll0_map, 696 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 697 .clkr.hw.init = &(struct clk_init_data){ 698 .name = "blsp2_uart1_apps_clk_src", 699 .parent_data = gcc_xo_gpll0, 700 .num_parents = 2, 701 .ops = &clk_rcg2_ops, 702 }, 703 }; 704 705 static struct clk_rcg2 blsp2_uart2_apps_clk_src = { 706 .cmd_rcgr = 0x0a4c, 707 .mnd_width = 16, 708 .hid_width = 5, 709 .parent_map = gcc_xo_gpll0_map, 710 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 711 .clkr.hw.init = &(struct clk_init_data){ 712 .name = "blsp2_uart2_apps_clk_src", 713 .parent_data = gcc_xo_gpll0, 714 .num_parents = 2, 715 .ops = &clk_rcg2_ops, 716 }, 717 }; 718 719 static struct clk_rcg2 blsp2_uart3_apps_clk_src = { 720 .cmd_rcgr = 0x0acc, 721 .mnd_width = 16, 722 .hid_width = 5, 723 .parent_map = gcc_xo_gpll0_map, 724 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 725 .clkr.hw.init = &(struct clk_init_data){ 726 .name = "blsp2_uart3_apps_clk_src", 727 .parent_data = gcc_xo_gpll0, 728 .num_parents = 2, 729 .ops = &clk_rcg2_ops, 730 }, 731 }; 732 733 static struct clk_rcg2 blsp2_uart4_apps_clk_src = { 734 .cmd_rcgr = 0x0b4c, 735 .mnd_width = 16, 736 .hid_width = 5, 737 .parent_map = gcc_xo_gpll0_map, 738 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 739 .clkr.hw.init = &(struct clk_init_data){ 740 .name = "blsp2_uart4_apps_clk_src", 741 .parent_data = gcc_xo_gpll0, 742 .num_parents = 2, 743 .ops = &clk_rcg2_ops, 744 }, 745 }; 746 747 static struct clk_rcg2 blsp2_uart5_apps_clk_src = { 748 .cmd_rcgr = 0x0bcc, 749 .mnd_width = 16, 750 .hid_width = 5, 751 .parent_map = gcc_xo_gpll0_map, 752 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 753 .clkr.hw.init = &(struct clk_init_data){ 754 .name = "blsp2_uart5_apps_clk_src", 755 .parent_data = gcc_xo_gpll0, 756 .num_parents = 2, 757 .ops = &clk_rcg2_ops, 758 }, 759 }; 760 761 static struct clk_rcg2 blsp2_uart6_apps_clk_src = { 762 .cmd_rcgr = 0x0c4c, 763 .mnd_width = 16, 764 .hid_width = 5, 765 .parent_map = gcc_xo_gpll0_map, 766 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 767 .clkr.hw.init = &(struct clk_init_data){ 768 .name = "blsp2_uart6_apps_clk_src", 769 .parent_data = gcc_xo_gpll0, 770 .num_parents = 2, 771 .ops = &clk_rcg2_ops, 772 }, 773 }; 774 775 static struct freq_tbl ftbl_gp1_clk_src[] = { 776 F(19200000, P_XO, 1, 0, 0), 777 F(100000000, P_GPLL0, 6, 0, 0), 778 F(200000000, P_GPLL0, 3, 0, 0), 779 { } 780 }; 781 782 static struct clk_rcg2 gp1_clk_src = { 783 .cmd_rcgr = 0x1904, 784 .mnd_width = 8, 785 .hid_width = 5, 786 .parent_map = gcc_xo_gpll0_map, 787 .freq_tbl = ftbl_gp1_clk_src, 788 .clkr.hw.init = &(struct clk_init_data){ 789 .name = "gp1_clk_src", 790 .parent_data = gcc_xo_gpll0, 791 .num_parents = 2, 792 .ops = &clk_rcg2_ops, 793 }, 794 }; 795 796 static struct freq_tbl ftbl_gp2_clk_src[] = { 797 F(19200000, P_XO, 1, 0, 0), 798 F(100000000, P_GPLL0, 6, 0, 0), 799 F(200000000, P_GPLL0, 3, 0, 0), 800 { } 801 }; 802 803 static struct clk_rcg2 gp2_clk_src = { 804 .cmd_rcgr = 0x1944, 805 .mnd_width = 8, 806 .hid_width = 5, 807 .parent_map = gcc_xo_gpll0_map, 808 .freq_tbl = ftbl_gp2_clk_src, 809 .clkr.hw.init = &(struct clk_init_data){ 810 .name = "gp2_clk_src", 811 .parent_data = gcc_xo_gpll0, 812 .num_parents = 2, 813 .ops = &clk_rcg2_ops, 814 }, 815 }; 816 817 static struct freq_tbl ftbl_gp3_clk_src[] = { 818 F(19200000, P_XO, 1, 0, 0), 819 F(100000000, P_GPLL0, 6, 0, 0), 820 F(200000000, P_GPLL0, 3, 0, 0), 821 { } 822 }; 823 824 static struct clk_rcg2 gp3_clk_src = { 825 .cmd_rcgr = 0x1984, 826 .mnd_width = 8, 827 .hid_width = 5, 828 .parent_map = gcc_xo_gpll0_map, 829 .freq_tbl = ftbl_gp3_clk_src, 830 .clkr.hw.init = &(struct clk_init_data){ 831 .name = "gp3_clk_src", 832 .parent_data = gcc_xo_gpll0, 833 .num_parents = 2, 834 .ops = &clk_rcg2_ops, 835 }, 836 }; 837 838 static struct freq_tbl ftbl_pcie_0_aux_clk_src[] = { 839 F(1011000, P_XO, 1, 1, 19), 840 { } 841 }; 842 843 static struct clk_rcg2 pcie_0_aux_clk_src = { 844 .cmd_rcgr = 0x1b00, 845 .mnd_width = 8, 846 .hid_width = 5, 847 .freq_tbl = ftbl_pcie_0_aux_clk_src, 848 .clkr.hw.init = &(struct clk_init_data){ 849 .name = "pcie_0_aux_clk_src", 850 .parent_data = &(const struct clk_parent_data){ 851 .fw_name = "xo", 852 }, 853 .num_parents = 1, 854 .ops = &clk_rcg2_ops, 855 }, 856 }; 857 858 static struct freq_tbl ftbl_pcie_pipe_clk_src[] = { 859 F(125000000, P_XO, 1, 0, 0), 860 { } 861 }; 862 863 static struct clk_rcg2 pcie_0_pipe_clk_src = { 864 .cmd_rcgr = 0x1adc, 865 .hid_width = 5, 866 .freq_tbl = ftbl_pcie_pipe_clk_src, 867 .clkr.hw.init = &(struct clk_init_data){ 868 .name = "pcie_0_pipe_clk_src", 869 .parent_data = &(const struct clk_parent_data){ 870 .fw_name = "xo", 871 }, 872 .num_parents = 1, 873 .ops = &clk_rcg2_ops, 874 }, 875 }; 876 877 static struct freq_tbl ftbl_pcie_1_aux_clk_src[] = { 878 F(1011000, P_XO, 1, 1, 19), 879 { } 880 }; 881 882 static struct clk_rcg2 pcie_1_aux_clk_src = { 883 .cmd_rcgr = 0x1b80, 884 .mnd_width = 8, 885 .hid_width = 5, 886 .freq_tbl = ftbl_pcie_1_aux_clk_src, 887 .clkr.hw.init = &(struct clk_init_data){ 888 .name = "pcie_1_aux_clk_src", 889 .parent_data = &(const struct clk_parent_data){ 890 .fw_name = "xo", 891 }, 892 .num_parents = 1, 893 .ops = &clk_rcg2_ops, 894 }, 895 }; 896 897 static struct clk_rcg2 pcie_1_pipe_clk_src = { 898 .cmd_rcgr = 0x1b5c, 899 .hid_width = 5, 900 .freq_tbl = ftbl_pcie_pipe_clk_src, 901 .clkr.hw.init = &(struct clk_init_data){ 902 .name = "pcie_1_pipe_clk_src", 903 .parent_data = &(const struct clk_parent_data){ 904 .fw_name = "xo", 905 }, 906 .num_parents = 1, 907 .ops = &clk_rcg2_ops, 908 }, 909 }; 910 911 static struct freq_tbl ftbl_pdm2_clk_src[] = { 912 F(60000000, P_GPLL0, 10, 0, 0), 913 { } 914 }; 915 916 static struct clk_rcg2 pdm2_clk_src = { 917 .cmd_rcgr = 0x0cd0, 918 .hid_width = 5, 919 .parent_map = gcc_xo_gpll0_map, 920 .freq_tbl = ftbl_pdm2_clk_src, 921 .clkr.hw.init = &(struct clk_init_data){ 922 .name = "pdm2_clk_src", 923 .parent_data = gcc_xo_gpll0, 924 .num_parents = 2, 925 .ops = &clk_rcg2_ops, 926 }, 927 }; 928 929 static struct freq_tbl ftbl_sdcc1_apps_clk_src[] = { 930 F(144000, P_XO, 16, 3, 25), 931 F(400000, P_XO, 12, 1, 4), 932 F(20000000, P_GPLL0, 15, 1, 2), 933 F(25000000, P_GPLL0, 12, 1, 2), 934 F(50000000, P_GPLL0, 12, 0, 0), 935 F(100000000, P_GPLL0, 6, 0, 0), 936 F(192000000, P_GPLL4, 2, 0, 0), 937 F(384000000, P_GPLL4, 1, 0, 0), 938 { } 939 }; 940 941 static struct clk_rcg2 sdcc1_apps_clk_src = { 942 .cmd_rcgr = 0x04d0, 943 .mnd_width = 8, 944 .hid_width = 5, 945 .parent_map = gcc_xo_gpll0_gpll4_map, 946 .freq_tbl = ftbl_sdcc1_apps_clk_src, 947 .clkr.hw.init = &(struct clk_init_data){ 948 .name = "sdcc1_apps_clk_src", 949 .parent_data = gcc_xo_gpll0_gpll4, 950 .num_parents = 3, 951 .ops = &clk_rcg2_floor_ops, 952 }, 953 }; 954 955 static struct freq_tbl ftbl_sdcc2_4_apps_clk_src[] = { 956 F(144000, P_XO, 16, 3, 25), 957 F(400000, P_XO, 12, 1, 4), 958 F(20000000, P_GPLL0, 15, 1, 2), 959 F(25000000, P_GPLL0, 12, 1, 2), 960 F(50000000, P_GPLL0, 12, 0, 0), 961 F(100000000, P_GPLL0, 6, 0, 0), 962 F(200000000, P_GPLL0, 3, 0, 0), 963 { } 964 }; 965 966 static struct clk_rcg2 sdcc2_apps_clk_src = { 967 .cmd_rcgr = 0x0510, 968 .mnd_width = 8, 969 .hid_width = 5, 970 .parent_map = gcc_xo_gpll0_map, 971 .freq_tbl = ftbl_sdcc2_4_apps_clk_src, 972 .clkr.hw.init = &(struct clk_init_data){ 973 .name = "sdcc2_apps_clk_src", 974 .parent_data = gcc_xo_gpll0, 975 .num_parents = 2, 976 .ops = &clk_rcg2_floor_ops, 977 }, 978 }; 979 980 static struct clk_rcg2 sdcc3_apps_clk_src = { 981 .cmd_rcgr = 0x0550, 982 .mnd_width = 8, 983 .hid_width = 5, 984 .parent_map = gcc_xo_gpll0_map, 985 .freq_tbl = ftbl_sdcc2_4_apps_clk_src, 986 .clkr.hw.init = &(struct clk_init_data){ 987 .name = "sdcc3_apps_clk_src", 988 .parent_data = gcc_xo_gpll0, 989 .num_parents = 2, 990 .ops = &clk_rcg2_floor_ops, 991 }, 992 }; 993 994 static struct clk_rcg2 sdcc4_apps_clk_src = { 995 .cmd_rcgr = 0x0590, 996 .mnd_width = 8, 997 .hid_width = 5, 998 .parent_map = gcc_xo_gpll0_map, 999 .freq_tbl = ftbl_sdcc2_4_apps_clk_src, 1000 .clkr.hw.init = &(struct clk_init_data){ 1001 .name = "sdcc4_apps_clk_src", 1002 .parent_data = gcc_xo_gpll0, 1003 .num_parents = 2, 1004 .ops = &clk_rcg2_floor_ops, 1005 }, 1006 }; 1007 1008 static struct freq_tbl ftbl_tsif_ref_clk_src[] = { 1009 F(105500, P_XO, 1, 1, 182), 1010 { } 1011 }; 1012 1013 static struct clk_rcg2 tsif_ref_clk_src = { 1014 .cmd_rcgr = 0x0d90, 1015 .mnd_width = 8, 1016 .hid_width = 5, 1017 .freq_tbl = ftbl_tsif_ref_clk_src, 1018 .clkr.hw.init = &(struct clk_init_data){ 1019 .name = "tsif_ref_clk_src", 1020 .parent_data = &(const struct clk_parent_data){ 1021 .fw_name = "xo", 1022 }, 1023 .num_parents = 1, 1024 .ops = &clk_rcg2_ops, 1025 }, 1026 }; 1027 1028 static struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = { 1029 F(19200000, P_XO, 1, 0, 0), 1030 F(60000000, P_GPLL0, 10, 0, 0), 1031 { } 1032 }; 1033 1034 static struct clk_rcg2 usb30_mock_utmi_clk_src = { 1035 .cmd_rcgr = 0x03e8, 1036 .hid_width = 5, 1037 .parent_map = gcc_xo_gpll0_map, 1038 .freq_tbl = ftbl_usb30_mock_utmi_clk_src, 1039 .clkr.hw.init = &(struct clk_init_data){ 1040 .name = "usb30_mock_utmi_clk_src", 1041 .parent_data = gcc_xo_gpll0, 1042 .num_parents = 2, 1043 .ops = &clk_rcg2_ops, 1044 }, 1045 }; 1046 1047 static struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = { 1048 F(1200000, P_XO, 16, 0, 0), 1049 { } 1050 }; 1051 1052 static struct clk_rcg2 usb3_phy_aux_clk_src = { 1053 .cmd_rcgr = 0x1414, 1054 .hid_width = 5, 1055 .freq_tbl = ftbl_usb3_phy_aux_clk_src, 1056 .clkr.hw.init = &(struct clk_init_data){ 1057 .name = "usb3_phy_aux_clk_src", 1058 .parent_data = &(const struct clk_parent_data){ 1059 .fw_name = "xo", 1060 }, 1061 .num_parents = 1, 1062 .ops = &clk_rcg2_ops, 1063 }, 1064 }; 1065 1066 static struct freq_tbl ftbl_usb_hs_system_clk_src[] = { 1067 F(75000000, P_GPLL0, 8, 0, 0), 1068 { } 1069 }; 1070 1071 static struct clk_rcg2 usb_hs_system_clk_src = { 1072 .cmd_rcgr = 0x0490, 1073 .hid_width = 5, 1074 .parent_map = gcc_xo_gpll0_map, 1075 .freq_tbl = ftbl_usb_hs_system_clk_src, 1076 .clkr.hw.init = &(struct clk_init_data){ 1077 .name = "usb_hs_system_clk_src", 1078 .parent_data = gcc_xo_gpll0, 1079 .num_parents = 2, 1080 .ops = &clk_rcg2_ops, 1081 }, 1082 }; 1083 1084 static struct clk_branch gcc_blsp1_ahb_clk = { 1085 .halt_reg = 0x05c4, 1086 .halt_check = BRANCH_HALT_VOTED, 1087 .clkr = { 1088 .enable_reg = 0x1484, 1089 .enable_mask = BIT(17), 1090 .hw.init = &(struct clk_init_data){ 1091 .name = "gcc_blsp1_ahb_clk", 1092 .ops = &clk_branch2_ops, 1093 }, 1094 }, 1095 }; 1096 1097 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { 1098 .halt_reg = 0x0648, 1099 .clkr = { 1100 .enable_reg = 0x0648, 1101 .enable_mask = BIT(0), 1102 .hw.init = &(struct clk_init_data){ 1103 .name = "gcc_blsp1_qup1_i2c_apps_clk", 1104 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup1_i2c_apps_clk_src.clkr.hw }, 1105 .num_parents = 1, 1106 .flags = CLK_SET_RATE_PARENT, 1107 .ops = &clk_branch2_ops, 1108 }, 1109 }, 1110 }; 1111 1112 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { 1113 .halt_reg = 0x0644, 1114 .clkr = { 1115 .enable_reg = 0x0644, 1116 .enable_mask = BIT(0), 1117 .hw.init = &(struct clk_init_data){ 1118 .name = "gcc_blsp1_qup1_spi_apps_clk", 1119 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup1_spi_apps_clk_src.clkr.hw }, 1120 .num_parents = 1, 1121 .flags = CLK_SET_RATE_PARENT, 1122 .ops = &clk_branch2_ops, 1123 }, 1124 }, 1125 }; 1126 1127 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { 1128 .halt_reg = 0x06c8, 1129 .clkr = { 1130 .enable_reg = 0x06c8, 1131 .enable_mask = BIT(0), 1132 .hw.init = &(struct clk_init_data){ 1133 .name = "gcc_blsp1_qup2_i2c_apps_clk", 1134 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup2_i2c_apps_clk_src.clkr.hw }, 1135 .num_parents = 1, 1136 .flags = CLK_SET_RATE_PARENT, 1137 .ops = &clk_branch2_ops, 1138 }, 1139 }, 1140 }; 1141 1142 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { 1143 .halt_reg = 0x06c4, 1144 .clkr = { 1145 .enable_reg = 0x06c4, 1146 .enable_mask = BIT(0), 1147 .hw.init = &(struct clk_init_data){ 1148 .name = "gcc_blsp1_qup2_spi_apps_clk", 1149 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup2_spi_apps_clk_src.clkr.hw }, 1150 .num_parents = 1, 1151 .flags = CLK_SET_RATE_PARENT, 1152 .ops = &clk_branch2_ops, 1153 }, 1154 }, 1155 }; 1156 1157 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = { 1158 .halt_reg = 0x0748, 1159 .clkr = { 1160 .enable_reg = 0x0748, 1161 .enable_mask = BIT(0), 1162 .hw.init = &(struct clk_init_data){ 1163 .name = "gcc_blsp1_qup3_i2c_apps_clk", 1164 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup3_i2c_apps_clk_src.clkr.hw }, 1165 .num_parents = 1, 1166 .flags = CLK_SET_RATE_PARENT, 1167 .ops = &clk_branch2_ops, 1168 }, 1169 }, 1170 }; 1171 1172 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = { 1173 .halt_reg = 0x0744, 1174 .clkr = { 1175 .enable_reg = 0x0744, 1176 .enable_mask = BIT(0), 1177 .hw.init = &(struct clk_init_data){ 1178 .name = "gcc_blsp1_qup3_spi_apps_clk", 1179 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup3_spi_apps_clk_src.clkr.hw }, 1180 .num_parents = 1, 1181 .flags = CLK_SET_RATE_PARENT, 1182 .ops = &clk_branch2_ops, 1183 }, 1184 }, 1185 }; 1186 1187 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = { 1188 .halt_reg = 0x07c8, 1189 .clkr = { 1190 .enable_reg = 0x07c8, 1191 .enable_mask = BIT(0), 1192 .hw.init = &(struct clk_init_data){ 1193 .name = "gcc_blsp1_qup4_i2c_apps_clk", 1194 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup4_i2c_apps_clk_src.clkr.hw }, 1195 .num_parents = 1, 1196 .flags = CLK_SET_RATE_PARENT, 1197 .ops = &clk_branch2_ops, 1198 }, 1199 }, 1200 }; 1201 1202 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = { 1203 .halt_reg = 0x07c4, 1204 .clkr = { 1205 .enable_reg = 0x07c4, 1206 .enable_mask = BIT(0), 1207 .hw.init = &(struct clk_init_data){ 1208 .name = "gcc_blsp1_qup4_spi_apps_clk", 1209 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup4_spi_apps_clk_src.clkr.hw }, 1210 .num_parents = 1, 1211 .flags = CLK_SET_RATE_PARENT, 1212 .ops = &clk_branch2_ops, 1213 }, 1214 }, 1215 }; 1216 1217 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = { 1218 .halt_reg = 0x0848, 1219 .clkr = { 1220 .enable_reg = 0x0848, 1221 .enable_mask = BIT(0), 1222 .hw.init = &(struct clk_init_data){ 1223 .name = "gcc_blsp1_qup5_i2c_apps_clk", 1224 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup5_i2c_apps_clk_src.clkr.hw }, 1225 .num_parents = 1, 1226 .flags = CLK_SET_RATE_PARENT, 1227 .ops = &clk_branch2_ops, 1228 }, 1229 }, 1230 }; 1231 1232 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = { 1233 .halt_reg = 0x0844, 1234 .clkr = { 1235 .enable_reg = 0x0844, 1236 .enable_mask = BIT(0), 1237 .hw.init = &(struct clk_init_data){ 1238 .name = "gcc_blsp1_qup5_spi_apps_clk", 1239 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup5_spi_apps_clk_src.clkr.hw }, 1240 .num_parents = 1, 1241 .flags = CLK_SET_RATE_PARENT, 1242 .ops = &clk_branch2_ops, 1243 }, 1244 }, 1245 }; 1246 1247 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = { 1248 .halt_reg = 0x08c8, 1249 .clkr = { 1250 .enable_reg = 0x08c8, 1251 .enable_mask = BIT(0), 1252 .hw.init = &(struct clk_init_data){ 1253 .name = "gcc_blsp1_qup6_i2c_apps_clk", 1254 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup6_i2c_apps_clk_src.clkr.hw }, 1255 .num_parents = 1, 1256 .flags = CLK_SET_RATE_PARENT, 1257 .ops = &clk_branch2_ops, 1258 }, 1259 }, 1260 }; 1261 1262 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = { 1263 .halt_reg = 0x08c4, 1264 .clkr = { 1265 .enable_reg = 0x08c4, 1266 .enable_mask = BIT(0), 1267 .hw.init = &(struct clk_init_data){ 1268 .name = "gcc_blsp1_qup6_spi_apps_clk", 1269 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup6_spi_apps_clk_src.clkr.hw }, 1270 .num_parents = 1, 1271 .flags = CLK_SET_RATE_PARENT, 1272 .ops = &clk_branch2_ops, 1273 }, 1274 }, 1275 }; 1276 1277 static struct clk_branch gcc_blsp1_uart1_apps_clk = { 1278 .halt_reg = 0x0684, 1279 .clkr = { 1280 .enable_reg = 0x0684, 1281 .enable_mask = BIT(0), 1282 .hw.init = &(struct clk_init_data){ 1283 .name = "gcc_blsp1_uart1_apps_clk", 1284 .parent_hws = (const struct clk_hw *[]){ &blsp1_uart1_apps_clk_src.clkr.hw }, 1285 .num_parents = 1, 1286 .flags = CLK_SET_RATE_PARENT, 1287 .ops = &clk_branch2_ops, 1288 }, 1289 }, 1290 }; 1291 1292 static struct clk_branch gcc_blsp1_uart2_apps_clk = { 1293 .halt_reg = 0x0704, 1294 .clkr = { 1295 .enable_reg = 0x0704, 1296 .enable_mask = BIT(0), 1297 .hw.init = &(struct clk_init_data){ 1298 .name = "gcc_blsp1_uart2_apps_clk", 1299 .parent_hws = (const struct clk_hw *[]){ &blsp1_uart2_apps_clk_src.clkr.hw }, 1300 .num_parents = 1, 1301 .flags = CLK_SET_RATE_PARENT, 1302 .ops = &clk_branch2_ops, 1303 }, 1304 }, 1305 }; 1306 1307 static struct clk_branch gcc_blsp1_uart3_apps_clk = { 1308 .halt_reg = 0x0784, 1309 .clkr = { 1310 .enable_reg = 0x0784, 1311 .enable_mask = BIT(0), 1312 .hw.init = &(struct clk_init_data){ 1313 .name = "gcc_blsp1_uart3_apps_clk", 1314 .parent_hws = (const struct clk_hw *[]){ &blsp1_uart3_apps_clk_src.clkr.hw }, 1315 .num_parents = 1, 1316 .flags = CLK_SET_RATE_PARENT, 1317 .ops = &clk_branch2_ops, 1318 }, 1319 }, 1320 }; 1321 1322 static struct clk_branch gcc_blsp1_uart4_apps_clk = { 1323 .halt_reg = 0x0804, 1324 .clkr = { 1325 .enable_reg = 0x0804, 1326 .enable_mask = BIT(0), 1327 .hw.init = &(struct clk_init_data){ 1328 .name = "gcc_blsp1_uart4_apps_clk", 1329 .parent_hws = (const struct clk_hw *[]){ &blsp1_uart4_apps_clk_src.clkr.hw }, 1330 .num_parents = 1, 1331 .flags = CLK_SET_RATE_PARENT, 1332 .ops = &clk_branch2_ops, 1333 }, 1334 }, 1335 }; 1336 1337 static struct clk_branch gcc_blsp1_uart5_apps_clk = { 1338 .halt_reg = 0x0884, 1339 .clkr = { 1340 .enable_reg = 0x0884, 1341 .enable_mask = BIT(0), 1342 .hw.init = &(struct clk_init_data){ 1343 .name = "gcc_blsp1_uart5_apps_clk", 1344 .parent_hws = (const struct clk_hw *[]){ &blsp1_uart5_apps_clk_src.clkr.hw }, 1345 .num_parents = 1, 1346 .flags = CLK_SET_RATE_PARENT, 1347 .ops = &clk_branch2_ops, 1348 }, 1349 }, 1350 }; 1351 1352 static struct clk_branch gcc_blsp1_uart6_apps_clk = { 1353 .halt_reg = 0x0904, 1354 .clkr = { 1355 .enable_reg = 0x0904, 1356 .enable_mask = BIT(0), 1357 .hw.init = &(struct clk_init_data){ 1358 .name = "gcc_blsp1_uart6_apps_clk", 1359 .parent_hws = (const struct clk_hw *[]){ &blsp1_uart6_apps_clk_src.clkr.hw }, 1360 .num_parents = 1, 1361 .flags = CLK_SET_RATE_PARENT, 1362 .ops = &clk_branch2_ops, 1363 }, 1364 }, 1365 }; 1366 1367 static struct clk_branch gcc_blsp2_ahb_clk = { 1368 .halt_reg = 0x0944, 1369 .halt_check = BRANCH_HALT_VOTED, 1370 .clkr = { 1371 .enable_reg = 0x1484, 1372 .enable_mask = BIT(15), 1373 .hw.init = &(struct clk_init_data){ 1374 .name = "gcc_blsp2_ahb_clk", 1375 .ops = &clk_branch2_ops, 1376 }, 1377 }, 1378 }; 1379 1380 static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = { 1381 .halt_reg = 0x0988, 1382 .clkr = { 1383 .enable_reg = 0x0988, 1384 .enable_mask = BIT(0), 1385 .hw.init = &(struct clk_init_data){ 1386 .name = "gcc_blsp2_qup1_i2c_apps_clk", 1387 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup1_i2c_apps_clk_src.clkr.hw }, 1388 .num_parents = 1, 1389 .flags = CLK_SET_RATE_PARENT, 1390 .ops = &clk_branch2_ops, 1391 }, 1392 }, 1393 }; 1394 1395 static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = { 1396 .halt_reg = 0x0984, 1397 .clkr = { 1398 .enable_reg = 0x0984, 1399 .enable_mask = BIT(0), 1400 .hw.init = &(struct clk_init_data){ 1401 .name = "gcc_blsp2_qup1_spi_apps_clk", 1402 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup1_spi_apps_clk_src.clkr.hw }, 1403 .num_parents = 1, 1404 .flags = CLK_SET_RATE_PARENT, 1405 .ops = &clk_branch2_ops, 1406 }, 1407 }, 1408 }; 1409 1410 static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = { 1411 .halt_reg = 0x0a08, 1412 .clkr = { 1413 .enable_reg = 0x0a08, 1414 .enable_mask = BIT(0), 1415 .hw.init = &(struct clk_init_data){ 1416 .name = "gcc_blsp2_qup2_i2c_apps_clk", 1417 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup2_i2c_apps_clk_src.clkr.hw }, 1418 .num_parents = 1, 1419 .flags = CLK_SET_RATE_PARENT, 1420 .ops = &clk_branch2_ops, 1421 }, 1422 }, 1423 }; 1424 1425 static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = { 1426 .halt_reg = 0x0a04, 1427 .clkr = { 1428 .enable_reg = 0x0a04, 1429 .enable_mask = BIT(0), 1430 .hw.init = &(struct clk_init_data){ 1431 .name = "gcc_blsp2_qup2_spi_apps_clk", 1432 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup2_spi_apps_clk_src.clkr.hw }, 1433 .num_parents = 1, 1434 .flags = CLK_SET_RATE_PARENT, 1435 .ops = &clk_branch2_ops, 1436 }, 1437 }, 1438 }; 1439 1440 static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = { 1441 .halt_reg = 0x0a88, 1442 .clkr = { 1443 .enable_reg = 0x0a88, 1444 .enable_mask = BIT(0), 1445 .hw.init = &(struct clk_init_data){ 1446 .name = "gcc_blsp2_qup3_i2c_apps_clk", 1447 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup3_i2c_apps_clk_src.clkr.hw }, 1448 .num_parents = 1, 1449 .flags = CLK_SET_RATE_PARENT, 1450 .ops = &clk_branch2_ops, 1451 }, 1452 }, 1453 }; 1454 1455 static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = { 1456 .halt_reg = 0x0a84, 1457 .clkr = { 1458 .enable_reg = 0x0a84, 1459 .enable_mask = BIT(0), 1460 .hw.init = &(struct clk_init_data){ 1461 .name = "gcc_blsp2_qup3_spi_apps_clk", 1462 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup3_spi_apps_clk_src.clkr.hw }, 1463 .num_parents = 1, 1464 .flags = CLK_SET_RATE_PARENT, 1465 .ops = &clk_branch2_ops, 1466 }, 1467 }, 1468 }; 1469 1470 static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = { 1471 .halt_reg = 0x0b08, 1472 .clkr = { 1473 .enable_reg = 0x0b08, 1474 .enable_mask = BIT(0), 1475 .hw.init = &(struct clk_init_data){ 1476 .name = "gcc_blsp2_qup4_i2c_apps_clk", 1477 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup4_i2c_apps_clk_src.clkr.hw }, 1478 .num_parents = 1, 1479 .flags = CLK_SET_RATE_PARENT, 1480 .ops = &clk_branch2_ops, 1481 }, 1482 }, 1483 }; 1484 1485 static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = { 1486 .halt_reg = 0x0b04, 1487 .clkr = { 1488 .enable_reg = 0x0b04, 1489 .enable_mask = BIT(0), 1490 .hw.init = &(struct clk_init_data){ 1491 .name = "gcc_blsp2_qup4_spi_apps_clk", 1492 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup4_spi_apps_clk_src.clkr.hw }, 1493 .num_parents = 1, 1494 .flags = CLK_SET_RATE_PARENT, 1495 .ops = &clk_branch2_ops, 1496 }, 1497 }, 1498 }; 1499 1500 static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = { 1501 .halt_reg = 0x0b88, 1502 .clkr = { 1503 .enable_reg = 0x0b88, 1504 .enable_mask = BIT(0), 1505 .hw.init = &(struct clk_init_data){ 1506 .name = "gcc_blsp2_qup5_i2c_apps_clk", 1507 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup5_i2c_apps_clk_src.clkr.hw }, 1508 .num_parents = 1, 1509 .flags = CLK_SET_RATE_PARENT, 1510 .ops = &clk_branch2_ops, 1511 }, 1512 }, 1513 }; 1514 1515 static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = { 1516 .halt_reg = 0x0b84, 1517 .clkr = { 1518 .enable_reg = 0x0b84, 1519 .enable_mask = BIT(0), 1520 .hw.init = &(struct clk_init_data){ 1521 .name = "gcc_blsp2_qup5_spi_apps_clk", 1522 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup5_spi_apps_clk_src.clkr.hw }, 1523 .num_parents = 1, 1524 .flags = CLK_SET_RATE_PARENT, 1525 .ops = &clk_branch2_ops, 1526 }, 1527 }, 1528 }; 1529 1530 static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = { 1531 .halt_reg = 0x0c08, 1532 .clkr = { 1533 .enable_reg = 0x0c08, 1534 .enable_mask = BIT(0), 1535 .hw.init = &(struct clk_init_data){ 1536 .name = "gcc_blsp2_qup6_i2c_apps_clk", 1537 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup6_i2c_apps_clk_src.clkr.hw }, 1538 .num_parents = 1, 1539 .flags = CLK_SET_RATE_PARENT, 1540 .ops = &clk_branch2_ops, 1541 }, 1542 }, 1543 }; 1544 1545 static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = { 1546 .halt_reg = 0x0c04, 1547 .clkr = { 1548 .enable_reg = 0x0c04, 1549 .enable_mask = BIT(0), 1550 .hw.init = &(struct clk_init_data){ 1551 .name = "gcc_blsp2_qup6_spi_apps_clk", 1552 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup6_spi_apps_clk_src.clkr.hw }, 1553 .num_parents = 1, 1554 .flags = CLK_SET_RATE_PARENT, 1555 .ops = &clk_branch2_ops, 1556 }, 1557 }, 1558 }; 1559 1560 static struct clk_branch gcc_blsp2_uart1_apps_clk = { 1561 .halt_reg = 0x09c4, 1562 .clkr = { 1563 .enable_reg = 0x09c4, 1564 .enable_mask = BIT(0), 1565 .hw.init = &(struct clk_init_data){ 1566 .name = "gcc_blsp2_uart1_apps_clk", 1567 .parent_hws = (const struct clk_hw *[]){ &blsp2_uart1_apps_clk_src.clkr.hw }, 1568 .num_parents = 1, 1569 .flags = CLK_SET_RATE_PARENT, 1570 .ops = &clk_branch2_ops, 1571 }, 1572 }, 1573 }; 1574 1575 static struct clk_branch gcc_blsp2_uart2_apps_clk = { 1576 .halt_reg = 0x0a44, 1577 .clkr = { 1578 .enable_reg = 0x0a44, 1579 .enable_mask = BIT(0), 1580 .hw.init = &(struct clk_init_data){ 1581 .name = "gcc_blsp2_uart2_apps_clk", 1582 .parent_hws = (const struct clk_hw *[]){ &blsp2_uart2_apps_clk_src.clkr.hw }, 1583 .num_parents = 1, 1584 .flags = CLK_SET_RATE_PARENT, 1585 .ops = &clk_branch2_ops, 1586 }, 1587 }, 1588 }; 1589 1590 static struct clk_branch gcc_blsp2_uart3_apps_clk = { 1591 .halt_reg = 0x0ac4, 1592 .clkr = { 1593 .enable_reg = 0x0ac4, 1594 .enable_mask = BIT(0), 1595 .hw.init = &(struct clk_init_data){ 1596 .name = "gcc_blsp2_uart3_apps_clk", 1597 .parent_hws = (const struct clk_hw *[]){ &blsp2_uart3_apps_clk_src.clkr.hw }, 1598 .num_parents = 1, 1599 .flags = CLK_SET_RATE_PARENT, 1600 .ops = &clk_branch2_ops, 1601 }, 1602 }, 1603 }; 1604 1605 static struct clk_branch gcc_blsp2_uart4_apps_clk = { 1606 .halt_reg = 0x0b44, 1607 .clkr = { 1608 .enable_reg = 0x0b44, 1609 .enable_mask = BIT(0), 1610 .hw.init = &(struct clk_init_data){ 1611 .name = "gcc_blsp2_uart4_apps_clk", 1612 .parent_hws = (const struct clk_hw *[]){ &blsp2_uart4_apps_clk_src.clkr.hw }, 1613 .num_parents = 1, 1614 .flags = CLK_SET_RATE_PARENT, 1615 .ops = &clk_branch2_ops, 1616 }, 1617 }, 1618 }; 1619 1620 static struct clk_branch gcc_blsp2_uart5_apps_clk = { 1621 .halt_reg = 0x0bc4, 1622 .clkr = { 1623 .enable_reg = 0x0bc4, 1624 .enable_mask = BIT(0), 1625 .hw.init = &(struct clk_init_data){ 1626 .name = "gcc_blsp2_uart5_apps_clk", 1627 .parent_hws = (const struct clk_hw *[]){ &blsp2_uart5_apps_clk_src.clkr.hw }, 1628 .num_parents = 1, 1629 .flags = CLK_SET_RATE_PARENT, 1630 .ops = &clk_branch2_ops, 1631 }, 1632 }, 1633 }; 1634 1635 static struct clk_branch gcc_blsp2_uart6_apps_clk = { 1636 .halt_reg = 0x0c44, 1637 .clkr = { 1638 .enable_reg = 0x0c44, 1639 .enable_mask = BIT(0), 1640 .hw.init = &(struct clk_init_data){ 1641 .name = "gcc_blsp2_uart6_apps_clk", 1642 .parent_hws = (const struct clk_hw *[]){ &blsp2_uart6_apps_clk_src.clkr.hw }, 1643 .num_parents = 1, 1644 .flags = CLK_SET_RATE_PARENT, 1645 .ops = &clk_branch2_ops, 1646 }, 1647 }, 1648 }; 1649 1650 static struct clk_branch gcc_gp1_clk = { 1651 .halt_reg = 0x1900, 1652 .clkr = { 1653 .enable_reg = 0x1900, 1654 .enable_mask = BIT(0), 1655 .hw.init = &(struct clk_init_data){ 1656 .name = "gcc_gp1_clk", 1657 .parent_hws = (const struct clk_hw *[]){ &gp1_clk_src.clkr.hw }, 1658 .num_parents = 1, 1659 .flags = CLK_SET_RATE_PARENT, 1660 .ops = &clk_branch2_ops, 1661 }, 1662 }, 1663 }; 1664 1665 static struct clk_branch gcc_gp2_clk = { 1666 .halt_reg = 0x1940, 1667 .clkr = { 1668 .enable_reg = 0x1940, 1669 .enable_mask = BIT(0), 1670 .hw.init = &(struct clk_init_data){ 1671 .name = "gcc_gp2_clk", 1672 .parent_hws = (const struct clk_hw *[]){ &gp2_clk_src.clkr.hw }, 1673 .num_parents = 1, 1674 .flags = CLK_SET_RATE_PARENT, 1675 .ops = &clk_branch2_ops, 1676 }, 1677 }, 1678 }; 1679 1680 static struct clk_branch gcc_gp3_clk = { 1681 .halt_reg = 0x1980, 1682 .clkr = { 1683 .enable_reg = 0x1980, 1684 .enable_mask = BIT(0), 1685 .hw.init = &(struct clk_init_data){ 1686 .name = "gcc_gp3_clk", 1687 .parent_hws = (const struct clk_hw *[]){ &gp3_clk_src.clkr.hw }, 1688 .num_parents = 1, 1689 .flags = CLK_SET_RATE_PARENT, 1690 .ops = &clk_branch2_ops, 1691 }, 1692 }, 1693 }; 1694 1695 static struct clk_branch gcc_lpass_q6_axi_clk = { 1696 .halt_reg = 0x0280, 1697 .clkr = { 1698 .enable_reg = 0x0280, 1699 .enable_mask = BIT(0), 1700 .hw.init = &(struct clk_init_data){ 1701 .name = "gcc_lpass_q6_axi_clk", 1702 .ops = &clk_branch2_ops, 1703 }, 1704 }, 1705 }; 1706 1707 static struct clk_branch gcc_mss_q6_bimc_axi_clk = { 1708 .halt_reg = 0x0284, 1709 .clkr = { 1710 .enable_reg = 0x0284, 1711 .enable_mask = BIT(0), 1712 .hw.init = &(struct clk_init_data){ 1713 .name = "gcc_mss_q6_bimc_axi_clk", 1714 .ops = &clk_branch2_ops, 1715 }, 1716 }, 1717 }; 1718 1719 static struct clk_branch gcc_pcie_0_aux_clk = { 1720 .halt_reg = 0x1ad4, 1721 .clkr = { 1722 .enable_reg = 0x1ad4, 1723 .enable_mask = BIT(0), 1724 .hw.init = &(struct clk_init_data){ 1725 .name = "gcc_pcie_0_aux_clk", 1726 .parent_hws = (const struct clk_hw *[]){ &pcie_0_aux_clk_src.clkr.hw }, 1727 .num_parents = 1, 1728 .flags = CLK_SET_RATE_PARENT, 1729 .ops = &clk_branch2_ops, 1730 }, 1731 }, 1732 }; 1733 1734 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { 1735 .halt_reg = 0x1ad0, 1736 .clkr = { 1737 .enable_reg = 0x1ad0, 1738 .enable_mask = BIT(0), 1739 .hw.init = &(struct clk_init_data){ 1740 .name = "gcc_pcie_0_cfg_ahb_clk", 1741 .ops = &clk_branch2_ops, 1742 }, 1743 }, 1744 }; 1745 1746 static struct clk_branch gcc_pcie_0_mstr_axi_clk = { 1747 .halt_reg = 0x1acc, 1748 .clkr = { 1749 .enable_reg = 0x1acc, 1750 .enable_mask = BIT(0), 1751 .hw.init = &(struct clk_init_data){ 1752 .name = "gcc_pcie_0_mstr_axi_clk", 1753 .ops = &clk_branch2_ops, 1754 }, 1755 }, 1756 }; 1757 1758 static struct clk_branch gcc_pcie_0_pipe_clk = { 1759 .halt_reg = 0x1ad8, 1760 .halt_check = BRANCH_HALT_DELAY, 1761 .clkr = { 1762 .enable_reg = 0x1ad8, 1763 .enable_mask = BIT(0), 1764 .hw.init = &(struct clk_init_data){ 1765 .name = "gcc_pcie_0_pipe_clk", 1766 .parent_hws = (const struct clk_hw *[]){ &pcie_0_pipe_clk_src.clkr.hw }, 1767 .num_parents = 1, 1768 .flags = CLK_SET_RATE_PARENT, 1769 .ops = &clk_branch2_ops, 1770 }, 1771 }, 1772 }; 1773 1774 static struct clk_branch gcc_pcie_0_slv_axi_clk = { 1775 .halt_reg = 0x1ac8, 1776 .halt_check = BRANCH_HALT_DELAY, 1777 .clkr = { 1778 .enable_reg = 0x1ac8, 1779 .enable_mask = BIT(0), 1780 .hw.init = &(struct clk_init_data){ 1781 .name = "gcc_pcie_0_slv_axi_clk", 1782 .ops = &clk_branch2_ops, 1783 }, 1784 }, 1785 }; 1786 1787 static struct clk_branch gcc_pcie_1_aux_clk = { 1788 .halt_reg = 0x1b54, 1789 .clkr = { 1790 .enable_reg = 0x1b54, 1791 .enable_mask = BIT(0), 1792 .hw.init = &(struct clk_init_data){ 1793 .name = "gcc_pcie_1_aux_clk", 1794 .parent_hws = (const struct clk_hw *[]){ &pcie_1_aux_clk_src.clkr.hw }, 1795 .num_parents = 1, 1796 .flags = CLK_SET_RATE_PARENT, 1797 .ops = &clk_branch2_ops, 1798 }, 1799 }, 1800 }; 1801 1802 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { 1803 .halt_reg = 0x1b54, 1804 .clkr = { 1805 .enable_reg = 0x1b54, 1806 .enable_mask = BIT(0), 1807 .hw.init = &(struct clk_init_data){ 1808 .name = "gcc_pcie_1_cfg_ahb_clk", 1809 .ops = &clk_branch2_ops, 1810 }, 1811 }, 1812 }; 1813 1814 static struct clk_branch gcc_pcie_1_mstr_axi_clk = { 1815 .halt_reg = 0x1b50, 1816 .clkr = { 1817 .enable_reg = 0x1b50, 1818 .enable_mask = BIT(0), 1819 .hw.init = &(struct clk_init_data){ 1820 .name = "gcc_pcie_1_mstr_axi_clk", 1821 .ops = &clk_branch2_ops, 1822 }, 1823 }, 1824 }; 1825 1826 static struct clk_branch gcc_pcie_1_pipe_clk = { 1827 .halt_reg = 0x1b58, 1828 .halt_check = BRANCH_HALT_DELAY, 1829 .clkr = { 1830 .enable_reg = 0x1b58, 1831 .enable_mask = BIT(0), 1832 .hw.init = &(struct clk_init_data){ 1833 .name = "gcc_pcie_1_pipe_clk", 1834 .parent_hws = (const struct clk_hw *[]){ &pcie_1_pipe_clk_src.clkr.hw }, 1835 .num_parents = 1, 1836 .flags = CLK_SET_RATE_PARENT, 1837 .ops = &clk_branch2_ops, 1838 }, 1839 }, 1840 }; 1841 1842 static struct clk_branch gcc_pcie_1_slv_axi_clk = { 1843 .halt_reg = 0x1b48, 1844 .clkr = { 1845 .enable_reg = 0x1b48, 1846 .enable_mask = BIT(0), 1847 .hw.init = &(struct clk_init_data){ 1848 .name = "gcc_pcie_1_slv_axi_clk", 1849 .ops = &clk_branch2_ops, 1850 }, 1851 }, 1852 }; 1853 1854 static struct clk_branch gcc_pdm2_clk = { 1855 .halt_reg = 0x0ccc, 1856 .clkr = { 1857 .enable_reg = 0x0ccc, 1858 .enable_mask = BIT(0), 1859 .hw.init = &(struct clk_init_data){ 1860 .name = "gcc_pdm2_clk", 1861 .parent_hws = (const struct clk_hw *[]){ &pdm2_clk_src.clkr.hw }, 1862 .num_parents = 1, 1863 .flags = CLK_SET_RATE_PARENT, 1864 .ops = &clk_branch2_ops, 1865 }, 1866 }, 1867 }; 1868 1869 static struct clk_branch gcc_pdm_ahb_clk = { 1870 .halt_reg = 0x0cc4, 1871 .clkr = { 1872 .enable_reg = 0x0cc4, 1873 .enable_mask = BIT(0), 1874 .hw.init = &(struct clk_init_data){ 1875 .name = "gcc_pdm_ahb_clk", 1876 .ops = &clk_branch2_ops, 1877 }, 1878 }, 1879 }; 1880 1881 static struct clk_branch gcc_sdcc1_apps_clk = { 1882 .halt_reg = 0x04c4, 1883 .clkr = { 1884 .enable_reg = 0x04c4, 1885 .enable_mask = BIT(0), 1886 .hw.init = &(struct clk_init_data){ 1887 .name = "gcc_sdcc1_apps_clk", 1888 .parent_hws = (const struct clk_hw *[]){ &sdcc1_apps_clk_src.clkr.hw }, 1889 .num_parents = 1, 1890 .flags = CLK_SET_RATE_PARENT, 1891 .ops = &clk_branch2_ops, 1892 }, 1893 }, 1894 }; 1895 1896 static struct clk_branch gcc_sdcc1_ahb_clk = { 1897 .halt_reg = 0x04c8, 1898 .clkr = { 1899 .enable_reg = 0x04c8, 1900 .enable_mask = BIT(0), 1901 .hw.init = &(struct clk_init_data){ 1902 .name = "gcc_sdcc1_ahb_clk", 1903 .parent_names = (const char *[]){ 1904 "periph_noc_clk_src", 1905 }, 1906 .num_parents = 1, 1907 .ops = &clk_branch2_ops, 1908 }, 1909 }, 1910 }; 1911 1912 static struct clk_branch gcc_sdcc2_ahb_clk = { 1913 .halt_reg = 0x0508, 1914 .clkr = { 1915 .enable_reg = 0x0508, 1916 .enable_mask = BIT(0), 1917 .hw.init = &(struct clk_init_data){ 1918 .name = "gcc_sdcc2_ahb_clk", 1919 .parent_names = (const char *[]){ 1920 "periph_noc_clk_src", 1921 }, 1922 .num_parents = 1, 1923 .ops = &clk_branch2_ops, 1924 }, 1925 }, 1926 }; 1927 1928 static struct clk_branch gcc_sdcc2_apps_clk = { 1929 .halt_reg = 0x0504, 1930 .clkr = { 1931 .enable_reg = 0x0504, 1932 .enable_mask = BIT(0), 1933 .hw.init = &(struct clk_init_data){ 1934 .name = "gcc_sdcc2_apps_clk", 1935 .parent_hws = (const struct clk_hw *[]){ &sdcc2_apps_clk_src.clkr.hw }, 1936 .num_parents = 1, 1937 .flags = CLK_SET_RATE_PARENT, 1938 .ops = &clk_branch2_ops, 1939 }, 1940 }, 1941 }; 1942 1943 static struct clk_branch gcc_sdcc3_ahb_clk = { 1944 .halt_reg = 0x0548, 1945 .clkr = { 1946 .enable_reg = 0x0548, 1947 .enable_mask = BIT(0), 1948 .hw.init = &(struct clk_init_data){ 1949 .name = "gcc_sdcc3_ahb_clk", 1950 .parent_names = (const char *[]){ 1951 "periph_noc_clk_src", 1952 }, 1953 .num_parents = 1, 1954 .ops = &clk_branch2_ops, 1955 }, 1956 }, 1957 }; 1958 1959 static struct clk_branch gcc_sdcc3_apps_clk = { 1960 .halt_reg = 0x0544, 1961 .clkr = { 1962 .enable_reg = 0x0544, 1963 .enable_mask = BIT(0), 1964 .hw.init = &(struct clk_init_data){ 1965 .name = "gcc_sdcc3_apps_clk", 1966 .parent_hws = (const struct clk_hw *[]){ &sdcc3_apps_clk_src.clkr.hw }, 1967 .num_parents = 1, 1968 .flags = CLK_SET_RATE_PARENT, 1969 .ops = &clk_branch2_ops, 1970 }, 1971 }, 1972 }; 1973 1974 static struct clk_branch gcc_sdcc4_ahb_clk = { 1975 .halt_reg = 0x0588, 1976 .clkr = { 1977 .enable_reg = 0x0588, 1978 .enable_mask = BIT(0), 1979 .hw.init = &(struct clk_init_data){ 1980 .name = "gcc_sdcc4_ahb_clk", 1981 .parent_names = (const char *[]){ 1982 "periph_noc_clk_src", 1983 }, 1984 .num_parents = 1, 1985 .ops = &clk_branch2_ops, 1986 }, 1987 }, 1988 }; 1989 1990 static struct clk_branch gcc_sdcc4_apps_clk = { 1991 .halt_reg = 0x0584, 1992 .clkr = { 1993 .enable_reg = 0x0584, 1994 .enable_mask = BIT(0), 1995 .hw.init = &(struct clk_init_data){ 1996 .name = "gcc_sdcc4_apps_clk", 1997 .parent_hws = (const struct clk_hw *[]){ &sdcc4_apps_clk_src.clkr.hw }, 1998 .num_parents = 1, 1999 .flags = CLK_SET_RATE_PARENT, 2000 .ops = &clk_branch2_ops, 2001 }, 2002 }, 2003 }; 2004 2005 static struct clk_branch gcc_sys_noc_ufs_axi_clk = { 2006 .halt_reg = 0x1d7c, 2007 .clkr = { 2008 .enable_reg = 0x1d7c, 2009 .enable_mask = BIT(0), 2010 .hw.init = &(struct clk_init_data){ 2011 .name = "gcc_sys_noc_ufs_axi_clk", 2012 .parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw }, 2013 .num_parents = 1, 2014 .flags = CLK_SET_RATE_PARENT, 2015 .ops = &clk_branch2_ops, 2016 }, 2017 }, 2018 }; 2019 2020 static struct clk_branch gcc_sys_noc_usb3_axi_clk = { 2021 .halt_reg = 0x03fc, 2022 .clkr = { 2023 .enable_reg = 0x03fc, 2024 .enable_mask = BIT(0), 2025 .hw.init = &(struct clk_init_data){ 2026 .name = "gcc_sys_noc_usb3_axi_clk", 2027 .parent_hws = (const struct clk_hw *[]){ &usb30_master_clk_src.clkr.hw }, 2028 .num_parents = 1, 2029 .flags = CLK_SET_RATE_PARENT, 2030 .ops = &clk_branch2_ops, 2031 }, 2032 }, 2033 }; 2034 2035 static struct clk_branch gcc_tsif_ahb_clk = { 2036 .halt_reg = 0x0d84, 2037 .clkr = { 2038 .enable_reg = 0x0d84, 2039 .enable_mask = BIT(0), 2040 .hw.init = &(struct clk_init_data){ 2041 .name = "gcc_tsif_ahb_clk", 2042 .ops = &clk_branch2_ops, 2043 }, 2044 }, 2045 }; 2046 2047 static struct clk_branch gcc_tsif_ref_clk = { 2048 .halt_reg = 0x0d88, 2049 .clkr = { 2050 .enable_reg = 0x0d88, 2051 .enable_mask = BIT(0), 2052 .hw.init = &(struct clk_init_data){ 2053 .name = "gcc_tsif_ref_clk", 2054 .parent_hws = (const struct clk_hw *[]){ &tsif_ref_clk_src.clkr.hw }, 2055 .num_parents = 1, 2056 .flags = CLK_SET_RATE_PARENT, 2057 .ops = &clk_branch2_ops, 2058 }, 2059 }, 2060 }; 2061 2062 static struct clk_branch gcc_ufs_ahb_clk = { 2063 .halt_reg = 0x1d4c, 2064 .clkr = { 2065 .enable_reg = 0x1d4c, 2066 .enable_mask = BIT(0), 2067 .hw.init = &(struct clk_init_data){ 2068 .name = "gcc_ufs_ahb_clk", 2069 .ops = &clk_branch2_ops, 2070 }, 2071 }, 2072 }; 2073 2074 static struct clk_branch gcc_ufs_axi_clk = { 2075 .halt_reg = 0x1d48, 2076 .clkr = { 2077 .enable_reg = 0x1d48, 2078 .enable_mask = BIT(0), 2079 .hw.init = &(struct clk_init_data){ 2080 .name = "gcc_ufs_axi_clk", 2081 .parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw }, 2082 .num_parents = 1, 2083 .flags = CLK_SET_RATE_PARENT, 2084 .ops = &clk_branch2_ops, 2085 }, 2086 }, 2087 }; 2088 2089 static struct clk_branch gcc_ufs_rx_cfg_clk = { 2090 .halt_reg = 0x1d54, 2091 .clkr = { 2092 .enable_reg = 0x1d54, 2093 .enable_mask = BIT(0), 2094 .hw.init = &(struct clk_init_data){ 2095 .name = "gcc_ufs_rx_cfg_clk", 2096 .parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw }, 2097 .num_parents = 1, 2098 .flags = CLK_SET_RATE_PARENT, 2099 .ops = &clk_branch2_ops, 2100 }, 2101 }, 2102 }; 2103 2104 static struct clk_branch gcc_ufs_rx_symbol_0_clk = { 2105 .halt_reg = 0x1d60, 2106 .halt_check = BRANCH_HALT_DELAY, 2107 .clkr = { 2108 .enable_reg = 0x1d60, 2109 .enable_mask = BIT(0), 2110 .hw.init = &(struct clk_init_data){ 2111 .name = "gcc_ufs_rx_symbol_0_clk", 2112 .ops = &clk_branch2_ops, 2113 }, 2114 }, 2115 }; 2116 2117 static struct clk_branch gcc_ufs_rx_symbol_1_clk = { 2118 .halt_reg = 0x1d64, 2119 .halt_check = BRANCH_HALT_DELAY, 2120 .clkr = { 2121 .enable_reg = 0x1d64, 2122 .enable_mask = BIT(0), 2123 .hw.init = &(struct clk_init_data){ 2124 .name = "gcc_ufs_rx_symbol_1_clk", 2125 .ops = &clk_branch2_ops, 2126 }, 2127 }, 2128 }; 2129 2130 static struct clk_branch gcc_ufs_tx_cfg_clk = { 2131 .halt_reg = 0x1d50, 2132 .clkr = { 2133 .enable_reg = 0x1d50, 2134 .enable_mask = BIT(0), 2135 .hw.init = &(struct clk_init_data){ 2136 .name = "gcc_ufs_tx_cfg_clk", 2137 .parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw }, 2138 .num_parents = 1, 2139 .flags = CLK_SET_RATE_PARENT, 2140 .ops = &clk_branch2_ops, 2141 }, 2142 }, 2143 }; 2144 2145 static struct clk_branch gcc_ufs_tx_symbol_0_clk = { 2146 .halt_reg = 0x1d58, 2147 .halt_check = BRANCH_HALT_DELAY, 2148 .clkr = { 2149 .enable_reg = 0x1d58, 2150 .enable_mask = BIT(0), 2151 .hw.init = &(struct clk_init_data){ 2152 .name = "gcc_ufs_tx_symbol_0_clk", 2153 .ops = &clk_branch2_ops, 2154 }, 2155 }, 2156 }; 2157 2158 static struct clk_branch gcc_ufs_tx_symbol_1_clk = { 2159 .halt_reg = 0x1d5c, 2160 .halt_check = BRANCH_HALT_DELAY, 2161 .clkr = { 2162 .enable_reg = 0x1d5c, 2163 .enable_mask = BIT(0), 2164 .hw.init = &(struct clk_init_data){ 2165 .name = "gcc_ufs_tx_symbol_1_clk", 2166 .ops = &clk_branch2_ops, 2167 }, 2168 }, 2169 }; 2170 2171 static struct clk_branch gcc_usb2_hs_phy_sleep_clk = { 2172 .halt_reg = 0x04ac, 2173 .clkr = { 2174 .enable_reg = 0x04ac, 2175 .enable_mask = BIT(0), 2176 .hw.init = &(struct clk_init_data){ 2177 .name = "gcc_usb2_hs_phy_sleep_clk", 2178 .parent_data = &(const struct clk_parent_data){ 2179 .fw_name = "sleep", 2180 .name = "sleep" 2181 }, 2182 .num_parents = 1, 2183 .ops = &clk_branch2_ops, 2184 }, 2185 }, 2186 }; 2187 2188 static struct clk_branch gcc_usb30_master_clk = { 2189 .halt_reg = 0x03c8, 2190 .clkr = { 2191 .enable_reg = 0x03c8, 2192 .enable_mask = BIT(0), 2193 .hw.init = &(struct clk_init_data){ 2194 .name = "gcc_usb30_master_clk", 2195 .parent_hws = (const struct clk_hw *[]){ &usb30_master_clk_src.clkr.hw }, 2196 .num_parents = 1, 2197 .flags = CLK_SET_RATE_PARENT, 2198 .ops = &clk_branch2_ops, 2199 }, 2200 }, 2201 }; 2202 2203 static struct clk_branch gcc_usb30_mock_utmi_clk = { 2204 .halt_reg = 0x03d0, 2205 .clkr = { 2206 .enable_reg = 0x03d0, 2207 .enable_mask = BIT(0), 2208 .hw.init = &(struct clk_init_data){ 2209 .name = "gcc_usb30_mock_utmi_clk", 2210 .parent_hws = (const struct clk_hw *[]){ &usb30_mock_utmi_clk_src.clkr.hw }, 2211 .num_parents = 1, 2212 .flags = CLK_SET_RATE_PARENT, 2213 .ops = &clk_branch2_ops, 2214 }, 2215 }, 2216 }; 2217 2218 static struct clk_branch gcc_usb30_sleep_clk = { 2219 .halt_reg = 0x03cc, 2220 .clkr = { 2221 .enable_reg = 0x03cc, 2222 .enable_mask = BIT(0), 2223 .hw.init = &(struct clk_init_data){ 2224 .name = "gcc_usb30_sleep_clk", 2225 .parent_data = &(const struct clk_parent_data){ 2226 .fw_name = "sleep", 2227 .name = "sleep" 2228 }, 2229 .num_parents = 1, 2230 .ops = &clk_branch2_ops, 2231 }, 2232 }, 2233 }; 2234 2235 static struct clk_branch gcc_usb3_phy_aux_clk = { 2236 .halt_reg = 0x1408, 2237 .clkr = { 2238 .enable_reg = 0x1408, 2239 .enable_mask = BIT(0), 2240 .hw.init = &(struct clk_init_data){ 2241 .name = "gcc_usb3_phy_aux_clk", 2242 .parent_hws = (const struct clk_hw *[]){ &usb3_phy_aux_clk_src.clkr.hw }, 2243 .num_parents = 1, 2244 .flags = CLK_SET_RATE_PARENT, 2245 .ops = &clk_branch2_ops, 2246 }, 2247 }, 2248 }; 2249 2250 static struct clk_branch gcc_usb_hs_ahb_clk = { 2251 .halt_reg = 0x0488, 2252 .clkr = { 2253 .enable_reg = 0x0488, 2254 .enable_mask = BIT(0), 2255 .hw.init = &(struct clk_init_data){ 2256 .name = "gcc_usb_hs_ahb_clk", 2257 .ops = &clk_branch2_ops, 2258 }, 2259 }, 2260 }; 2261 2262 static struct clk_branch gcc_usb_hs_system_clk = { 2263 .halt_reg = 0x0484, 2264 .clkr = { 2265 .enable_reg = 0x0484, 2266 .enable_mask = BIT(0), 2267 .hw.init = &(struct clk_init_data){ 2268 .name = "gcc_usb_hs_system_clk", 2269 .parent_hws = (const struct clk_hw *[]){ &usb_hs_system_clk_src.clkr.hw }, 2270 .num_parents = 1, 2271 .flags = CLK_SET_RATE_PARENT, 2272 .ops = &clk_branch2_ops, 2273 }, 2274 }, 2275 }; 2276 2277 static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = { 2278 .halt_reg = 0x1a84, 2279 .clkr = { 2280 .enable_reg = 0x1a84, 2281 .enable_mask = BIT(0), 2282 .hw.init = &(struct clk_init_data){ 2283 .name = "gcc_usb_phy_cfg_ahb2phy_clk", 2284 .ops = &clk_branch2_ops, 2285 }, 2286 }, 2287 }; 2288 2289 static struct gdsc pcie_gdsc = { 2290 .gdscr = 0x1e18, 2291 .pd = { 2292 .name = "pcie", 2293 }, 2294 .pwrsts = PWRSTS_OFF_ON, 2295 }; 2296 2297 static struct gdsc pcie_0_gdsc = { 2298 .gdscr = 0x1ac4, 2299 .pd = { 2300 .name = "pcie_0", 2301 }, 2302 .pwrsts = PWRSTS_OFF_ON, 2303 }; 2304 2305 static struct gdsc pcie_1_gdsc = { 2306 .gdscr = 0x1b44, 2307 .pd = { 2308 .name = "pcie_1", 2309 }, 2310 .pwrsts = PWRSTS_OFF_ON, 2311 }; 2312 2313 static struct gdsc usb30_gdsc = { 2314 .gdscr = 0x3c4, 2315 .pd = { 2316 .name = "usb30", 2317 }, 2318 .pwrsts = PWRSTS_OFF_ON, 2319 }; 2320 2321 static struct gdsc ufs_gdsc = { 2322 .gdscr = 0x1d44, 2323 .pd = { 2324 .name = "ufs", 2325 }, 2326 .pwrsts = PWRSTS_OFF_ON, 2327 }; 2328 2329 static struct clk_regmap *gcc_msm8994_clocks[] = { 2330 [GPLL0_EARLY] = &gpll0_early.clkr, 2331 [GPLL0] = &gpll0.clkr, 2332 [GPLL4_EARLY] = &gpll4_early.clkr, 2333 [GPLL4] = &gpll4.clkr, 2334 [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr, 2335 [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr, 2336 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr, 2337 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr, 2338 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr, 2339 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr, 2340 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr, 2341 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr, 2342 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr, 2343 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr, 2344 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr, 2345 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr, 2346 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr, 2347 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr, 2348 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr, 2349 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr, 2350 [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr, 2351 [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr, 2352 [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr, 2353 [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr, 2354 [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr, 2355 [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr, 2356 [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr, 2357 [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr, 2358 [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr, 2359 [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr, 2360 [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr, 2361 [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr, 2362 [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr, 2363 [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr, 2364 [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr, 2365 [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr, 2366 [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr, 2367 [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr, 2368 [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr, 2369 [BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr, 2370 [BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr, 2371 [BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr, 2372 [GP1_CLK_SRC] = &gp1_clk_src.clkr, 2373 [GP2_CLK_SRC] = &gp2_clk_src.clkr, 2374 [GP3_CLK_SRC] = &gp3_clk_src.clkr, 2375 [PCIE_0_AUX_CLK_SRC] = &pcie_0_aux_clk_src.clkr, 2376 [PCIE_0_PIPE_CLK_SRC] = &pcie_0_pipe_clk_src.clkr, 2377 [PCIE_1_AUX_CLK_SRC] = &pcie_1_aux_clk_src.clkr, 2378 [PCIE_1_PIPE_CLK_SRC] = &pcie_1_pipe_clk_src.clkr, 2379 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr, 2380 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr, 2381 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr, 2382 [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr, 2383 [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr, 2384 [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr, 2385 [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr, 2386 [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr, 2387 [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr, 2388 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr, 2389 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr, 2390 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr, 2391 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr, 2392 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr, 2393 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr, 2394 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr, 2395 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr, 2396 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr, 2397 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr, 2398 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr, 2399 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr, 2400 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr, 2401 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, 2402 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr, 2403 [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr, 2404 [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr, 2405 [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr, 2406 [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr, 2407 [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr, 2408 [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr, 2409 [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr, 2410 [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr, 2411 [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr, 2412 [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr, 2413 [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr, 2414 [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr, 2415 [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr, 2416 [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr, 2417 [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr, 2418 [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr, 2419 [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr, 2420 [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr, 2421 [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr, 2422 [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr, 2423 [GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr, 2424 [GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr, 2425 [GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr, 2426 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 2427 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 2428 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 2429 [GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr, 2430 [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr, 2431 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, 2432 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, 2433 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, 2434 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, 2435 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, 2436 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr, 2437 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr, 2438 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr, 2439 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr, 2440 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr, 2441 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 2442 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 2443 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, 2444 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, 2445 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 2446 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 2447 [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr, 2448 [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr, 2449 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, 2450 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, 2451 [GCC_SYS_NOC_UFS_AXI_CLK] = &gcc_sys_noc_ufs_axi_clk.clkr, 2452 [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr, 2453 [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr, 2454 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr, 2455 [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr, 2456 [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr, 2457 [GCC_UFS_RX_CFG_CLK] = &gcc_ufs_rx_cfg_clk.clkr, 2458 [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr, 2459 [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr, 2460 [GCC_UFS_TX_CFG_CLK] = &gcc_ufs_tx_cfg_clk.clkr, 2461 [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr, 2462 [GCC_UFS_TX_SYMBOL_1_CLK] = &gcc_ufs_tx_symbol_1_clk.clkr, 2463 [GCC_USB2_HS_PHY_SLEEP_CLK] = &gcc_usb2_hs_phy_sleep_clk.clkr, 2464 [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr, 2465 [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr, 2466 [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr, 2467 [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr, 2468 [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr, 2469 [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr, 2470 [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr, 2471 }; 2472 2473 static struct gdsc *gcc_msm8994_gdscs[] = { 2474 [PCIE_GDSC] = &pcie_gdsc, 2475 [PCIE_0_GDSC] = &pcie_0_gdsc, 2476 [PCIE_1_GDSC] = &pcie_1_gdsc, 2477 [USB30_GDSC] = &usb30_gdsc, 2478 [UFS_GDSC] = &ufs_gdsc, 2479 }; 2480 2481 static const struct qcom_reset_map gcc_msm8994_resets[] = { 2482 [USB3_PHY_RESET] = { 0x1400 }, 2483 [USB3PHY_PHY_RESET] = { 0x1404 }, 2484 [PCIE_PHY_0_RESET] = { 0x1b18 }, 2485 [PCIE_PHY_1_RESET] = { 0x1b98 }, 2486 [QUSB2_PHY_RESET] = { 0x04b8 }, 2487 }; 2488 2489 static const struct regmap_config gcc_msm8994_regmap_config = { 2490 .reg_bits = 32, 2491 .reg_stride = 4, 2492 .val_bits = 32, 2493 .max_register = 0x2000, 2494 .fast_io = true, 2495 }; 2496 2497 static const struct qcom_cc_desc gcc_msm8994_desc = { 2498 .config = &gcc_msm8994_regmap_config, 2499 .clks = gcc_msm8994_clocks, 2500 .num_clks = ARRAY_SIZE(gcc_msm8994_clocks), 2501 .resets = gcc_msm8994_resets, 2502 .num_resets = ARRAY_SIZE(gcc_msm8994_resets), 2503 .gdscs = gcc_msm8994_gdscs, 2504 .num_gdscs = ARRAY_SIZE(gcc_msm8994_gdscs), 2505 }; 2506 2507 static const struct of_device_id gcc_msm8994_match_table[] = { 2508 { .compatible = "qcom,gcc-msm8994" }, 2509 {} 2510 }; 2511 MODULE_DEVICE_TABLE(of, gcc_msm8994_match_table); 2512 2513 static int gcc_msm8994_probe(struct platform_device *pdev) 2514 { 2515 return qcom_cc_probe(pdev, &gcc_msm8994_desc); 2516 } 2517 2518 static struct platform_driver gcc_msm8994_driver = { 2519 .probe = gcc_msm8994_probe, 2520 .driver = { 2521 .name = "gcc-msm8994", 2522 .of_match_table = gcc_msm8994_match_table, 2523 }, 2524 }; 2525 2526 static int __init gcc_msm8994_init(void) 2527 { 2528 return platform_driver_register(&gcc_msm8994_driver); 2529 } 2530 core_initcall(gcc_msm8994_init); 2531 2532 static void __exit gcc_msm8994_exit(void) 2533 { 2534 platform_driver_unregister(&gcc_msm8994_driver); 2535 } 2536 module_exit(gcc_msm8994_exit); 2537 2538 MODULE_DESCRIPTION("Qualcomm GCC MSM8994 Driver"); 2539 MODULE_LICENSE("GPL v2"); 2540 MODULE_ALIAS("platform:gcc-msm8994"); 2541