1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. 3 */ 4 5 #include <linux/clk-provider.h> 6 #include <linux/kernel.h> 7 #include <linux/init.h> 8 #include <linux/err.h> 9 #include <linux/ctype.h> 10 #include <linux/io.h> 11 #include <linux/of.h> 12 #include <linux/of_device.h> 13 #include <linux/platform_device.h> 14 #include <linux/module.h> 15 #include <linux/regmap.h> 16 17 #include <dt-bindings/clock/qcom,gcc-msm8994.h> 18 19 #include "common.h" 20 #include "clk-regmap.h" 21 #include "clk-alpha-pll.h" 22 #include "clk-rcg.h" 23 #include "clk-branch.h" 24 #include "reset.h" 25 #include "gdsc.h" 26 27 enum { 28 P_XO, 29 P_GPLL0, 30 P_GPLL4, 31 }; 32 33 static struct clk_alpha_pll gpll0_early = { 34 .offset = 0, 35 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 36 .clkr = { 37 .enable_reg = 0x1480, 38 .enable_mask = BIT(0), 39 .hw.init = &(struct clk_init_data){ 40 .name = "gpll0_early", 41 .parent_data = &(const struct clk_parent_data){ 42 .fw_name = "xo", 43 }, 44 .num_parents = 1, 45 .ops = &clk_alpha_pll_ops, 46 }, 47 }, 48 }; 49 50 static struct clk_alpha_pll_postdiv gpll0 = { 51 .offset = 0, 52 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 53 .clkr.hw.init = &(struct clk_init_data){ 54 .name = "gpll0", 55 .parent_names = (const char *[]) { "gpll0_early" }, 56 .num_parents = 1, 57 .ops = &clk_alpha_pll_postdiv_ops, 58 }, 59 }; 60 61 static struct clk_alpha_pll gpll4_early = { 62 .offset = 0x1dc0, 63 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 64 .clkr = { 65 .enable_reg = 0x1480, 66 .enable_mask = BIT(4), 67 .hw.init = &(struct clk_init_data){ 68 .name = "gpll4_early", 69 .parent_data = &(const struct clk_parent_data){ 70 .fw_name = "xo", 71 }, 72 .num_parents = 1, 73 .ops = &clk_alpha_pll_ops, 74 }, 75 }, 76 }; 77 78 static struct clk_alpha_pll_postdiv gpll4 = { 79 .offset = 0x1dc0, 80 .width = 4, 81 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 82 .clkr.hw.init = &(struct clk_init_data){ 83 .name = "gpll4", 84 .parent_names = (const char *[]) { "gpll4_early" }, 85 .num_parents = 1, 86 .ops = &clk_alpha_pll_postdiv_ops, 87 }, 88 }; 89 90 static const struct parent_map gcc_xo_gpll0_map[] = { 91 { P_XO, 0 }, 92 { P_GPLL0, 1 }, 93 }; 94 95 static const struct clk_parent_data gcc_xo_gpll0[] = { 96 { .fw_name = "xo" }, 97 { .hw = &gpll0.clkr.hw }, 98 }; 99 100 static const struct parent_map gcc_xo_gpll0_gpll4_map[] = { 101 { P_XO, 0 }, 102 { P_GPLL0, 1 }, 103 { P_GPLL4, 5 }, 104 }; 105 106 static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = { 107 { .fw_name = "xo" }, 108 { .hw = &gpll0.clkr.hw }, 109 { .hw = &gpll4.clkr.hw }, 110 }; 111 112 static struct clk_rcg2 system_noc_clk_src = { 113 .cmd_rcgr = 0x0120, 114 .hid_width = 5, 115 .parent_map = gcc_xo_gpll0_map, 116 .clkr.hw.init = &(struct clk_init_data){ 117 .name = "system_noc_clk_src", 118 .parent_data = gcc_xo_gpll0, 119 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 120 .ops = &clk_rcg2_ops, 121 }, 122 }; 123 124 static struct clk_rcg2 config_noc_clk_src = { 125 .cmd_rcgr = 0x0150, 126 .hid_width = 5, 127 .parent_map = gcc_xo_gpll0_map, 128 .clkr.hw.init = &(struct clk_init_data){ 129 .name = "config_noc_clk_src", 130 .parent_data = gcc_xo_gpll0, 131 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 132 .ops = &clk_rcg2_ops, 133 }, 134 }; 135 136 static struct clk_rcg2 periph_noc_clk_src = { 137 .cmd_rcgr = 0x0190, 138 .hid_width = 5, 139 .parent_map = gcc_xo_gpll0_map, 140 .clkr.hw.init = &(struct clk_init_data){ 141 .name = "periph_noc_clk_src", 142 .parent_data = gcc_xo_gpll0, 143 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 144 .ops = &clk_rcg2_ops, 145 }, 146 }; 147 148 static struct freq_tbl ftbl_ufs_axi_clk_src[] = { 149 F(50000000, P_GPLL0, 12, 0, 0), 150 F(100000000, P_GPLL0, 6, 0, 0), 151 F(150000000, P_GPLL0, 4, 0, 0), 152 F(171430000, P_GPLL0, 3.5, 0, 0), 153 F(200000000, P_GPLL0, 3, 0, 0), 154 F(240000000, P_GPLL0, 2.5, 0, 0), 155 { } 156 }; 157 158 static struct clk_rcg2 ufs_axi_clk_src = { 159 .cmd_rcgr = 0x1d68, 160 .mnd_width = 8, 161 .hid_width = 5, 162 .parent_map = gcc_xo_gpll0_map, 163 .freq_tbl = ftbl_ufs_axi_clk_src, 164 .clkr.hw.init = &(struct clk_init_data){ 165 .name = "ufs_axi_clk_src", 166 .parent_data = gcc_xo_gpll0, 167 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 168 .ops = &clk_rcg2_ops, 169 }, 170 }; 171 172 static struct freq_tbl ftbl_usb30_master_clk_src[] = { 173 F(19200000, P_XO, 1, 0, 0), 174 F(125000000, P_GPLL0, 1, 5, 24), 175 { } 176 }; 177 178 static struct clk_rcg2 usb30_master_clk_src = { 179 .cmd_rcgr = 0x03d4, 180 .mnd_width = 8, 181 .hid_width = 5, 182 .parent_map = gcc_xo_gpll0_map, 183 .freq_tbl = ftbl_usb30_master_clk_src, 184 .clkr.hw.init = &(struct clk_init_data){ 185 .name = "usb30_master_clk_src", 186 .parent_data = gcc_xo_gpll0, 187 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 188 .ops = &clk_rcg2_ops, 189 }, 190 }; 191 192 static struct freq_tbl ftbl_blsp_i2c_apps_clk_src[] = { 193 F(19200000, P_XO, 1, 0, 0), 194 F(50000000, P_GPLL0, 12, 0, 0), 195 { } 196 }; 197 198 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { 199 .cmd_rcgr = 0x0660, 200 .hid_width = 5, 201 .parent_map = gcc_xo_gpll0_map, 202 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 203 .clkr.hw.init = &(struct clk_init_data){ 204 .name = "blsp1_qup1_i2c_apps_clk_src", 205 .parent_data = gcc_xo_gpll0, 206 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 207 .ops = &clk_rcg2_ops, 208 }, 209 }; 210 211 static struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = { 212 F(960000, P_XO, 10, 1, 2), 213 F(4800000, P_XO, 4, 0, 0), 214 F(9600000, P_XO, 2, 0, 0), 215 F(15000000, P_GPLL0, 10, 1, 4), 216 F(19200000, P_XO, 1, 0, 0), 217 F(24000000, P_GPLL0, 12.5, 1, 2), 218 F(25000000, P_GPLL0, 12, 1, 2), 219 F(48000000, P_GPLL0, 12.5, 0, 0), 220 F(50000000, P_GPLL0, 12, 0, 0), 221 { } 222 }; 223 224 static struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src_8992[] = { 225 F(960000, P_XO, 10, 1, 2), 226 F(4800000, P_XO, 4, 0, 0), 227 F(9600000, P_XO, 2, 0, 0), 228 F(15000000, P_GPLL0, 10, 1, 4), 229 F(19200000, P_XO, 1, 0, 0), 230 F(25000000, P_GPLL0, 12, 1, 2), 231 F(50000000, P_GPLL0, 12, 0, 0), 232 { } 233 }; 234 235 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { 236 .cmd_rcgr = 0x064c, 237 .mnd_width = 8, 238 .hid_width = 5, 239 .parent_map = gcc_xo_gpll0_map, 240 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 241 .clkr.hw.init = &(struct clk_init_data){ 242 .name = "blsp1_qup1_spi_apps_clk_src", 243 .parent_data = gcc_xo_gpll0, 244 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 245 .ops = &clk_rcg2_ops, 246 }, 247 }; 248 249 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { 250 .cmd_rcgr = 0x06e0, 251 .hid_width = 5, 252 .parent_map = gcc_xo_gpll0_map, 253 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 254 .clkr.hw.init = &(struct clk_init_data){ 255 .name = "blsp1_qup2_i2c_apps_clk_src", 256 .parent_data = gcc_xo_gpll0, 257 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 258 .ops = &clk_rcg2_ops, 259 }, 260 }; 261 262 static struct freq_tbl ftbl_blsp1_qup2_spi_apps_clk_src[] = { 263 F(960000, P_XO, 10, 1, 2), 264 F(4800000, P_XO, 4, 0, 0), 265 F(9600000, P_XO, 2, 0, 0), 266 F(15000000, P_GPLL0, 10, 1, 4), 267 F(19200000, P_XO, 1, 0, 0), 268 F(24000000, P_GPLL0, 12.5, 1, 2), 269 F(25000000, P_GPLL0, 12, 1, 2), 270 F(42860000, P_GPLL0, 14, 0, 0), 271 F(46150000, P_GPLL0, 13, 0, 0), 272 { } 273 }; 274 275 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { 276 .cmd_rcgr = 0x06cc, 277 .mnd_width = 8, 278 .hid_width = 5, 279 .parent_map = gcc_xo_gpll0_map, 280 .freq_tbl = ftbl_blsp1_qup2_spi_apps_clk_src, 281 .clkr.hw.init = &(struct clk_init_data){ 282 .name = "blsp1_qup2_spi_apps_clk_src", 283 .parent_data = gcc_xo_gpll0, 284 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 285 .ops = &clk_rcg2_ops, 286 }, 287 }; 288 289 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { 290 .cmd_rcgr = 0x0760, 291 .hid_width = 5, 292 .parent_map = gcc_xo_gpll0_map, 293 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 294 .clkr.hw.init = &(struct clk_init_data){ 295 .name = "blsp1_qup3_i2c_apps_clk_src", 296 .parent_data = gcc_xo_gpll0, 297 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 298 .ops = &clk_rcg2_ops, 299 }, 300 }; 301 302 static struct freq_tbl ftbl_blsp1_qup3_4_spi_apps_clk_src[] = { 303 F(960000, P_XO, 10, 1, 2), 304 F(4800000, P_XO, 4, 0, 0), 305 F(9600000, P_XO, 2, 0, 0), 306 F(15000000, P_GPLL0, 10, 1, 4), 307 F(19200000, P_XO, 1, 0, 0), 308 F(24000000, P_GPLL0, 12.5, 1, 2), 309 F(25000000, P_GPLL0, 12, 1, 2), 310 F(42860000, P_GPLL0, 14, 0, 0), 311 F(44440000, P_GPLL0, 13.5, 0, 0), 312 { } 313 }; 314 315 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { 316 .cmd_rcgr = 0x074c, 317 .mnd_width = 8, 318 .hid_width = 5, 319 .parent_map = gcc_xo_gpll0_map, 320 .freq_tbl = ftbl_blsp1_qup3_4_spi_apps_clk_src, 321 .clkr.hw.init = &(struct clk_init_data){ 322 .name = "blsp1_qup3_spi_apps_clk_src", 323 .parent_data = gcc_xo_gpll0, 324 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 325 .ops = &clk_rcg2_ops, 326 }, 327 }; 328 329 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { 330 .cmd_rcgr = 0x07e0, 331 .hid_width = 5, 332 .parent_map = gcc_xo_gpll0_map, 333 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 334 .clkr.hw.init = &(struct clk_init_data){ 335 .name = "blsp1_qup4_i2c_apps_clk_src", 336 .parent_data = gcc_xo_gpll0, 337 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 338 .ops = &clk_rcg2_ops, 339 }, 340 }; 341 342 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { 343 .cmd_rcgr = 0x07cc, 344 .mnd_width = 8, 345 .hid_width = 5, 346 .parent_map = gcc_xo_gpll0_map, 347 .freq_tbl = ftbl_blsp1_qup3_4_spi_apps_clk_src, 348 .clkr.hw.init = &(struct clk_init_data){ 349 .name = "blsp1_qup4_spi_apps_clk_src", 350 .parent_data = gcc_xo_gpll0, 351 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 352 .ops = &clk_rcg2_ops, 353 }, 354 }; 355 356 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = { 357 .cmd_rcgr = 0x0860, 358 .hid_width = 5, 359 .parent_map = gcc_xo_gpll0_map, 360 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 361 .clkr.hw.init = &(struct clk_init_data){ 362 .name = "blsp1_qup5_i2c_apps_clk_src", 363 .parent_data = gcc_xo_gpll0, 364 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 365 .ops = &clk_rcg2_ops, 366 }, 367 }; 368 369 static struct freq_tbl ftbl_blsp1_qup5_spi_apps_clk_src[] = { 370 F(960000, P_XO, 10, 1, 2), 371 F(4800000, P_XO, 4, 0, 0), 372 F(9600000, P_XO, 2, 0, 0), 373 F(15000000, P_GPLL0, 10, 1, 4), 374 F(19200000, P_XO, 1, 0, 0), 375 F(24000000, P_GPLL0, 12.5, 1, 2), 376 F(25000000, P_GPLL0, 12, 1, 2), 377 F(40000000, P_GPLL0, 15, 0, 0), 378 F(42860000, P_GPLL0, 14, 0, 0), 379 { } 380 }; 381 382 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = { 383 .cmd_rcgr = 0x084c, 384 .mnd_width = 8, 385 .hid_width = 5, 386 .parent_map = gcc_xo_gpll0_map, 387 .freq_tbl = ftbl_blsp1_qup5_spi_apps_clk_src, 388 .clkr.hw.init = &(struct clk_init_data){ 389 .name = "blsp1_qup5_spi_apps_clk_src", 390 .parent_data = gcc_xo_gpll0, 391 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 392 .ops = &clk_rcg2_ops, 393 }, 394 }; 395 396 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = { 397 .cmd_rcgr = 0x08e0, 398 .hid_width = 5, 399 .parent_map = gcc_xo_gpll0_map, 400 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 401 .clkr.hw.init = &(struct clk_init_data){ 402 .name = "blsp1_qup6_i2c_apps_clk_src", 403 .parent_data = gcc_xo_gpll0, 404 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 405 .ops = &clk_rcg2_ops, 406 }, 407 }; 408 409 static struct freq_tbl ftbl_blsp1_qup6_spi_apps_clk_src[] = { 410 F(960000, P_XO, 10, 1, 2), 411 F(4800000, P_XO, 4, 0, 0), 412 F(9600000, P_XO, 2, 0, 0), 413 F(15000000, P_GPLL0, 10, 1, 4), 414 F(19200000, P_XO, 1, 0, 0), 415 F(24000000, P_GPLL0, 12.5, 1, 2), 416 F(27906976, P_GPLL0, 1, 2, 43), 417 F(41380000, P_GPLL0, 15, 0, 0), 418 F(42860000, P_GPLL0, 14, 0, 0), 419 { } 420 }; 421 422 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = { 423 .cmd_rcgr = 0x08cc, 424 .mnd_width = 8, 425 .hid_width = 5, 426 .parent_map = gcc_xo_gpll0_map, 427 .freq_tbl = ftbl_blsp1_qup6_spi_apps_clk_src, 428 .clkr.hw.init = &(struct clk_init_data){ 429 .name = "blsp1_qup6_spi_apps_clk_src", 430 .parent_data = gcc_xo_gpll0, 431 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 432 .ops = &clk_rcg2_ops, 433 }, 434 }; 435 436 static struct freq_tbl ftbl_blsp_uart_apps_clk_src[] = { 437 F(3686400, P_GPLL0, 1, 96, 15625), 438 F(7372800, P_GPLL0, 1, 192, 15625), 439 F(14745600, P_GPLL0, 1, 384, 15625), 440 F(16000000, P_GPLL0, 5, 2, 15), 441 F(19200000, P_XO, 1, 0, 0), 442 F(24000000, P_GPLL0, 5, 1, 5), 443 F(32000000, P_GPLL0, 1, 4, 75), 444 F(40000000, P_GPLL0, 15, 0, 0), 445 F(46400000, P_GPLL0, 1, 29, 375), 446 F(48000000, P_GPLL0, 12.5, 0, 0), 447 F(51200000, P_GPLL0, 1, 32, 375), 448 F(56000000, P_GPLL0, 1, 7, 75), 449 F(58982400, P_GPLL0, 1, 1536, 15625), 450 F(60000000, P_GPLL0, 10, 0, 0), 451 F(63160000, P_GPLL0, 9.5, 0, 0), 452 { } 453 }; 454 455 static struct clk_rcg2 blsp1_uart1_apps_clk_src = { 456 .cmd_rcgr = 0x068c, 457 .mnd_width = 16, 458 .hid_width = 5, 459 .parent_map = gcc_xo_gpll0_map, 460 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 461 .clkr.hw.init = &(struct clk_init_data){ 462 .name = "blsp1_uart1_apps_clk_src", 463 .parent_data = gcc_xo_gpll0, 464 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 465 .ops = &clk_rcg2_ops, 466 }, 467 }; 468 469 static struct clk_rcg2 blsp1_uart2_apps_clk_src = { 470 .cmd_rcgr = 0x070c, 471 .mnd_width = 16, 472 .hid_width = 5, 473 .parent_map = gcc_xo_gpll0_map, 474 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 475 .clkr.hw.init = &(struct clk_init_data){ 476 .name = "blsp1_uart2_apps_clk_src", 477 .parent_data = gcc_xo_gpll0, 478 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 479 .ops = &clk_rcg2_ops, 480 }, 481 }; 482 483 static struct clk_rcg2 blsp1_uart3_apps_clk_src = { 484 .cmd_rcgr = 0x078c, 485 .mnd_width = 16, 486 .hid_width = 5, 487 .parent_map = gcc_xo_gpll0_map, 488 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 489 .clkr.hw.init = &(struct clk_init_data){ 490 .name = "blsp1_uart3_apps_clk_src", 491 .parent_data = gcc_xo_gpll0, 492 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 493 .ops = &clk_rcg2_ops, 494 }, 495 }; 496 497 static struct clk_rcg2 blsp1_uart4_apps_clk_src = { 498 .cmd_rcgr = 0x080c, 499 .mnd_width = 16, 500 .hid_width = 5, 501 .parent_map = gcc_xo_gpll0_map, 502 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 503 .clkr.hw.init = &(struct clk_init_data){ 504 .name = "blsp1_uart4_apps_clk_src", 505 .parent_data = gcc_xo_gpll0, 506 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 507 .ops = &clk_rcg2_ops, 508 }, 509 }; 510 511 static struct clk_rcg2 blsp1_uart5_apps_clk_src = { 512 .cmd_rcgr = 0x088c, 513 .mnd_width = 16, 514 .hid_width = 5, 515 .parent_map = gcc_xo_gpll0_map, 516 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 517 .clkr.hw.init = &(struct clk_init_data){ 518 .name = "blsp1_uart5_apps_clk_src", 519 .parent_data = gcc_xo_gpll0, 520 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 521 .ops = &clk_rcg2_ops, 522 }, 523 }; 524 525 static struct clk_rcg2 blsp1_uart6_apps_clk_src = { 526 .cmd_rcgr = 0x090c, 527 .mnd_width = 16, 528 .hid_width = 5, 529 .parent_map = gcc_xo_gpll0_map, 530 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 531 .clkr.hw.init = &(struct clk_init_data){ 532 .name = "blsp1_uart6_apps_clk_src", 533 .parent_data = gcc_xo_gpll0, 534 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 535 .ops = &clk_rcg2_ops, 536 }, 537 }; 538 539 static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = { 540 .cmd_rcgr = 0x09a0, 541 .hid_width = 5, 542 .parent_map = gcc_xo_gpll0_map, 543 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 544 .clkr.hw.init = &(struct clk_init_data){ 545 .name = "blsp2_qup1_i2c_apps_clk_src", 546 .parent_data = gcc_xo_gpll0, 547 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 548 .ops = &clk_rcg2_ops, 549 }, 550 }; 551 552 static struct freq_tbl ftbl_blsp2_qup1_2_spi_apps_clk_src[] = { 553 F(960000, P_XO, 10, 1, 2), 554 F(4800000, P_XO, 4, 0, 0), 555 F(9600000, P_XO, 2, 0, 0), 556 F(15000000, P_GPLL0, 10, 1, 4), 557 F(19200000, P_XO, 1, 0, 0), 558 F(24000000, P_GPLL0, 12.5, 1, 2), 559 F(25000000, P_GPLL0, 12, 1, 2), 560 F(42860000, P_GPLL0, 14, 0, 0), 561 F(44440000, P_GPLL0, 13.5, 0, 0), 562 { } 563 }; 564 565 static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = { 566 .cmd_rcgr = 0x098c, 567 .mnd_width = 8, 568 .hid_width = 5, 569 .parent_map = gcc_xo_gpll0_map, 570 .freq_tbl = ftbl_blsp2_qup1_2_spi_apps_clk_src, 571 .clkr.hw.init = &(struct clk_init_data){ 572 .name = "blsp2_qup1_spi_apps_clk_src", 573 .parent_data = gcc_xo_gpll0, 574 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 575 .ops = &clk_rcg2_ops, 576 }, 577 }; 578 579 static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = { 580 .cmd_rcgr = 0x0a20, 581 .hid_width = 5, 582 .parent_map = gcc_xo_gpll0_map, 583 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 584 .clkr.hw.init = &(struct clk_init_data){ 585 .name = "blsp2_qup2_i2c_apps_clk_src", 586 .parent_data = gcc_xo_gpll0, 587 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 588 .ops = &clk_rcg2_ops, 589 }, 590 }; 591 592 static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = { 593 .cmd_rcgr = 0x0a0c, 594 .mnd_width = 8, 595 .hid_width = 5, 596 .parent_map = gcc_xo_gpll0_map, 597 .freq_tbl = ftbl_blsp2_qup1_2_spi_apps_clk_src, 598 .clkr.hw.init = &(struct clk_init_data){ 599 .name = "blsp2_qup2_spi_apps_clk_src", 600 .parent_data = gcc_xo_gpll0, 601 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 602 .ops = &clk_rcg2_ops, 603 }, 604 }; 605 606 static struct freq_tbl ftbl_blsp2_qup3_4_spi_apps_clk_src[] = { 607 F(960000, P_XO, 10, 1, 2), 608 F(4800000, P_XO, 4, 0, 0), 609 F(9600000, P_XO, 2, 0, 0), 610 F(15000000, P_GPLL0, 10, 1, 4), 611 F(19200000, P_XO, 1, 0, 0), 612 F(24000000, P_GPLL0, 12.5, 1, 2), 613 F(25000000, P_GPLL0, 12, 1, 2), 614 F(42860000, P_GPLL0, 14, 0, 0), 615 F(48000000, P_GPLL0, 12.5, 0, 0), 616 { } 617 }; 618 619 static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = { 620 .cmd_rcgr = 0x0aa0, 621 .hid_width = 5, 622 .parent_map = gcc_xo_gpll0_map, 623 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 624 .clkr.hw.init = &(struct clk_init_data){ 625 .name = "blsp2_qup3_i2c_apps_clk_src", 626 .parent_data = gcc_xo_gpll0, 627 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 628 .ops = &clk_rcg2_ops, 629 }, 630 }; 631 632 static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = { 633 .cmd_rcgr = 0x0a8c, 634 .mnd_width = 8, 635 .hid_width = 5, 636 .parent_map = gcc_xo_gpll0_map, 637 .freq_tbl = ftbl_blsp2_qup3_4_spi_apps_clk_src, 638 .clkr.hw.init = &(struct clk_init_data){ 639 .name = "blsp2_qup3_spi_apps_clk_src", 640 .parent_data = gcc_xo_gpll0, 641 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 642 .ops = &clk_rcg2_ops, 643 }, 644 }; 645 646 static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = { 647 .cmd_rcgr = 0x0b20, 648 .hid_width = 5, 649 .parent_map = gcc_xo_gpll0_map, 650 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 651 .clkr.hw.init = &(struct clk_init_data){ 652 .name = "blsp2_qup4_i2c_apps_clk_src", 653 .parent_data = gcc_xo_gpll0, 654 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 655 .ops = &clk_rcg2_ops, 656 }, 657 }; 658 659 static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = { 660 .cmd_rcgr = 0x0b0c, 661 .mnd_width = 8, 662 .hid_width = 5, 663 .parent_map = gcc_xo_gpll0_map, 664 .freq_tbl = ftbl_blsp2_qup3_4_spi_apps_clk_src, 665 .clkr.hw.init = &(struct clk_init_data){ 666 .name = "blsp2_qup4_spi_apps_clk_src", 667 .parent_data = gcc_xo_gpll0, 668 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 669 .ops = &clk_rcg2_ops, 670 }, 671 }; 672 673 static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = { 674 .cmd_rcgr = 0x0ba0, 675 .hid_width = 5, 676 .parent_map = gcc_xo_gpll0_map, 677 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 678 .clkr.hw.init = &(struct clk_init_data){ 679 .name = "blsp2_qup5_i2c_apps_clk_src", 680 .parent_data = gcc_xo_gpll0, 681 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 682 .ops = &clk_rcg2_ops, 683 }, 684 }; 685 686 static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = { 687 .cmd_rcgr = 0x0b8c, 688 .mnd_width = 8, 689 .hid_width = 5, 690 .parent_map = gcc_xo_gpll0_map, 691 /* BLSP1 QUP1 and BLSP2 QUP5 use the same freqs */ 692 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 693 .clkr.hw.init = &(struct clk_init_data){ 694 .name = "blsp2_qup5_spi_apps_clk_src", 695 .parent_data = gcc_xo_gpll0, 696 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 697 .ops = &clk_rcg2_ops, 698 }, 699 }; 700 701 static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = { 702 .cmd_rcgr = 0x0c20, 703 .hid_width = 5, 704 .parent_map = gcc_xo_gpll0_map, 705 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 706 .clkr.hw.init = &(struct clk_init_data){ 707 .name = "blsp2_qup6_i2c_apps_clk_src", 708 .parent_data = gcc_xo_gpll0, 709 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 710 .ops = &clk_rcg2_ops, 711 }, 712 }; 713 714 static struct freq_tbl ftbl_blsp2_qup6_spi_apps_clk_src[] = { 715 F(960000, P_XO, 10, 1, 2), 716 F(4800000, P_XO, 4, 0, 0), 717 F(9600000, P_XO, 2, 0, 0), 718 F(15000000, P_GPLL0, 10, 1, 4), 719 F(19200000, P_XO, 1, 0, 0), 720 F(24000000, P_GPLL0, 12.5, 1, 2), 721 F(25000000, P_GPLL0, 12, 1, 2), 722 F(44440000, P_GPLL0, 13.5, 0, 0), 723 F(48000000, P_GPLL0, 12.5, 0, 0), 724 { } 725 }; 726 727 static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = { 728 .cmd_rcgr = 0x0c0c, 729 .mnd_width = 8, 730 .hid_width = 5, 731 .parent_map = gcc_xo_gpll0_map, 732 .freq_tbl = ftbl_blsp2_qup6_spi_apps_clk_src, 733 .clkr.hw.init = &(struct clk_init_data){ 734 .name = "blsp2_qup6_spi_apps_clk_src", 735 .parent_data = gcc_xo_gpll0, 736 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 737 .ops = &clk_rcg2_ops, 738 }, 739 }; 740 741 static struct clk_rcg2 blsp2_uart1_apps_clk_src = { 742 .cmd_rcgr = 0x09cc, 743 .mnd_width = 16, 744 .hid_width = 5, 745 .parent_map = gcc_xo_gpll0_map, 746 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 747 .clkr.hw.init = &(struct clk_init_data){ 748 .name = "blsp2_uart1_apps_clk_src", 749 .parent_data = gcc_xo_gpll0, 750 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 751 .ops = &clk_rcg2_ops, 752 }, 753 }; 754 755 static struct clk_rcg2 blsp2_uart2_apps_clk_src = { 756 .cmd_rcgr = 0x0a4c, 757 .mnd_width = 16, 758 .hid_width = 5, 759 .parent_map = gcc_xo_gpll0_map, 760 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 761 .clkr.hw.init = &(struct clk_init_data){ 762 .name = "blsp2_uart2_apps_clk_src", 763 .parent_data = gcc_xo_gpll0, 764 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 765 .ops = &clk_rcg2_ops, 766 }, 767 }; 768 769 static struct clk_rcg2 blsp2_uart3_apps_clk_src = { 770 .cmd_rcgr = 0x0acc, 771 .mnd_width = 16, 772 .hid_width = 5, 773 .parent_map = gcc_xo_gpll0_map, 774 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 775 .clkr.hw.init = &(struct clk_init_data){ 776 .name = "blsp2_uart3_apps_clk_src", 777 .parent_data = gcc_xo_gpll0, 778 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 779 .ops = &clk_rcg2_ops, 780 }, 781 }; 782 783 static struct clk_rcg2 blsp2_uart4_apps_clk_src = { 784 .cmd_rcgr = 0x0b4c, 785 .mnd_width = 16, 786 .hid_width = 5, 787 .parent_map = gcc_xo_gpll0_map, 788 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 789 .clkr.hw.init = &(struct clk_init_data){ 790 .name = "blsp2_uart4_apps_clk_src", 791 .parent_data = gcc_xo_gpll0, 792 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 793 .ops = &clk_rcg2_ops, 794 }, 795 }; 796 797 static struct clk_rcg2 blsp2_uart5_apps_clk_src = { 798 .cmd_rcgr = 0x0bcc, 799 .mnd_width = 16, 800 .hid_width = 5, 801 .parent_map = gcc_xo_gpll0_map, 802 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 803 .clkr.hw.init = &(struct clk_init_data){ 804 .name = "blsp2_uart5_apps_clk_src", 805 .parent_data = gcc_xo_gpll0, 806 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 807 .ops = &clk_rcg2_ops, 808 }, 809 }; 810 811 static struct clk_rcg2 blsp2_uart6_apps_clk_src = { 812 .cmd_rcgr = 0x0c4c, 813 .mnd_width = 16, 814 .hid_width = 5, 815 .parent_map = gcc_xo_gpll0_map, 816 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 817 .clkr.hw.init = &(struct clk_init_data){ 818 .name = "blsp2_uart6_apps_clk_src", 819 .parent_data = gcc_xo_gpll0, 820 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 821 .ops = &clk_rcg2_ops, 822 }, 823 }; 824 825 static struct freq_tbl ftbl_gp1_clk_src[] = { 826 F(19200000, P_XO, 1, 0, 0), 827 F(100000000, P_GPLL0, 6, 0, 0), 828 F(200000000, P_GPLL0, 3, 0, 0), 829 { } 830 }; 831 832 static struct clk_rcg2 gp1_clk_src = { 833 .cmd_rcgr = 0x1904, 834 .mnd_width = 8, 835 .hid_width = 5, 836 .parent_map = gcc_xo_gpll0_map, 837 .freq_tbl = ftbl_gp1_clk_src, 838 .clkr.hw.init = &(struct clk_init_data){ 839 .name = "gp1_clk_src", 840 .parent_data = gcc_xo_gpll0, 841 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 842 .ops = &clk_rcg2_ops, 843 }, 844 }; 845 846 static struct freq_tbl ftbl_gp2_clk_src[] = { 847 F(19200000, P_XO, 1, 0, 0), 848 F(100000000, P_GPLL0, 6, 0, 0), 849 F(200000000, P_GPLL0, 3, 0, 0), 850 { } 851 }; 852 853 static struct clk_rcg2 gp2_clk_src = { 854 .cmd_rcgr = 0x1944, 855 .mnd_width = 8, 856 .hid_width = 5, 857 .parent_map = gcc_xo_gpll0_map, 858 .freq_tbl = ftbl_gp2_clk_src, 859 .clkr.hw.init = &(struct clk_init_data){ 860 .name = "gp2_clk_src", 861 .parent_data = gcc_xo_gpll0, 862 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 863 .ops = &clk_rcg2_ops, 864 }, 865 }; 866 867 static struct freq_tbl ftbl_gp3_clk_src[] = { 868 F(19200000, P_XO, 1, 0, 0), 869 F(100000000, P_GPLL0, 6, 0, 0), 870 F(200000000, P_GPLL0, 3, 0, 0), 871 { } 872 }; 873 874 static struct clk_rcg2 gp3_clk_src = { 875 .cmd_rcgr = 0x1984, 876 .mnd_width = 8, 877 .hid_width = 5, 878 .parent_map = gcc_xo_gpll0_map, 879 .freq_tbl = ftbl_gp3_clk_src, 880 .clkr.hw.init = &(struct clk_init_data){ 881 .name = "gp3_clk_src", 882 .parent_data = gcc_xo_gpll0, 883 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 884 .ops = &clk_rcg2_ops, 885 }, 886 }; 887 888 static struct freq_tbl ftbl_pcie_0_aux_clk_src[] = { 889 F(1011000, P_XO, 1, 1, 19), 890 { } 891 }; 892 893 static struct clk_rcg2 pcie_0_aux_clk_src = { 894 .cmd_rcgr = 0x1b00, 895 .mnd_width = 8, 896 .hid_width = 5, 897 .freq_tbl = ftbl_pcie_0_aux_clk_src, 898 .clkr.hw.init = &(struct clk_init_data){ 899 .name = "pcie_0_aux_clk_src", 900 .parent_data = &(const struct clk_parent_data){ 901 .fw_name = "xo", 902 }, 903 .num_parents = 1, 904 .ops = &clk_rcg2_ops, 905 }, 906 }; 907 908 static struct freq_tbl ftbl_pcie_pipe_clk_src[] = { 909 F(125000000, P_XO, 1, 0, 0), 910 { } 911 }; 912 913 static struct clk_rcg2 pcie_0_pipe_clk_src = { 914 .cmd_rcgr = 0x1adc, 915 .hid_width = 5, 916 .freq_tbl = ftbl_pcie_pipe_clk_src, 917 .clkr.hw.init = &(struct clk_init_data){ 918 .name = "pcie_0_pipe_clk_src", 919 .parent_data = &(const struct clk_parent_data){ 920 .fw_name = "xo", 921 }, 922 .num_parents = 1, 923 .ops = &clk_rcg2_ops, 924 }, 925 }; 926 927 static struct freq_tbl ftbl_pcie_1_aux_clk_src[] = { 928 F(1011000, P_XO, 1, 1, 19), 929 { } 930 }; 931 932 static struct clk_rcg2 pcie_1_aux_clk_src = { 933 .cmd_rcgr = 0x1b80, 934 .mnd_width = 8, 935 .hid_width = 5, 936 .freq_tbl = ftbl_pcie_1_aux_clk_src, 937 .clkr.hw.init = &(struct clk_init_data){ 938 .name = "pcie_1_aux_clk_src", 939 .parent_data = &(const struct clk_parent_data){ 940 .fw_name = "xo", 941 }, 942 .num_parents = 1, 943 .ops = &clk_rcg2_ops, 944 }, 945 }; 946 947 static struct clk_rcg2 pcie_1_pipe_clk_src = { 948 .cmd_rcgr = 0x1b5c, 949 .hid_width = 5, 950 .freq_tbl = ftbl_pcie_pipe_clk_src, 951 .clkr.hw.init = &(struct clk_init_data){ 952 .name = "pcie_1_pipe_clk_src", 953 .parent_data = &(const struct clk_parent_data){ 954 .fw_name = "xo", 955 }, 956 .num_parents = 1, 957 .ops = &clk_rcg2_ops, 958 }, 959 }; 960 961 static struct freq_tbl ftbl_pdm2_clk_src[] = { 962 F(60000000, P_GPLL0, 10, 0, 0), 963 { } 964 }; 965 966 static struct clk_rcg2 pdm2_clk_src = { 967 .cmd_rcgr = 0x0cd0, 968 .hid_width = 5, 969 .parent_map = gcc_xo_gpll0_map, 970 .freq_tbl = ftbl_pdm2_clk_src, 971 .clkr.hw.init = &(struct clk_init_data){ 972 .name = "pdm2_clk_src", 973 .parent_data = gcc_xo_gpll0, 974 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 975 .ops = &clk_rcg2_ops, 976 }, 977 }; 978 979 static struct freq_tbl ftbl_sdcc1_apps_clk_src[] = { 980 F(144000, P_XO, 16, 3, 25), 981 F(400000, P_XO, 12, 1, 4), 982 F(20000000, P_GPLL0, 15, 1, 2), 983 F(25000000, P_GPLL0, 12, 1, 2), 984 F(50000000, P_GPLL0, 12, 0, 0), 985 F(100000000, P_GPLL0, 6, 0, 0), 986 F(192000000, P_GPLL4, 2, 0, 0), 987 F(384000000, P_GPLL4, 1, 0, 0), 988 { } 989 }; 990 991 static struct freq_tbl ftbl_sdcc1_apps_clk_src_8992[] = { 992 F(144000, P_XO, 16, 3, 25), 993 F(400000, P_XO, 12, 1, 4), 994 F(20000000, P_GPLL0, 15, 1, 2), 995 F(25000000, P_GPLL0, 12, 1, 2), 996 F(50000000, P_GPLL0, 12, 0, 0), 997 F(100000000, P_GPLL0, 6, 0, 0), 998 F(172000000, P_GPLL4, 2, 0, 0), 999 F(344000000, P_GPLL4, 1, 0, 0), 1000 { } 1001 }; 1002 1003 static struct clk_rcg2 sdcc1_apps_clk_src = { 1004 .cmd_rcgr = 0x04d0, 1005 .mnd_width = 8, 1006 .hid_width = 5, 1007 .parent_map = gcc_xo_gpll0_gpll4_map, 1008 .freq_tbl = ftbl_sdcc1_apps_clk_src, 1009 .clkr.hw.init = &(struct clk_init_data){ 1010 .name = "sdcc1_apps_clk_src", 1011 .parent_data = gcc_xo_gpll0_gpll4, 1012 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4), 1013 .ops = &clk_rcg2_floor_ops, 1014 }, 1015 }; 1016 1017 static struct freq_tbl ftbl_sdcc2_4_apps_clk_src[] = { 1018 F(144000, P_XO, 16, 3, 25), 1019 F(400000, P_XO, 12, 1, 4), 1020 F(20000000, P_GPLL0, 15, 1, 2), 1021 F(25000000, P_GPLL0, 12, 1, 2), 1022 F(50000000, P_GPLL0, 12, 0, 0), 1023 F(100000000, P_GPLL0, 6, 0, 0), 1024 F(200000000, P_GPLL0, 3, 0, 0), 1025 { } 1026 }; 1027 1028 static struct clk_rcg2 sdcc2_apps_clk_src = { 1029 .cmd_rcgr = 0x0510, 1030 .mnd_width = 8, 1031 .hid_width = 5, 1032 .parent_map = gcc_xo_gpll0_map, 1033 .freq_tbl = ftbl_sdcc2_4_apps_clk_src, 1034 .clkr.hw.init = &(struct clk_init_data){ 1035 .name = "sdcc2_apps_clk_src", 1036 .parent_data = gcc_xo_gpll0, 1037 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1038 .ops = &clk_rcg2_floor_ops, 1039 }, 1040 }; 1041 1042 static struct clk_rcg2 sdcc3_apps_clk_src = { 1043 .cmd_rcgr = 0x0550, 1044 .mnd_width = 8, 1045 .hid_width = 5, 1046 .parent_map = gcc_xo_gpll0_map, 1047 .freq_tbl = ftbl_sdcc2_4_apps_clk_src, 1048 .clkr.hw.init = &(struct clk_init_data){ 1049 .name = "sdcc3_apps_clk_src", 1050 .parent_data = gcc_xo_gpll0, 1051 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1052 .ops = &clk_rcg2_floor_ops, 1053 }, 1054 }; 1055 1056 static struct clk_rcg2 sdcc4_apps_clk_src = { 1057 .cmd_rcgr = 0x0590, 1058 .mnd_width = 8, 1059 .hid_width = 5, 1060 .parent_map = gcc_xo_gpll0_map, 1061 .freq_tbl = ftbl_sdcc2_4_apps_clk_src, 1062 .clkr.hw.init = &(struct clk_init_data){ 1063 .name = "sdcc4_apps_clk_src", 1064 .parent_data = gcc_xo_gpll0, 1065 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1066 .ops = &clk_rcg2_floor_ops, 1067 }, 1068 }; 1069 1070 static struct freq_tbl ftbl_tsif_ref_clk_src[] = { 1071 F(105500, P_XO, 1, 1, 182), 1072 { } 1073 }; 1074 1075 static struct clk_rcg2 tsif_ref_clk_src = { 1076 .cmd_rcgr = 0x0d90, 1077 .mnd_width = 8, 1078 .hid_width = 5, 1079 .freq_tbl = ftbl_tsif_ref_clk_src, 1080 .clkr.hw.init = &(struct clk_init_data){ 1081 .name = "tsif_ref_clk_src", 1082 .parent_data = &(const struct clk_parent_data){ 1083 .fw_name = "xo", 1084 }, 1085 .num_parents = 1, 1086 .ops = &clk_rcg2_ops, 1087 }, 1088 }; 1089 1090 static struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = { 1091 F(19200000, P_XO, 1, 0, 0), 1092 F(60000000, P_GPLL0, 10, 0, 0), 1093 { } 1094 }; 1095 1096 static struct clk_rcg2 usb30_mock_utmi_clk_src = { 1097 .cmd_rcgr = 0x03e8, 1098 .hid_width = 5, 1099 .parent_map = gcc_xo_gpll0_map, 1100 .freq_tbl = ftbl_usb30_mock_utmi_clk_src, 1101 .clkr.hw.init = &(struct clk_init_data){ 1102 .name = "usb30_mock_utmi_clk_src", 1103 .parent_data = gcc_xo_gpll0, 1104 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1105 .ops = &clk_rcg2_ops, 1106 }, 1107 }; 1108 1109 static struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = { 1110 F(1200000, P_XO, 16, 0, 0), 1111 { } 1112 }; 1113 1114 static struct clk_rcg2 usb3_phy_aux_clk_src = { 1115 .cmd_rcgr = 0x1414, 1116 .hid_width = 5, 1117 .freq_tbl = ftbl_usb3_phy_aux_clk_src, 1118 .clkr.hw.init = &(struct clk_init_data){ 1119 .name = "usb3_phy_aux_clk_src", 1120 .parent_data = &(const struct clk_parent_data){ 1121 .fw_name = "xo", 1122 }, 1123 .num_parents = 1, 1124 .ops = &clk_rcg2_ops, 1125 }, 1126 }; 1127 1128 static struct freq_tbl ftbl_usb_hs_system_clk_src[] = { 1129 F(75000000, P_GPLL0, 8, 0, 0), 1130 { } 1131 }; 1132 1133 static struct clk_rcg2 usb_hs_system_clk_src = { 1134 .cmd_rcgr = 0x0490, 1135 .hid_width = 5, 1136 .parent_map = gcc_xo_gpll0_map, 1137 .freq_tbl = ftbl_usb_hs_system_clk_src, 1138 .clkr.hw.init = &(struct clk_init_data){ 1139 .name = "usb_hs_system_clk_src", 1140 .parent_data = gcc_xo_gpll0, 1141 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1142 .ops = &clk_rcg2_ops, 1143 }, 1144 }; 1145 1146 static struct clk_branch gcc_blsp1_ahb_clk = { 1147 .halt_reg = 0x05c4, 1148 .halt_check = BRANCH_HALT_VOTED, 1149 .clkr = { 1150 .enable_reg = 0x1484, 1151 .enable_mask = BIT(17), 1152 .hw.init = &(struct clk_init_data){ 1153 .name = "gcc_blsp1_ahb_clk", 1154 .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw }, 1155 .num_parents = 1, 1156 .ops = &clk_branch2_ops, 1157 }, 1158 }, 1159 }; 1160 1161 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { 1162 .halt_reg = 0x0648, 1163 .clkr = { 1164 .enable_reg = 0x0648, 1165 .enable_mask = BIT(0), 1166 .hw.init = &(struct clk_init_data){ 1167 .name = "gcc_blsp1_qup1_i2c_apps_clk", 1168 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup1_i2c_apps_clk_src.clkr.hw }, 1169 .num_parents = 1, 1170 .flags = CLK_SET_RATE_PARENT, 1171 .ops = &clk_branch2_ops, 1172 }, 1173 }, 1174 }; 1175 1176 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { 1177 .halt_reg = 0x0644, 1178 .clkr = { 1179 .enable_reg = 0x0644, 1180 .enable_mask = BIT(0), 1181 .hw.init = &(struct clk_init_data){ 1182 .name = "gcc_blsp1_qup1_spi_apps_clk", 1183 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup1_spi_apps_clk_src.clkr.hw }, 1184 .num_parents = 1, 1185 .flags = CLK_SET_RATE_PARENT, 1186 .ops = &clk_branch2_ops, 1187 }, 1188 }, 1189 }; 1190 1191 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { 1192 .halt_reg = 0x06c8, 1193 .clkr = { 1194 .enable_reg = 0x06c8, 1195 .enable_mask = BIT(0), 1196 .hw.init = &(struct clk_init_data){ 1197 .name = "gcc_blsp1_qup2_i2c_apps_clk", 1198 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup2_i2c_apps_clk_src.clkr.hw }, 1199 .num_parents = 1, 1200 .flags = CLK_SET_RATE_PARENT, 1201 .ops = &clk_branch2_ops, 1202 }, 1203 }, 1204 }; 1205 1206 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { 1207 .halt_reg = 0x06c4, 1208 .clkr = { 1209 .enable_reg = 0x06c4, 1210 .enable_mask = BIT(0), 1211 .hw.init = &(struct clk_init_data){ 1212 .name = "gcc_blsp1_qup2_spi_apps_clk", 1213 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup2_spi_apps_clk_src.clkr.hw }, 1214 .num_parents = 1, 1215 .flags = CLK_SET_RATE_PARENT, 1216 .ops = &clk_branch2_ops, 1217 }, 1218 }, 1219 }; 1220 1221 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = { 1222 .halt_reg = 0x0748, 1223 .clkr = { 1224 .enable_reg = 0x0748, 1225 .enable_mask = BIT(0), 1226 .hw.init = &(struct clk_init_data){ 1227 .name = "gcc_blsp1_qup3_i2c_apps_clk", 1228 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup3_i2c_apps_clk_src.clkr.hw }, 1229 .num_parents = 1, 1230 .flags = CLK_SET_RATE_PARENT, 1231 .ops = &clk_branch2_ops, 1232 }, 1233 }, 1234 }; 1235 1236 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = { 1237 .halt_reg = 0x0744, 1238 .clkr = { 1239 .enable_reg = 0x0744, 1240 .enable_mask = BIT(0), 1241 .hw.init = &(struct clk_init_data){ 1242 .name = "gcc_blsp1_qup3_spi_apps_clk", 1243 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup3_spi_apps_clk_src.clkr.hw }, 1244 .num_parents = 1, 1245 .flags = CLK_SET_RATE_PARENT, 1246 .ops = &clk_branch2_ops, 1247 }, 1248 }, 1249 }; 1250 1251 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = { 1252 .halt_reg = 0x07c8, 1253 .clkr = { 1254 .enable_reg = 0x07c8, 1255 .enable_mask = BIT(0), 1256 .hw.init = &(struct clk_init_data){ 1257 .name = "gcc_blsp1_qup4_i2c_apps_clk", 1258 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup4_i2c_apps_clk_src.clkr.hw }, 1259 .num_parents = 1, 1260 .flags = CLK_SET_RATE_PARENT, 1261 .ops = &clk_branch2_ops, 1262 }, 1263 }, 1264 }; 1265 1266 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = { 1267 .halt_reg = 0x07c4, 1268 .clkr = { 1269 .enable_reg = 0x07c4, 1270 .enable_mask = BIT(0), 1271 .hw.init = &(struct clk_init_data){ 1272 .name = "gcc_blsp1_qup4_spi_apps_clk", 1273 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup4_spi_apps_clk_src.clkr.hw }, 1274 .num_parents = 1, 1275 .flags = CLK_SET_RATE_PARENT, 1276 .ops = &clk_branch2_ops, 1277 }, 1278 }, 1279 }; 1280 1281 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = { 1282 .halt_reg = 0x0848, 1283 .clkr = { 1284 .enable_reg = 0x0848, 1285 .enable_mask = BIT(0), 1286 .hw.init = &(struct clk_init_data){ 1287 .name = "gcc_blsp1_qup5_i2c_apps_clk", 1288 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup5_i2c_apps_clk_src.clkr.hw }, 1289 .num_parents = 1, 1290 .flags = CLK_SET_RATE_PARENT, 1291 .ops = &clk_branch2_ops, 1292 }, 1293 }, 1294 }; 1295 1296 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = { 1297 .halt_reg = 0x0844, 1298 .clkr = { 1299 .enable_reg = 0x0844, 1300 .enable_mask = BIT(0), 1301 .hw.init = &(struct clk_init_data){ 1302 .name = "gcc_blsp1_qup5_spi_apps_clk", 1303 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup5_spi_apps_clk_src.clkr.hw }, 1304 .num_parents = 1, 1305 .flags = CLK_SET_RATE_PARENT, 1306 .ops = &clk_branch2_ops, 1307 }, 1308 }, 1309 }; 1310 1311 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = { 1312 .halt_reg = 0x08c8, 1313 .clkr = { 1314 .enable_reg = 0x08c8, 1315 .enable_mask = BIT(0), 1316 .hw.init = &(struct clk_init_data){ 1317 .name = "gcc_blsp1_qup6_i2c_apps_clk", 1318 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup6_i2c_apps_clk_src.clkr.hw }, 1319 .num_parents = 1, 1320 .flags = CLK_SET_RATE_PARENT, 1321 .ops = &clk_branch2_ops, 1322 }, 1323 }, 1324 }; 1325 1326 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = { 1327 .halt_reg = 0x08c4, 1328 .clkr = { 1329 .enable_reg = 0x08c4, 1330 .enable_mask = BIT(0), 1331 .hw.init = &(struct clk_init_data){ 1332 .name = "gcc_blsp1_qup6_spi_apps_clk", 1333 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup6_spi_apps_clk_src.clkr.hw }, 1334 .num_parents = 1, 1335 .flags = CLK_SET_RATE_PARENT, 1336 .ops = &clk_branch2_ops, 1337 }, 1338 }, 1339 }; 1340 1341 static struct clk_branch gcc_blsp1_uart1_apps_clk = { 1342 .halt_reg = 0x0684, 1343 .clkr = { 1344 .enable_reg = 0x0684, 1345 .enable_mask = BIT(0), 1346 .hw.init = &(struct clk_init_data){ 1347 .name = "gcc_blsp1_uart1_apps_clk", 1348 .parent_hws = (const struct clk_hw *[]){ &blsp1_uart1_apps_clk_src.clkr.hw }, 1349 .num_parents = 1, 1350 .flags = CLK_SET_RATE_PARENT, 1351 .ops = &clk_branch2_ops, 1352 }, 1353 }, 1354 }; 1355 1356 static struct clk_branch gcc_blsp1_uart2_apps_clk = { 1357 .halt_reg = 0x0704, 1358 .clkr = { 1359 .enable_reg = 0x0704, 1360 .enable_mask = BIT(0), 1361 .hw.init = &(struct clk_init_data){ 1362 .name = "gcc_blsp1_uart2_apps_clk", 1363 .parent_hws = (const struct clk_hw *[]){ &blsp1_uart2_apps_clk_src.clkr.hw }, 1364 .num_parents = 1, 1365 .flags = CLK_SET_RATE_PARENT, 1366 .ops = &clk_branch2_ops, 1367 }, 1368 }, 1369 }; 1370 1371 static struct clk_branch gcc_blsp1_uart3_apps_clk = { 1372 .halt_reg = 0x0784, 1373 .clkr = { 1374 .enable_reg = 0x0784, 1375 .enable_mask = BIT(0), 1376 .hw.init = &(struct clk_init_data){ 1377 .name = "gcc_blsp1_uart3_apps_clk", 1378 .parent_hws = (const struct clk_hw *[]){ &blsp1_uart3_apps_clk_src.clkr.hw }, 1379 .num_parents = 1, 1380 .flags = CLK_SET_RATE_PARENT, 1381 .ops = &clk_branch2_ops, 1382 }, 1383 }, 1384 }; 1385 1386 static struct clk_branch gcc_blsp1_uart4_apps_clk = { 1387 .halt_reg = 0x0804, 1388 .clkr = { 1389 .enable_reg = 0x0804, 1390 .enable_mask = BIT(0), 1391 .hw.init = &(struct clk_init_data){ 1392 .name = "gcc_blsp1_uart4_apps_clk", 1393 .parent_hws = (const struct clk_hw *[]){ &blsp1_uart4_apps_clk_src.clkr.hw }, 1394 .num_parents = 1, 1395 .flags = CLK_SET_RATE_PARENT, 1396 .ops = &clk_branch2_ops, 1397 }, 1398 }, 1399 }; 1400 1401 static struct clk_branch gcc_blsp1_uart5_apps_clk = { 1402 .halt_reg = 0x0884, 1403 .clkr = { 1404 .enable_reg = 0x0884, 1405 .enable_mask = BIT(0), 1406 .hw.init = &(struct clk_init_data){ 1407 .name = "gcc_blsp1_uart5_apps_clk", 1408 .parent_hws = (const struct clk_hw *[]){ &blsp1_uart5_apps_clk_src.clkr.hw }, 1409 .num_parents = 1, 1410 .flags = CLK_SET_RATE_PARENT, 1411 .ops = &clk_branch2_ops, 1412 }, 1413 }, 1414 }; 1415 1416 static struct clk_branch gcc_blsp1_uart6_apps_clk = { 1417 .halt_reg = 0x0904, 1418 .clkr = { 1419 .enable_reg = 0x0904, 1420 .enable_mask = BIT(0), 1421 .hw.init = &(struct clk_init_data){ 1422 .name = "gcc_blsp1_uart6_apps_clk", 1423 .parent_hws = (const struct clk_hw *[]){ &blsp1_uart6_apps_clk_src.clkr.hw }, 1424 .num_parents = 1, 1425 .flags = CLK_SET_RATE_PARENT, 1426 .ops = &clk_branch2_ops, 1427 }, 1428 }, 1429 }; 1430 1431 static struct clk_branch gcc_blsp2_ahb_clk = { 1432 .halt_reg = 0x0944, 1433 .halt_check = BRANCH_HALT_VOTED, 1434 .clkr = { 1435 .enable_reg = 0x1484, 1436 .enable_mask = BIT(15), 1437 .hw.init = &(struct clk_init_data){ 1438 .name = "gcc_blsp2_ahb_clk", 1439 .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw }, 1440 .num_parents = 1, 1441 .ops = &clk_branch2_ops, 1442 }, 1443 }, 1444 }; 1445 1446 static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = { 1447 .halt_reg = 0x0988, 1448 .clkr = { 1449 .enable_reg = 0x0988, 1450 .enable_mask = BIT(0), 1451 .hw.init = &(struct clk_init_data){ 1452 .name = "gcc_blsp2_qup1_i2c_apps_clk", 1453 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup1_i2c_apps_clk_src.clkr.hw }, 1454 .num_parents = 1, 1455 .flags = CLK_SET_RATE_PARENT, 1456 .ops = &clk_branch2_ops, 1457 }, 1458 }, 1459 }; 1460 1461 static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = { 1462 .halt_reg = 0x0984, 1463 .clkr = { 1464 .enable_reg = 0x0984, 1465 .enable_mask = BIT(0), 1466 .hw.init = &(struct clk_init_data){ 1467 .name = "gcc_blsp2_qup1_spi_apps_clk", 1468 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup1_spi_apps_clk_src.clkr.hw }, 1469 .num_parents = 1, 1470 .flags = CLK_SET_RATE_PARENT, 1471 .ops = &clk_branch2_ops, 1472 }, 1473 }, 1474 }; 1475 1476 static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = { 1477 .halt_reg = 0x0a08, 1478 .clkr = { 1479 .enable_reg = 0x0a08, 1480 .enable_mask = BIT(0), 1481 .hw.init = &(struct clk_init_data){ 1482 .name = "gcc_blsp2_qup2_i2c_apps_clk", 1483 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup2_i2c_apps_clk_src.clkr.hw }, 1484 .num_parents = 1, 1485 .flags = CLK_SET_RATE_PARENT, 1486 .ops = &clk_branch2_ops, 1487 }, 1488 }, 1489 }; 1490 1491 static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = { 1492 .halt_reg = 0x0a04, 1493 .clkr = { 1494 .enable_reg = 0x0a04, 1495 .enable_mask = BIT(0), 1496 .hw.init = &(struct clk_init_data){ 1497 .name = "gcc_blsp2_qup2_spi_apps_clk", 1498 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup2_spi_apps_clk_src.clkr.hw }, 1499 .num_parents = 1, 1500 .flags = CLK_SET_RATE_PARENT, 1501 .ops = &clk_branch2_ops, 1502 }, 1503 }, 1504 }; 1505 1506 static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = { 1507 .halt_reg = 0x0a88, 1508 .clkr = { 1509 .enable_reg = 0x0a88, 1510 .enable_mask = BIT(0), 1511 .hw.init = &(struct clk_init_data){ 1512 .name = "gcc_blsp2_qup3_i2c_apps_clk", 1513 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup3_i2c_apps_clk_src.clkr.hw }, 1514 .num_parents = 1, 1515 .flags = CLK_SET_RATE_PARENT, 1516 .ops = &clk_branch2_ops, 1517 }, 1518 }, 1519 }; 1520 1521 static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = { 1522 .halt_reg = 0x0a84, 1523 .clkr = { 1524 .enable_reg = 0x0a84, 1525 .enable_mask = BIT(0), 1526 .hw.init = &(struct clk_init_data){ 1527 .name = "gcc_blsp2_qup3_spi_apps_clk", 1528 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup3_spi_apps_clk_src.clkr.hw }, 1529 .num_parents = 1, 1530 .flags = CLK_SET_RATE_PARENT, 1531 .ops = &clk_branch2_ops, 1532 }, 1533 }, 1534 }; 1535 1536 static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = { 1537 .halt_reg = 0x0b08, 1538 .clkr = { 1539 .enable_reg = 0x0b08, 1540 .enable_mask = BIT(0), 1541 .hw.init = &(struct clk_init_data){ 1542 .name = "gcc_blsp2_qup4_i2c_apps_clk", 1543 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup4_i2c_apps_clk_src.clkr.hw }, 1544 .num_parents = 1, 1545 .flags = CLK_SET_RATE_PARENT, 1546 .ops = &clk_branch2_ops, 1547 }, 1548 }, 1549 }; 1550 1551 static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = { 1552 .halt_reg = 0x0b04, 1553 .clkr = { 1554 .enable_reg = 0x0b04, 1555 .enable_mask = BIT(0), 1556 .hw.init = &(struct clk_init_data){ 1557 .name = "gcc_blsp2_qup4_spi_apps_clk", 1558 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup4_spi_apps_clk_src.clkr.hw }, 1559 .num_parents = 1, 1560 .flags = CLK_SET_RATE_PARENT, 1561 .ops = &clk_branch2_ops, 1562 }, 1563 }, 1564 }; 1565 1566 static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = { 1567 .halt_reg = 0x0b88, 1568 .clkr = { 1569 .enable_reg = 0x0b88, 1570 .enable_mask = BIT(0), 1571 .hw.init = &(struct clk_init_data){ 1572 .name = "gcc_blsp2_qup5_i2c_apps_clk", 1573 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup5_i2c_apps_clk_src.clkr.hw }, 1574 .num_parents = 1, 1575 .flags = CLK_SET_RATE_PARENT, 1576 .ops = &clk_branch2_ops, 1577 }, 1578 }, 1579 }; 1580 1581 static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = { 1582 .halt_reg = 0x0b84, 1583 .clkr = { 1584 .enable_reg = 0x0b84, 1585 .enable_mask = BIT(0), 1586 .hw.init = &(struct clk_init_data){ 1587 .name = "gcc_blsp2_qup5_spi_apps_clk", 1588 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup5_spi_apps_clk_src.clkr.hw }, 1589 .num_parents = 1, 1590 .flags = CLK_SET_RATE_PARENT, 1591 .ops = &clk_branch2_ops, 1592 }, 1593 }, 1594 }; 1595 1596 static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = { 1597 .halt_reg = 0x0c08, 1598 .clkr = { 1599 .enable_reg = 0x0c08, 1600 .enable_mask = BIT(0), 1601 .hw.init = &(struct clk_init_data){ 1602 .name = "gcc_blsp2_qup6_i2c_apps_clk", 1603 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup6_i2c_apps_clk_src.clkr.hw }, 1604 .num_parents = 1, 1605 .flags = CLK_SET_RATE_PARENT, 1606 .ops = &clk_branch2_ops, 1607 }, 1608 }, 1609 }; 1610 1611 static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = { 1612 .halt_reg = 0x0c04, 1613 .clkr = { 1614 .enable_reg = 0x0c04, 1615 .enable_mask = BIT(0), 1616 .hw.init = &(struct clk_init_data){ 1617 .name = "gcc_blsp2_qup6_spi_apps_clk", 1618 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup6_spi_apps_clk_src.clkr.hw }, 1619 .num_parents = 1, 1620 .flags = CLK_SET_RATE_PARENT, 1621 .ops = &clk_branch2_ops, 1622 }, 1623 }, 1624 }; 1625 1626 static struct clk_branch gcc_blsp2_uart1_apps_clk = { 1627 .halt_reg = 0x09c4, 1628 .clkr = { 1629 .enable_reg = 0x09c4, 1630 .enable_mask = BIT(0), 1631 .hw.init = &(struct clk_init_data){ 1632 .name = "gcc_blsp2_uart1_apps_clk", 1633 .parent_hws = (const struct clk_hw *[]){ &blsp2_uart1_apps_clk_src.clkr.hw }, 1634 .num_parents = 1, 1635 .flags = CLK_SET_RATE_PARENT, 1636 .ops = &clk_branch2_ops, 1637 }, 1638 }, 1639 }; 1640 1641 static struct clk_branch gcc_blsp2_uart2_apps_clk = { 1642 .halt_reg = 0x0a44, 1643 .clkr = { 1644 .enable_reg = 0x0a44, 1645 .enable_mask = BIT(0), 1646 .hw.init = &(struct clk_init_data){ 1647 .name = "gcc_blsp2_uart2_apps_clk", 1648 .parent_hws = (const struct clk_hw *[]){ &blsp2_uart2_apps_clk_src.clkr.hw }, 1649 .num_parents = 1, 1650 .flags = CLK_SET_RATE_PARENT, 1651 .ops = &clk_branch2_ops, 1652 }, 1653 }, 1654 }; 1655 1656 static struct clk_branch gcc_blsp2_uart3_apps_clk = { 1657 .halt_reg = 0x0ac4, 1658 .clkr = { 1659 .enable_reg = 0x0ac4, 1660 .enable_mask = BIT(0), 1661 .hw.init = &(struct clk_init_data){ 1662 .name = "gcc_blsp2_uart3_apps_clk", 1663 .parent_hws = (const struct clk_hw *[]){ &blsp2_uart3_apps_clk_src.clkr.hw }, 1664 .num_parents = 1, 1665 .flags = CLK_SET_RATE_PARENT, 1666 .ops = &clk_branch2_ops, 1667 }, 1668 }, 1669 }; 1670 1671 static struct clk_branch gcc_blsp2_uart4_apps_clk = { 1672 .halt_reg = 0x0b44, 1673 .clkr = { 1674 .enable_reg = 0x0b44, 1675 .enable_mask = BIT(0), 1676 .hw.init = &(struct clk_init_data){ 1677 .name = "gcc_blsp2_uart4_apps_clk", 1678 .parent_hws = (const struct clk_hw *[]){ &blsp2_uart4_apps_clk_src.clkr.hw }, 1679 .num_parents = 1, 1680 .flags = CLK_SET_RATE_PARENT, 1681 .ops = &clk_branch2_ops, 1682 }, 1683 }, 1684 }; 1685 1686 static struct clk_branch gcc_blsp2_uart5_apps_clk = { 1687 .halt_reg = 0x0bc4, 1688 .clkr = { 1689 .enable_reg = 0x0bc4, 1690 .enable_mask = BIT(0), 1691 .hw.init = &(struct clk_init_data){ 1692 .name = "gcc_blsp2_uart5_apps_clk", 1693 .parent_hws = (const struct clk_hw *[]){ &blsp2_uart5_apps_clk_src.clkr.hw }, 1694 .num_parents = 1, 1695 .flags = CLK_SET_RATE_PARENT, 1696 .ops = &clk_branch2_ops, 1697 }, 1698 }, 1699 }; 1700 1701 static struct clk_branch gcc_blsp2_uart6_apps_clk = { 1702 .halt_reg = 0x0c44, 1703 .clkr = { 1704 .enable_reg = 0x0c44, 1705 .enable_mask = BIT(0), 1706 .hw.init = &(struct clk_init_data){ 1707 .name = "gcc_blsp2_uart6_apps_clk", 1708 .parent_hws = (const struct clk_hw *[]){ &blsp2_uart6_apps_clk_src.clkr.hw }, 1709 .num_parents = 1, 1710 .flags = CLK_SET_RATE_PARENT, 1711 .ops = &clk_branch2_ops, 1712 }, 1713 }, 1714 }; 1715 1716 static struct clk_branch gcc_gp1_clk = { 1717 .halt_reg = 0x1900, 1718 .clkr = { 1719 .enable_reg = 0x1900, 1720 .enable_mask = BIT(0), 1721 .hw.init = &(struct clk_init_data){ 1722 .name = "gcc_gp1_clk", 1723 .parent_hws = (const struct clk_hw *[]){ &gp1_clk_src.clkr.hw }, 1724 .num_parents = 1, 1725 .flags = CLK_SET_RATE_PARENT, 1726 .ops = &clk_branch2_ops, 1727 }, 1728 }, 1729 }; 1730 1731 static struct clk_branch gcc_gp2_clk = { 1732 .halt_reg = 0x1940, 1733 .clkr = { 1734 .enable_reg = 0x1940, 1735 .enable_mask = BIT(0), 1736 .hw.init = &(struct clk_init_data){ 1737 .name = "gcc_gp2_clk", 1738 .parent_hws = (const struct clk_hw *[]){ &gp2_clk_src.clkr.hw }, 1739 .num_parents = 1, 1740 .flags = CLK_SET_RATE_PARENT, 1741 .ops = &clk_branch2_ops, 1742 }, 1743 }, 1744 }; 1745 1746 static struct clk_branch gcc_gp3_clk = { 1747 .halt_reg = 0x1980, 1748 .clkr = { 1749 .enable_reg = 0x1980, 1750 .enable_mask = BIT(0), 1751 .hw.init = &(struct clk_init_data){ 1752 .name = "gcc_gp3_clk", 1753 .parent_hws = (const struct clk_hw *[]){ &gp3_clk_src.clkr.hw }, 1754 .num_parents = 1, 1755 .flags = CLK_SET_RATE_PARENT, 1756 .ops = &clk_branch2_ops, 1757 }, 1758 }, 1759 }; 1760 1761 static struct clk_branch gcc_lpass_q6_axi_clk = { 1762 .halt_reg = 0x0280, 1763 .clkr = { 1764 .enable_reg = 0x0280, 1765 .enable_mask = BIT(0), 1766 .hw.init = &(struct clk_init_data){ 1767 .name = "gcc_lpass_q6_axi_clk", 1768 .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw }, 1769 .num_parents = 1, 1770 .ops = &clk_branch2_ops, 1771 }, 1772 }, 1773 }; 1774 1775 static struct clk_branch gcc_mss_q6_bimc_axi_clk = { 1776 .halt_reg = 0x0284, 1777 .clkr = { 1778 .enable_reg = 0x0284, 1779 .enable_mask = BIT(0), 1780 .hw.init = &(struct clk_init_data){ 1781 .name = "gcc_mss_q6_bimc_axi_clk", 1782 .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw }, 1783 .num_parents = 1, 1784 .ops = &clk_branch2_ops, 1785 }, 1786 }, 1787 }; 1788 1789 static struct clk_branch gcc_pcie_0_aux_clk = { 1790 .halt_reg = 0x1ad4, 1791 .clkr = { 1792 .enable_reg = 0x1ad4, 1793 .enable_mask = BIT(0), 1794 .hw.init = &(struct clk_init_data){ 1795 .name = "gcc_pcie_0_aux_clk", 1796 .parent_hws = (const struct clk_hw *[]){ &pcie_0_aux_clk_src.clkr.hw }, 1797 .num_parents = 1, 1798 .flags = CLK_SET_RATE_PARENT, 1799 .ops = &clk_branch2_ops, 1800 }, 1801 }, 1802 }; 1803 1804 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { 1805 .halt_reg = 0x1ad0, 1806 .clkr = { 1807 .enable_reg = 0x1ad0, 1808 .enable_mask = BIT(0), 1809 .hw.init = &(struct clk_init_data){ 1810 .name = "gcc_pcie_0_cfg_ahb_clk", 1811 .parent_hws = (const struct clk_hw *[]){ &config_noc_clk_src.clkr.hw }, 1812 .num_parents = 1, 1813 .flags = CLK_SET_RATE_PARENT, 1814 .ops = &clk_branch2_ops, 1815 }, 1816 }, 1817 }; 1818 1819 static struct clk_branch gcc_pcie_0_mstr_axi_clk = { 1820 .halt_reg = 0x1acc, 1821 .clkr = { 1822 .enable_reg = 0x1acc, 1823 .enable_mask = BIT(0), 1824 .hw.init = &(struct clk_init_data){ 1825 .name = "gcc_pcie_0_mstr_axi_clk", 1826 .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw }, 1827 .num_parents = 1, 1828 .flags = CLK_SET_RATE_PARENT, 1829 .ops = &clk_branch2_ops, 1830 }, 1831 }, 1832 }; 1833 1834 static struct clk_branch gcc_pcie_0_pipe_clk = { 1835 .halt_reg = 0x1ad8, 1836 .halt_check = BRANCH_HALT_DELAY, 1837 .clkr = { 1838 .enable_reg = 0x1ad8, 1839 .enable_mask = BIT(0), 1840 .hw.init = &(struct clk_init_data){ 1841 .name = "gcc_pcie_0_pipe_clk", 1842 .parent_hws = (const struct clk_hw *[]){ &pcie_0_pipe_clk_src.clkr.hw }, 1843 .num_parents = 1, 1844 .flags = CLK_SET_RATE_PARENT, 1845 .ops = &clk_branch2_ops, 1846 }, 1847 }, 1848 }; 1849 1850 static struct clk_branch gcc_pcie_0_slv_axi_clk = { 1851 .halt_reg = 0x1ac8, 1852 .halt_check = BRANCH_HALT_DELAY, 1853 .clkr = { 1854 .enable_reg = 0x1ac8, 1855 .enable_mask = BIT(0), 1856 .hw.init = &(struct clk_init_data){ 1857 .name = "gcc_pcie_0_slv_axi_clk", 1858 .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw }, 1859 .num_parents = 1, 1860 .flags = CLK_SET_RATE_PARENT, 1861 .ops = &clk_branch2_ops, 1862 }, 1863 }, 1864 }; 1865 1866 static struct clk_branch gcc_pcie_1_aux_clk = { 1867 .halt_reg = 0x1b54, 1868 .clkr = { 1869 .enable_reg = 0x1b54, 1870 .enable_mask = BIT(0), 1871 .hw.init = &(struct clk_init_data){ 1872 .name = "gcc_pcie_1_aux_clk", 1873 .parent_hws = (const struct clk_hw *[]){ &pcie_1_aux_clk_src.clkr.hw }, 1874 .num_parents = 1, 1875 .flags = CLK_SET_RATE_PARENT, 1876 .ops = &clk_branch2_ops, 1877 }, 1878 }, 1879 }; 1880 1881 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { 1882 .halt_reg = 0x1b54, 1883 .clkr = { 1884 .enable_reg = 0x1b54, 1885 .enable_mask = BIT(0), 1886 .hw.init = &(struct clk_init_data){ 1887 .name = "gcc_pcie_1_cfg_ahb_clk", 1888 .parent_hws = (const struct clk_hw *[]){ &config_noc_clk_src.clkr.hw }, 1889 .num_parents = 1, 1890 .flags = CLK_SET_RATE_PARENT, 1891 .ops = &clk_branch2_ops, 1892 }, 1893 }, 1894 }; 1895 1896 static struct clk_branch gcc_pcie_1_mstr_axi_clk = { 1897 .halt_reg = 0x1b50, 1898 .clkr = { 1899 .enable_reg = 0x1b50, 1900 .enable_mask = BIT(0), 1901 .hw.init = &(struct clk_init_data){ 1902 .name = "gcc_pcie_1_mstr_axi_clk", 1903 .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw }, 1904 .num_parents = 1, 1905 .flags = CLK_SET_RATE_PARENT, 1906 .ops = &clk_branch2_ops, 1907 }, 1908 }, 1909 }; 1910 1911 static struct clk_branch gcc_pcie_1_pipe_clk = { 1912 .halt_reg = 0x1b58, 1913 .halt_check = BRANCH_HALT_DELAY, 1914 .clkr = { 1915 .enable_reg = 0x1b58, 1916 .enable_mask = BIT(0), 1917 .hw.init = &(struct clk_init_data){ 1918 .name = "gcc_pcie_1_pipe_clk", 1919 .parent_hws = (const struct clk_hw *[]){ &pcie_1_pipe_clk_src.clkr.hw }, 1920 .num_parents = 1, 1921 .flags = CLK_SET_RATE_PARENT, 1922 .ops = &clk_branch2_ops, 1923 }, 1924 }, 1925 }; 1926 1927 static struct clk_branch gcc_pcie_1_slv_axi_clk = { 1928 .halt_reg = 0x1b48, 1929 .clkr = { 1930 .enable_reg = 0x1b48, 1931 .enable_mask = BIT(0), 1932 .hw.init = &(struct clk_init_data){ 1933 .name = "gcc_pcie_1_slv_axi_clk", 1934 .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw }, 1935 .num_parents = 1, 1936 .flags = CLK_SET_RATE_PARENT, 1937 .ops = &clk_branch2_ops, 1938 }, 1939 }, 1940 }; 1941 1942 static struct clk_branch gcc_pdm2_clk = { 1943 .halt_reg = 0x0ccc, 1944 .clkr = { 1945 .enable_reg = 0x0ccc, 1946 .enable_mask = BIT(0), 1947 .hw.init = &(struct clk_init_data){ 1948 .name = "gcc_pdm2_clk", 1949 .parent_hws = (const struct clk_hw *[]){ &pdm2_clk_src.clkr.hw }, 1950 .num_parents = 1, 1951 .flags = CLK_SET_RATE_PARENT, 1952 .ops = &clk_branch2_ops, 1953 }, 1954 }, 1955 }; 1956 1957 static struct clk_branch gcc_pdm_ahb_clk = { 1958 .halt_reg = 0x0cc4, 1959 .clkr = { 1960 .enable_reg = 0x0cc4, 1961 .enable_mask = BIT(0), 1962 .hw.init = &(struct clk_init_data){ 1963 .name = "gcc_pdm_ahb_clk", 1964 .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw }, 1965 .num_parents = 1, 1966 .ops = &clk_branch2_ops, 1967 }, 1968 }, 1969 }; 1970 1971 static struct clk_branch gcc_sdcc1_apps_clk = { 1972 .halt_reg = 0x04c4, 1973 .clkr = { 1974 .enable_reg = 0x04c4, 1975 .enable_mask = BIT(0), 1976 .hw.init = &(struct clk_init_data){ 1977 .name = "gcc_sdcc1_apps_clk", 1978 .parent_hws = (const struct clk_hw *[]){ &sdcc1_apps_clk_src.clkr.hw }, 1979 .num_parents = 1, 1980 .flags = CLK_SET_RATE_PARENT, 1981 .ops = &clk_branch2_ops, 1982 }, 1983 }, 1984 }; 1985 1986 static struct clk_branch gcc_sdcc1_ahb_clk = { 1987 .halt_reg = 0x04c8, 1988 .clkr = { 1989 .enable_reg = 0x04c8, 1990 .enable_mask = BIT(0), 1991 .hw.init = &(struct clk_init_data){ 1992 .name = "gcc_sdcc1_ahb_clk", 1993 .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw }, 1994 .num_parents = 1, 1995 .flags = CLK_SET_RATE_PARENT, 1996 .ops = &clk_branch2_ops, 1997 }, 1998 }, 1999 }; 2000 2001 static struct clk_branch gcc_sdcc2_ahb_clk = { 2002 .halt_reg = 0x0508, 2003 .clkr = { 2004 .enable_reg = 0x0508, 2005 .enable_mask = BIT(0), 2006 .hw.init = &(struct clk_init_data){ 2007 .name = "gcc_sdcc2_ahb_clk", 2008 .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw }, 2009 .num_parents = 1, 2010 .flags = CLK_SET_RATE_PARENT, 2011 .ops = &clk_branch2_ops, 2012 }, 2013 }, 2014 }; 2015 2016 static struct clk_branch gcc_sdcc2_apps_clk = { 2017 .halt_reg = 0x0504, 2018 .clkr = { 2019 .enable_reg = 0x0504, 2020 .enable_mask = BIT(0), 2021 .hw.init = &(struct clk_init_data){ 2022 .name = "gcc_sdcc2_apps_clk", 2023 .parent_hws = (const struct clk_hw *[]){ &sdcc2_apps_clk_src.clkr.hw }, 2024 .num_parents = 1, 2025 .flags = CLK_SET_RATE_PARENT, 2026 .ops = &clk_branch2_ops, 2027 }, 2028 }, 2029 }; 2030 2031 static struct clk_branch gcc_sdcc3_ahb_clk = { 2032 .halt_reg = 0x0548, 2033 .clkr = { 2034 .enable_reg = 0x0548, 2035 .enable_mask = BIT(0), 2036 .hw.init = &(struct clk_init_data){ 2037 .name = "gcc_sdcc3_ahb_clk", 2038 .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw }, 2039 .num_parents = 1, 2040 .flags = CLK_SET_RATE_PARENT, 2041 .ops = &clk_branch2_ops, 2042 }, 2043 }, 2044 }; 2045 2046 static struct clk_branch gcc_sdcc3_apps_clk = { 2047 .halt_reg = 0x0544, 2048 .clkr = { 2049 .enable_reg = 0x0544, 2050 .enable_mask = BIT(0), 2051 .hw.init = &(struct clk_init_data){ 2052 .name = "gcc_sdcc3_apps_clk", 2053 .parent_hws = (const struct clk_hw *[]){ &sdcc3_apps_clk_src.clkr.hw }, 2054 .num_parents = 1, 2055 .flags = CLK_SET_RATE_PARENT, 2056 .ops = &clk_branch2_ops, 2057 }, 2058 }, 2059 }; 2060 2061 static struct clk_branch gcc_sdcc4_ahb_clk = { 2062 .halt_reg = 0x0588, 2063 .clkr = { 2064 .enable_reg = 0x0588, 2065 .enable_mask = BIT(0), 2066 .hw.init = &(struct clk_init_data){ 2067 .name = "gcc_sdcc4_ahb_clk", 2068 .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw }, 2069 .num_parents = 1, 2070 .flags = CLK_SET_RATE_PARENT, 2071 .ops = &clk_branch2_ops, 2072 }, 2073 }, 2074 }; 2075 2076 static struct clk_branch gcc_sdcc4_apps_clk = { 2077 .halt_reg = 0x0584, 2078 .clkr = { 2079 .enable_reg = 0x0584, 2080 .enable_mask = BIT(0), 2081 .hw.init = &(struct clk_init_data){ 2082 .name = "gcc_sdcc4_apps_clk", 2083 .parent_hws = (const struct clk_hw *[]){ &sdcc4_apps_clk_src.clkr.hw }, 2084 .num_parents = 1, 2085 .flags = CLK_SET_RATE_PARENT, 2086 .ops = &clk_branch2_ops, 2087 }, 2088 }, 2089 }; 2090 2091 static struct clk_branch gcc_sys_noc_ufs_axi_clk = { 2092 .halt_reg = 0x1d7c, 2093 .clkr = { 2094 .enable_reg = 0x1d7c, 2095 .enable_mask = BIT(0), 2096 .hw.init = &(struct clk_init_data){ 2097 .name = "gcc_sys_noc_ufs_axi_clk", 2098 .parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw }, 2099 .num_parents = 1, 2100 .flags = CLK_SET_RATE_PARENT, 2101 .ops = &clk_branch2_ops, 2102 }, 2103 }, 2104 }; 2105 2106 static struct clk_branch gcc_sys_noc_usb3_axi_clk = { 2107 .halt_reg = 0x03fc, 2108 .clkr = { 2109 .enable_reg = 0x03fc, 2110 .enable_mask = BIT(0), 2111 .hw.init = &(struct clk_init_data){ 2112 .name = "gcc_sys_noc_usb3_axi_clk", 2113 .parent_hws = (const struct clk_hw *[]){ &usb30_master_clk_src.clkr.hw }, 2114 .num_parents = 1, 2115 .flags = CLK_SET_RATE_PARENT, 2116 .ops = &clk_branch2_ops, 2117 }, 2118 }, 2119 }; 2120 2121 static struct clk_branch gcc_tsif_ahb_clk = { 2122 .halt_reg = 0x0d84, 2123 .clkr = { 2124 .enable_reg = 0x0d84, 2125 .enable_mask = BIT(0), 2126 .hw.init = &(struct clk_init_data){ 2127 .name = "gcc_tsif_ahb_clk", 2128 .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw }, 2129 .num_parents = 1, 2130 .ops = &clk_branch2_ops, 2131 }, 2132 }, 2133 }; 2134 2135 static struct clk_branch gcc_tsif_ref_clk = { 2136 .halt_reg = 0x0d88, 2137 .clkr = { 2138 .enable_reg = 0x0d88, 2139 .enable_mask = BIT(0), 2140 .hw.init = &(struct clk_init_data){ 2141 .name = "gcc_tsif_ref_clk", 2142 .parent_hws = (const struct clk_hw *[]){ &tsif_ref_clk_src.clkr.hw }, 2143 .num_parents = 1, 2144 .flags = CLK_SET_RATE_PARENT, 2145 .ops = &clk_branch2_ops, 2146 }, 2147 }, 2148 }; 2149 2150 static struct clk_branch gcc_ufs_ahb_clk = { 2151 .halt_reg = 0x1d4c, 2152 .clkr = { 2153 .enable_reg = 0x1d4c, 2154 .enable_mask = BIT(0), 2155 .hw.init = &(struct clk_init_data){ 2156 .name = "gcc_ufs_ahb_clk", 2157 .parent_hws = (const struct clk_hw *[]){ &config_noc_clk_src.clkr.hw }, 2158 .num_parents = 1, 2159 .ops = &clk_branch2_ops, 2160 }, 2161 }, 2162 }; 2163 2164 static struct clk_branch gcc_ufs_axi_clk = { 2165 .halt_reg = 0x1d48, 2166 .clkr = { 2167 .enable_reg = 0x1d48, 2168 .enable_mask = BIT(0), 2169 .hw.init = &(struct clk_init_data){ 2170 .name = "gcc_ufs_axi_clk", 2171 .parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw }, 2172 .num_parents = 1, 2173 .flags = CLK_SET_RATE_PARENT, 2174 .ops = &clk_branch2_ops, 2175 }, 2176 }, 2177 }; 2178 2179 static struct clk_branch gcc_ufs_rx_cfg_clk = { 2180 .halt_reg = 0x1d54, 2181 .clkr = { 2182 .enable_reg = 0x1d54, 2183 .enable_mask = BIT(0), 2184 .hw.init = &(struct clk_init_data){ 2185 .name = "gcc_ufs_rx_cfg_clk", 2186 .parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw }, 2187 .num_parents = 1, 2188 .flags = CLK_SET_RATE_PARENT, 2189 .ops = &clk_branch2_ops, 2190 }, 2191 }, 2192 }; 2193 2194 static struct clk_branch gcc_ufs_rx_symbol_0_clk = { 2195 .halt_reg = 0x1d60, 2196 .halt_check = BRANCH_HALT_DELAY, 2197 .clkr = { 2198 .enable_reg = 0x1d60, 2199 .enable_mask = BIT(0), 2200 .hw.init = &(struct clk_init_data){ 2201 .name = "gcc_ufs_rx_symbol_0_clk", 2202 .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw }, 2203 .num_parents = 1, 2204 .ops = &clk_branch2_ops, 2205 }, 2206 }, 2207 }; 2208 2209 static struct clk_branch gcc_ufs_rx_symbol_1_clk = { 2210 .halt_reg = 0x1d64, 2211 .halt_check = BRANCH_HALT_DELAY, 2212 .clkr = { 2213 .enable_reg = 0x1d64, 2214 .enable_mask = BIT(0), 2215 .hw.init = &(struct clk_init_data){ 2216 .name = "gcc_ufs_rx_symbol_1_clk", 2217 .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw }, 2218 .num_parents = 1, 2219 .ops = &clk_branch2_ops, 2220 }, 2221 }, 2222 }; 2223 2224 static struct clk_branch gcc_ufs_tx_cfg_clk = { 2225 .halt_reg = 0x1d50, 2226 .clkr = { 2227 .enable_reg = 0x1d50, 2228 .enable_mask = BIT(0), 2229 .hw.init = &(struct clk_init_data){ 2230 .name = "gcc_ufs_tx_cfg_clk", 2231 .parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw }, 2232 .num_parents = 1, 2233 .flags = CLK_SET_RATE_PARENT, 2234 .ops = &clk_branch2_ops, 2235 }, 2236 }, 2237 }; 2238 2239 static struct clk_branch gcc_ufs_tx_symbol_0_clk = { 2240 .halt_reg = 0x1d58, 2241 .halt_check = BRANCH_HALT_DELAY, 2242 .clkr = { 2243 .enable_reg = 0x1d58, 2244 .enable_mask = BIT(0), 2245 .hw.init = &(struct clk_init_data){ 2246 .name = "gcc_ufs_tx_symbol_0_clk", 2247 .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw }, 2248 .num_parents = 1, 2249 .ops = &clk_branch2_ops, 2250 }, 2251 }, 2252 }; 2253 2254 static struct clk_branch gcc_ufs_tx_symbol_1_clk = { 2255 .halt_reg = 0x1d5c, 2256 .halt_check = BRANCH_HALT_DELAY, 2257 .clkr = { 2258 .enable_reg = 0x1d5c, 2259 .enable_mask = BIT(0), 2260 .hw.init = &(struct clk_init_data){ 2261 .name = "gcc_ufs_tx_symbol_1_clk", 2262 .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw }, 2263 .num_parents = 1, 2264 .ops = &clk_branch2_ops, 2265 }, 2266 }, 2267 }; 2268 2269 static struct clk_branch gcc_usb2_hs_phy_sleep_clk = { 2270 .halt_reg = 0x04ac, 2271 .clkr = { 2272 .enable_reg = 0x04ac, 2273 .enable_mask = BIT(0), 2274 .hw.init = &(struct clk_init_data){ 2275 .name = "gcc_usb2_hs_phy_sleep_clk", 2276 .parent_data = &(const struct clk_parent_data){ 2277 .fw_name = "sleep", 2278 .name = "sleep" 2279 }, 2280 .num_parents = 1, 2281 .ops = &clk_branch2_ops, 2282 }, 2283 }, 2284 }; 2285 2286 static struct clk_branch gcc_usb30_master_clk = { 2287 .halt_reg = 0x03c8, 2288 .clkr = { 2289 .enable_reg = 0x03c8, 2290 .enable_mask = BIT(0), 2291 .hw.init = &(struct clk_init_data){ 2292 .name = "gcc_usb30_master_clk", 2293 .parent_hws = (const struct clk_hw *[]){ &usb30_master_clk_src.clkr.hw }, 2294 .num_parents = 1, 2295 .flags = CLK_SET_RATE_PARENT, 2296 .ops = &clk_branch2_ops, 2297 }, 2298 }, 2299 }; 2300 2301 static struct clk_branch gcc_usb30_mock_utmi_clk = { 2302 .halt_reg = 0x03d0, 2303 .clkr = { 2304 .enable_reg = 0x03d0, 2305 .enable_mask = BIT(0), 2306 .hw.init = &(struct clk_init_data){ 2307 .name = "gcc_usb30_mock_utmi_clk", 2308 .parent_hws = (const struct clk_hw *[]){ &usb30_mock_utmi_clk_src.clkr.hw }, 2309 .num_parents = 1, 2310 .flags = CLK_SET_RATE_PARENT, 2311 .ops = &clk_branch2_ops, 2312 }, 2313 }, 2314 }; 2315 2316 static struct clk_branch gcc_usb30_sleep_clk = { 2317 .halt_reg = 0x03cc, 2318 .clkr = { 2319 .enable_reg = 0x03cc, 2320 .enable_mask = BIT(0), 2321 .hw.init = &(struct clk_init_data){ 2322 .name = "gcc_usb30_sleep_clk", 2323 .parent_data = &(const struct clk_parent_data){ 2324 .fw_name = "sleep", 2325 .name = "sleep" 2326 }, 2327 .num_parents = 1, 2328 .ops = &clk_branch2_ops, 2329 }, 2330 }, 2331 }; 2332 2333 static struct clk_branch gcc_usb3_phy_aux_clk = { 2334 .halt_reg = 0x1408, 2335 .clkr = { 2336 .enable_reg = 0x1408, 2337 .enable_mask = BIT(0), 2338 .hw.init = &(struct clk_init_data){ 2339 .name = "gcc_usb3_phy_aux_clk", 2340 .parent_hws = (const struct clk_hw *[]){ &usb3_phy_aux_clk_src.clkr.hw }, 2341 .num_parents = 1, 2342 .flags = CLK_SET_RATE_PARENT, 2343 .ops = &clk_branch2_ops, 2344 }, 2345 }, 2346 }; 2347 2348 static struct clk_branch gcc_usb3_phy_pipe_clk = { 2349 .halt_reg = 0x140c, 2350 .halt_check = BRANCH_HALT_SKIP, 2351 .clkr = { 2352 .enable_reg = 0x140c, 2353 .enable_mask = BIT(0), 2354 .hw.init = &(struct clk_init_data){ 2355 .name = "gcc_usb3_phy_pipe_clk", 2356 .ops = &clk_branch2_ops, 2357 }, 2358 }, 2359 }; 2360 2361 static struct clk_branch gcc_usb_hs_ahb_clk = { 2362 .halt_reg = 0x0488, 2363 .clkr = { 2364 .enable_reg = 0x0488, 2365 .enable_mask = BIT(0), 2366 .hw.init = &(struct clk_init_data){ 2367 .name = "gcc_usb_hs_ahb_clk", 2368 .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw }, 2369 .num_parents = 1, 2370 .ops = &clk_branch2_ops, 2371 }, 2372 }, 2373 }; 2374 2375 static struct clk_branch gcc_usb_hs_system_clk = { 2376 .halt_reg = 0x0484, 2377 .clkr = { 2378 .enable_reg = 0x0484, 2379 .enable_mask = BIT(0), 2380 .hw.init = &(struct clk_init_data){ 2381 .name = "gcc_usb_hs_system_clk", 2382 .parent_hws = (const struct clk_hw *[]){ &usb_hs_system_clk_src.clkr.hw }, 2383 .num_parents = 1, 2384 .flags = CLK_SET_RATE_PARENT, 2385 .ops = &clk_branch2_ops, 2386 }, 2387 }, 2388 }; 2389 2390 static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = { 2391 .halt_reg = 0x1a84, 2392 .clkr = { 2393 .enable_reg = 0x1a84, 2394 .enable_mask = BIT(0), 2395 .hw.init = &(struct clk_init_data){ 2396 .name = "gcc_usb_phy_cfg_ahb2phy_clk", 2397 .ops = &clk_branch2_ops, 2398 }, 2399 }, 2400 }; 2401 2402 static struct clk_branch gpll0_out_mmsscc = { 2403 .halt_check = BRANCH_HALT_DELAY, 2404 .clkr = { 2405 .enable_reg = 0x1484, 2406 .enable_mask = BIT(26), 2407 .hw.init = &(struct clk_init_data){ 2408 .name = "gpll0_out_mmsscc", 2409 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw }, 2410 .num_parents = 1, 2411 .ops = &clk_branch2_ops, 2412 }, 2413 }, 2414 }; 2415 2416 static struct clk_branch gpll0_out_msscc = { 2417 .halt_check = BRANCH_HALT_DELAY, 2418 .clkr = { 2419 .enable_reg = 0x1484, 2420 .enable_mask = BIT(27), 2421 .hw.init = &(struct clk_init_data){ 2422 .name = "gpll0_out_msscc", 2423 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw }, 2424 .num_parents = 1, 2425 .ops = &clk_branch2_ops, 2426 }, 2427 }, 2428 }; 2429 2430 static struct clk_branch pcie_0_phy_ldo = { 2431 .halt_reg = 0x1e00, 2432 .halt_check = BRANCH_HALT_SKIP, 2433 .clkr = { 2434 .enable_reg = 0x1E00, 2435 .enable_mask = BIT(0), 2436 .hw.init = &(struct clk_init_data){ 2437 .name = "pcie_0_phy_ldo", 2438 .ops = &clk_branch2_ops, 2439 }, 2440 }, 2441 }; 2442 2443 static struct clk_branch pcie_1_phy_ldo = { 2444 .halt_reg = 0x1e04, 2445 .halt_check = BRANCH_HALT_SKIP, 2446 .clkr = { 2447 .enable_reg = 0x1E04, 2448 .enable_mask = BIT(0), 2449 .hw.init = &(struct clk_init_data){ 2450 .name = "pcie_1_phy_ldo", 2451 .ops = &clk_branch2_ops, 2452 }, 2453 }, 2454 }; 2455 2456 static struct clk_branch ufs_phy_ldo = { 2457 .halt_reg = 0x1e0c, 2458 .halt_check = BRANCH_HALT_SKIP, 2459 .clkr = { 2460 .enable_reg = 0x1E0C, 2461 .enable_mask = BIT(0), 2462 .hw.init = &(struct clk_init_data){ 2463 .name = "ufs_phy_ldo", 2464 .ops = &clk_branch2_ops, 2465 }, 2466 }, 2467 }; 2468 2469 static struct clk_branch usb_ss_phy_ldo = { 2470 .halt_reg = 0x1e08, 2471 .halt_check = BRANCH_HALT_SKIP, 2472 .clkr = { 2473 .enable_reg = 0x1E08, 2474 .enable_mask = BIT(0), 2475 .hw.init = &(struct clk_init_data){ 2476 .name = "usb_ss_phy_ldo", 2477 .ops = &clk_branch2_ops, 2478 }, 2479 }, 2480 }; 2481 2482 static struct clk_branch gcc_boot_rom_ahb_clk = { 2483 .halt_reg = 0x0e04, 2484 .halt_check = BRANCH_HALT_VOTED, 2485 .hwcg_reg = 0x0e04, 2486 .hwcg_bit = 1, 2487 .clkr = { 2488 .enable_reg = 0x1484, 2489 .enable_mask = BIT(10), 2490 .hw.init = &(struct clk_init_data){ 2491 .name = "gcc_boot_rom_ahb_clk", 2492 .parent_hws = (const struct clk_hw *[]){ &config_noc_clk_src.clkr.hw }, 2493 .num_parents = 1, 2494 .ops = &clk_branch2_ops, 2495 }, 2496 }, 2497 }; 2498 2499 static struct clk_branch gcc_prng_ahb_clk = { 2500 .halt_reg = 0x0d04, 2501 .halt_check = BRANCH_HALT_VOTED, 2502 .clkr = { 2503 .enable_reg = 0x1484, 2504 .enable_mask = BIT(13), 2505 .hw.init = &(struct clk_init_data){ 2506 .name = "gcc_prng_ahb_clk", 2507 .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw }, 2508 .num_parents = 1, 2509 .ops = &clk_branch2_ops, 2510 }, 2511 }, 2512 }; 2513 2514 static struct gdsc pcie_0_gdsc = { 2515 .gdscr = 0x1ac4, 2516 .pd = { 2517 .name = "pcie_0", 2518 }, 2519 .pwrsts = PWRSTS_OFF_ON, 2520 }; 2521 2522 static struct gdsc pcie_1_gdsc = { 2523 .gdscr = 0x1b44, 2524 .pd = { 2525 .name = "pcie_1", 2526 }, 2527 .pwrsts = PWRSTS_OFF_ON, 2528 }; 2529 2530 static struct gdsc usb30_gdsc = { 2531 .gdscr = 0x3c4, 2532 .pd = { 2533 .name = "usb30", 2534 }, 2535 .pwrsts = PWRSTS_OFF_ON, 2536 }; 2537 2538 static struct gdsc ufs_gdsc = { 2539 .gdscr = 0x1d44, 2540 .pd = { 2541 .name = "ufs", 2542 }, 2543 .pwrsts = PWRSTS_OFF_ON, 2544 }; 2545 2546 static struct clk_regmap *gcc_msm8994_clocks[] = { 2547 [GPLL0_EARLY] = &gpll0_early.clkr, 2548 [GPLL0] = &gpll0.clkr, 2549 [GPLL4_EARLY] = &gpll4_early.clkr, 2550 [GPLL4] = &gpll4.clkr, 2551 [CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr, 2552 [PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr, 2553 [SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr, 2554 [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr, 2555 [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr, 2556 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr, 2557 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr, 2558 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr, 2559 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr, 2560 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr, 2561 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr, 2562 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr, 2563 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr, 2564 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr, 2565 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr, 2566 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr, 2567 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr, 2568 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr, 2569 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr, 2570 [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr, 2571 [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr, 2572 [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr, 2573 [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr, 2574 [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr, 2575 [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr, 2576 [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr, 2577 [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr, 2578 [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr, 2579 [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr, 2580 [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr, 2581 [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr, 2582 [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr, 2583 [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr, 2584 [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr, 2585 [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr, 2586 [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr, 2587 [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr, 2588 [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr, 2589 [BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr, 2590 [BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr, 2591 [BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr, 2592 [GP1_CLK_SRC] = &gp1_clk_src.clkr, 2593 [GP2_CLK_SRC] = &gp2_clk_src.clkr, 2594 [GP3_CLK_SRC] = &gp3_clk_src.clkr, 2595 [PCIE_0_AUX_CLK_SRC] = &pcie_0_aux_clk_src.clkr, 2596 [PCIE_0_PIPE_CLK_SRC] = &pcie_0_pipe_clk_src.clkr, 2597 [PCIE_1_AUX_CLK_SRC] = &pcie_1_aux_clk_src.clkr, 2598 [PCIE_1_PIPE_CLK_SRC] = &pcie_1_pipe_clk_src.clkr, 2599 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr, 2600 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr, 2601 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr, 2602 [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr, 2603 [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr, 2604 [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr, 2605 [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr, 2606 [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr, 2607 [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr, 2608 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr, 2609 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr, 2610 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr, 2611 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr, 2612 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr, 2613 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr, 2614 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr, 2615 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr, 2616 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr, 2617 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr, 2618 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr, 2619 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr, 2620 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr, 2621 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, 2622 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr, 2623 [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr, 2624 [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr, 2625 [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr, 2626 [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr, 2627 [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr, 2628 [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr, 2629 [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr, 2630 [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr, 2631 [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr, 2632 [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr, 2633 [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr, 2634 [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr, 2635 [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr, 2636 [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr, 2637 [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr, 2638 [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr, 2639 [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr, 2640 [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr, 2641 [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr, 2642 [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr, 2643 [GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr, 2644 [GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr, 2645 [GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr, 2646 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 2647 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 2648 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 2649 [GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr, 2650 [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr, 2651 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, 2652 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, 2653 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, 2654 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, 2655 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, 2656 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr, 2657 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr, 2658 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr, 2659 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr, 2660 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr, 2661 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 2662 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 2663 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, 2664 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, 2665 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 2666 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 2667 [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr, 2668 [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr, 2669 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, 2670 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, 2671 [GCC_SYS_NOC_UFS_AXI_CLK] = &gcc_sys_noc_ufs_axi_clk.clkr, 2672 [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr, 2673 [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr, 2674 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr, 2675 [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr, 2676 [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr, 2677 [GCC_UFS_RX_CFG_CLK] = &gcc_ufs_rx_cfg_clk.clkr, 2678 [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr, 2679 [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr, 2680 [GCC_UFS_TX_CFG_CLK] = &gcc_ufs_tx_cfg_clk.clkr, 2681 [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr, 2682 [GCC_UFS_TX_SYMBOL_1_CLK] = &gcc_ufs_tx_symbol_1_clk.clkr, 2683 [GCC_USB2_HS_PHY_SLEEP_CLK] = &gcc_usb2_hs_phy_sleep_clk.clkr, 2684 [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr, 2685 [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr, 2686 [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr, 2687 [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr, 2688 [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr, 2689 [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr, 2690 [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr, 2691 [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr, 2692 [GPLL0_OUT_MMSSCC] = &gpll0_out_mmsscc.clkr, 2693 [GPLL0_OUT_MSSCC] = &gpll0_out_msscc.clkr, 2694 [PCIE_0_PHY_LDO] = &pcie_0_phy_ldo.clkr, 2695 [PCIE_1_PHY_LDO] = &pcie_1_phy_ldo.clkr, 2696 [UFS_PHY_LDO] = &ufs_phy_ldo.clkr, 2697 [USB_SS_PHY_LDO] = &usb_ss_phy_ldo.clkr, 2698 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 2699 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, 2700 }; 2701 2702 static struct gdsc *gcc_msm8994_gdscs[] = { 2703 /* This GDSC does not exist, but ABI has to remain intact */ 2704 [PCIE_GDSC] = NULL, 2705 [PCIE_0_GDSC] = &pcie_0_gdsc, 2706 [PCIE_1_GDSC] = &pcie_1_gdsc, 2707 [USB30_GDSC] = &usb30_gdsc, 2708 [UFS_GDSC] = &ufs_gdsc, 2709 }; 2710 2711 static const struct qcom_reset_map gcc_msm8994_resets[] = { 2712 [USB3_PHY_RESET] = { 0x1400 }, 2713 [USB3PHY_PHY_RESET] = { 0x1404 }, 2714 [MSS_RESET] = { 0x1680 }, 2715 [PCIE_PHY_0_RESET] = { 0x1b18 }, 2716 [PCIE_PHY_1_RESET] = { 0x1b98 }, 2717 [QUSB2_PHY_RESET] = { 0x04b8 }, 2718 }; 2719 2720 static const struct regmap_config gcc_msm8994_regmap_config = { 2721 .reg_bits = 32, 2722 .reg_stride = 4, 2723 .val_bits = 32, 2724 .max_register = 0x2000, 2725 .fast_io = true, 2726 }; 2727 2728 static const struct qcom_cc_desc gcc_msm8994_desc = { 2729 .config = &gcc_msm8994_regmap_config, 2730 .clks = gcc_msm8994_clocks, 2731 .num_clks = ARRAY_SIZE(gcc_msm8994_clocks), 2732 .resets = gcc_msm8994_resets, 2733 .num_resets = ARRAY_SIZE(gcc_msm8994_resets), 2734 .gdscs = gcc_msm8994_gdscs, 2735 .num_gdscs = ARRAY_SIZE(gcc_msm8994_gdscs), 2736 }; 2737 2738 static const struct of_device_id gcc_msm8994_match_table[] = { 2739 { .compatible = "qcom,gcc-msm8992" }, 2740 { .compatible = "qcom,gcc-msm8994" }, /* V2 and V2.1 */ 2741 {} 2742 }; 2743 MODULE_DEVICE_TABLE(of, gcc_msm8994_match_table); 2744 2745 static int gcc_msm8994_probe(struct platform_device *pdev) 2746 { 2747 if (of_device_is_compatible(pdev->dev.of_node, "qcom,gcc-msm8992")) { 2748 /* MSM8992 features less clocks and some have different freq tables */ 2749 gcc_msm8994_desc.clks[UFS_AXI_CLK_SRC] = NULL; 2750 gcc_msm8994_desc.clks[GCC_LPASS_Q6_AXI_CLK] = NULL; 2751 gcc_msm8994_desc.clks[UFS_PHY_LDO] = NULL; 2752 gcc_msm8994_desc.clks[GCC_UFS_AHB_CLK] = NULL; 2753 gcc_msm8994_desc.clks[GCC_UFS_AXI_CLK] = NULL; 2754 gcc_msm8994_desc.clks[GCC_UFS_RX_CFG_CLK] = NULL; 2755 gcc_msm8994_desc.clks[GCC_UFS_RX_SYMBOL_0_CLK] = NULL; 2756 gcc_msm8994_desc.clks[GCC_UFS_RX_SYMBOL_1_CLK] = NULL; 2757 gcc_msm8994_desc.clks[GCC_UFS_TX_CFG_CLK] = NULL; 2758 gcc_msm8994_desc.clks[GCC_UFS_TX_SYMBOL_0_CLK] = NULL; 2759 gcc_msm8994_desc.clks[GCC_UFS_TX_SYMBOL_1_CLK] = NULL; 2760 2761 sdcc1_apps_clk_src.freq_tbl = ftbl_sdcc1_apps_clk_src_8992; 2762 blsp1_qup1_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992; 2763 blsp1_qup2_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992; 2764 blsp1_qup3_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992; 2765 blsp1_qup4_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992; 2766 blsp1_qup5_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992; 2767 blsp1_qup6_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992; 2768 blsp2_qup1_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992; 2769 blsp2_qup2_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992; 2770 blsp2_qup3_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992; 2771 blsp2_qup4_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992; 2772 blsp2_qup5_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992; 2773 blsp2_qup6_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992; 2774 2775 /* 2776 * Some 8992 boards might *possibly* use 2777 * PCIe1 clocks and controller, but it's not 2778 * standard and they should be disabled otherwise. 2779 */ 2780 gcc_msm8994_desc.clks[PCIE_1_AUX_CLK_SRC] = NULL; 2781 gcc_msm8994_desc.clks[PCIE_1_PIPE_CLK_SRC] = NULL; 2782 gcc_msm8994_desc.clks[PCIE_1_PHY_LDO] = NULL; 2783 gcc_msm8994_desc.clks[GCC_PCIE_1_AUX_CLK] = NULL; 2784 gcc_msm8994_desc.clks[GCC_PCIE_1_CFG_AHB_CLK] = NULL; 2785 gcc_msm8994_desc.clks[GCC_PCIE_1_MSTR_AXI_CLK] = NULL; 2786 gcc_msm8994_desc.clks[GCC_PCIE_1_PIPE_CLK] = NULL; 2787 gcc_msm8994_desc.clks[GCC_PCIE_1_SLV_AXI_CLK] = NULL; 2788 gcc_msm8994_desc.clks[GCC_SYS_NOC_UFS_AXI_CLK] = NULL; 2789 } 2790 2791 return qcom_cc_probe(pdev, &gcc_msm8994_desc); 2792 } 2793 2794 static struct platform_driver gcc_msm8994_driver = { 2795 .probe = gcc_msm8994_probe, 2796 .driver = { 2797 .name = "gcc-msm8994", 2798 .of_match_table = gcc_msm8994_match_table, 2799 }, 2800 }; 2801 2802 static int __init gcc_msm8994_init(void) 2803 { 2804 return platform_driver_register(&gcc_msm8994_driver); 2805 } 2806 core_initcall(gcc_msm8994_init); 2807 2808 static void __exit gcc_msm8994_exit(void) 2809 { 2810 platform_driver_unregister(&gcc_msm8994_driver); 2811 } 2812 module_exit(gcc_msm8994_exit); 2813 2814 MODULE_DESCRIPTION("Qualcomm GCC MSM8994 Driver"); 2815 MODULE_LICENSE("GPL v2"); 2816 MODULE_ALIAS("platform:gcc-msm8994"); 2817