1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. 3 */ 4 5 #include <linux/clk-provider.h> 6 #include <linux/kernel.h> 7 #include <linux/init.h> 8 #include <linux/err.h> 9 #include <linux/ctype.h> 10 #include <linux/io.h> 11 #include <linux/of.h> 12 #include <linux/of_device.h> 13 #include <linux/platform_device.h> 14 #include <linux/module.h> 15 #include <linux/regmap.h> 16 17 #include <dt-bindings/clock/qcom,gcc-msm8994.h> 18 19 #include "common.h" 20 #include "clk-regmap.h" 21 #include "clk-alpha-pll.h" 22 #include "clk-rcg.h" 23 #include "clk-branch.h" 24 #include "reset.h" 25 #include "gdsc.h" 26 27 enum { 28 P_XO, 29 P_GPLL0, 30 P_GPLL4, 31 }; 32 33 static struct clk_alpha_pll gpll0_early = { 34 .offset = 0, 35 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 36 .clkr = { 37 .enable_reg = 0x1480, 38 .enable_mask = BIT(0), 39 .hw.init = &(struct clk_init_data){ 40 .name = "gpll0_early", 41 .parent_data = &(const struct clk_parent_data){ 42 .fw_name = "xo", 43 }, 44 .num_parents = 1, 45 .ops = &clk_alpha_pll_ops, 46 }, 47 }, 48 }; 49 50 static struct clk_alpha_pll_postdiv gpll0 = { 51 .offset = 0, 52 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 53 .clkr.hw.init = &(struct clk_init_data){ 54 .name = "gpll0", 55 .parent_names = (const char *[]) { "gpll0_early" }, 56 .num_parents = 1, 57 .ops = &clk_alpha_pll_postdiv_ops, 58 }, 59 }; 60 61 static struct clk_alpha_pll gpll4_early = { 62 .offset = 0x1dc0, 63 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 64 .clkr = { 65 .enable_reg = 0x1480, 66 .enable_mask = BIT(4), 67 .hw.init = &(struct clk_init_data){ 68 .name = "gpll4_early", 69 .parent_data = &(const struct clk_parent_data){ 70 .fw_name = "xo", 71 }, 72 .num_parents = 1, 73 .ops = &clk_alpha_pll_ops, 74 }, 75 }, 76 }; 77 78 static struct clk_alpha_pll_postdiv gpll4 = { 79 .offset = 0x1dc0, 80 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 81 .clkr.hw.init = &(struct clk_init_data){ 82 .name = "gpll4", 83 .parent_names = (const char *[]) { "gpll4_early" }, 84 .num_parents = 1, 85 .ops = &clk_alpha_pll_postdiv_ops, 86 }, 87 }; 88 89 static const struct parent_map gcc_xo_gpll0_map[] = { 90 { P_XO, 0 }, 91 { P_GPLL0, 1 }, 92 }; 93 94 static const struct clk_parent_data gcc_xo_gpll0[] = { 95 { .fw_name = "xo" }, 96 { .hw = &gpll0.clkr.hw }, 97 }; 98 99 static const struct parent_map gcc_xo_gpll0_gpll4_map[] = { 100 { P_XO, 0 }, 101 { P_GPLL0, 1 }, 102 { P_GPLL4, 5 }, 103 }; 104 105 static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = { 106 { .fw_name = "xo" }, 107 { .hw = &gpll0.clkr.hw }, 108 { .hw = &gpll4.clkr.hw }, 109 }; 110 111 static struct freq_tbl ftbl_ufs_axi_clk_src[] = { 112 F(50000000, P_GPLL0, 12, 0, 0), 113 F(100000000, P_GPLL0, 6, 0, 0), 114 F(150000000, P_GPLL0, 4, 0, 0), 115 F(171430000, P_GPLL0, 3.5, 0, 0), 116 F(200000000, P_GPLL0, 3, 0, 0), 117 F(240000000, P_GPLL0, 2.5, 0, 0), 118 { } 119 }; 120 121 static struct clk_rcg2 ufs_axi_clk_src = { 122 .cmd_rcgr = 0x1d68, 123 .mnd_width = 8, 124 .hid_width = 5, 125 .parent_map = gcc_xo_gpll0_map, 126 .freq_tbl = ftbl_ufs_axi_clk_src, 127 .clkr.hw.init = &(struct clk_init_data){ 128 .name = "ufs_axi_clk_src", 129 .parent_data = gcc_xo_gpll0, 130 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 131 .ops = &clk_rcg2_ops, 132 }, 133 }; 134 135 static struct freq_tbl ftbl_usb30_master_clk_src[] = { 136 F(19200000, P_XO, 1, 0, 0), 137 F(125000000, P_GPLL0, 1, 5, 24), 138 { } 139 }; 140 141 static struct clk_rcg2 usb30_master_clk_src = { 142 .cmd_rcgr = 0x03d4, 143 .mnd_width = 8, 144 .hid_width = 5, 145 .parent_map = gcc_xo_gpll0_map, 146 .freq_tbl = ftbl_usb30_master_clk_src, 147 .clkr.hw.init = &(struct clk_init_data){ 148 .name = "usb30_master_clk_src", 149 .parent_data = gcc_xo_gpll0, 150 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 151 .ops = &clk_rcg2_ops, 152 }, 153 }; 154 155 static struct freq_tbl ftbl_blsp_i2c_apps_clk_src[] = { 156 F(19200000, P_XO, 1, 0, 0), 157 F(50000000, P_GPLL0, 12, 0, 0), 158 { } 159 }; 160 161 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { 162 .cmd_rcgr = 0x0660, 163 .hid_width = 5, 164 .parent_map = gcc_xo_gpll0_map, 165 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 166 .clkr.hw.init = &(struct clk_init_data){ 167 .name = "blsp1_qup1_i2c_apps_clk_src", 168 .parent_data = gcc_xo_gpll0, 169 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 170 .ops = &clk_rcg2_ops, 171 }, 172 }; 173 174 static struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = { 175 F(960000, P_XO, 10, 1, 2), 176 F(4800000, P_XO, 4, 0, 0), 177 F(9600000, P_XO, 2, 0, 0), 178 F(15000000, P_GPLL0, 10, 1, 4), 179 F(19200000, P_XO, 1, 0, 0), 180 F(24000000, P_GPLL0, 12.5, 1, 2), 181 F(25000000, P_GPLL0, 12, 1, 2), 182 F(48000000, P_GPLL0, 12.5, 0, 0), 183 F(50000000, P_GPLL0, 12, 0, 0), 184 { } 185 }; 186 187 static struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src_8992[] = { 188 F(960000, P_XO, 10, 1, 2), 189 F(4800000, P_XO, 4, 0, 0), 190 F(9600000, P_XO, 2, 0, 0), 191 F(15000000, P_GPLL0, 10, 1, 4), 192 F(19200000, P_XO, 1, 0, 0), 193 F(25000000, P_GPLL0, 12, 1, 2), 194 F(50000000, P_GPLL0, 12, 0, 0), 195 { } 196 }; 197 198 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { 199 .cmd_rcgr = 0x064c, 200 .mnd_width = 8, 201 .hid_width = 5, 202 .parent_map = gcc_xo_gpll0_map, 203 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 204 .clkr.hw.init = &(struct clk_init_data){ 205 .name = "blsp1_qup1_spi_apps_clk_src", 206 .parent_data = gcc_xo_gpll0, 207 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 208 .ops = &clk_rcg2_ops, 209 }, 210 }; 211 212 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { 213 .cmd_rcgr = 0x06e0, 214 .hid_width = 5, 215 .parent_map = gcc_xo_gpll0_map, 216 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 217 .clkr.hw.init = &(struct clk_init_data){ 218 .name = "blsp1_qup2_i2c_apps_clk_src", 219 .parent_data = gcc_xo_gpll0, 220 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 221 .ops = &clk_rcg2_ops, 222 }, 223 }; 224 225 static struct freq_tbl ftbl_blsp1_qup2_spi_apps_clk_src[] = { 226 F(960000, P_XO, 10, 1, 2), 227 F(4800000, P_XO, 4, 0, 0), 228 F(9600000, P_XO, 2, 0, 0), 229 F(15000000, P_GPLL0, 10, 1, 4), 230 F(19200000, P_XO, 1, 0, 0), 231 F(24000000, P_GPLL0, 12.5, 1, 2), 232 F(25000000, P_GPLL0, 12, 1, 2), 233 F(42860000, P_GPLL0, 14, 0, 0), 234 F(46150000, P_GPLL0, 13, 0, 0), 235 { } 236 }; 237 238 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { 239 .cmd_rcgr = 0x06cc, 240 .mnd_width = 8, 241 .hid_width = 5, 242 .parent_map = gcc_xo_gpll0_map, 243 .freq_tbl = ftbl_blsp1_qup2_spi_apps_clk_src, 244 .clkr.hw.init = &(struct clk_init_data){ 245 .name = "blsp1_qup2_spi_apps_clk_src", 246 .parent_data = gcc_xo_gpll0, 247 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 248 .ops = &clk_rcg2_ops, 249 }, 250 }; 251 252 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { 253 .cmd_rcgr = 0x0760, 254 .hid_width = 5, 255 .parent_map = gcc_xo_gpll0_map, 256 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 257 .clkr.hw.init = &(struct clk_init_data){ 258 .name = "blsp1_qup3_i2c_apps_clk_src", 259 .parent_data = gcc_xo_gpll0, 260 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 261 .ops = &clk_rcg2_ops, 262 }, 263 }; 264 265 static struct freq_tbl ftbl_blsp1_qup3_4_spi_apps_clk_src[] = { 266 F(960000, P_XO, 10, 1, 2), 267 F(4800000, P_XO, 4, 0, 0), 268 F(9600000, P_XO, 2, 0, 0), 269 F(15000000, P_GPLL0, 10, 1, 4), 270 F(19200000, P_XO, 1, 0, 0), 271 F(24000000, P_GPLL0, 12.5, 1, 2), 272 F(25000000, P_GPLL0, 12, 1, 2), 273 F(42860000, P_GPLL0, 14, 0, 0), 274 F(44440000, P_GPLL0, 13.5, 0, 0), 275 { } 276 }; 277 278 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { 279 .cmd_rcgr = 0x074c, 280 .mnd_width = 8, 281 .hid_width = 5, 282 .parent_map = gcc_xo_gpll0_map, 283 .freq_tbl = ftbl_blsp1_qup3_4_spi_apps_clk_src, 284 .clkr.hw.init = &(struct clk_init_data){ 285 .name = "blsp1_qup3_spi_apps_clk_src", 286 .parent_data = gcc_xo_gpll0, 287 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 288 .ops = &clk_rcg2_ops, 289 }, 290 }; 291 292 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { 293 .cmd_rcgr = 0x07e0, 294 .hid_width = 5, 295 .parent_map = gcc_xo_gpll0_map, 296 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 297 .clkr.hw.init = &(struct clk_init_data){ 298 .name = "blsp1_qup4_i2c_apps_clk_src", 299 .parent_data = gcc_xo_gpll0, 300 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 301 .ops = &clk_rcg2_ops, 302 }, 303 }; 304 305 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { 306 .cmd_rcgr = 0x07cc, 307 .mnd_width = 8, 308 .hid_width = 5, 309 .parent_map = gcc_xo_gpll0_map, 310 .freq_tbl = ftbl_blsp1_qup3_4_spi_apps_clk_src, 311 .clkr.hw.init = &(struct clk_init_data){ 312 .name = "blsp1_qup4_spi_apps_clk_src", 313 .parent_data = gcc_xo_gpll0, 314 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 315 .ops = &clk_rcg2_ops, 316 }, 317 }; 318 319 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = { 320 .cmd_rcgr = 0x0860, 321 .hid_width = 5, 322 .parent_map = gcc_xo_gpll0_map, 323 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 324 .clkr.hw.init = &(struct clk_init_data){ 325 .name = "blsp1_qup5_i2c_apps_clk_src", 326 .parent_data = gcc_xo_gpll0, 327 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 328 .ops = &clk_rcg2_ops, 329 }, 330 }; 331 332 static struct freq_tbl ftbl_blsp1_qup5_spi_apps_clk_src[] = { 333 F(960000, P_XO, 10, 1, 2), 334 F(4800000, P_XO, 4, 0, 0), 335 F(9600000, P_XO, 2, 0, 0), 336 F(15000000, P_GPLL0, 10, 1, 4), 337 F(19200000, P_XO, 1, 0, 0), 338 F(24000000, P_GPLL0, 12.5, 1, 2), 339 F(25000000, P_GPLL0, 12, 1, 2), 340 F(40000000, P_GPLL0, 15, 0, 0), 341 F(42860000, P_GPLL0, 14, 0, 0), 342 { } 343 }; 344 345 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = { 346 .cmd_rcgr = 0x084c, 347 .mnd_width = 8, 348 .hid_width = 5, 349 .parent_map = gcc_xo_gpll0_map, 350 .freq_tbl = ftbl_blsp1_qup5_spi_apps_clk_src, 351 .clkr.hw.init = &(struct clk_init_data){ 352 .name = "blsp1_qup5_spi_apps_clk_src", 353 .parent_data = gcc_xo_gpll0, 354 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 355 .ops = &clk_rcg2_ops, 356 }, 357 }; 358 359 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = { 360 .cmd_rcgr = 0x08e0, 361 .hid_width = 5, 362 .parent_map = gcc_xo_gpll0_map, 363 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 364 .clkr.hw.init = &(struct clk_init_data){ 365 .name = "blsp1_qup6_i2c_apps_clk_src", 366 .parent_data = gcc_xo_gpll0, 367 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 368 .ops = &clk_rcg2_ops, 369 }, 370 }; 371 372 static struct freq_tbl ftbl_blsp1_qup6_spi_apps_clk_src[] = { 373 F(960000, P_XO, 10, 1, 2), 374 F(4800000, P_XO, 4, 0, 0), 375 F(9600000, P_XO, 2, 0, 0), 376 F(15000000, P_GPLL0, 10, 1, 4), 377 F(19200000, P_XO, 1, 0, 0), 378 F(24000000, P_GPLL0, 12.5, 1, 2), 379 F(27906976, P_GPLL0, 1, 2, 43), 380 F(41380000, P_GPLL0, 15, 0, 0), 381 F(42860000, P_GPLL0, 14, 0, 0), 382 { } 383 }; 384 385 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = { 386 .cmd_rcgr = 0x08cc, 387 .mnd_width = 8, 388 .hid_width = 5, 389 .parent_map = gcc_xo_gpll0_map, 390 .freq_tbl = ftbl_blsp1_qup6_spi_apps_clk_src, 391 .clkr.hw.init = &(struct clk_init_data){ 392 .name = "blsp1_qup6_spi_apps_clk_src", 393 .parent_data = gcc_xo_gpll0, 394 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 395 .ops = &clk_rcg2_ops, 396 }, 397 }; 398 399 static struct freq_tbl ftbl_blsp_uart_apps_clk_src[] = { 400 F(3686400, P_GPLL0, 1, 96, 15625), 401 F(7372800, P_GPLL0, 1, 192, 15625), 402 F(14745600, P_GPLL0, 1, 384, 15625), 403 F(16000000, P_GPLL0, 5, 2, 15), 404 F(19200000, P_XO, 1, 0, 0), 405 F(24000000, P_GPLL0, 5, 1, 5), 406 F(32000000, P_GPLL0, 1, 4, 75), 407 F(40000000, P_GPLL0, 15, 0, 0), 408 F(46400000, P_GPLL0, 1, 29, 375), 409 F(48000000, P_GPLL0, 12.5, 0, 0), 410 F(51200000, P_GPLL0, 1, 32, 375), 411 F(56000000, P_GPLL0, 1, 7, 75), 412 F(58982400, P_GPLL0, 1, 1536, 15625), 413 F(60000000, P_GPLL0, 10, 0, 0), 414 F(63160000, P_GPLL0, 9.5, 0, 0), 415 { } 416 }; 417 418 static struct clk_rcg2 blsp1_uart1_apps_clk_src = { 419 .cmd_rcgr = 0x068c, 420 .mnd_width = 16, 421 .hid_width = 5, 422 .parent_map = gcc_xo_gpll0_map, 423 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 424 .clkr.hw.init = &(struct clk_init_data){ 425 .name = "blsp1_uart1_apps_clk_src", 426 .parent_data = gcc_xo_gpll0, 427 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 428 .ops = &clk_rcg2_ops, 429 }, 430 }; 431 432 static struct clk_rcg2 blsp1_uart2_apps_clk_src = { 433 .cmd_rcgr = 0x070c, 434 .mnd_width = 16, 435 .hid_width = 5, 436 .parent_map = gcc_xo_gpll0_map, 437 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 438 .clkr.hw.init = &(struct clk_init_data){ 439 .name = "blsp1_uart2_apps_clk_src", 440 .parent_data = gcc_xo_gpll0, 441 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 442 .ops = &clk_rcg2_ops, 443 }, 444 }; 445 446 static struct clk_rcg2 blsp1_uart3_apps_clk_src = { 447 .cmd_rcgr = 0x078c, 448 .mnd_width = 16, 449 .hid_width = 5, 450 .parent_map = gcc_xo_gpll0_map, 451 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 452 .clkr.hw.init = &(struct clk_init_data){ 453 .name = "blsp1_uart3_apps_clk_src", 454 .parent_data = gcc_xo_gpll0, 455 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 456 .ops = &clk_rcg2_ops, 457 }, 458 }; 459 460 static struct clk_rcg2 blsp1_uart4_apps_clk_src = { 461 .cmd_rcgr = 0x080c, 462 .mnd_width = 16, 463 .hid_width = 5, 464 .parent_map = gcc_xo_gpll0_map, 465 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 466 .clkr.hw.init = &(struct clk_init_data){ 467 .name = "blsp1_uart4_apps_clk_src", 468 .parent_data = gcc_xo_gpll0, 469 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 470 .ops = &clk_rcg2_ops, 471 }, 472 }; 473 474 static struct clk_rcg2 blsp1_uart5_apps_clk_src = { 475 .cmd_rcgr = 0x088c, 476 .mnd_width = 16, 477 .hid_width = 5, 478 .parent_map = gcc_xo_gpll0_map, 479 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 480 .clkr.hw.init = &(struct clk_init_data){ 481 .name = "blsp1_uart5_apps_clk_src", 482 .parent_data = gcc_xo_gpll0, 483 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 484 .ops = &clk_rcg2_ops, 485 }, 486 }; 487 488 static struct clk_rcg2 blsp1_uart6_apps_clk_src = { 489 .cmd_rcgr = 0x090c, 490 .mnd_width = 16, 491 .hid_width = 5, 492 .parent_map = gcc_xo_gpll0_map, 493 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 494 .clkr.hw.init = &(struct clk_init_data){ 495 .name = "blsp1_uart6_apps_clk_src", 496 .parent_data = gcc_xo_gpll0, 497 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 498 .ops = &clk_rcg2_ops, 499 }, 500 }; 501 502 static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = { 503 .cmd_rcgr = 0x09a0, 504 .hid_width = 5, 505 .parent_map = gcc_xo_gpll0_map, 506 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 507 .clkr.hw.init = &(struct clk_init_data){ 508 .name = "blsp2_qup1_i2c_apps_clk_src", 509 .parent_data = gcc_xo_gpll0, 510 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 511 .ops = &clk_rcg2_ops, 512 }, 513 }; 514 515 static struct freq_tbl ftbl_blsp2_qup1_2_spi_apps_clk_src[] = { 516 F(960000, P_XO, 10, 1, 2), 517 F(4800000, P_XO, 4, 0, 0), 518 F(9600000, P_XO, 2, 0, 0), 519 F(15000000, P_GPLL0, 10, 1, 4), 520 F(19200000, P_XO, 1, 0, 0), 521 F(24000000, P_GPLL0, 12.5, 1, 2), 522 F(25000000, P_GPLL0, 12, 1, 2), 523 F(42860000, P_GPLL0, 14, 0, 0), 524 F(44440000, P_GPLL0, 13.5, 0, 0), 525 { } 526 }; 527 528 static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = { 529 .cmd_rcgr = 0x098c, 530 .mnd_width = 8, 531 .hid_width = 5, 532 .parent_map = gcc_xo_gpll0_map, 533 .freq_tbl = ftbl_blsp2_qup1_2_spi_apps_clk_src, 534 .clkr.hw.init = &(struct clk_init_data){ 535 .name = "blsp2_qup1_spi_apps_clk_src", 536 .parent_data = gcc_xo_gpll0, 537 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 538 .ops = &clk_rcg2_ops, 539 }, 540 }; 541 542 static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = { 543 .cmd_rcgr = 0x0a20, 544 .hid_width = 5, 545 .parent_map = gcc_xo_gpll0_map, 546 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 547 .clkr.hw.init = &(struct clk_init_data){ 548 .name = "blsp2_qup2_i2c_apps_clk_src", 549 .parent_data = gcc_xo_gpll0, 550 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 551 .ops = &clk_rcg2_ops, 552 }, 553 }; 554 555 static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = { 556 .cmd_rcgr = 0x0a0c, 557 .mnd_width = 8, 558 .hid_width = 5, 559 .parent_map = gcc_xo_gpll0_map, 560 .freq_tbl = ftbl_blsp2_qup1_2_spi_apps_clk_src, 561 .clkr.hw.init = &(struct clk_init_data){ 562 .name = "blsp2_qup2_spi_apps_clk_src", 563 .parent_data = gcc_xo_gpll0, 564 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 565 .ops = &clk_rcg2_ops, 566 }, 567 }; 568 569 static struct freq_tbl ftbl_blsp2_qup3_4_spi_apps_clk_src[] = { 570 F(960000, P_XO, 10, 1, 2), 571 F(4800000, P_XO, 4, 0, 0), 572 F(9600000, P_XO, 2, 0, 0), 573 F(15000000, P_GPLL0, 10, 1, 4), 574 F(19200000, P_XO, 1, 0, 0), 575 F(24000000, P_GPLL0, 12.5, 1, 2), 576 F(25000000, P_GPLL0, 12, 1, 2), 577 F(42860000, P_GPLL0, 14, 0, 0), 578 F(48000000, P_GPLL0, 12.5, 0, 0), 579 { } 580 }; 581 582 static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = { 583 .cmd_rcgr = 0x0aa0, 584 .hid_width = 5, 585 .parent_map = gcc_xo_gpll0_map, 586 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 587 .clkr.hw.init = &(struct clk_init_data){ 588 .name = "blsp2_qup3_i2c_apps_clk_src", 589 .parent_data = gcc_xo_gpll0, 590 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 591 .ops = &clk_rcg2_ops, 592 }, 593 }; 594 595 static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = { 596 .cmd_rcgr = 0x0a8c, 597 .mnd_width = 8, 598 .hid_width = 5, 599 .parent_map = gcc_xo_gpll0_map, 600 .freq_tbl = ftbl_blsp2_qup3_4_spi_apps_clk_src, 601 .clkr.hw.init = &(struct clk_init_data){ 602 .name = "blsp2_qup3_spi_apps_clk_src", 603 .parent_data = gcc_xo_gpll0, 604 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 605 .ops = &clk_rcg2_ops, 606 }, 607 }; 608 609 static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = { 610 .cmd_rcgr = 0x0b20, 611 .hid_width = 5, 612 .parent_map = gcc_xo_gpll0_map, 613 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 614 .clkr.hw.init = &(struct clk_init_data){ 615 .name = "blsp2_qup4_i2c_apps_clk_src", 616 .parent_data = gcc_xo_gpll0, 617 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 618 .ops = &clk_rcg2_ops, 619 }, 620 }; 621 622 static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = { 623 .cmd_rcgr = 0x0b0c, 624 .mnd_width = 8, 625 .hid_width = 5, 626 .parent_map = gcc_xo_gpll0_map, 627 .freq_tbl = ftbl_blsp2_qup3_4_spi_apps_clk_src, 628 .clkr.hw.init = &(struct clk_init_data){ 629 .name = "blsp2_qup4_spi_apps_clk_src", 630 .parent_data = gcc_xo_gpll0, 631 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 632 .ops = &clk_rcg2_ops, 633 }, 634 }; 635 636 static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = { 637 .cmd_rcgr = 0x0ba0, 638 .hid_width = 5, 639 .parent_map = gcc_xo_gpll0_map, 640 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 641 .clkr.hw.init = &(struct clk_init_data){ 642 .name = "blsp2_qup5_i2c_apps_clk_src", 643 .parent_data = gcc_xo_gpll0, 644 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 645 .ops = &clk_rcg2_ops, 646 }, 647 }; 648 649 static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = { 650 .cmd_rcgr = 0x0b8c, 651 .mnd_width = 8, 652 .hid_width = 5, 653 .parent_map = gcc_xo_gpll0_map, 654 /* BLSP1 QUP1 and BLSP2 QUP5 use the same freqs */ 655 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 656 .clkr.hw.init = &(struct clk_init_data){ 657 .name = "blsp2_qup5_spi_apps_clk_src", 658 .parent_data = gcc_xo_gpll0, 659 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 660 .ops = &clk_rcg2_ops, 661 }, 662 }; 663 664 static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = { 665 .cmd_rcgr = 0x0c20, 666 .hid_width = 5, 667 .parent_map = gcc_xo_gpll0_map, 668 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 669 .clkr.hw.init = &(struct clk_init_data){ 670 .name = "blsp2_qup6_i2c_apps_clk_src", 671 .parent_data = gcc_xo_gpll0, 672 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 673 .ops = &clk_rcg2_ops, 674 }, 675 }; 676 677 static struct freq_tbl ftbl_blsp2_qup6_spi_apps_clk_src[] = { 678 F(960000, P_XO, 10, 1, 2), 679 F(4800000, P_XO, 4, 0, 0), 680 F(9600000, P_XO, 2, 0, 0), 681 F(15000000, P_GPLL0, 10, 1, 4), 682 F(19200000, P_XO, 1, 0, 0), 683 F(24000000, P_GPLL0, 12.5, 1, 2), 684 F(25000000, P_GPLL0, 12, 1, 2), 685 F(44440000, P_GPLL0, 13.5, 0, 0), 686 F(48000000, P_GPLL0, 12.5, 0, 0), 687 { } 688 }; 689 690 static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = { 691 .cmd_rcgr = 0x0c0c, 692 .mnd_width = 8, 693 .hid_width = 5, 694 .parent_map = gcc_xo_gpll0_map, 695 .freq_tbl = ftbl_blsp2_qup6_spi_apps_clk_src, 696 .clkr.hw.init = &(struct clk_init_data){ 697 .name = "blsp2_qup6_spi_apps_clk_src", 698 .parent_data = gcc_xo_gpll0, 699 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 700 .ops = &clk_rcg2_ops, 701 }, 702 }; 703 704 static struct clk_rcg2 blsp2_uart1_apps_clk_src = { 705 .cmd_rcgr = 0x09cc, 706 .mnd_width = 16, 707 .hid_width = 5, 708 .parent_map = gcc_xo_gpll0_map, 709 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 710 .clkr.hw.init = &(struct clk_init_data){ 711 .name = "blsp2_uart1_apps_clk_src", 712 .parent_data = gcc_xo_gpll0, 713 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 714 .ops = &clk_rcg2_ops, 715 }, 716 }; 717 718 static struct clk_rcg2 blsp2_uart2_apps_clk_src = { 719 .cmd_rcgr = 0x0a4c, 720 .mnd_width = 16, 721 .hid_width = 5, 722 .parent_map = gcc_xo_gpll0_map, 723 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 724 .clkr.hw.init = &(struct clk_init_data){ 725 .name = "blsp2_uart2_apps_clk_src", 726 .parent_data = gcc_xo_gpll0, 727 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 728 .ops = &clk_rcg2_ops, 729 }, 730 }; 731 732 static struct clk_rcg2 blsp2_uart3_apps_clk_src = { 733 .cmd_rcgr = 0x0acc, 734 .mnd_width = 16, 735 .hid_width = 5, 736 .parent_map = gcc_xo_gpll0_map, 737 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 738 .clkr.hw.init = &(struct clk_init_data){ 739 .name = "blsp2_uart3_apps_clk_src", 740 .parent_data = gcc_xo_gpll0, 741 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 742 .ops = &clk_rcg2_ops, 743 }, 744 }; 745 746 static struct clk_rcg2 blsp2_uart4_apps_clk_src = { 747 .cmd_rcgr = 0x0b4c, 748 .mnd_width = 16, 749 .hid_width = 5, 750 .parent_map = gcc_xo_gpll0_map, 751 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 752 .clkr.hw.init = &(struct clk_init_data){ 753 .name = "blsp2_uart4_apps_clk_src", 754 .parent_data = gcc_xo_gpll0, 755 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 756 .ops = &clk_rcg2_ops, 757 }, 758 }; 759 760 static struct clk_rcg2 blsp2_uart5_apps_clk_src = { 761 .cmd_rcgr = 0x0bcc, 762 .mnd_width = 16, 763 .hid_width = 5, 764 .parent_map = gcc_xo_gpll0_map, 765 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 766 .clkr.hw.init = &(struct clk_init_data){ 767 .name = "blsp2_uart5_apps_clk_src", 768 .parent_data = gcc_xo_gpll0, 769 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 770 .ops = &clk_rcg2_ops, 771 }, 772 }; 773 774 static struct clk_rcg2 blsp2_uart6_apps_clk_src = { 775 .cmd_rcgr = 0x0c4c, 776 .mnd_width = 16, 777 .hid_width = 5, 778 .parent_map = gcc_xo_gpll0_map, 779 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 780 .clkr.hw.init = &(struct clk_init_data){ 781 .name = "blsp2_uart6_apps_clk_src", 782 .parent_data = gcc_xo_gpll0, 783 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 784 .ops = &clk_rcg2_ops, 785 }, 786 }; 787 788 static struct freq_tbl ftbl_gp1_clk_src[] = { 789 F(19200000, P_XO, 1, 0, 0), 790 F(100000000, P_GPLL0, 6, 0, 0), 791 F(200000000, P_GPLL0, 3, 0, 0), 792 { } 793 }; 794 795 static struct clk_rcg2 gp1_clk_src = { 796 .cmd_rcgr = 0x1904, 797 .mnd_width = 8, 798 .hid_width = 5, 799 .parent_map = gcc_xo_gpll0_map, 800 .freq_tbl = ftbl_gp1_clk_src, 801 .clkr.hw.init = &(struct clk_init_data){ 802 .name = "gp1_clk_src", 803 .parent_data = gcc_xo_gpll0, 804 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 805 .ops = &clk_rcg2_ops, 806 }, 807 }; 808 809 static struct freq_tbl ftbl_gp2_clk_src[] = { 810 F(19200000, P_XO, 1, 0, 0), 811 F(100000000, P_GPLL0, 6, 0, 0), 812 F(200000000, P_GPLL0, 3, 0, 0), 813 { } 814 }; 815 816 static struct clk_rcg2 gp2_clk_src = { 817 .cmd_rcgr = 0x1944, 818 .mnd_width = 8, 819 .hid_width = 5, 820 .parent_map = gcc_xo_gpll0_map, 821 .freq_tbl = ftbl_gp2_clk_src, 822 .clkr.hw.init = &(struct clk_init_data){ 823 .name = "gp2_clk_src", 824 .parent_data = gcc_xo_gpll0, 825 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 826 .ops = &clk_rcg2_ops, 827 }, 828 }; 829 830 static struct freq_tbl ftbl_gp3_clk_src[] = { 831 F(19200000, P_XO, 1, 0, 0), 832 F(100000000, P_GPLL0, 6, 0, 0), 833 F(200000000, P_GPLL0, 3, 0, 0), 834 { } 835 }; 836 837 static struct clk_rcg2 gp3_clk_src = { 838 .cmd_rcgr = 0x1984, 839 .mnd_width = 8, 840 .hid_width = 5, 841 .parent_map = gcc_xo_gpll0_map, 842 .freq_tbl = ftbl_gp3_clk_src, 843 .clkr.hw.init = &(struct clk_init_data){ 844 .name = "gp3_clk_src", 845 .parent_data = gcc_xo_gpll0, 846 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 847 .ops = &clk_rcg2_ops, 848 }, 849 }; 850 851 static struct freq_tbl ftbl_pcie_0_aux_clk_src[] = { 852 F(1011000, P_XO, 1, 1, 19), 853 { } 854 }; 855 856 static struct clk_rcg2 pcie_0_aux_clk_src = { 857 .cmd_rcgr = 0x1b00, 858 .mnd_width = 8, 859 .hid_width = 5, 860 .freq_tbl = ftbl_pcie_0_aux_clk_src, 861 .clkr.hw.init = &(struct clk_init_data){ 862 .name = "pcie_0_aux_clk_src", 863 .parent_data = &(const struct clk_parent_data){ 864 .fw_name = "xo", 865 }, 866 .num_parents = 1, 867 .ops = &clk_rcg2_ops, 868 }, 869 }; 870 871 static struct freq_tbl ftbl_pcie_pipe_clk_src[] = { 872 F(125000000, P_XO, 1, 0, 0), 873 { } 874 }; 875 876 static struct clk_rcg2 pcie_0_pipe_clk_src = { 877 .cmd_rcgr = 0x1adc, 878 .hid_width = 5, 879 .freq_tbl = ftbl_pcie_pipe_clk_src, 880 .clkr.hw.init = &(struct clk_init_data){ 881 .name = "pcie_0_pipe_clk_src", 882 .parent_data = &(const struct clk_parent_data){ 883 .fw_name = "xo", 884 }, 885 .num_parents = 1, 886 .ops = &clk_rcg2_ops, 887 }, 888 }; 889 890 static struct freq_tbl ftbl_pcie_1_aux_clk_src[] = { 891 F(1011000, P_XO, 1, 1, 19), 892 { } 893 }; 894 895 static struct clk_rcg2 pcie_1_aux_clk_src = { 896 .cmd_rcgr = 0x1b80, 897 .mnd_width = 8, 898 .hid_width = 5, 899 .freq_tbl = ftbl_pcie_1_aux_clk_src, 900 .clkr.hw.init = &(struct clk_init_data){ 901 .name = "pcie_1_aux_clk_src", 902 .parent_data = &(const struct clk_parent_data){ 903 .fw_name = "xo", 904 }, 905 .num_parents = 1, 906 .ops = &clk_rcg2_ops, 907 }, 908 }; 909 910 static struct clk_rcg2 pcie_1_pipe_clk_src = { 911 .cmd_rcgr = 0x1b5c, 912 .hid_width = 5, 913 .freq_tbl = ftbl_pcie_pipe_clk_src, 914 .clkr.hw.init = &(struct clk_init_data){ 915 .name = "pcie_1_pipe_clk_src", 916 .parent_data = &(const struct clk_parent_data){ 917 .fw_name = "xo", 918 }, 919 .num_parents = 1, 920 .ops = &clk_rcg2_ops, 921 }, 922 }; 923 924 static struct freq_tbl ftbl_pdm2_clk_src[] = { 925 F(60000000, P_GPLL0, 10, 0, 0), 926 { } 927 }; 928 929 static struct clk_rcg2 pdm2_clk_src = { 930 .cmd_rcgr = 0x0cd0, 931 .hid_width = 5, 932 .parent_map = gcc_xo_gpll0_map, 933 .freq_tbl = ftbl_pdm2_clk_src, 934 .clkr.hw.init = &(struct clk_init_data){ 935 .name = "pdm2_clk_src", 936 .parent_data = gcc_xo_gpll0, 937 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 938 .ops = &clk_rcg2_ops, 939 }, 940 }; 941 942 static struct freq_tbl ftbl_sdcc1_apps_clk_src[] = { 943 F(144000, P_XO, 16, 3, 25), 944 F(400000, P_XO, 12, 1, 4), 945 F(20000000, P_GPLL0, 15, 1, 2), 946 F(25000000, P_GPLL0, 12, 1, 2), 947 F(50000000, P_GPLL0, 12, 0, 0), 948 F(100000000, P_GPLL0, 6, 0, 0), 949 F(192000000, P_GPLL4, 2, 0, 0), 950 F(384000000, P_GPLL4, 1, 0, 0), 951 { } 952 }; 953 954 static struct freq_tbl ftbl_sdcc1_apps_clk_src_8992[] = { 955 F(144000, P_XO, 16, 3, 25), 956 F(400000, P_XO, 12, 1, 4), 957 F(20000000, P_GPLL0, 15, 1, 2), 958 F(25000000, P_GPLL0, 12, 1, 2), 959 F(50000000, P_GPLL0, 12, 0, 0), 960 F(100000000, P_GPLL0, 6, 0, 0), 961 F(172000000, P_GPLL4, 2, 0, 0), 962 F(344000000, P_GPLL4, 1, 0, 0), 963 { } 964 }; 965 966 static struct clk_rcg2 sdcc1_apps_clk_src = { 967 .cmd_rcgr = 0x04d0, 968 .mnd_width = 8, 969 .hid_width = 5, 970 .parent_map = gcc_xo_gpll0_gpll4_map, 971 .freq_tbl = ftbl_sdcc1_apps_clk_src, 972 .clkr.hw.init = &(struct clk_init_data){ 973 .name = "sdcc1_apps_clk_src", 974 .parent_data = gcc_xo_gpll0_gpll4, 975 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4), 976 .ops = &clk_rcg2_floor_ops, 977 }, 978 }; 979 980 static struct freq_tbl ftbl_sdcc2_4_apps_clk_src[] = { 981 F(144000, P_XO, 16, 3, 25), 982 F(400000, P_XO, 12, 1, 4), 983 F(20000000, P_GPLL0, 15, 1, 2), 984 F(25000000, P_GPLL0, 12, 1, 2), 985 F(50000000, P_GPLL0, 12, 0, 0), 986 F(100000000, P_GPLL0, 6, 0, 0), 987 F(200000000, P_GPLL0, 3, 0, 0), 988 { } 989 }; 990 991 static struct clk_rcg2 sdcc2_apps_clk_src = { 992 .cmd_rcgr = 0x0510, 993 .mnd_width = 8, 994 .hid_width = 5, 995 .parent_map = gcc_xo_gpll0_map, 996 .freq_tbl = ftbl_sdcc2_4_apps_clk_src, 997 .clkr.hw.init = &(struct clk_init_data){ 998 .name = "sdcc2_apps_clk_src", 999 .parent_data = gcc_xo_gpll0, 1000 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1001 .ops = &clk_rcg2_floor_ops, 1002 }, 1003 }; 1004 1005 static struct clk_rcg2 sdcc3_apps_clk_src = { 1006 .cmd_rcgr = 0x0550, 1007 .mnd_width = 8, 1008 .hid_width = 5, 1009 .parent_map = gcc_xo_gpll0_map, 1010 .freq_tbl = ftbl_sdcc2_4_apps_clk_src, 1011 .clkr.hw.init = &(struct clk_init_data){ 1012 .name = "sdcc3_apps_clk_src", 1013 .parent_data = gcc_xo_gpll0, 1014 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1015 .ops = &clk_rcg2_floor_ops, 1016 }, 1017 }; 1018 1019 static struct clk_rcg2 sdcc4_apps_clk_src = { 1020 .cmd_rcgr = 0x0590, 1021 .mnd_width = 8, 1022 .hid_width = 5, 1023 .parent_map = gcc_xo_gpll0_map, 1024 .freq_tbl = ftbl_sdcc2_4_apps_clk_src, 1025 .clkr.hw.init = &(struct clk_init_data){ 1026 .name = "sdcc4_apps_clk_src", 1027 .parent_data = gcc_xo_gpll0, 1028 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1029 .ops = &clk_rcg2_floor_ops, 1030 }, 1031 }; 1032 1033 static struct freq_tbl ftbl_tsif_ref_clk_src[] = { 1034 F(105500, P_XO, 1, 1, 182), 1035 { } 1036 }; 1037 1038 static struct clk_rcg2 tsif_ref_clk_src = { 1039 .cmd_rcgr = 0x0d90, 1040 .mnd_width = 8, 1041 .hid_width = 5, 1042 .freq_tbl = ftbl_tsif_ref_clk_src, 1043 .clkr.hw.init = &(struct clk_init_data){ 1044 .name = "tsif_ref_clk_src", 1045 .parent_data = &(const struct clk_parent_data){ 1046 .fw_name = "xo", 1047 }, 1048 .num_parents = 1, 1049 .ops = &clk_rcg2_ops, 1050 }, 1051 }; 1052 1053 static struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = { 1054 F(19200000, P_XO, 1, 0, 0), 1055 F(60000000, P_GPLL0, 10, 0, 0), 1056 { } 1057 }; 1058 1059 static struct clk_rcg2 usb30_mock_utmi_clk_src = { 1060 .cmd_rcgr = 0x03e8, 1061 .hid_width = 5, 1062 .parent_map = gcc_xo_gpll0_map, 1063 .freq_tbl = ftbl_usb30_mock_utmi_clk_src, 1064 .clkr.hw.init = &(struct clk_init_data){ 1065 .name = "usb30_mock_utmi_clk_src", 1066 .parent_data = gcc_xo_gpll0, 1067 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1068 .ops = &clk_rcg2_ops, 1069 }, 1070 }; 1071 1072 static struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = { 1073 F(1200000, P_XO, 16, 0, 0), 1074 { } 1075 }; 1076 1077 static struct clk_rcg2 usb3_phy_aux_clk_src = { 1078 .cmd_rcgr = 0x1414, 1079 .hid_width = 5, 1080 .freq_tbl = ftbl_usb3_phy_aux_clk_src, 1081 .clkr.hw.init = &(struct clk_init_data){ 1082 .name = "usb3_phy_aux_clk_src", 1083 .parent_data = &(const struct clk_parent_data){ 1084 .fw_name = "xo", 1085 }, 1086 .num_parents = 1, 1087 .ops = &clk_rcg2_ops, 1088 }, 1089 }; 1090 1091 static struct freq_tbl ftbl_usb_hs_system_clk_src[] = { 1092 F(75000000, P_GPLL0, 8, 0, 0), 1093 { } 1094 }; 1095 1096 static struct clk_rcg2 usb_hs_system_clk_src = { 1097 .cmd_rcgr = 0x0490, 1098 .hid_width = 5, 1099 .parent_map = gcc_xo_gpll0_map, 1100 .freq_tbl = ftbl_usb_hs_system_clk_src, 1101 .clkr.hw.init = &(struct clk_init_data){ 1102 .name = "usb_hs_system_clk_src", 1103 .parent_data = gcc_xo_gpll0, 1104 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1105 .ops = &clk_rcg2_ops, 1106 }, 1107 }; 1108 1109 static struct clk_branch gcc_blsp1_ahb_clk = { 1110 .halt_reg = 0x05c4, 1111 .halt_check = BRANCH_HALT_VOTED, 1112 .clkr = { 1113 .enable_reg = 0x1484, 1114 .enable_mask = BIT(17), 1115 .hw.init = &(struct clk_init_data){ 1116 .name = "gcc_blsp1_ahb_clk", 1117 .ops = &clk_branch2_ops, 1118 }, 1119 }, 1120 }; 1121 1122 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { 1123 .halt_reg = 0x0648, 1124 .clkr = { 1125 .enable_reg = 0x0648, 1126 .enable_mask = BIT(0), 1127 .hw.init = &(struct clk_init_data){ 1128 .name = "gcc_blsp1_qup1_i2c_apps_clk", 1129 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup1_i2c_apps_clk_src.clkr.hw }, 1130 .num_parents = 1, 1131 .flags = CLK_SET_RATE_PARENT, 1132 .ops = &clk_branch2_ops, 1133 }, 1134 }, 1135 }; 1136 1137 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { 1138 .halt_reg = 0x0644, 1139 .clkr = { 1140 .enable_reg = 0x0644, 1141 .enable_mask = BIT(0), 1142 .hw.init = &(struct clk_init_data){ 1143 .name = "gcc_blsp1_qup1_spi_apps_clk", 1144 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup1_spi_apps_clk_src.clkr.hw }, 1145 .num_parents = 1, 1146 .flags = CLK_SET_RATE_PARENT, 1147 .ops = &clk_branch2_ops, 1148 }, 1149 }, 1150 }; 1151 1152 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { 1153 .halt_reg = 0x06c8, 1154 .clkr = { 1155 .enable_reg = 0x06c8, 1156 .enable_mask = BIT(0), 1157 .hw.init = &(struct clk_init_data){ 1158 .name = "gcc_blsp1_qup2_i2c_apps_clk", 1159 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup2_i2c_apps_clk_src.clkr.hw }, 1160 .num_parents = 1, 1161 .flags = CLK_SET_RATE_PARENT, 1162 .ops = &clk_branch2_ops, 1163 }, 1164 }, 1165 }; 1166 1167 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { 1168 .halt_reg = 0x06c4, 1169 .clkr = { 1170 .enable_reg = 0x06c4, 1171 .enable_mask = BIT(0), 1172 .hw.init = &(struct clk_init_data){ 1173 .name = "gcc_blsp1_qup2_spi_apps_clk", 1174 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup2_spi_apps_clk_src.clkr.hw }, 1175 .num_parents = 1, 1176 .flags = CLK_SET_RATE_PARENT, 1177 .ops = &clk_branch2_ops, 1178 }, 1179 }, 1180 }; 1181 1182 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = { 1183 .halt_reg = 0x0748, 1184 .clkr = { 1185 .enable_reg = 0x0748, 1186 .enable_mask = BIT(0), 1187 .hw.init = &(struct clk_init_data){ 1188 .name = "gcc_blsp1_qup3_i2c_apps_clk", 1189 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup3_i2c_apps_clk_src.clkr.hw }, 1190 .num_parents = 1, 1191 .flags = CLK_SET_RATE_PARENT, 1192 .ops = &clk_branch2_ops, 1193 }, 1194 }, 1195 }; 1196 1197 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = { 1198 .halt_reg = 0x0744, 1199 .clkr = { 1200 .enable_reg = 0x0744, 1201 .enable_mask = BIT(0), 1202 .hw.init = &(struct clk_init_data){ 1203 .name = "gcc_blsp1_qup3_spi_apps_clk", 1204 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup3_spi_apps_clk_src.clkr.hw }, 1205 .num_parents = 1, 1206 .flags = CLK_SET_RATE_PARENT, 1207 .ops = &clk_branch2_ops, 1208 }, 1209 }, 1210 }; 1211 1212 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = { 1213 .halt_reg = 0x07c8, 1214 .clkr = { 1215 .enable_reg = 0x07c8, 1216 .enable_mask = BIT(0), 1217 .hw.init = &(struct clk_init_data){ 1218 .name = "gcc_blsp1_qup4_i2c_apps_clk", 1219 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup4_i2c_apps_clk_src.clkr.hw }, 1220 .num_parents = 1, 1221 .flags = CLK_SET_RATE_PARENT, 1222 .ops = &clk_branch2_ops, 1223 }, 1224 }, 1225 }; 1226 1227 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = { 1228 .halt_reg = 0x07c4, 1229 .clkr = { 1230 .enable_reg = 0x07c4, 1231 .enable_mask = BIT(0), 1232 .hw.init = &(struct clk_init_data){ 1233 .name = "gcc_blsp1_qup4_spi_apps_clk", 1234 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup4_spi_apps_clk_src.clkr.hw }, 1235 .num_parents = 1, 1236 .flags = CLK_SET_RATE_PARENT, 1237 .ops = &clk_branch2_ops, 1238 }, 1239 }, 1240 }; 1241 1242 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = { 1243 .halt_reg = 0x0848, 1244 .clkr = { 1245 .enable_reg = 0x0848, 1246 .enable_mask = BIT(0), 1247 .hw.init = &(struct clk_init_data){ 1248 .name = "gcc_blsp1_qup5_i2c_apps_clk", 1249 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup5_i2c_apps_clk_src.clkr.hw }, 1250 .num_parents = 1, 1251 .flags = CLK_SET_RATE_PARENT, 1252 .ops = &clk_branch2_ops, 1253 }, 1254 }, 1255 }; 1256 1257 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = { 1258 .halt_reg = 0x0844, 1259 .clkr = { 1260 .enable_reg = 0x0844, 1261 .enable_mask = BIT(0), 1262 .hw.init = &(struct clk_init_data){ 1263 .name = "gcc_blsp1_qup5_spi_apps_clk", 1264 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup5_spi_apps_clk_src.clkr.hw }, 1265 .num_parents = 1, 1266 .flags = CLK_SET_RATE_PARENT, 1267 .ops = &clk_branch2_ops, 1268 }, 1269 }, 1270 }; 1271 1272 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = { 1273 .halt_reg = 0x08c8, 1274 .clkr = { 1275 .enable_reg = 0x08c8, 1276 .enable_mask = BIT(0), 1277 .hw.init = &(struct clk_init_data){ 1278 .name = "gcc_blsp1_qup6_i2c_apps_clk", 1279 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup6_i2c_apps_clk_src.clkr.hw }, 1280 .num_parents = 1, 1281 .flags = CLK_SET_RATE_PARENT, 1282 .ops = &clk_branch2_ops, 1283 }, 1284 }, 1285 }; 1286 1287 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = { 1288 .halt_reg = 0x08c4, 1289 .clkr = { 1290 .enable_reg = 0x08c4, 1291 .enable_mask = BIT(0), 1292 .hw.init = &(struct clk_init_data){ 1293 .name = "gcc_blsp1_qup6_spi_apps_clk", 1294 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup6_spi_apps_clk_src.clkr.hw }, 1295 .num_parents = 1, 1296 .flags = CLK_SET_RATE_PARENT, 1297 .ops = &clk_branch2_ops, 1298 }, 1299 }, 1300 }; 1301 1302 static struct clk_branch gcc_blsp1_uart1_apps_clk = { 1303 .halt_reg = 0x0684, 1304 .clkr = { 1305 .enable_reg = 0x0684, 1306 .enable_mask = BIT(0), 1307 .hw.init = &(struct clk_init_data){ 1308 .name = "gcc_blsp1_uart1_apps_clk", 1309 .parent_hws = (const struct clk_hw *[]){ &blsp1_uart1_apps_clk_src.clkr.hw }, 1310 .num_parents = 1, 1311 .flags = CLK_SET_RATE_PARENT, 1312 .ops = &clk_branch2_ops, 1313 }, 1314 }, 1315 }; 1316 1317 static struct clk_branch gcc_blsp1_uart2_apps_clk = { 1318 .halt_reg = 0x0704, 1319 .clkr = { 1320 .enable_reg = 0x0704, 1321 .enable_mask = BIT(0), 1322 .hw.init = &(struct clk_init_data){ 1323 .name = "gcc_blsp1_uart2_apps_clk", 1324 .parent_hws = (const struct clk_hw *[]){ &blsp1_uart2_apps_clk_src.clkr.hw }, 1325 .num_parents = 1, 1326 .flags = CLK_SET_RATE_PARENT, 1327 .ops = &clk_branch2_ops, 1328 }, 1329 }, 1330 }; 1331 1332 static struct clk_branch gcc_blsp1_uart3_apps_clk = { 1333 .halt_reg = 0x0784, 1334 .clkr = { 1335 .enable_reg = 0x0784, 1336 .enable_mask = BIT(0), 1337 .hw.init = &(struct clk_init_data){ 1338 .name = "gcc_blsp1_uart3_apps_clk", 1339 .parent_hws = (const struct clk_hw *[]){ &blsp1_uart3_apps_clk_src.clkr.hw }, 1340 .num_parents = 1, 1341 .flags = CLK_SET_RATE_PARENT, 1342 .ops = &clk_branch2_ops, 1343 }, 1344 }, 1345 }; 1346 1347 static struct clk_branch gcc_blsp1_uart4_apps_clk = { 1348 .halt_reg = 0x0804, 1349 .clkr = { 1350 .enable_reg = 0x0804, 1351 .enable_mask = BIT(0), 1352 .hw.init = &(struct clk_init_data){ 1353 .name = "gcc_blsp1_uart4_apps_clk", 1354 .parent_hws = (const struct clk_hw *[]){ &blsp1_uart4_apps_clk_src.clkr.hw }, 1355 .num_parents = 1, 1356 .flags = CLK_SET_RATE_PARENT, 1357 .ops = &clk_branch2_ops, 1358 }, 1359 }, 1360 }; 1361 1362 static struct clk_branch gcc_blsp1_uart5_apps_clk = { 1363 .halt_reg = 0x0884, 1364 .clkr = { 1365 .enable_reg = 0x0884, 1366 .enable_mask = BIT(0), 1367 .hw.init = &(struct clk_init_data){ 1368 .name = "gcc_blsp1_uart5_apps_clk", 1369 .parent_hws = (const struct clk_hw *[]){ &blsp1_uart5_apps_clk_src.clkr.hw }, 1370 .num_parents = 1, 1371 .flags = CLK_SET_RATE_PARENT, 1372 .ops = &clk_branch2_ops, 1373 }, 1374 }, 1375 }; 1376 1377 static struct clk_branch gcc_blsp1_uart6_apps_clk = { 1378 .halt_reg = 0x0904, 1379 .clkr = { 1380 .enable_reg = 0x0904, 1381 .enable_mask = BIT(0), 1382 .hw.init = &(struct clk_init_data){ 1383 .name = "gcc_blsp1_uart6_apps_clk", 1384 .parent_hws = (const struct clk_hw *[]){ &blsp1_uart6_apps_clk_src.clkr.hw }, 1385 .num_parents = 1, 1386 .flags = CLK_SET_RATE_PARENT, 1387 .ops = &clk_branch2_ops, 1388 }, 1389 }, 1390 }; 1391 1392 static struct clk_branch gcc_blsp2_ahb_clk = { 1393 .halt_reg = 0x0944, 1394 .halt_check = BRANCH_HALT_VOTED, 1395 .clkr = { 1396 .enable_reg = 0x1484, 1397 .enable_mask = BIT(15), 1398 .hw.init = &(struct clk_init_data){ 1399 .name = "gcc_blsp2_ahb_clk", 1400 .ops = &clk_branch2_ops, 1401 }, 1402 }, 1403 }; 1404 1405 static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = { 1406 .halt_reg = 0x0988, 1407 .clkr = { 1408 .enable_reg = 0x0988, 1409 .enable_mask = BIT(0), 1410 .hw.init = &(struct clk_init_data){ 1411 .name = "gcc_blsp2_qup1_i2c_apps_clk", 1412 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup1_i2c_apps_clk_src.clkr.hw }, 1413 .num_parents = 1, 1414 .flags = CLK_SET_RATE_PARENT, 1415 .ops = &clk_branch2_ops, 1416 }, 1417 }, 1418 }; 1419 1420 static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = { 1421 .halt_reg = 0x0984, 1422 .clkr = { 1423 .enable_reg = 0x0984, 1424 .enable_mask = BIT(0), 1425 .hw.init = &(struct clk_init_data){ 1426 .name = "gcc_blsp2_qup1_spi_apps_clk", 1427 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup1_spi_apps_clk_src.clkr.hw }, 1428 .num_parents = 1, 1429 .flags = CLK_SET_RATE_PARENT, 1430 .ops = &clk_branch2_ops, 1431 }, 1432 }, 1433 }; 1434 1435 static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = { 1436 .halt_reg = 0x0a08, 1437 .clkr = { 1438 .enable_reg = 0x0a08, 1439 .enable_mask = BIT(0), 1440 .hw.init = &(struct clk_init_data){ 1441 .name = "gcc_blsp2_qup2_i2c_apps_clk", 1442 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup2_i2c_apps_clk_src.clkr.hw }, 1443 .num_parents = 1, 1444 .flags = CLK_SET_RATE_PARENT, 1445 .ops = &clk_branch2_ops, 1446 }, 1447 }, 1448 }; 1449 1450 static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = { 1451 .halt_reg = 0x0a04, 1452 .clkr = { 1453 .enable_reg = 0x0a04, 1454 .enable_mask = BIT(0), 1455 .hw.init = &(struct clk_init_data){ 1456 .name = "gcc_blsp2_qup2_spi_apps_clk", 1457 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup2_spi_apps_clk_src.clkr.hw }, 1458 .num_parents = 1, 1459 .flags = CLK_SET_RATE_PARENT, 1460 .ops = &clk_branch2_ops, 1461 }, 1462 }, 1463 }; 1464 1465 static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = { 1466 .halt_reg = 0x0a88, 1467 .clkr = { 1468 .enable_reg = 0x0a88, 1469 .enable_mask = BIT(0), 1470 .hw.init = &(struct clk_init_data){ 1471 .name = "gcc_blsp2_qup3_i2c_apps_clk", 1472 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup3_i2c_apps_clk_src.clkr.hw }, 1473 .num_parents = 1, 1474 .flags = CLK_SET_RATE_PARENT, 1475 .ops = &clk_branch2_ops, 1476 }, 1477 }, 1478 }; 1479 1480 static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = { 1481 .halt_reg = 0x0a84, 1482 .clkr = { 1483 .enable_reg = 0x0a84, 1484 .enable_mask = BIT(0), 1485 .hw.init = &(struct clk_init_data){ 1486 .name = "gcc_blsp2_qup3_spi_apps_clk", 1487 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup3_spi_apps_clk_src.clkr.hw }, 1488 .num_parents = 1, 1489 .flags = CLK_SET_RATE_PARENT, 1490 .ops = &clk_branch2_ops, 1491 }, 1492 }, 1493 }; 1494 1495 static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = { 1496 .halt_reg = 0x0b08, 1497 .clkr = { 1498 .enable_reg = 0x0b08, 1499 .enable_mask = BIT(0), 1500 .hw.init = &(struct clk_init_data){ 1501 .name = "gcc_blsp2_qup4_i2c_apps_clk", 1502 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup4_i2c_apps_clk_src.clkr.hw }, 1503 .num_parents = 1, 1504 .flags = CLK_SET_RATE_PARENT, 1505 .ops = &clk_branch2_ops, 1506 }, 1507 }, 1508 }; 1509 1510 static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = { 1511 .halt_reg = 0x0b04, 1512 .clkr = { 1513 .enable_reg = 0x0b04, 1514 .enable_mask = BIT(0), 1515 .hw.init = &(struct clk_init_data){ 1516 .name = "gcc_blsp2_qup4_spi_apps_clk", 1517 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup4_spi_apps_clk_src.clkr.hw }, 1518 .num_parents = 1, 1519 .flags = CLK_SET_RATE_PARENT, 1520 .ops = &clk_branch2_ops, 1521 }, 1522 }, 1523 }; 1524 1525 static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = { 1526 .halt_reg = 0x0b88, 1527 .clkr = { 1528 .enable_reg = 0x0b88, 1529 .enable_mask = BIT(0), 1530 .hw.init = &(struct clk_init_data){ 1531 .name = "gcc_blsp2_qup5_i2c_apps_clk", 1532 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup5_i2c_apps_clk_src.clkr.hw }, 1533 .num_parents = 1, 1534 .flags = CLK_SET_RATE_PARENT, 1535 .ops = &clk_branch2_ops, 1536 }, 1537 }, 1538 }; 1539 1540 static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = { 1541 .halt_reg = 0x0b84, 1542 .clkr = { 1543 .enable_reg = 0x0b84, 1544 .enable_mask = BIT(0), 1545 .hw.init = &(struct clk_init_data){ 1546 .name = "gcc_blsp2_qup5_spi_apps_clk", 1547 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup5_spi_apps_clk_src.clkr.hw }, 1548 .num_parents = 1, 1549 .flags = CLK_SET_RATE_PARENT, 1550 .ops = &clk_branch2_ops, 1551 }, 1552 }, 1553 }; 1554 1555 static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = { 1556 .halt_reg = 0x0c08, 1557 .clkr = { 1558 .enable_reg = 0x0c08, 1559 .enable_mask = BIT(0), 1560 .hw.init = &(struct clk_init_data){ 1561 .name = "gcc_blsp2_qup6_i2c_apps_clk", 1562 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup6_i2c_apps_clk_src.clkr.hw }, 1563 .num_parents = 1, 1564 .flags = CLK_SET_RATE_PARENT, 1565 .ops = &clk_branch2_ops, 1566 }, 1567 }, 1568 }; 1569 1570 static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = { 1571 .halt_reg = 0x0c04, 1572 .clkr = { 1573 .enable_reg = 0x0c04, 1574 .enable_mask = BIT(0), 1575 .hw.init = &(struct clk_init_data){ 1576 .name = "gcc_blsp2_qup6_spi_apps_clk", 1577 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup6_spi_apps_clk_src.clkr.hw }, 1578 .num_parents = 1, 1579 .flags = CLK_SET_RATE_PARENT, 1580 .ops = &clk_branch2_ops, 1581 }, 1582 }, 1583 }; 1584 1585 static struct clk_branch gcc_blsp2_uart1_apps_clk = { 1586 .halt_reg = 0x09c4, 1587 .clkr = { 1588 .enable_reg = 0x09c4, 1589 .enable_mask = BIT(0), 1590 .hw.init = &(struct clk_init_data){ 1591 .name = "gcc_blsp2_uart1_apps_clk", 1592 .parent_hws = (const struct clk_hw *[]){ &blsp2_uart1_apps_clk_src.clkr.hw }, 1593 .num_parents = 1, 1594 .flags = CLK_SET_RATE_PARENT, 1595 .ops = &clk_branch2_ops, 1596 }, 1597 }, 1598 }; 1599 1600 static struct clk_branch gcc_blsp2_uart2_apps_clk = { 1601 .halt_reg = 0x0a44, 1602 .clkr = { 1603 .enable_reg = 0x0a44, 1604 .enable_mask = BIT(0), 1605 .hw.init = &(struct clk_init_data){ 1606 .name = "gcc_blsp2_uart2_apps_clk", 1607 .parent_hws = (const struct clk_hw *[]){ &blsp2_uart2_apps_clk_src.clkr.hw }, 1608 .num_parents = 1, 1609 .flags = CLK_SET_RATE_PARENT, 1610 .ops = &clk_branch2_ops, 1611 }, 1612 }, 1613 }; 1614 1615 static struct clk_branch gcc_blsp2_uart3_apps_clk = { 1616 .halt_reg = 0x0ac4, 1617 .clkr = { 1618 .enable_reg = 0x0ac4, 1619 .enable_mask = BIT(0), 1620 .hw.init = &(struct clk_init_data){ 1621 .name = "gcc_blsp2_uart3_apps_clk", 1622 .parent_hws = (const struct clk_hw *[]){ &blsp2_uart3_apps_clk_src.clkr.hw }, 1623 .num_parents = 1, 1624 .flags = CLK_SET_RATE_PARENT, 1625 .ops = &clk_branch2_ops, 1626 }, 1627 }, 1628 }; 1629 1630 static struct clk_branch gcc_blsp2_uart4_apps_clk = { 1631 .halt_reg = 0x0b44, 1632 .clkr = { 1633 .enable_reg = 0x0b44, 1634 .enable_mask = BIT(0), 1635 .hw.init = &(struct clk_init_data){ 1636 .name = "gcc_blsp2_uart4_apps_clk", 1637 .parent_hws = (const struct clk_hw *[]){ &blsp2_uart4_apps_clk_src.clkr.hw }, 1638 .num_parents = 1, 1639 .flags = CLK_SET_RATE_PARENT, 1640 .ops = &clk_branch2_ops, 1641 }, 1642 }, 1643 }; 1644 1645 static struct clk_branch gcc_blsp2_uart5_apps_clk = { 1646 .halt_reg = 0x0bc4, 1647 .clkr = { 1648 .enable_reg = 0x0bc4, 1649 .enable_mask = BIT(0), 1650 .hw.init = &(struct clk_init_data){ 1651 .name = "gcc_blsp2_uart5_apps_clk", 1652 .parent_hws = (const struct clk_hw *[]){ &blsp2_uart5_apps_clk_src.clkr.hw }, 1653 .num_parents = 1, 1654 .flags = CLK_SET_RATE_PARENT, 1655 .ops = &clk_branch2_ops, 1656 }, 1657 }, 1658 }; 1659 1660 static struct clk_branch gcc_blsp2_uart6_apps_clk = { 1661 .halt_reg = 0x0c44, 1662 .clkr = { 1663 .enable_reg = 0x0c44, 1664 .enable_mask = BIT(0), 1665 .hw.init = &(struct clk_init_data){ 1666 .name = "gcc_blsp2_uart6_apps_clk", 1667 .parent_hws = (const struct clk_hw *[]){ &blsp2_uart6_apps_clk_src.clkr.hw }, 1668 .num_parents = 1, 1669 .flags = CLK_SET_RATE_PARENT, 1670 .ops = &clk_branch2_ops, 1671 }, 1672 }, 1673 }; 1674 1675 static struct clk_branch gcc_gp1_clk = { 1676 .halt_reg = 0x1900, 1677 .clkr = { 1678 .enable_reg = 0x1900, 1679 .enable_mask = BIT(0), 1680 .hw.init = &(struct clk_init_data){ 1681 .name = "gcc_gp1_clk", 1682 .parent_hws = (const struct clk_hw *[]){ &gp1_clk_src.clkr.hw }, 1683 .num_parents = 1, 1684 .flags = CLK_SET_RATE_PARENT, 1685 .ops = &clk_branch2_ops, 1686 }, 1687 }, 1688 }; 1689 1690 static struct clk_branch gcc_gp2_clk = { 1691 .halt_reg = 0x1940, 1692 .clkr = { 1693 .enable_reg = 0x1940, 1694 .enable_mask = BIT(0), 1695 .hw.init = &(struct clk_init_data){ 1696 .name = "gcc_gp2_clk", 1697 .parent_hws = (const struct clk_hw *[]){ &gp2_clk_src.clkr.hw }, 1698 .num_parents = 1, 1699 .flags = CLK_SET_RATE_PARENT, 1700 .ops = &clk_branch2_ops, 1701 }, 1702 }, 1703 }; 1704 1705 static struct clk_branch gcc_gp3_clk = { 1706 .halt_reg = 0x1980, 1707 .clkr = { 1708 .enable_reg = 0x1980, 1709 .enable_mask = BIT(0), 1710 .hw.init = &(struct clk_init_data){ 1711 .name = "gcc_gp3_clk", 1712 .parent_hws = (const struct clk_hw *[]){ &gp3_clk_src.clkr.hw }, 1713 .num_parents = 1, 1714 .flags = CLK_SET_RATE_PARENT, 1715 .ops = &clk_branch2_ops, 1716 }, 1717 }, 1718 }; 1719 1720 static struct clk_branch gcc_lpass_q6_axi_clk = { 1721 .halt_reg = 0x0280, 1722 .clkr = { 1723 .enable_reg = 0x0280, 1724 .enable_mask = BIT(0), 1725 .hw.init = &(struct clk_init_data){ 1726 .name = "gcc_lpass_q6_axi_clk", 1727 .ops = &clk_branch2_ops, 1728 }, 1729 }, 1730 }; 1731 1732 static struct clk_branch gcc_mss_q6_bimc_axi_clk = { 1733 .halt_reg = 0x0284, 1734 .clkr = { 1735 .enable_reg = 0x0284, 1736 .enable_mask = BIT(0), 1737 .hw.init = &(struct clk_init_data){ 1738 .name = "gcc_mss_q6_bimc_axi_clk", 1739 .ops = &clk_branch2_ops, 1740 }, 1741 }, 1742 }; 1743 1744 static struct clk_branch gcc_pcie_0_aux_clk = { 1745 .halt_reg = 0x1ad4, 1746 .clkr = { 1747 .enable_reg = 0x1ad4, 1748 .enable_mask = BIT(0), 1749 .hw.init = &(struct clk_init_data){ 1750 .name = "gcc_pcie_0_aux_clk", 1751 .parent_hws = (const struct clk_hw *[]){ &pcie_0_aux_clk_src.clkr.hw }, 1752 .num_parents = 1, 1753 .flags = CLK_SET_RATE_PARENT, 1754 .ops = &clk_branch2_ops, 1755 }, 1756 }, 1757 }; 1758 1759 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { 1760 .halt_reg = 0x1ad0, 1761 .clkr = { 1762 .enable_reg = 0x1ad0, 1763 .enable_mask = BIT(0), 1764 .hw.init = &(struct clk_init_data){ 1765 .name = "gcc_pcie_0_cfg_ahb_clk", 1766 .ops = &clk_branch2_ops, 1767 }, 1768 }, 1769 }; 1770 1771 static struct clk_branch gcc_pcie_0_mstr_axi_clk = { 1772 .halt_reg = 0x1acc, 1773 .clkr = { 1774 .enable_reg = 0x1acc, 1775 .enable_mask = BIT(0), 1776 .hw.init = &(struct clk_init_data){ 1777 .name = "gcc_pcie_0_mstr_axi_clk", 1778 .ops = &clk_branch2_ops, 1779 }, 1780 }, 1781 }; 1782 1783 static struct clk_branch gcc_pcie_0_pipe_clk = { 1784 .halt_reg = 0x1ad8, 1785 .halt_check = BRANCH_HALT_DELAY, 1786 .clkr = { 1787 .enable_reg = 0x1ad8, 1788 .enable_mask = BIT(0), 1789 .hw.init = &(struct clk_init_data){ 1790 .name = "gcc_pcie_0_pipe_clk", 1791 .parent_hws = (const struct clk_hw *[]){ &pcie_0_pipe_clk_src.clkr.hw }, 1792 .num_parents = 1, 1793 .flags = CLK_SET_RATE_PARENT, 1794 .ops = &clk_branch2_ops, 1795 }, 1796 }, 1797 }; 1798 1799 static struct clk_branch gcc_pcie_0_slv_axi_clk = { 1800 .halt_reg = 0x1ac8, 1801 .halt_check = BRANCH_HALT_DELAY, 1802 .clkr = { 1803 .enable_reg = 0x1ac8, 1804 .enable_mask = BIT(0), 1805 .hw.init = &(struct clk_init_data){ 1806 .name = "gcc_pcie_0_slv_axi_clk", 1807 .ops = &clk_branch2_ops, 1808 }, 1809 }, 1810 }; 1811 1812 static struct clk_branch gcc_pcie_1_aux_clk = { 1813 .halt_reg = 0x1b54, 1814 .clkr = { 1815 .enable_reg = 0x1b54, 1816 .enable_mask = BIT(0), 1817 .hw.init = &(struct clk_init_data){ 1818 .name = "gcc_pcie_1_aux_clk", 1819 .parent_hws = (const struct clk_hw *[]){ &pcie_1_aux_clk_src.clkr.hw }, 1820 .num_parents = 1, 1821 .flags = CLK_SET_RATE_PARENT, 1822 .ops = &clk_branch2_ops, 1823 }, 1824 }, 1825 }; 1826 1827 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { 1828 .halt_reg = 0x1b54, 1829 .clkr = { 1830 .enable_reg = 0x1b54, 1831 .enable_mask = BIT(0), 1832 .hw.init = &(struct clk_init_data){ 1833 .name = "gcc_pcie_1_cfg_ahb_clk", 1834 .ops = &clk_branch2_ops, 1835 }, 1836 }, 1837 }; 1838 1839 static struct clk_branch gcc_pcie_1_mstr_axi_clk = { 1840 .halt_reg = 0x1b50, 1841 .clkr = { 1842 .enable_reg = 0x1b50, 1843 .enable_mask = BIT(0), 1844 .hw.init = &(struct clk_init_data){ 1845 .name = "gcc_pcie_1_mstr_axi_clk", 1846 .ops = &clk_branch2_ops, 1847 }, 1848 }, 1849 }; 1850 1851 static struct clk_branch gcc_pcie_1_pipe_clk = { 1852 .halt_reg = 0x1b58, 1853 .halt_check = BRANCH_HALT_DELAY, 1854 .clkr = { 1855 .enable_reg = 0x1b58, 1856 .enable_mask = BIT(0), 1857 .hw.init = &(struct clk_init_data){ 1858 .name = "gcc_pcie_1_pipe_clk", 1859 .parent_hws = (const struct clk_hw *[]){ &pcie_1_pipe_clk_src.clkr.hw }, 1860 .num_parents = 1, 1861 .flags = CLK_SET_RATE_PARENT, 1862 .ops = &clk_branch2_ops, 1863 }, 1864 }, 1865 }; 1866 1867 static struct clk_branch gcc_pcie_1_slv_axi_clk = { 1868 .halt_reg = 0x1b48, 1869 .clkr = { 1870 .enable_reg = 0x1b48, 1871 .enable_mask = BIT(0), 1872 .hw.init = &(struct clk_init_data){ 1873 .name = "gcc_pcie_1_slv_axi_clk", 1874 .ops = &clk_branch2_ops, 1875 }, 1876 }, 1877 }; 1878 1879 static struct clk_branch gcc_pdm2_clk = { 1880 .halt_reg = 0x0ccc, 1881 .clkr = { 1882 .enable_reg = 0x0ccc, 1883 .enable_mask = BIT(0), 1884 .hw.init = &(struct clk_init_data){ 1885 .name = "gcc_pdm2_clk", 1886 .parent_hws = (const struct clk_hw *[]){ &pdm2_clk_src.clkr.hw }, 1887 .num_parents = 1, 1888 .flags = CLK_SET_RATE_PARENT, 1889 .ops = &clk_branch2_ops, 1890 }, 1891 }, 1892 }; 1893 1894 static struct clk_branch gcc_pdm_ahb_clk = { 1895 .halt_reg = 0x0cc4, 1896 .clkr = { 1897 .enable_reg = 0x0cc4, 1898 .enable_mask = BIT(0), 1899 .hw.init = &(struct clk_init_data){ 1900 .name = "gcc_pdm_ahb_clk", 1901 .ops = &clk_branch2_ops, 1902 }, 1903 }, 1904 }; 1905 1906 static struct clk_branch gcc_sdcc1_apps_clk = { 1907 .halt_reg = 0x04c4, 1908 .clkr = { 1909 .enable_reg = 0x04c4, 1910 .enable_mask = BIT(0), 1911 .hw.init = &(struct clk_init_data){ 1912 .name = "gcc_sdcc1_apps_clk", 1913 .parent_hws = (const struct clk_hw *[]){ &sdcc1_apps_clk_src.clkr.hw }, 1914 .num_parents = 1, 1915 .flags = CLK_SET_RATE_PARENT, 1916 .ops = &clk_branch2_ops, 1917 }, 1918 }, 1919 }; 1920 1921 static struct clk_branch gcc_sdcc1_ahb_clk = { 1922 .halt_reg = 0x04c8, 1923 .clkr = { 1924 .enable_reg = 0x04c8, 1925 .enable_mask = BIT(0), 1926 .hw.init = &(struct clk_init_data){ 1927 .name = "gcc_sdcc1_ahb_clk", 1928 .ops = &clk_branch2_ops, 1929 }, 1930 }, 1931 }; 1932 1933 static struct clk_branch gcc_sdcc2_ahb_clk = { 1934 .halt_reg = 0x0508, 1935 .clkr = { 1936 .enable_reg = 0x0508, 1937 .enable_mask = BIT(0), 1938 .hw.init = &(struct clk_init_data){ 1939 .name = "gcc_sdcc2_ahb_clk", 1940 .ops = &clk_branch2_ops, 1941 }, 1942 }, 1943 }; 1944 1945 static struct clk_branch gcc_sdcc2_apps_clk = { 1946 .halt_reg = 0x0504, 1947 .clkr = { 1948 .enable_reg = 0x0504, 1949 .enable_mask = BIT(0), 1950 .hw.init = &(struct clk_init_data){ 1951 .name = "gcc_sdcc2_apps_clk", 1952 .parent_hws = (const struct clk_hw *[]){ &sdcc2_apps_clk_src.clkr.hw }, 1953 .num_parents = 1, 1954 .flags = CLK_SET_RATE_PARENT, 1955 .ops = &clk_branch2_ops, 1956 }, 1957 }, 1958 }; 1959 1960 static struct clk_branch gcc_sdcc3_ahb_clk = { 1961 .halt_reg = 0x0548, 1962 .clkr = { 1963 .enable_reg = 0x0548, 1964 .enable_mask = BIT(0), 1965 .hw.init = &(struct clk_init_data){ 1966 .name = "gcc_sdcc3_ahb_clk", 1967 .ops = &clk_branch2_ops, 1968 }, 1969 }, 1970 }; 1971 1972 static struct clk_branch gcc_sdcc3_apps_clk = { 1973 .halt_reg = 0x0544, 1974 .clkr = { 1975 .enable_reg = 0x0544, 1976 .enable_mask = BIT(0), 1977 .hw.init = &(struct clk_init_data){ 1978 .name = "gcc_sdcc3_apps_clk", 1979 .parent_hws = (const struct clk_hw *[]){ &sdcc3_apps_clk_src.clkr.hw }, 1980 .num_parents = 1, 1981 .flags = CLK_SET_RATE_PARENT, 1982 .ops = &clk_branch2_ops, 1983 }, 1984 }, 1985 }; 1986 1987 static struct clk_branch gcc_sdcc4_ahb_clk = { 1988 .halt_reg = 0x0588, 1989 .clkr = { 1990 .enable_reg = 0x0588, 1991 .enable_mask = BIT(0), 1992 .hw.init = &(struct clk_init_data){ 1993 .name = "gcc_sdcc4_ahb_clk", 1994 .ops = &clk_branch2_ops, 1995 }, 1996 }, 1997 }; 1998 1999 static struct clk_branch gcc_sdcc4_apps_clk = { 2000 .halt_reg = 0x0584, 2001 .clkr = { 2002 .enable_reg = 0x0584, 2003 .enable_mask = BIT(0), 2004 .hw.init = &(struct clk_init_data){ 2005 .name = "gcc_sdcc4_apps_clk", 2006 .parent_hws = (const struct clk_hw *[]){ &sdcc4_apps_clk_src.clkr.hw }, 2007 .num_parents = 1, 2008 .flags = CLK_SET_RATE_PARENT, 2009 .ops = &clk_branch2_ops, 2010 }, 2011 }, 2012 }; 2013 2014 static struct clk_branch gcc_sys_noc_ufs_axi_clk = { 2015 .halt_reg = 0x1d7c, 2016 .clkr = { 2017 .enable_reg = 0x1d7c, 2018 .enable_mask = BIT(0), 2019 .hw.init = &(struct clk_init_data){ 2020 .name = "gcc_sys_noc_ufs_axi_clk", 2021 .parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw }, 2022 .num_parents = 1, 2023 .flags = CLK_SET_RATE_PARENT, 2024 .ops = &clk_branch2_ops, 2025 }, 2026 }, 2027 }; 2028 2029 static struct clk_branch gcc_sys_noc_usb3_axi_clk = { 2030 .halt_reg = 0x03fc, 2031 .clkr = { 2032 .enable_reg = 0x03fc, 2033 .enable_mask = BIT(0), 2034 .hw.init = &(struct clk_init_data){ 2035 .name = "gcc_sys_noc_usb3_axi_clk", 2036 .parent_hws = (const struct clk_hw *[]){ &usb30_master_clk_src.clkr.hw }, 2037 .num_parents = 1, 2038 .flags = CLK_SET_RATE_PARENT, 2039 .ops = &clk_branch2_ops, 2040 }, 2041 }, 2042 }; 2043 2044 static struct clk_branch gcc_tsif_ahb_clk = { 2045 .halt_reg = 0x0d84, 2046 .clkr = { 2047 .enable_reg = 0x0d84, 2048 .enable_mask = BIT(0), 2049 .hw.init = &(struct clk_init_data){ 2050 .name = "gcc_tsif_ahb_clk", 2051 .ops = &clk_branch2_ops, 2052 }, 2053 }, 2054 }; 2055 2056 static struct clk_branch gcc_tsif_ref_clk = { 2057 .halt_reg = 0x0d88, 2058 .clkr = { 2059 .enable_reg = 0x0d88, 2060 .enable_mask = BIT(0), 2061 .hw.init = &(struct clk_init_data){ 2062 .name = "gcc_tsif_ref_clk", 2063 .parent_hws = (const struct clk_hw *[]){ &tsif_ref_clk_src.clkr.hw }, 2064 .num_parents = 1, 2065 .flags = CLK_SET_RATE_PARENT, 2066 .ops = &clk_branch2_ops, 2067 }, 2068 }, 2069 }; 2070 2071 static struct clk_branch gcc_ufs_ahb_clk = { 2072 .halt_reg = 0x1d4c, 2073 .clkr = { 2074 .enable_reg = 0x1d4c, 2075 .enable_mask = BIT(0), 2076 .hw.init = &(struct clk_init_data){ 2077 .name = "gcc_ufs_ahb_clk", 2078 .ops = &clk_branch2_ops, 2079 }, 2080 }, 2081 }; 2082 2083 static struct clk_branch gcc_ufs_axi_clk = { 2084 .halt_reg = 0x1d48, 2085 .clkr = { 2086 .enable_reg = 0x1d48, 2087 .enable_mask = BIT(0), 2088 .hw.init = &(struct clk_init_data){ 2089 .name = "gcc_ufs_axi_clk", 2090 .parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw }, 2091 .num_parents = 1, 2092 .flags = CLK_SET_RATE_PARENT, 2093 .ops = &clk_branch2_ops, 2094 }, 2095 }, 2096 }; 2097 2098 static struct clk_branch gcc_ufs_rx_cfg_clk = { 2099 .halt_reg = 0x1d54, 2100 .clkr = { 2101 .enable_reg = 0x1d54, 2102 .enable_mask = BIT(0), 2103 .hw.init = &(struct clk_init_data){ 2104 .name = "gcc_ufs_rx_cfg_clk", 2105 .parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw }, 2106 .num_parents = 1, 2107 .flags = CLK_SET_RATE_PARENT, 2108 .ops = &clk_branch2_ops, 2109 }, 2110 }, 2111 }; 2112 2113 static struct clk_branch gcc_ufs_rx_symbol_0_clk = { 2114 .halt_reg = 0x1d60, 2115 .halt_check = BRANCH_HALT_DELAY, 2116 .clkr = { 2117 .enable_reg = 0x1d60, 2118 .enable_mask = BIT(0), 2119 .hw.init = &(struct clk_init_data){ 2120 .name = "gcc_ufs_rx_symbol_0_clk", 2121 .ops = &clk_branch2_ops, 2122 }, 2123 }, 2124 }; 2125 2126 static struct clk_branch gcc_ufs_rx_symbol_1_clk = { 2127 .halt_reg = 0x1d64, 2128 .halt_check = BRANCH_HALT_DELAY, 2129 .clkr = { 2130 .enable_reg = 0x1d64, 2131 .enable_mask = BIT(0), 2132 .hw.init = &(struct clk_init_data){ 2133 .name = "gcc_ufs_rx_symbol_1_clk", 2134 .ops = &clk_branch2_ops, 2135 }, 2136 }, 2137 }; 2138 2139 static struct clk_branch gcc_ufs_tx_cfg_clk = { 2140 .halt_reg = 0x1d50, 2141 .clkr = { 2142 .enable_reg = 0x1d50, 2143 .enable_mask = BIT(0), 2144 .hw.init = &(struct clk_init_data){ 2145 .name = "gcc_ufs_tx_cfg_clk", 2146 .parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw }, 2147 .num_parents = 1, 2148 .flags = CLK_SET_RATE_PARENT, 2149 .ops = &clk_branch2_ops, 2150 }, 2151 }, 2152 }; 2153 2154 static struct clk_branch gcc_ufs_tx_symbol_0_clk = { 2155 .halt_reg = 0x1d58, 2156 .halt_check = BRANCH_HALT_DELAY, 2157 .clkr = { 2158 .enable_reg = 0x1d58, 2159 .enable_mask = BIT(0), 2160 .hw.init = &(struct clk_init_data){ 2161 .name = "gcc_ufs_tx_symbol_0_clk", 2162 .ops = &clk_branch2_ops, 2163 }, 2164 }, 2165 }; 2166 2167 static struct clk_branch gcc_ufs_tx_symbol_1_clk = { 2168 .halt_reg = 0x1d5c, 2169 .halt_check = BRANCH_HALT_DELAY, 2170 .clkr = { 2171 .enable_reg = 0x1d5c, 2172 .enable_mask = BIT(0), 2173 .hw.init = &(struct clk_init_data){ 2174 .name = "gcc_ufs_tx_symbol_1_clk", 2175 .ops = &clk_branch2_ops, 2176 }, 2177 }, 2178 }; 2179 2180 static struct clk_branch gcc_usb2_hs_phy_sleep_clk = { 2181 .halt_reg = 0x04ac, 2182 .clkr = { 2183 .enable_reg = 0x04ac, 2184 .enable_mask = BIT(0), 2185 .hw.init = &(struct clk_init_data){ 2186 .name = "gcc_usb2_hs_phy_sleep_clk", 2187 .parent_data = &(const struct clk_parent_data){ 2188 .fw_name = "sleep", 2189 .name = "sleep" 2190 }, 2191 .num_parents = 1, 2192 .ops = &clk_branch2_ops, 2193 }, 2194 }, 2195 }; 2196 2197 static struct clk_branch gcc_usb30_master_clk = { 2198 .halt_reg = 0x03c8, 2199 .clkr = { 2200 .enable_reg = 0x03c8, 2201 .enable_mask = BIT(0), 2202 .hw.init = &(struct clk_init_data){ 2203 .name = "gcc_usb30_master_clk", 2204 .parent_hws = (const struct clk_hw *[]){ &usb30_master_clk_src.clkr.hw }, 2205 .num_parents = 1, 2206 .flags = CLK_SET_RATE_PARENT, 2207 .ops = &clk_branch2_ops, 2208 }, 2209 }, 2210 }; 2211 2212 static struct clk_branch gcc_usb30_mock_utmi_clk = { 2213 .halt_reg = 0x03d0, 2214 .clkr = { 2215 .enable_reg = 0x03d0, 2216 .enable_mask = BIT(0), 2217 .hw.init = &(struct clk_init_data){ 2218 .name = "gcc_usb30_mock_utmi_clk", 2219 .parent_hws = (const struct clk_hw *[]){ &usb30_mock_utmi_clk_src.clkr.hw }, 2220 .num_parents = 1, 2221 .flags = CLK_SET_RATE_PARENT, 2222 .ops = &clk_branch2_ops, 2223 }, 2224 }, 2225 }; 2226 2227 static struct clk_branch gcc_usb30_sleep_clk = { 2228 .halt_reg = 0x03cc, 2229 .clkr = { 2230 .enable_reg = 0x03cc, 2231 .enable_mask = BIT(0), 2232 .hw.init = &(struct clk_init_data){ 2233 .name = "gcc_usb30_sleep_clk", 2234 .parent_data = &(const struct clk_parent_data){ 2235 .fw_name = "sleep", 2236 .name = "sleep" 2237 }, 2238 .num_parents = 1, 2239 .ops = &clk_branch2_ops, 2240 }, 2241 }, 2242 }; 2243 2244 static struct clk_branch gcc_usb3_phy_aux_clk = { 2245 .halt_reg = 0x1408, 2246 .clkr = { 2247 .enable_reg = 0x1408, 2248 .enable_mask = BIT(0), 2249 .hw.init = &(struct clk_init_data){ 2250 .name = "gcc_usb3_phy_aux_clk", 2251 .parent_hws = (const struct clk_hw *[]){ &usb3_phy_aux_clk_src.clkr.hw }, 2252 .num_parents = 1, 2253 .flags = CLK_SET_RATE_PARENT, 2254 .ops = &clk_branch2_ops, 2255 }, 2256 }, 2257 }; 2258 2259 static struct clk_branch gcc_usb3_phy_pipe_clk = { 2260 .halt_reg = 0x140c, 2261 .halt_check = BRANCH_HALT_SKIP, 2262 .clkr = { 2263 .enable_reg = 0x140c, 2264 .enable_mask = BIT(0), 2265 .hw.init = &(struct clk_init_data){ 2266 .name = "gcc_usb3_phy_pipe_clk", 2267 .ops = &clk_branch2_ops, 2268 }, 2269 }, 2270 }; 2271 2272 static struct clk_branch gcc_usb_hs_ahb_clk = { 2273 .halt_reg = 0x0488, 2274 .clkr = { 2275 .enable_reg = 0x0488, 2276 .enable_mask = BIT(0), 2277 .hw.init = &(struct clk_init_data){ 2278 .name = "gcc_usb_hs_ahb_clk", 2279 .ops = &clk_branch2_ops, 2280 }, 2281 }, 2282 }; 2283 2284 static struct clk_branch gcc_usb_hs_system_clk = { 2285 .halt_reg = 0x0484, 2286 .clkr = { 2287 .enable_reg = 0x0484, 2288 .enable_mask = BIT(0), 2289 .hw.init = &(struct clk_init_data){ 2290 .name = "gcc_usb_hs_system_clk", 2291 .parent_hws = (const struct clk_hw *[]){ &usb_hs_system_clk_src.clkr.hw }, 2292 .num_parents = 1, 2293 .flags = CLK_SET_RATE_PARENT, 2294 .ops = &clk_branch2_ops, 2295 }, 2296 }, 2297 }; 2298 2299 static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = { 2300 .halt_reg = 0x1a84, 2301 .clkr = { 2302 .enable_reg = 0x1a84, 2303 .enable_mask = BIT(0), 2304 .hw.init = &(struct clk_init_data){ 2305 .name = "gcc_usb_phy_cfg_ahb2phy_clk", 2306 .ops = &clk_branch2_ops, 2307 }, 2308 }, 2309 }; 2310 2311 static struct clk_branch gpll0_out_mmsscc = { 2312 .halt_check = BRANCH_HALT_DELAY, 2313 .clkr = { 2314 .enable_reg = 0x1484, 2315 .enable_mask = BIT(26), 2316 .hw.init = &(struct clk_init_data){ 2317 .name = "gpll0_out_mmsscc", 2318 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw }, 2319 .num_parents = 1, 2320 .ops = &clk_branch2_ops, 2321 }, 2322 }, 2323 }; 2324 2325 static struct clk_branch gpll0_out_msscc = { 2326 .halt_check = BRANCH_HALT_DELAY, 2327 .clkr = { 2328 .enable_reg = 0x1484, 2329 .enable_mask = BIT(27), 2330 .hw.init = &(struct clk_init_data){ 2331 .name = "gpll0_out_msscc", 2332 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw }, 2333 .num_parents = 1, 2334 .ops = &clk_branch2_ops, 2335 }, 2336 }, 2337 }; 2338 2339 static struct clk_branch pcie_0_phy_ldo = { 2340 .halt_reg = 0x1e00, 2341 .halt_check = BRANCH_HALT_SKIP, 2342 .clkr = { 2343 .enable_reg = 0x1E00, 2344 .enable_mask = BIT(0), 2345 .hw.init = &(struct clk_init_data){ 2346 .name = "pcie_0_phy_ldo", 2347 .ops = &clk_branch2_ops, 2348 }, 2349 }, 2350 }; 2351 2352 static struct clk_branch pcie_1_phy_ldo = { 2353 .halt_reg = 0x1e04, 2354 .halt_check = BRANCH_HALT_SKIP, 2355 .clkr = { 2356 .enable_reg = 0x1E04, 2357 .enable_mask = BIT(0), 2358 .hw.init = &(struct clk_init_data){ 2359 .name = "pcie_1_phy_ldo", 2360 .ops = &clk_branch2_ops, 2361 }, 2362 }, 2363 }; 2364 2365 static struct clk_branch ufs_phy_ldo = { 2366 .halt_reg = 0x1e0c, 2367 .halt_check = BRANCH_HALT_SKIP, 2368 .clkr = { 2369 .enable_reg = 0x1E0C, 2370 .enable_mask = BIT(0), 2371 .hw.init = &(struct clk_init_data){ 2372 .name = "ufs_phy_ldo", 2373 .ops = &clk_branch2_ops, 2374 }, 2375 }, 2376 }; 2377 2378 static struct clk_branch usb_ss_phy_ldo = { 2379 .halt_reg = 0x1e08, 2380 .halt_check = BRANCH_HALT_SKIP, 2381 .clkr = { 2382 .enable_reg = 0x1E08, 2383 .enable_mask = BIT(0), 2384 .hw.init = &(struct clk_init_data){ 2385 .name = "usb_ss_phy_ldo", 2386 .ops = &clk_branch2_ops, 2387 }, 2388 }, 2389 }; 2390 2391 static struct clk_branch gcc_boot_rom_ahb_clk = { 2392 .halt_reg = 0x0e04, 2393 .halt_check = BRANCH_HALT_VOTED, 2394 .hwcg_reg = 0x0e04, 2395 .hwcg_bit = 1, 2396 .clkr = { 2397 .enable_reg = 0x1484, 2398 .enable_mask = BIT(10), 2399 .hw.init = &(struct clk_init_data){ 2400 .name = "gcc_boot_rom_ahb_clk", 2401 .ops = &clk_branch2_ops, 2402 }, 2403 }, 2404 }; 2405 2406 static struct clk_branch gcc_prng_ahb_clk = { 2407 .halt_reg = 0x0d04, 2408 .halt_check = BRANCH_HALT_VOTED, 2409 .clkr = { 2410 .enable_reg = 0x1484, 2411 .enable_mask = BIT(13), 2412 .hw.init = &(struct clk_init_data){ 2413 .name = "gcc_prng_ahb_clk", 2414 .ops = &clk_branch2_ops, 2415 }, 2416 }, 2417 }; 2418 2419 static struct gdsc pcie_0_gdsc = { 2420 .gdscr = 0x1ac4, 2421 .pd = { 2422 .name = "pcie_0", 2423 }, 2424 .pwrsts = PWRSTS_OFF_ON, 2425 }; 2426 2427 static struct gdsc pcie_1_gdsc = { 2428 .gdscr = 0x1b44, 2429 .pd = { 2430 .name = "pcie_1", 2431 }, 2432 .pwrsts = PWRSTS_OFF_ON, 2433 }; 2434 2435 static struct gdsc usb30_gdsc = { 2436 .gdscr = 0x3c4, 2437 .pd = { 2438 .name = "usb30", 2439 }, 2440 .pwrsts = PWRSTS_OFF_ON, 2441 }; 2442 2443 static struct gdsc ufs_gdsc = { 2444 .gdscr = 0x1d44, 2445 .pd = { 2446 .name = "ufs", 2447 }, 2448 .pwrsts = PWRSTS_OFF_ON, 2449 }; 2450 2451 static struct clk_regmap *gcc_msm8994_clocks[] = { 2452 [GPLL0_EARLY] = &gpll0_early.clkr, 2453 [GPLL0] = &gpll0.clkr, 2454 [GPLL4_EARLY] = &gpll4_early.clkr, 2455 [GPLL4] = &gpll4.clkr, 2456 [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr, 2457 [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr, 2458 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr, 2459 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr, 2460 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr, 2461 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr, 2462 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr, 2463 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr, 2464 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr, 2465 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr, 2466 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr, 2467 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr, 2468 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr, 2469 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr, 2470 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr, 2471 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr, 2472 [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr, 2473 [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr, 2474 [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr, 2475 [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr, 2476 [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr, 2477 [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr, 2478 [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr, 2479 [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr, 2480 [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr, 2481 [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr, 2482 [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr, 2483 [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr, 2484 [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr, 2485 [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr, 2486 [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr, 2487 [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr, 2488 [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr, 2489 [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr, 2490 [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr, 2491 [BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr, 2492 [BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr, 2493 [BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr, 2494 [GP1_CLK_SRC] = &gp1_clk_src.clkr, 2495 [GP2_CLK_SRC] = &gp2_clk_src.clkr, 2496 [GP3_CLK_SRC] = &gp3_clk_src.clkr, 2497 [PCIE_0_AUX_CLK_SRC] = &pcie_0_aux_clk_src.clkr, 2498 [PCIE_0_PIPE_CLK_SRC] = &pcie_0_pipe_clk_src.clkr, 2499 [PCIE_1_AUX_CLK_SRC] = &pcie_1_aux_clk_src.clkr, 2500 [PCIE_1_PIPE_CLK_SRC] = &pcie_1_pipe_clk_src.clkr, 2501 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr, 2502 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr, 2503 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr, 2504 [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr, 2505 [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr, 2506 [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr, 2507 [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr, 2508 [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr, 2509 [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr, 2510 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr, 2511 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr, 2512 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr, 2513 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr, 2514 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr, 2515 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr, 2516 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr, 2517 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr, 2518 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr, 2519 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr, 2520 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr, 2521 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr, 2522 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr, 2523 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, 2524 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr, 2525 [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr, 2526 [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr, 2527 [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr, 2528 [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr, 2529 [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr, 2530 [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr, 2531 [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr, 2532 [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr, 2533 [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr, 2534 [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr, 2535 [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr, 2536 [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr, 2537 [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr, 2538 [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr, 2539 [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr, 2540 [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr, 2541 [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr, 2542 [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr, 2543 [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr, 2544 [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr, 2545 [GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr, 2546 [GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr, 2547 [GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr, 2548 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 2549 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 2550 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 2551 [GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr, 2552 [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr, 2553 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, 2554 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, 2555 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, 2556 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, 2557 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, 2558 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr, 2559 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr, 2560 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr, 2561 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr, 2562 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr, 2563 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 2564 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 2565 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, 2566 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, 2567 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 2568 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 2569 [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr, 2570 [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr, 2571 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, 2572 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, 2573 [GCC_SYS_NOC_UFS_AXI_CLK] = &gcc_sys_noc_ufs_axi_clk.clkr, 2574 [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr, 2575 [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr, 2576 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr, 2577 [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr, 2578 [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr, 2579 [GCC_UFS_RX_CFG_CLK] = &gcc_ufs_rx_cfg_clk.clkr, 2580 [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr, 2581 [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr, 2582 [GCC_UFS_TX_CFG_CLK] = &gcc_ufs_tx_cfg_clk.clkr, 2583 [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr, 2584 [GCC_UFS_TX_SYMBOL_1_CLK] = &gcc_ufs_tx_symbol_1_clk.clkr, 2585 [GCC_USB2_HS_PHY_SLEEP_CLK] = &gcc_usb2_hs_phy_sleep_clk.clkr, 2586 [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr, 2587 [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr, 2588 [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr, 2589 [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr, 2590 [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr, 2591 [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr, 2592 [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr, 2593 [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr, 2594 [GPLL0_OUT_MMSSCC] = &gpll0_out_mmsscc.clkr, 2595 [GPLL0_OUT_MSSCC] = &gpll0_out_msscc.clkr, 2596 [PCIE_0_PHY_LDO] = &pcie_0_phy_ldo.clkr, 2597 [PCIE_1_PHY_LDO] = &pcie_1_phy_ldo.clkr, 2598 [UFS_PHY_LDO] = &ufs_phy_ldo.clkr, 2599 [USB_SS_PHY_LDO] = &usb_ss_phy_ldo.clkr, 2600 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 2601 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, 2602 2603 /* 2604 * The following clocks should NOT be managed by this driver, but they once were 2605 * mistakengly added. Now they are only here to indicate that they are not defined 2606 * on purpose, even though the names will stay in the header file (for ABI sanity). 2607 */ 2608 [CONFIG_NOC_CLK_SRC] = NULL, 2609 [PERIPH_NOC_CLK_SRC] = NULL, 2610 [SYSTEM_NOC_CLK_SRC] = NULL, 2611 }; 2612 2613 static struct gdsc *gcc_msm8994_gdscs[] = { 2614 /* This GDSC does not exist, but ABI has to remain intact */ 2615 [PCIE_GDSC] = NULL, 2616 [PCIE_0_GDSC] = &pcie_0_gdsc, 2617 [PCIE_1_GDSC] = &pcie_1_gdsc, 2618 [USB30_GDSC] = &usb30_gdsc, 2619 [UFS_GDSC] = &ufs_gdsc, 2620 }; 2621 2622 static const struct qcom_reset_map gcc_msm8994_resets[] = { 2623 [USB3_PHY_RESET] = { 0x1400 }, 2624 [USB3PHY_PHY_RESET] = { 0x1404 }, 2625 [MSS_RESET] = { 0x1680 }, 2626 [PCIE_PHY_0_RESET] = { 0x1b18 }, 2627 [PCIE_PHY_1_RESET] = { 0x1b98 }, 2628 [QUSB2_PHY_RESET] = { 0x04b8 }, 2629 }; 2630 2631 static const struct regmap_config gcc_msm8994_regmap_config = { 2632 .reg_bits = 32, 2633 .reg_stride = 4, 2634 .val_bits = 32, 2635 .max_register = 0x2000, 2636 .fast_io = true, 2637 }; 2638 2639 static const struct qcom_cc_desc gcc_msm8994_desc = { 2640 .config = &gcc_msm8994_regmap_config, 2641 .clks = gcc_msm8994_clocks, 2642 .num_clks = ARRAY_SIZE(gcc_msm8994_clocks), 2643 .resets = gcc_msm8994_resets, 2644 .num_resets = ARRAY_SIZE(gcc_msm8994_resets), 2645 .gdscs = gcc_msm8994_gdscs, 2646 .num_gdscs = ARRAY_SIZE(gcc_msm8994_gdscs), 2647 }; 2648 2649 static const struct of_device_id gcc_msm8994_match_table[] = { 2650 { .compatible = "qcom,gcc-msm8992" }, 2651 { .compatible = "qcom,gcc-msm8994" }, /* V2 and V2.1 */ 2652 {} 2653 }; 2654 MODULE_DEVICE_TABLE(of, gcc_msm8994_match_table); 2655 2656 static int gcc_msm8994_probe(struct platform_device *pdev) 2657 { 2658 if (of_device_is_compatible(pdev->dev.of_node, "qcom,gcc-msm8992")) { 2659 /* MSM8992 features less clocks and some have different freq tables */ 2660 gcc_msm8994_desc.clks[UFS_AXI_CLK_SRC] = NULL; 2661 gcc_msm8994_desc.clks[GCC_LPASS_Q6_AXI_CLK] = NULL; 2662 gcc_msm8994_desc.clks[UFS_PHY_LDO] = NULL; 2663 gcc_msm8994_desc.clks[GCC_UFS_AHB_CLK] = NULL; 2664 gcc_msm8994_desc.clks[GCC_UFS_AXI_CLK] = NULL; 2665 gcc_msm8994_desc.clks[GCC_UFS_RX_CFG_CLK] = NULL; 2666 gcc_msm8994_desc.clks[GCC_UFS_RX_SYMBOL_0_CLK] = NULL; 2667 gcc_msm8994_desc.clks[GCC_UFS_RX_SYMBOL_1_CLK] = NULL; 2668 gcc_msm8994_desc.clks[GCC_UFS_TX_CFG_CLK] = NULL; 2669 gcc_msm8994_desc.clks[GCC_UFS_TX_SYMBOL_0_CLK] = NULL; 2670 gcc_msm8994_desc.clks[GCC_UFS_TX_SYMBOL_1_CLK] = NULL; 2671 2672 sdcc1_apps_clk_src.freq_tbl = ftbl_sdcc1_apps_clk_src_8992; 2673 blsp1_qup1_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992; 2674 blsp1_qup2_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992; 2675 blsp1_qup3_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992; 2676 blsp1_qup4_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992; 2677 blsp1_qup5_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992; 2678 blsp1_qup6_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992; 2679 blsp2_qup1_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992; 2680 blsp2_qup2_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992; 2681 blsp2_qup3_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992; 2682 blsp2_qup4_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992; 2683 blsp2_qup5_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992; 2684 blsp2_qup6_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992; 2685 2686 /* 2687 * Some 8992 boards might *possibly* use 2688 * PCIe1 clocks and controller, but it's not 2689 * standard and they should be disabled otherwise. 2690 */ 2691 gcc_msm8994_desc.clks[PCIE_1_AUX_CLK_SRC] = NULL; 2692 gcc_msm8994_desc.clks[PCIE_1_PIPE_CLK_SRC] = NULL; 2693 gcc_msm8994_desc.clks[PCIE_1_PHY_LDO] = NULL; 2694 gcc_msm8994_desc.clks[GCC_PCIE_1_AUX_CLK] = NULL; 2695 gcc_msm8994_desc.clks[GCC_PCIE_1_CFG_AHB_CLK] = NULL; 2696 gcc_msm8994_desc.clks[GCC_PCIE_1_MSTR_AXI_CLK] = NULL; 2697 gcc_msm8994_desc.clks[GCC_PCIE_1_PIPE_CLK] = NULL; 2698 gcc_msm8994_desc.clks[GCC_PCIE_1_SLV_AXI_CLK] = NULL; 2699 gcc_msm8994_desc.clks[GCC_SYS_NOC_UFS_AXI_CLK] = NULL; 2700 } 2701 2702 return qcom_cc_probe(pdev, &gcc_msm8994_desc); 2703 } 2704 2705 static struct platform_driver gcc_msm8994_driver = { 2706 .probe = gcc_msm8994_probe, 2707 .driver = { 2708 .name = "gcc-msm8994", 2709 .of_match_table = gcc_msm8994_match_table, 2710 }, 2711 }; 2712 2713 static int __init gcc_msm8994_init(void) 2714 { 2715 return platform_driver_register(&gcc_msm8994_driver); 2716 } 2717 core_initcall(gcc_msm8994_init); 2718 2719 static void __exit gcc_msm8994_exit(void) 2720 { 2721 platform_driver_unregister(&gcc_msm8994_driver); 2722 } 2723 module_exit(gcc_msm8994_exit); 2724 2725 MODULE_DESCRIPTION("Qualcomm GCC MSM8994 Driver"); 2726 MODULE_LICENSE("GPL v2"); 2727 MODULE_ALIAS("platform:gcc-msm8994"); 2728