1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. 3 */ 4 5 #include <linux/kernel.h> 6 #include <linux/init.h> 7 #include <linux/err.h> 8 #include <linux/ctype.h> 9 #include <linux/io.h> 10 #include <linux/of.h> 11 #include <linux/platform_device.h> 12 #include <linux/module.h> 13 #include <linux/regmap.h> 14 15 #include <dt-bindings/clock/qcom,gcc-msm8994.h> 16 17 #include "common.h" 18 #include "clk-regmap.h" 19 #include "clk-alpha-pll.h" 20 #include "clk-rcg.h" 21 #include "clk-branch.h" 22 #include "reset.h" 23 #include "gdsc.h" 24 25 enum { 26 P_XO, 27 P_GPLL0, 28 P_GPLL4, 29 }; 30 31 static struct clk_alpha_pll gpll0_early = { 32 .offset = 0, 33 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 34 .clkr = { 35 .enable_reg = 0x1480, 36 .enable_mask = BIT(0), 37 .hw.init = &(struct clk_init_data){ 38 .name = "gpll0_early", 39 .parent_data = &(const struct clk_parent_data){ 40 .fw_name = "xo", 41 }, 42 .num_parents = 1, 43 .ops = &clk_alpha_pll_ops, 44 }, 45 }, 46 }; 47 48 static struct clk_alpha_pll_postdiv gpll0 = { 49 .offset = 0, 50 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 51 .clkr.hw.init = &(struct clk_init_data){ 52 .name = "gpll0", 53 .parent_names = (const char *[]) { "gpll0_early" }, 54 .num_parents = 1, 55 .ops = &clk_alpha_pll_postdiv_ops, 56 }, 57 }; 58 59 static struct clk_alpha_pll gpll4_early = { 60 .offset = 0x1dc0, 61 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 62 .clkr = { 63 .enable_reg = 0x1480, 64 .enable_mask = BIT(4), 65 .hw.init = &(struct clk_init_data){ 66 .name = "gpll4_early", 67 .parent_data = &(const struct clk_parent_data){ 68 .fw_name = "xo", 69 }, 70 .num_parents = 1, 71 .ops = &clk_alpha_pll_ops, 72 }, 73 }, 74 }; 75 76 static struct clk_alpha_pll_postdiv gpll4 = { 77 .offset = 0x1dc0, 78 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 79 .clkr.hw.init = &(struct clk_init_data){ 80 .name = "gpll4", 81 .parent_names = (const char *[]) { "gpll4_early" }, 82 .num_parents = 1, 83 .ops = &clk_alpha_pll_postdiv_ops, 84 }, 85 }; 86 87 static const struct parent_map gcc_xo_gpll0_map[] = { 88 { P_XO, 0 }, 89 { P_GPLL0, 1 }, 90 }; 91 92 static const struct clk_parent_data gcc_xo_gpll0[] = { 93 { .fw_name = "xo" }, 94 { .hw = &gpll0.clkr.hw }, 95 }; 96 97 static const struct parent_map gcc_xo_gpll0_gpll4_map[] = { 98 { P_XO, 0 }, 99 { P_GPLL0, 1 }, 100 { P_GPLL4, 5 }, 101 }; 102 103 static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = { 104 { .fw_name = "xo" }, 105 { .hw = &gpll0.clkr.hw }, 106 { .hw = &gpll4.clkr.hw }, 107 }; 108 109 static struct freq_tbl ftbl_ufs_axi_clk_src[] = { 110 F(50000000, P_GPLL0, 12, 0, 0), 111 F(100000000, P_GPLL0, 6, 0, 0), 112 F(150000000, P_GPLL0, 4, 0, 0), 113 F(171430000, P_GPLL0, 3.5, 0, 0), 114 F(200000000, P_GPLL0, 3, 0, 0), 115 F(240000000, P_GPLL0, 2.5, 0, 0), 116 { } 117 }; 118 119 static struct clk_rcg2 ufs_axi_clk_src = { 120 .cmd_rcgr = 0x1d68, 121 .mnd_width = 8, 122 .hid_width = 5, 123 .parent_map = gcc_xo_gpll0_map, 124 .freq_tbl = ftbl_ufs_axi_clk_src, 125 .clkr.hw.init = &(struct clk_init_data){ 126 .name = "ufs_axi_clk_src", 127 .parent_data = gcc_xo_gpll0, 128 .num_parents = 2, 129 .ops = &clk_rcg2_ops, 130 }, 131 }; 132 133 static struct freq_tbl ftbl_usb30_master_clk_src[] = { 134 F(19200000, P_XO, 1, 0, 0), 135 F(125000000, P_GPLL0, 1, 5, 24), 136 { } 137 }; 138 139 static struct clk_rcg2 usb30_master_clk_src = { 140 .cmd_rcgr = 0x03d4, 141 .mnd_width = 8, 142 .hid_width = 5, 143 .parent_map = gcc_xo_gpll0_map, 144 .freq_tbl = ftbl_usb30_master_clk_src, 145 .clkr.hw.init = &(struct clk_init_data){ 146 .name = "usb30_master_clk_src", 147 .parent_data = gcc_xo_gpll0, 148 .num_parents = 2, 149 .ops = &clk_rcg2_ops, 150 }, 151 }; 152 153 static struct freq_tbl ftbl_blsp_i2c_apps_clk_src[] = { 154 F(19200000, P_XO, 1, 0, 0), 155 F(50000000, P_GPLL0, 12, 0, 0), 156 { } 157 }; 158 159 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { 160 .cmd_rcgr = 0x0660, 161 .hid_width = 5, 162 .parent_map = gcc_xo_gpll0_map, 163 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 164 .clkr.hw.init = &(struct clk_init_data){ 165 .name = "blsp1_qup1_i2c_apps_clk_src", 166 .parent_data = gcc_xo_gpll0, 167 .num_parents = 2, 168 .ops = &clk_rcg2_ops, 169 }, 170 }; 171 172 static struct freq_tbl ftbl_blspqup_spi_apps_clk_src[] = { 173 F(960000, P_XO, 10, 1, 2), 174 F(4800000, P_XO, 4, 0, 0), 175 F(9600000, P_XO, 2, 0, 0), 176 F(15000000, P_GPLL0, 10, 1, 4), 177 F(19200000, P_XO, 1, 0, 0), 178 F(24000000, P_GPLL0, 12.5, 1, 2), 179 F(25000000, P_GPLL0, 12, 1, 2), 180 F(48000000, P_GPLL0, 12.5, 0, 0), 181 F(50000000, P_GPLL0, 12, 0, 0), 182 { } 183 }; 184 185 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { 186 .cmd_rcgr = 0x064c, 187 .mnd_width = 8, 188 .hid_width = 5, 189 .parent_map = gcc_xo_gpll0_map, 190 .freq_tbl = ftbl_blspqup_spi_apps_clk_src, 191 .clkr.hw.init = &(struct clk_init_data){ 192 .name = "blsp1_qup1_spi_apps_clk_src", 193 .parent_data = gcc_xo_gpll0, 194 .num_parents = 2, 195 .ops = &clk_rcg2_ops, 196 }, 197 }; 198 199 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { 200 .cmd_rcgr = 0x06e0, 201 .hid_width = 5, 202 .parent_map = gcc_xo_gpll0_map, 203 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 204 .clkr.hw.init = &(struct clk_init_data){ 205 .name = "blsp1_qup2_i2c_apps_clk_src", 206 .parent_data = gcc_xo_gpll0, 207 .num_parents = 2, 208 .ops = &clk_rcg2_ops, 209 }, 210 }; 211 212 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { 213 .cmd_rcgr = 0x06cc, 214 .mnd_width = 8, 215 .hid_width = 5, 216 .parent_map = gcc_xo_gpll0_map, 217 .freq_tbl = ftbl_blspqup_spi_apps_clk_src, 218 .clkr.hw.init = &(struct clk_init_data){ 219 .name = "blsp1_qup2_spi_apps_clk_src", 220 .parent_data = gcc_xo_gpll0, 221 .num_parents = 2, 222 .ops = &clk_rcg2_ops, 223 }, 224 }; 225 226 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { 227 .cmd_rcgr = 0x0760, 228 .hid_width = 5, 229 .parent_map = gcc_xo_gpll0_map, 230 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 231 .clkr.hw.init = &(struct clk_init_data){ 232 .name = "blsp1_qup3_i2c_apps_clk_src", 233 .parent_data = gcc_xo_gpll0, 234 .num_parents = 2, 235 .ops = &clk_rcg2_ops, 236 }, 237 }; 238 239 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { 240 .cmd_rcgr = 0x074c, 241 .mnd_width = 8, 242 .hid_width = 5, 243 .parent_map = gcc_xo_gpll0_map, 244 .freq_tbl = ftbl_blspqup_spi_apps_clk_src, 245 .clkr.hw.init = &(struct clk_init_data){ 246 .name = "blsp1_qup3_spi_apps_clk_src", 247 .parent_data = gcc_xo_gpll0, 248 .num_parents = 2, 249 .ops = &clk_rcg2_ops, 250 }, 251 }; 252 253 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { 254 .cmd_rcgr = 0x07e0, 255 .hid_width = 5, 256 .parent_map = gcc_xo_gpll0_map, 257 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 258 .clkr.hw.init = &(struct clk_init_data){ 259 .name = "blsp1_qup4_i2c_apps_clk_src", 260 .parent_data = gcc_xo_gpll0, 261 .num_parents = 2, 262 .ops = &clk_rcg2_ops, 263 }, 264 }; 265 266 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { 267 .cmd_rcgr = 0x07cc, 268 .mnd_width = 8, 269 .hid_width = 5, 270 .parent_map = gcc_xo_gpll0_map, 271 .freq_tbl = ftbl_blspqup_spi_apps_clk_src, 272 .clkr.hw.init = &(struct clk_init_data){ 273 .name = "blsp1_qup4_spi_apps_clk_src", 274 .parent_data = gcc_xo_gpll0, 275 .num_parents = 2, 276 .ops = &clk_rcg2_ops, 277 }, 278 }; 279 280 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = { 281 .cmd_rcgr = 0x0860, 282 .hid_width = 5, 283 .parent_map = gcc_xo_gpll0_map, 284 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 285 .clkr.hw.init = &(struct clk_init_data){ 286 .name = "blsp1_qup5_i2c_apps_clk_src", 287 .parent_data = gcc_xo_gpll0, 288 .num_parents = 2, 289 .ops = &clk_rcg2_ops, 290 }, 291 }; 292 293 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = { 294 .cmd_rcgr = 0x084c, 295 .mnd_width = 8, 296 .hid_width = 5, 297 .parent_map = gcc_xo_gpll0_map, 298 .freq_tbl = ftbl_blspqup_spi_apps_clk_src, 299 .clkr.hw.init = &(struct clk_init_data){ 300 .name = "blsp1_qup5_spi_apps_clk_src", 301 .parent_data = gcc_xo_gpll0, 302 .num_parents = 2, 303 .ops = &clk_rcg2_ops, 304 }, 305 }; 306 307 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = { 308 .cmd_rcgr = 0x08e0, 309 .hid_width = 5, 310 .parent_map = gcc_xo_gpll0_map, 311 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 312 .clkr.hw.init = &(struct clk_init_data){ 313 .name = "blsp1_qup6_i2c_apps_clk_src", 314 .parent_data = gcc_xo_gpll0, 315 .num_parents = 2, 316 .ops = &clk_rcg2_ops, 317 }, 318 }; 319 320 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = { 321 .cmd_rcgr = 0x08cc, 322 .mnd_width = 8, 323 .hid_width = 5, 324 .parent_map = gcc_xo_gpll0_map, 325 .freq_tbl = ftbl_blspqup_spi_apps_clk_src, 326 .clkr.hw.init = &(struct clk_init_data){ 327 .name = "blsp1_qup6_spi_apps_clk_src", 328 .parent_data = gcc_xo_gpll0, 329 .num_parents = 2, 330 .ops = &clk_rcg2_ops, 331 }, 332 }; 333 334 static struct freq_tbl ftbl_blsp_uart_apps_clk_src[] = { 335 F(3686400, P_GPLL0, 1, 96, 15625), 336 F(7372800, P_GPLL0, 1, 192, 15625), 337 F(14745600, P_GPLL0, 1, 384, 15625), 338 F(16000000, P_GPLL0, 5, 2, 15), 339 F(19200000, P_XO, 1, 0, 0), 340 F(24000000, P_GPLL0, 5, 1, 5), 341 F(32000000, P_GPLL0, 1, 4, 75), 342 F(40000000, P_GPLL0, 15, 0, 0), 343 F(46400000, P_GPLL0, 1, 29, 375), 344 F(48000000, P_GPLL0, 12.5, 0, 0), 345 F(51200000, P_GPLL0, 1, 32, 375), 346 F(56000000, P_GPLL0, 1, 7, 75), 347 F(58982400, P_GPLL0, 1, 1536, 15625), 348 F(60000000, P_GPLL0, 10, 0, 0), 349 F(63160000, P_GPLL0, 9.5, 0, 0), 350 { } 351 }; 352 353 static struct clk_rcg2 blsp1_uart1_apps_clk_src = { 354 .cmd_rcgr = 0x068c, 355 .mnd_width = 16, 356 .hid_width = 5, 357 .parent_map = gcc_xo_gpll0_map, 358 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 359 .clkr.hw.init = &(struct clk_init_data){ 360 .name = "blsp1_uart1_apps_clk_src", 361 .parent_data = gcc_xo_gpll0, 362 .num_parents = 2, 363 .ops = &clk_rcg2_ops, 364 }, 365 }; 366 367 static struct clk_rcg2 blsp1_uart2_apps_clk_src = { 368 .cmd_rcgr = 0x070c, 369 .mnd_width = 16, 370 .hid_width = 5, 371 .parent_map = gcc_xo_gpll0_map, 372 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 373 .clkr.hw.init = &(struct clk_init_data){ 374 .name = "blsp1_uart2_apps_clk_src", 375 .parent_data = gcc_xo_gpll0, 376 .num_parents = 2, 377 .ops = &clk_rcg2_ops, 378 }, 379 }; 380 381 static struct clk_rcg2 blsp1_uart3_apps_clk_src = { 382 .cmd_rcgr = 0x078c, 383 .mnd_width = 16, 384 .hid_width = 5, 385 .parent_map = gcc_xo_gpll0_map, 386 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 387 .clkr.hw.init = &(struct clk_init_data){ 388 .name = "blsp1_uart3_apps_clk_src", 389 .parent_data = gcc_xo_gpll0, 390 .num_parents = 2, 391 .ops = &clk_rcg2_ops, 392 }, 393 }; 394 395 static struct clk_rcg2 blsp1_uart4_apps_clk_src = { 396 .cmd_rcgr = 0x080c, 397 .mnd_width = 16, 398 .hid_width = 5, 399 .parent_map = gcc_xo_gpll0_map, 400 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 401 .clkr.hw.init = &(struct clk_init_data){ 402 .name = "blsp1_uart4_apps_clk_src", 403 .parent_data = gcc_xo_gpll0, 404 .num_parents = 2, 405 .ops = &clk_rcg2_ops, 406 }, 407 }; 408 409 static struct clk_rcg2 blsp1_uart5_apps_clk_src = { 410 .cmd_rcgr = 0x088c, 411 .mnd_width = 16, 412 .hid_width = 5, 413 .parent_map = gcc_xo_gpll0_map, 414 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 415 .clkr.hw.init = &(struct clk_init_data){ 416 .name = "blsp1_uart5_apps_clk_src", 417 .parent_data = gcc_xo_gpll0, 418 .num_parents = 2, 419 .ops = &clk_rcg2_ops, 420 }, 421 }; 422 423 static struct clk_rcg2 blsp1_uart6_apps_clk_src = { 424 .cmd_rcgr = 0x090c, 425 .mnd_width = 16, 426 .hid_width = 5, 427 .parent_map = gcc_xo_gpll0_map, 428 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 429 .clkr.hw.init = &(struct clk_init_data){ 430 .name = "blsp1_uart6_apps_clk_src", 431 .parent_data = gcc_xo_gpll0, 432 .num_parents = 2, 433 .ops = &clk_rcg2_ops, 434 }, 435 }; 436 437 static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = { 438 .cmd_rcgr = 0x09a0, 439 .hid_width = 5, 440 .parent_map = gcc_xo_gpll0_map, 441 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 442 .clkr.hw.init = &(struct clk_init_data){ 443 .name = "blsp2_qup1_i2c_apps_clk_src", 444 .parent_data = gcc_xo_gpll0, 445 .num_parents = 2, 446 .ops = &clk_rcg2_ops, 447 }, 448 }; 449 450 static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = { 451 .cmd_rcgr = 0x098c, 452 .mnd_width = 8, 453 .hid_width = 5, 454 .parent_map = gcc_xo_gpll0_map, 455 .freq_tbl = ftbl_blspqup_spi_apps_clk_src, 456 .clkr.hw.init = &(struct clk_init_data){ 457 .name = "blsp2_qup1_spi_apps_clk_src", 458 .parent_data = gcc_xo_gpll0, 459 .num_parents = 2, 460 .ops = &clk_rcg2_ops, 461 }, 462 }; 463 464 static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = { 465 .cmd_rcgr = 0x0a20, 466 .hid_width = 5, 467 .parent_map = gcc_xo_gpll0_map, 468 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 469 .clkr.hw.init = &(struct clk_init_data){ 470 .name = "blsp2_qup2_i2c_apps_clk_src", 471 .parent_data = gcc_xo_gpll0, 472 .num_parents = 2, 473 .ops = &clk_rcg2_ops, 474 }, 475 }; 476 477 static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = { 478 .cmd_rcgr = 0x0a0c, 479 .mnd_width = 8, 480 .hid_width = 5, 481 .parent_map = gcc_xo_gpll0_map, 482 .freq_tbl = ftbl_blspqup_spi_apps_clk_src, 483 .clkr.hw.init = &(struct clk_init_data){ 484 .name = "blsp2_qup2_spi_apps_clk_src", 485 .parent_data = gcc_xo_gpll0, 486 .num_parents = 2, 487 .ops = &clk_rcg2_ops, 488 }, 489 }; 490 491 static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = { 492 .cmd_rcgr = 0x0aa0, 493 .hid_width = 5, 494 .parent_map = gcc_xo_gpll0_map, 495 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 496 .clkr.hw.init = &(struct clk_init_data){ 497 .name = "blsp2_qup3_i2c_apps_clk_src", 498 .parent_data = gcc_xo_gpll0, 499 .num_parents = 2, 500 .ops = &clk_rcg2_ops, 501 }, 502 }; 503 504 static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = { 505 .cmd_rcgr = 0x0a8c, 506 .mnd_width = 8, 507 .hid_width = 5, 508 .parent_map = gcc_xo_gpll0_map, 509 .freq_tbl = ftbl_blspqup_spi_apps_clk_src, 510 .clkr.hw.init = &(struct clk_init_data){ 511 .name = "blsp2_qup3_spi_apps_clk_src", 512 .parent_data = gcc_xo_gpll0, 513 .num_parents = 2, 514 .ops = &clk_rcg2_ops, 515 }, 516 }; 517 518 static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = { 519 .cmd_rcgr = 0x0b20, 520 .hid_width = 5, 521 .parent_map = gcc_xo_gpll0_map, 522 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 523 .clkr.hw.init = &(struct clk_init_data){ 524 .name = "blsp2_qup4_i2c_apps_clk_src", 525 .parent_data = gcc_xo_gpll0, 526 .num_parents = 2, 527 .ops = &clk_rcg2_ops, 528 }, 529 }; 530 531 static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = { 532 .cmd_rcgr = 0x0b0c, 533 .mnd_width = 8, 534 .hid_width = 5, 535 .parent_map = gcc_xo_gpll0_map, 536 .freq_tbl = ftbl_blspqup_spi_apps_clk_src, 537 .clkr.hw.init = &(struct clk_init_data){ 538 .name = "blsp2_qup4_spi_apps_clk_src", 539 .parent_data = gcc_xo_gpll0, 540 .num_parents = 2, 541 .ops = &clk_rcg2_ops, 542 }, 543 }; 544 545 static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = { 546 .cmd_rcgr = 0x0ba0, 547 .hid_width = 5, 548 .parent_map = gcc_xo_gpll0_map, 549 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 550 .clkr.hw.init = &(struct clk_init_data){ 551 .name = "blsp2_qup5_i2c_apps_clk_src", 552 .parent_data = gcc_xo_gpll0, 553 .num_parents = 2, 554 .ops = &clk_rcg2_ops, 555 }, 556 }; 557 558 static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = { 559 .cmd_rcgr = 0x0b8c, 560 .mnd_width = 8, 561 .hid_width = 5, 562 .parent_map = gcc_xo_gpll0_map, 563 .freq_tbl = ftbl_blspqup_spi_apps_clk_src, 564 .clkr.hw.init = &(struct clk_init_data){ 565 .name = "blsp2_qup5_spi_apps_clk_src", 566 .parent_data = gcc_xo_gpll0, 567 .num_parents = 2, 568 .ops = &clk_rcg2_ops, 569 }, 570 }; 571 572 static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = { 573 .cmd_rcgr = 0x0c20, 574 .hid_width = 5, 575 .parent_map = gcc_xo_gpll0_map, 576 .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 577 .clkr.hw.init = &(struct clk_init_data){ 578 .name = "blsp2_qup6_i2c_apps_clk_src", 579 .parent_data = gcc_xo_gpll0, 580 .num_parents = 2, 581 .ops = &clk_rcg2_ops, 582 }, 583 }; 584 585 static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = { 586 .cmd_rcgr = 0x0c0c, 587 .mnd_width = 8, 588 .hid_width = 5, 589 .parent_map = gcc_xo_gpll0_map, 590 .freq_tbl = ftbl_blspqup_spi_apps_clk_src, 591 .clkr.hw.init = &(struct clk_init_data){ 592 .name = "blsp2_qup6_spi_apps_clk_src", 593 .parent_data = gcc_xo_gpll0, 594 .num_parents = 2, 595 .ops = &clk_rcg2_ops, 596 }, 597 }; 598 599 static struct clk_rcg2 blsp2_uart1_apps_clk_src = { 600 .cmd_rcgr = 0x09cc, 601 .mnd_width = 16, 602 .hid_width = 5, 603 .parent_map = gcc_xo_gpll0_map, 604 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 605 .clkr.hw.init = &(struct clk_init_data){ 606 .name = "blsp2_uart1_apps_clk_src", 607 .parent_data = gcc_xo_gpll0, 608 .num_parents = 2, 609 .ops = &clk_rcg2_ops, 610 }, 611 }; 612 613 static struct clk_rcg2 blsp2_uart2_apps_clk_src = { 614 .cmd_rcgr = 0x0a4c, 615 .mnd_width = 16, 616 .hid_width = 5, 617 .parent_map = gcc_xo_gpll0_map, 618 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 619 .clkr.hw.init = &(struct clk_init_data){ 620 .name = "blsp2_uart2_apps_clk_src", 621 .parent_data = gcc_xo_gpll0, 622 .num_parents = 2, 623 .ops = &clk_rcg2_ops, 624 }, 625 }; 626 627 static struct clk_rcg2 blsp2_uart3_apps_clk_src = { 628 .cmd_rcgr = 0x0acc, 629 .mnd_width = 16, 630 .hid_width = 5, 631 .parent_map = gcc_xo_gpll0_map, 632 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 633 .clkr.hw.init = &(struct clk_init_data){ 634 .name = "blsp2_uart3_apps_clk_src", 635 .parent_data = gcc_xo_gpll0, 636 .num_parents = 2, 637 .ops = &clk_rcg2_ops, 638 }, 639 }; 640 641 static struct clk_rcg2 blsp2_uart4_apps_clk_src = { 642 .cmd_rcgr = 0x0b4c, 643 .mnd_width = 16, 644 .hid_width = 5, 645 .parent_map = gcc_xo_gpll0_map, 646 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 647 .clkr.hw.init = &(struct clk_init_data){ 648 .name = "blsp2_uart4_apps_clk_src", 649 .parent_data = gcc_xo_gpll0, 650 .num_parents = 2, 651 .ops = &clk_rcg2_ops, 652 }, 653 }; 654 655 static struct clk_rcg2 blsp2_uart5_apps_clk_src = { 656 .cmd_rcgr = 0x0bcc, 657 .mnd_width = 16, 658 .hid_width = 5, 659 .parent_map = gcc_xo_gpll0_map, 660 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 661 .clkr.hw.init = &(struct clk_init_data){ 662 .name = "blsp2_uart5_apps_clk_src", 663 .parent_data = gcc_xo_gpll0, 664 .num_parents = 2, 665 .ops = &clk_rcg2_ops, 666 }, 667 }; 668 669 static struct clk_rcg2 blsp2_uart6_apps_clk_src = { 670 .cmd_rcgr = 0x0c4c, 671 .mnd_width = 16, 672 .hid_width = 5, 673 .parent_map = gcc_xo_gpll0_map, 674 .freq_tbl = ftbl_blsp_uart_apps_clk_src, 675 .clkr.hw.init = &(struct clk_init_data){ 676 .name = "blsp2_uart6_apps_clk_src", 677 .parent_data = gcc_xo_gpll0, 678 .num_parents = 2, 679 .ops = &clk_rcg2_ops, 680 }, 681 }; 682 683 static struct freq_tbl ftbl_gp1_clk_src[] = { 684 F(19200000, P_XO, 1, 0, 0), 685 F(100000000, P_GPLL0, 6, 0, 0), 686 F(200000000, P_GPLL0, 3, 0, 0), 687 { } 688 }; 689 690 static struct clk_rcg2 gp1_clk_src = { 691 .cmd_rcgr = 0x1904, 692 .mnd_width = 8, 693 .hid_width = 5, 694 .parent_map = gcc_xo_gpll0_map, 695 .freq_tbl = ftbl_gp1_clk_src, 696 .clkr.hw.init = &(struct clk_init_data){ 697 .name = "gp1_clk_src", 698 .parent_data = gcc_xo_gpll0, 699 .num_parents = 2, 700 .ops = &clk_rcg2_ops, 701 }, 702 }; 703 704 static struct freq_tbl ftbl_gp2_clk_src[] = { 705 F(19200000, P_XO, 1, 0, 0), 706 F(100000000, P_GPLL0, 6, 0, 0), 707 F(200000000, P_GPLL0, 3, 0, 0), 708 { } 709 }; 710 711 static struct clk_rcg2 gp2_clk_src = { 712 .cmd_rcgr = 0x1944, 713 .mnd_width = 8, 714 .hid_width = 5, 715 .parent_map = gcc_xo_gpll0_map, 716 .freq_tbl = ftbl_gp2_clk_src, 717 .clkr.hw.init = &(struct clk_init_data){ 718 .name = "gp2_clk_src", 719 .parent_data = gcc_xo_gpll0, 720 .num_parents = 2, 721 .ops = &clk_rcg2_ops, 722 }, 723 }; 724 725 static struct freq_tbl ftbl_gp3_clk_src[] = { 726 F(19200000, P_XO, 1, 0, 0), 727 F(100000000, P_GPLL0, 6, 0, 0), 728 F(200000000, P_GPLL0, 3, 0, 0), 729 { } 730 }; 731 732 static struct clk_rcg2 gp3_clk_src = { 733 .cmd_rcgr = 0x1984, 734 .mnd_width = 8, 735 .hid_width = 5, 736 .parent_map = gcc_xo_gpll0_map, 737 .freq_tbl = ftbl_gp3_clk_src, 738 .clkr.hw.init = &(struct clk_init_data){ 739 .name = "gp3_clk_src", 740 .parent_data = gcc_xo_gpll0, 741 .num_parents = 2, 742 .ops = &clk_rcg2_ops, 743 }, 744 }; 745 746 static struct freq_tbl ftbl_pcie_0_aux_clk_src[] = { 747 F(1011000, P_XO, 1, 1, 19), 748 { } 749 }; 750 751 static struct clk_rcg2 pcie_0_aux_clk_src = { 752 .cmd_rcgr = 0x1b00, 753 .mnd_width = 8, 754 .hid_width = 5, 755 .freq_tbl = ftbl_pcie_0_aux_clk_src, 756 .clkr.hw.init = &(struct clk_init_data){ 757 .name = "pcie_0_aux_clk_src", 758 .parent_data = &(const struct clk_parent_data){ 759 .fw_name = "xo", 760 }, 761 .num_parents = 1, 762 .ops = &clk_rcg2_ops, 763 }, 764 }; 765 766 static struct freq_tbl ftbl_pcie_pipe_clk_src[] = { 767 F(125000000, P_XO, 1, 0, 0), 768 { } 769 }; 770 771 static struct clk_rcg2 pcie_0_pipe_clk_src = { 772 .cmd_rcgr = 0x1adc, 773 .hid_width = 5, 774 .freq_tbl = ftbl_pcie_pipe_clk_src, 775 .clkr.hw.init = &(struct clk_init_data){ 776 .name = "pcie_0_pipe_clk_src", 777 .parent_data = &(const struct clk_parent_data){ 778 .fw_name = "xo", 779 }, 780 .num_parents = 1, 781 .ops = &clk_rcg2_ops, 782 }, 783 }; 784 785 static struct freq_tbl ftbl_pcie_1_aux_clk_src[] = { 786 F(1011000, P_XO, 1, 1, 19), 787 { } 788 }; 789 790 static struct clk_rcg2 pcie_1_aux_clk_src = { 791 .cmd_rcgr = 0x1b80, 792 .mnd_width = 8, 793 .hid_width = 5, 794 .freq_tbl = ftbl_pcie_1_aux_clk_src, 795 .clkr.hw.init = &(struct clk_init_data){ 796 .name = "pcie_1_aux_clk_src", 797 .parent_data = &(const struct clk_parent_data){ 798 .fw_name = "xo", 799 }, 800 .num_parents = 1, 801 .ops = &clk_rcg2_ops, 802 }, 803 }; 804 805 static struct clk_rcg2 pcie_1_pipe_clk_src = { 806 .cmd_rcgr = 0x1b5c, 807 .hid_width = 5, 808 .freq_tbl = ftbl_pcie_pipe_clk_src, 809 .clkr.hw.init = &(struct clk_init_data){ 810 .name = "pcie_1_pipe_clk_src", 811 .parent_data = &(const struct clk_parent_data){ 812 .fw_name = "xo", 813 }, 814 .num_parents = 1, 815 .ops = &clk_rcg2_ops, 816 }, 817 }; 818 819 static struct freq_tbl ftbl_pdm2_clk_src[] = { 820 F(60000000, P_GPLL0, 10, 0, 0), 821 { } 822 }; 823 824 static struct clk_rcg2 pdm2_clk_src = { 825 .cmd_rcgr = 0x0cd0, 826 .hid_width = 5, 827 .parent_map = gcc_xo_gpll0_map, 828 .freq_tbl = ftbl_pdm2_clk_src, 829 .clkr.hw.init = &(struct clk_init_data){ 830 .name = "pdm2_clk_src", 831 .parent_data = gcc_xo_gpll0, 832 .num_parents = 2, 833 .ops = &clk_rcg2_ops, 834 }, 835 }; 836 837 static struct freq_tbl ftbl_sdcc1_apps_clk_src[] = { 838 F(144000, P_XO, 16, 3, 25), 839 F(400000, P_XO, 12, 1, 4), 840 F(20000000, P_GPLL0, 15, 1, 2), 841 F(25000000, P_GPLL0, 12, 1, 2), 842 F(50000000, P_GPLL0, 12, 0, 0), 843 F(100000000, P_GPLL0, 6, 0, 0), 844 F(192000000, P_GPLL4, 2, 0, 0), 845 F(384000000, P_GPLL4, 1, 0, 0), 846 { } 847 }; 848 849 static struct clk_rcg2 sdcc1_apps_clk_src = { 850 .cmd_rcgr = 0x04d0, 851 .mnd_width = 8, 852 .hid_width = 5, 853 .parent_map = gcc_xo_gpll0_gpll4_map, 854 .freq_tbl = ftbl_sdcc1_apps_clk_src, 855 .clkr.hw.init = &(struct clk_init_data){ 856 .name = "sdcc1_apps_clk_src", 857 .parent_data = gcc_xo_gpll0_gpll4, 858 .num_parents = 3, 859 .ops = &clk_rcg2_floor_ops, 860 }, 861 }; 862 863 static struct freq_tbl ftbl_sdcc2_4_apps_clk_src[] = { 864 F(144000, P_XO, 16, 3, 25), 865 F(400000, P_XO, 12, 1, 4), 866 F(20000000, P_GPLL0, 15, 1, 2), 867 F(25000000, P_GPLL0, 12, 1, 2), 868 F(50000000, P_GPLL0, 12, 0, 0), 869 F(100000000, P_GPLL0, 6, 0, 0), 870 F(200000000, P_GPLL0, 3, 0, 0), 871 { } 872 }; 873 874 static struct clk_rcg2 sdcc2_apps_clk_src = { 875 .cmd_rcgr = 0x0510, 876 .mnd_width = 8, 877 .hid_width = 5, 878 .parent_map = gcc_xo_gpll0_map, 879 .freq_tbl = ftbl_sdcc2_4_apps_clk_src, 880 .clkr.hw.init = &(struct clk_init_data){ 881 .name = "sdcc2_apps_clk_src", 882 .parent_data = gcc_xo_gpll0, 883 .num_parents = 2, 884 .ops = &clk_rcg2_floor_ops, 885 }, 886 }; 887 888 static struct clk_rcg2 sdcc3_apps_clk_src = { 889 .cmd_rcgr = 0x0550, 890 .mnd_width = 8, 891 .hid_width = 5, 892 .parent_map = gcc_xo_gpll0_map, 893 .freq_tbl = ftbl_sdcc2_4_apps_clk_src, 894 .clkr.hw.init = &(struct clk_init_data){ 895 .name = "sdcc3_apps_clk_src", 896 .parent_data = gcc_xo_gpll0, 897 .num_parents = 2, 898 .ops = &clk_rcg2_floor_ops, 899 }, 900 }; 901 902 static struct clk_rcg2 sdcc4_apps_clk_src = { 903 .cmd_rcgr = 0x0590, 904 .mnd_width = 8, 905 .hid_width = 5, 906 .parent_map = gcc_xo_gpll0_map, 907 .freq_tbl = ftbl_sdcc2_4_apps_clk_src, 908 .clkr.hw.init = &(struct clk_init_data){ 909 .name = "sdcc4_apps_clk_src", 910 .parent_data = gcc_xo_gpll0, 911 .num_parents = 2, 912 .ops = &clk_rcg2_floor_ops, 913 }, 914 }; 915 916 static struct freq_tbl ftbl_tsif_ref_clk_src[] = { 917 F(105500, P_XO, 1, 1, 182), 918 { } 919 }; 920 921 static struct clk_rcg2 tsif_ref_clk_src = { 922 .cmd_rcgr = 0x0d90, 923 .mnd_width = 8, 924 .hid_width = 5, 925 .freq_tbl = ftbl_tsif_ref_clk_src, 926 .clkr.hw.init = &(struct clk_init_data){ 927 .name = "tsif_ref_clk_src", 928 .parent_data = &(const struct clk_parent_data){ 929 .fw_name = "xo", 930 }, 931 .num_parents = 1, 932 .ops = &clk_rcg2_ops, 933 }, 934 }; 935 936 static struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = { 937 F(19200000, P_XO, 1, 0, 0), 938 F(60000000, P_GPLL0, 10, 0, 0), 939 { } 940 }; 941 942 static struct clk_rcg2 usb30_mock_utmi_clk_src = { 943 .cmd_rcgr = 0x03e8, 944 .hid_width = 5, 945 .parent_map = gcc_xo_gpll0_map, 946 .freq_tbl = ftbl_usb30_mock_utmi_clk_src, 947 .clkr.hw.init = &(struct clk_init_data){ 948 .name = "usb30_mock_utmi_clk_src", 949 .parent_data = gcc_xo_gpll0, 950 .num_parents = 2, 951 .ops = &clk_rcg2_ops, 952 }, 953 }; 954 955 static struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = { 956 F(1200000, P_XO, 16, 0, 0), 957 { } 958 }; 959 960 static struct clk_rcg2 usb3_phy_aux_clk_src = { 961 .cmd_rcgr = 0x1414, 962 .hid_width = 5, 963 .freq_tbl = ftbl_usb3_phy_aux_clk_src, 964 .clkr.hw.init = &(struct clk_init_data){ 965 .name = "usb3_phy_aux_clk_src", 966 .parent_data = &(const struct clk_parent_data){ 967 .fw_name = "xo", 968 }, 969 .num_parents = 1, 970 .ops = &clk_rcg2_ops, 971 }, 972 }; 973 974 static struct freq_tbl ftbl_usb_hs_system_clk_src[] = { 975 F(75000000, P_GPLL0, 8, 0, 0), 976 { } 977 }; 978 979 static struct clk_rcg2 usb_hs_system_clk_src = { 980 .cmd_rcgr = 0x0490, 981 .hid_width = 5, 982 .parent_map = gcc_xo_gpll0_map, 983 .freq_tbl = ftbl_usb_hs_system_clk_src, 984 .clkr.hw.init = &(struct clk_init_data){ 985 .name = "usb_hs_system_clk_src", 986 .parent_data = gcc_xo_gpll0, 987 .num_parents = 2, 988 .ops = &clk_rcg2_ops, 989 }, 990 }; 991 992 static struct clk_branch gcc_blsp1_ahb_clk = { 993 .halt_reg = 0x05c4, 994 .halt_check = BRANCH_HALT_VOTED, 995 .clkr = { 996 .enable_reg = 0x1484, 997 .enable_mask = BIT(17), 998 .hw.init = &(struct clk_init_data){ 999 .name = "gcc_blsp1_ahb_clk", 1000 .ops = &clk_branch2_ops, 1001 }, 1002 }, 1003 }; 1004 1005 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { 1006 .halt_reg = 0x0648, 1007 .clkr = { 1008 .enable_reg = 0x0648, 1009 .enable_mask = BIT(0), 1010 .hw.init = &(struct clk_init_data){ 1011 .name = "gcc_blsp1_qup1_i2c_apps_clk", 1012 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup1_i2c_apps_clk_src.clkr.hw }, 1013 .num_parents = 1, 1014 .flags = CLK_SET_RATE_PARENT, 1015 .ops = &clk_branch2_ops, 1016 }, 1017 }, 1018 }; 1019 1020 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { 1021 .halt_reg = 0x0644, 1022 .clkr = { 1023 .enable_reg = 0x0644, 1024 .enable_mask = BIT(0), 1025 .hw.init = &(struct clk_init_data){ 1026 .name = "gcc_blsp1_qup1_spi_apps_clk", 1027 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup1_spi_apps_clk_src.clkr.hw }, 1028 .num_parents = 1, 1029 .flags = CLK_SET_RATE_PARENT, 1030 .ops = &clk_branch2_ops, 1031 }, 1032 }, 1033 }; 1034 1035 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { 1036 .halt_reg = 0x06c8, 1037 .clkr = { 1038 .enable_reg = 0x06c8, 1039 .enable_mask = BIT(0), 1040 .hw.init = &(struct clk_init_data){ 1041 .name = "gcc_blsp1_qup2_i2c_apps_clk", 1042 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup2_i2c_apps_clk_src.clkr.hw }, 1043 .num_parents = 1, 1044 .flags = CLK_SET_RATE_PARENT, 1045 .ops = &clk_branch2_ops, 1046 }, 1047 }, 1048 }; 1049 1050 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { 1051 .halt_reg = 0x06c4, 1052 .clkr = { 1053 .enable_reg = 0x06c4, 1054 .enable_mask = BIT(0), 1055 .hw.init = &(struct clk_init_data){ 1056 .name = "gcc_blsp1_qup2_spi_apps_clk", 1057 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup2_spi_apps_clk_src.clkr.hw }, 1058 .num_parents = 1, 1059 .flags = CLK_SET_RATE_PARENT, 1060 .ops = &clk_branch2_ops, 1061 }, 1062 }, 1063 }; 1064 1065 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = { 1066 .halt_reg = 0x0748, 1067 .clkr = { 1068 .enable_reg = 0x0748, 1069 .enable_mask = BIT(0), 1070 .hw.init = &(struct clk_init_data){ 1071 .name = "gcc_blsp1_qup3_i2c_apps_clk", 1072 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup3_i2c_apps_clk_src.clkr.hw }, 1073 .num_parents = 1, 1074 .flags = CLK_SET_RATE_PARENT, 1075 .ops = &clk_branch2_ops, 1076 }, 1077 }, 1078 }; 1079 1080 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = { 1081 .halt_reg = 0x0744, 1082 .clkr = { 1083 .enable_reg = 0x0744, 1084 .enable_mask = BIT(0), 1085 .hw.init = &(struct clk_init_data){ 1086 .name = "gcc_blsp1_qup3_spi_apps_clk", 1087 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup3_spi_apps_clk_src.clkr.hw }, 1088 .num_parents = 1, 1089 .flags = CLK_SET_RATE_PARENT, 1090 .ops = &clk_branch2_ops, 1091 }, 1092 }, 1093 }; 1094 1095 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = { 1096 .halt_reg = 0x07c8, 1097 .clkr = { 1098 .enable_reg = 0x07c8, 1099 .enable_mask = BIT(0), 1100 .hw.init = &(struct clk_init_data){ 1101 .name = "gcc_blsp1_qup4_i2c_apps_clk", 1102 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup4_i2c_apps_clk_src.clkr.hw }, 1103 .num_parents = 1, 1104 .flags = CLK_SET_RATE_PARENT, 1105 .ops = &clk_branch2_ops, 1106 }, 1107 }, 1108 }; 1109 1110 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = { 1111 .halt_reg = 0x07c4, 1112 .clkr = { 1113 .enable_reg = 0x07c4, 1114 .enable_mask = BIT(0), 1115 .hw.init = &(struct clk_init_data){ 1116 .name = "gcc_blsp1_qup4_spi_apps_clk", 1117 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup4_spi_apps_clk_src.clkr.hw }, 1118 .num_parents = 1, 1119 .flags = CLK_SET_RATE_PARENT, 1120 .ops = &clk_branch2_ops, 1121 }, 1122 }, 1123 }; 1124 1125 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = { 1126 .halt_reg = 0x0848, 1127 .clkr = { 1128 .enable_reg = 0x0848, 1129 .enable_mask = BIT(0), 1130 .hw.init = &(struct clk_init_data){ 1131 .name = "gcc_blsp1_qup5_i2c_apps_clk", 1132 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup5_i2c_apps_clk_src.clkr.hw }, 1133 .num_parents = 1, 1134 .flags = CLK_SET_RATE_PARENT, 1135 .ops = &clk_branch2_ops, 1136 }, 1137 }, 1138 }; 1139 1140 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = { 1141 .halt_reg = 0x0844, 1142 .clkr = { 1143 .enable_reg = 0x0844, 1144 .enable_mask = BIT(0), 1145 .hw.init = &(struct clk_init_data){ 1146 .name = "gcc_blsp1_qup5_spi_apps_clk", 1147 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup5_spi_apps_clk_src.clkr.hw }, 1148 .num_parents = 1, 1149 .flags = CLK_SET_RATE_PARENT, 1150 .ops = &clk_branch2_ops, 1151 }, 1152 }, 1153 }; 1154 1155 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = { 1156 .halt_reg = 0x08c8, 1157 .clkr = { 1158 .enable_reg = 0x08c8, 1159 .enable_mask = BIT(0), 1160 .hw.init = &(struct clk_init_data){ 1161 .name = "gcc_blsp1_qup6_i2c_apps_clk", 1162 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup6_i2c_apps_clk_src.clkr.hw }, 1163 .num_parents = 1, 1164 .flags = CLK_SET_RATE_PARENT, 1165 .ops = &clk_branch2_ops, 1166 }, 1167 }, 1168 }; 1169 1170 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = { 1171 .halt_reg = 0x08c4, 1172 .clkr = { 1173 .enable_reg = 0x08c4, 1174 .enable_mask = BIT(0), 1175 .hw.init = &(struct clk_init_data){ 1176 .name = "gcc_blsp1_qup6_spi_apps_clk", 1177 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup6_spi_apps_clk_src.clkr.hw }, 1178 .num_parents = 1, 1179 .flags = CLK_SET_RATE_PARENT, 1180 .ops = &clk_branch2_ops, 1181 }, 1182 }, 1183 }; 1184 1185 static struct clk_branch gcc_blsp1_uart1_apps_clk = { 1186 .halt_reg = 0x0684, 1187 .clkr = { 1188 .enable_reg = 0x0684, 1189 .enable_mask = BIT(0), 1190 .hw.init = &(struct clk_init_data){ 1191 .name = "gcc_blsp1_uart1_apps_clk", 1192 .parent_hws = (const struct clk_hw *[]){ &blsp1_uart1_apps_clk_src.clkr.hw }, 1193 .num_parents = 1, 1194 .flags = CLK_SET_RATE_PARENT, 1195 .ops = &clk_branch2_ops, 1196 }, 1197 }, 1198 }; 1199 1200 static struct clk_branch gcc_blsp1_uart2_apps_clk = { 1201 .halt_reg = 0x0704, 1202 .clkr = { 1203 .enable_reg = 0x0704, 1204 .enable_mask = BIT(0), 1205 .hw.init = &(struct clk_init_data){ 1206 .name = "gcc_blsp1_uart2_apps_clk", 1207 .parent_hws = (const struct clk_hw *[]){ &blsp1_uart2_apps_clk_src.clkr.hw }, 1208 .num_parents = 1, 1209 .flags = CLK_SET_RATE_PARENT, 1210 .ops = &clk_branch2_ops, 1211 }, 1212 }, 1213 }; 1214 1215 static struct clk_branch gcc_blsp1_uart3_apps_clk = { 1216 .halt_reg = 0x0784, 1217 .clkr = { 1218 .enable_reg = 0x0784, 1219 .enable_mask = BIT(0), 1220 .hw.init = &(struct clk_init_data){ 1221 .name = "gcc_blsp1_uart3_apps_clk", 1222 .parent_hws = (const struct clk_hw *[]){ &blsp1_uart3_apps_clk_src.clkr.hw }, 1223 .num_parents = 1, 1224 .flags = CLK_SET_RATE_PARENT, 1225 .ops = &clk_branch2_ops, 1226 }, 1227 }, 1228 }; 1229 1230 static struct clk_branch gcc_blsp1_uart4_apps_clk = { 1231 .halt_reg = 0x0804, 1232 .clkr = { 1233 .enable_reg = 0x0804, 1234 .enable_mask = BIT(0), 1235 .hw.init = &(struct clk_init_data){ 1236 .name = "gcc_blsp1_uart4_apps_clk", 1237 .parent_hws = (const struct clk_hw *[]){ &blsp1_uart4_apps_clk_src.clkr.hw }, 1238 .num_parents = 1, 1239 .flags = CLK_SET_RATE_PARENT, 1240 .ops = &clk_branch2_ops, 1241 }, 1242 }, 1243 }; 1244 1245 static struct clk_branch gcc_blsp1_uart5_apps_clk = { 1246 .halt_reg = 0x0884, 1247 .clkr = { 1248 .enable_reg = 0x0884, 1249 .enable_mask = BIT(0), 1250 .hw.init = &(struct clk_init_data){ 1251 .name = "gcc_blsp1_uart5_apps_clk", 1252 .parent_hws = (const struct clk_hw *[]){ &blsp1_uart5_apps_clk_src.clkr.hw }, 1253 .num_parents = 1, 1254 .flags = CLK_SET_RATE_PARENT, 1255 .ops = &clk_branch2_ops, 1256 }, 1257 }, 1258 }; 1259 1260 static struct clk_branch gcc_blsp1_uart6_apps_clk = { 1261 .halt_reg = 0x0904, 1262 .clkr = { 1263 .enable_reg = 0x0904, 1264 .enable_mask = BIT(0), 1265 .hw.init = &(struct clk_init_data){ 1266 .name = "gcc_blsp1_uart6_apps_clk", 1267 .parent_hws = (const struct clk_hw *[]){ &blsp1_uart6_apps_clk_src.clkr.hw }, 1268 .num_parents = 1, 1269 .flags = CLK_SET_RATE_PARENT, 1270 .ops = &clk_branch2_ops, 1271 }, 1272 }, 1273 }; 1274 1275 static struct clk_branch gcc_blsp2_ahb_clk = { 1276 .halt_reg = 0x0944, 1277 .halt_check = BRANCH_HALT_VOTED, 1278 .clkr = { 1279 .enable_reg = 0x1484, 1280 .enable_mask = BIT(15), 1281 .hw.init = &(struct clk_init_data){ 1282 .name = "gcc_blsp2_ahb_clk", 1283 .ops = &clk_branch2_ops, 1284 }, 1285 }, 1286 }; 1287 1288 static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = { 1289 .halt_reg = 0x0988, 1290 .clkr = { 1291 .enable_reg = 0x0988, 1292 .enable_mask = BIT(0), 1293 .hw.init = &(struct clk_init_data){ 1294 .name = "gcc_blsp2_qup1_i2c_apps_clk", 1295 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup1_i2c_apps_clk_src.clkr.hw }, 1296 .num_parents = 1, 1297 .flags = CLK_SET_RATE_PARENT, 1298 .ops = &clk_branch2_ops, 1299 }, 1300 }, 1301 }; 1302 1303 static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = { 1304 .halt_reg = 0x0984, 1305 .clkr = { 1306 .enable_reg = 0x0984, 1307 .enable_mask = BIT(0), 1308 .hw.init = &(struct clk_init_data){ 1309 .name = "gcc_blsp2_qup1_spi_apps_clk", 1310 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup1_spi_apps_clk_src.clkr.hw }, 1311 .num_parents = 1, 1312 .flags = CLK_SET_RATE_PARENT, 1313 .ops = &clk_branch2_ops, 1314 }, 1315 }, 1316 }; 1317 1318 static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = { 1319 .halt_reg = 0x0a08, 1320 .clkr = { 1321 .enable_reg = 0x0a08, 1322 .enable_mask = BIT(0), 1323 .hw.init = &(struct clk_init_data){ 1324 .name = "gcc_blsp2_qup2_i2c_apps_clk", 1325 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup2_i2c_apps_clk_src.clkr.hw }, 1326 .num_parents = 1, 1327 .flags = CLK_SET_RATE_PARENT, 1328 .ops = &clk_branch2_ops, 1329 }, 1330 }, 1331 }; 1332 1333 static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = { 1334 .halt_reg = 0x0a04, 1335 .clkr = { 1336 .enable_reg = 0x0a04, 1337 .enable_mask = BIT(0), 1338 .hw.init = &(struct clk_init_data){ 1339 .name = "gcc_blsp2_qup2_spi_apps_clk", 1340 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup2_spi_apps_clk_src.clkr.hw }, 1341 .num_parents = 1, 1342 .flags = CLK_SET_RATE_PARENT, 1343 .ops = &clk_branch2_ops, 1344 }, 1345 }, 1346 }; 1347 1348 static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = { 1349 .halt_reg = 0x0a88, 1350 .clkr = { 1351 .enable_reg = 0x0a88, 1352 .enable_mask = BIT(0), 1353 .hw.init = &(struct clk_init_data){ 1354 .name = "gcc_blsp2_qup3_i2c_apps_clk", 1355 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup3_i2c_apps_clk_src.clkr.hw }, 1356 .num_parents = 1, 1357 .flags = CLK_SET_RATE_PARENT, 1358 .ops = &clk_branch2_ops, 1359 }, 1360 }, 1361 }; 1362 1363 static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = { 1364 .halt_reg = 0x0a84, 1365 .clkr = { 1366 .enable_reg = 0x0a84, 1367 .enable_mask = BIT(0), 1368 .hw.init = &(struct clk_init_data){ 1369 .name = "gcc_blsp2_qup3_spi_apps_clk", 1370 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup3_spi_apps_clk_src.clkr.hw }, 1371 .num_parents = 1, 1372 .flags = CLK_SET_RATE_PARENT, 1373 .ops = &clk_branch2_ops, 1374 }, 1375 }, 1376 }; 1377 1378 static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = { 1379 .halt_reg = 0x0b08, 1380 .clkr = { 1381 .enable_reg = 0x0b08, 1382 .enable_mask = BIT(0), 1383 .hw.init = &(struct clk_init_data){ 1384 .name = "gcc_blsp2_qup4_i2c_apps_clk", 1385 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup4_i2c_apps_clk_src.clkr.hw }, 1386 .num_parents = 1, 1387 .flags = CLK_SET_RATE_PARENT, 1388 .ops = &clk_branch2_ops, 1389 }, 1390 }, 1391 }; 1392 1393 static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = { 1394 .halt_reg = 0x0b04, 1395 .clkr = { 1396 .enable_reg = 0x0b04, 1397 .enable_mask = BIT(0), 1398 .hw.init = &(struct clk_init_data){ 1399 .name = "gcc_blsp2_qup4_spi_apps_clk", 1400 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup4_spi_apps_clk_src.clkr.hw }, 1401 .num_parents = 1, 1402 .flags = CLK_SET_RATE_PARENT, 1403 .ops = &clk_branch2_ops, 1404 }, 1405 }, 1406 }; 1407 1408 static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = { 1409 .halt_reg = 0x0b88, 1410 .clkr = { 1411 .enable_reg = 0x0b88, 1412 .enable_mask = BIT(0), 1413 .hw.init = &(struct clk_init_data){ 1414 .name = "gcc_blsp2_qup5_i2c_apps_clk", 1415 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup5_i2c_apps_clk_src.clkr.hw }, 1416 .num_parents = 1, 1417 .flags = CLK_SET_RATE_PARENT, 1418 .ops = &clk_branch2_ops, 1419 }, 1420 }, 1421 }; 1422 1423 static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = { 1424 .halt_reg = 0x0b84, 1425 .clkr = { 1426 .enable_reg = 0x0b84, 1427 .enable_mask = BIT(0), 1428 .hw.init = &(struct clk_init_data){ 1429 .name = "gcc_blsp2_qup5_spi_apps_clk", 1430 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup5_spi_apps_clk_src.clkr.hw }, 1431 .num_parents = 1, 1432 .flags = CLK_SET_RATE_PARENT, 1433 .ops = &clk_branch2_ops, 1434 }, 1435 }, 1436 }; 1437 1438 static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = { 1439 .halt_reg = 0x0c08, 1440 .clkr = { 1441 .enable_reg = 0x0c08, 1442 .enable_mask = BIT(0), 1443 .hw.init = &(struct clk_init_data){ 1444 .name = "gcc_blsp2_qup6_i2c_apps_clk", 1445 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup6_i2c_apps_clk_src.clkr.hw }, 1446 .num_parents = 1, 1447 .flags = CLK_SET_RATE_PARENT, 1448 .ops = &clk_branch2_ops, 1449 }, 1450 }, 1451 }; 1452 1453 static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = { 1454 .halt_reg = 0x0c04, 1455 .clkr = { 1456 .enable_reg = 0x0c04, 1457 .enable_mask = BIT(0), 1458 .hw.init = &(struct clk_init_data){ 1459 .name = "gcc_blsp2_qup6_spi_apps_clk", 1460 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup6_spi_apps_clk_src.clkr.hw }, 1461 .num_parents = 1, 1462 .flags = CLK_SET_RATE_PARENT, 1463 .ops = &clk_branch2_ops, 1464 }, 1465 }, 1466 }; 1467 1468 static struct clk_branch gcc_blsp2_uart1_apps_clk = { 1469 .halt_reg = 0x09c4, 1470 .clkr = { 1471 .enable_reg = 0x09c4, 1472 .enable_mask = BIT(0), 1473 .hw.init = &(struct clk_init_data){ 1474 .name = "gcc_blsp2_uart1_apps_clk", 1475 .parent_hws = (const struct clk_hw *[]){ &blsp2_uart1_apps_clk_src.clkr.hw }, 1476 .num_parents = 1, 1477 .flags = CLK_SET_RATE_PARENT, 1478 .ops = &clk_branch2_ops, 1479 }, 1480 }, 1481 }; 1482 1483 static struct clk_branch gcc_blsp2_uart2_apps_clk = { 1484 .halt_reg = 0x0a44, 1485 .clkr = { 1486 .enable_reg = 0x0a44, 1487 .enable_mask = BIT(0), 1488 .hw.init = &(struct clk_init_data){ 1489 .name = "gcc_blsp2_uart2_apps_clk", 1490 .parent_hws = (const struct clk_hw *[]){ &blsp2_uart2_apps_clk_src.clkr.hw }, 1491 .num_parents = 1, 1492 .flags = CLK_SET_RATE_PARENT, 1493 .ops = &clk_branch2_ops, 1494 }, 1495 }, 1496 }; 1497 1498 static struct clk_branch gcc_blsp2_uart3_apps_clk = { 1499 .halt_reg = 0x0ac4, 1500 .clkr = { 1501 .enable_reg = 0x0ac4, 1502 .enable_mask = BIT(0), 1503 .hw.init = &(struct clk_init_data){ 1504 .name = "gcc_blsp2_uart3_apps_clk", 1505 .parent_hws = (const struct clk_hw *[]){ &blsp2_uart3_apps_clk_src.clkr.hw }, 1506 .num_parents = 1, 1507 .flags = CLK_SET_RATE_PARENT, 1508 .ops = &clk_branch2_ops, 1509 }, 1510 }, 1511 }; 1512 1513 static struct clk_branch gcc_blsp2_uart4_apps_clk = { 1514 .halt_reg = 0x0b44, 1515 .clkr = { 1516 .enable_reg = 0x0b44, 1517 .enable_mask = BIT(0), 1518 .hw.init = &(struct clk_init_data){ 1519 .name = "gcc_blsp2_uart4_apps_clk", 1520 .parent_hws = (const struct clk_hw *[]){ &blsp2_uart4_apps_clk_src.clkr.hw }, 1521 .num_parents = 1, 1522 .flags = CLK_SET_RATE_PARENT, 1523 .ops = &clk_branch2_ops, 1524 }, 1525 }, 1526 }; 1527 1528 static struct clk_branch gcc_blsp2_uart5_apps_clk = { 1529 .halt_reg = 0x0bc4, 1530 .clkr = { 1531 .enable_reg = 0x0bc4, 1532 .enable_mask = BIT(0), 1533 .hw.init = &(struct clk_init_data){ 1534 .name = "gcc_blsp2_uart5_apps_clk", 1535 .parent_hws = (const struct clk_hw *[]){ &blsp2_uart5_apps_clk_src.clkr.hw }, 1536 .num_parents = 1, 1537 .flags = CLK_SET_RATE_PARENT, 1538 .ops = &clk_branch2_ops, 1539 }, 1540 }, 1541 }; 1542 1543 static struct clk_branch gcc_blsp2_uart6_apps_clk = { 1544 .halt_reg = 0x0c44, 1545 .clkr = { 1546 .enable_reg = 0x0c44, 1547 .enable_mask = BIT(0), 1548 .hw.init = &(struct clk_init_data){ 1549 .name = "gcc_blsp2_uart6_apps_clk", 1550 .parent_hws = (const struct clk_hw *[]){ &blsp2_uart6_apps_clk_src.clkr.hw }, 1551 .num_parents = 1, 1552 .flags = CLK_SET_RATE_PARENT, 1553 .ops = &clk_branch2_ops, 1554 }, 1555 }, 1556 }; 1557 1558 static struct clk_branch gcc_gp1_clk = { 1559 .halt_reg = 0x1900, 1560 .clkr = { 1561 .enable_reg = 0x1900, 1562 .enable_mask = BIT(0), 1563 .hw.init = &(struct clk_init_data){ 1564 .name = "gcc_gp1_clk", 1565 .parent_hws = (const struct clk_hw *[]){ &gp1_clk_src.clkr.hw }, 1566 .num_parents = 1, 1567 .flags = CLK_SET_RATE_PARENT, 1568 .ops = &clk_branch2_ops, 1569 }, 1570 }, 1571 }; 1572 1573 static struct clk_branch gcc_gp2_clk = { 1574 .halt_reg = 0x1940, 1575 .clkr = { 1576 .enable_reg = 0x1940, 1577 .enable_mask = BIT(0), 1578 .hw.init = &(struct clk_init_data){ 1579 .name = "gcc_gp2_clk", 1580 .parent_hws = (const struct clk_hw *[]){ &gp2_clk_src.clkr.hw }, 1581 .num_parents = 1, 1582 .flags = CLK_SET_RATE_PARENT, 1583 .ops = &clk_branch2_ops, 1584 }, 1585 }, 1586 }; 1587 1588 static struct clk_branch gcc_gp3_clk = { 1589 .halt_reg = 0x1980, 1590 .clkr = { 1591 .enable_reg = 0x1980, 1592 .enable_mask = BIT(0), 1593 .hw.init = &(struct clk_init_data){ 1594 .name = "gcc_gp3_clk", 1595 .parent_hws = (const struct clk_hw *[]){ &gp3_clk_src.clkr.hw }, 1596 .num_parents = 1, 1597 .flags = CLK_SET_RATE_PARENT, 1598 .ops = &clk_branch2_ops, 1599 }, 1600 }, 1601 }; 1602 1603 static struct clk_branch gcc_lpass_q6_axi_clk = { 1604 .halt_reg = 0x0280, 1605 .clkr = { 1606 .enable_reg = 0x0280, 1607 .enable_mask = BIT(0), 1608 .hw.init = &(struct clk_init_data){ 1609 .name = "gcc_lpass_q6_axi_clk", 1610 .ops = &clk_branch2_ops, 1611 }, 1612 }, 1613 }; 1614 1615 static struct clk_branch gcc_mss_q6_bimc_axi_clk = { 1616 .halt_reg = 0x0284, 1617 .clkr = { 1618 .enable_reg = 0x0284, 1619 .enable_mask = BIT(0), 1620 .hw.init = &(struct clk_init_data){ 1621 .name = "gcc_mss_q6_bimc_axi_clk", 1622 .ops = &clk_branch2_ops, 1623 }, 1624 }, 1625 }; 1626 1627 static struct clk_branch gcc_pcie_0_aux_clk = { 1628 .halt_reg = 0x1ad4, 1629 .clkr = { 1630 .enable_reg = 0x1ad4, 1631 .enable_mask = BIT(0), 1632 .hw.init = &(struct clk_init_data){ 1633 .name = "gcc_pcie_0_aux_clk", 1634 .parent_hws = (const struct clk_hw *[]){ &pcie_0_aux_clk_src.clkr.hw }, 1635 .num_parents = 1, 1636 .flags = CLK_SET_RATE_PARENT, 1637 .ops = &clk_branch2_ops, 1638 }, 1639 }, 1640 }; 1641 1642 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { 1643 .halt_reg = 0x1ad0, 1644 .clkr = { 1645 .enable_reg = 0x1ad0, 1646 .enable_mask = BIT(0), 1647 .hw.init = &(struct clk_init_data){ 1648 .name = "gcc_pcie_0_cfg_ahb_clk", 1649 .ops = &clk_branch2_ops, 1650 }, 1651 }, 1652 }; 1653 1654 static struct clk_branch gcc_pcie_0_mstr_axi_clk = { 1655 .halt_reg = 0x1acc, 1656 .clkr = { 1657 .enable_reg = 0x1acc, 1658 .enable_mask = BIT(0), 1659 .hw.init = &(struct clk_init_data){ 1660 .name = "gcc_pcie_0_mstr_axi_clk", 1661 .ops = &clk_branch2_ops, 1662 }, 1663 }, 1664 }; 1665 1666 static struct clk_branch gcc_pcie_0_pipe_clk = { 1667 .halt_reg = 0x1ad8, 1668 .halt_check = BRANCH_HALT_DELAY, 1669 .clkr = { 1670 .enable_reg = 0x1ad8, 1671 .enable_mask = BIT(0), 1672 .hw.init = &(struct clk_init_data){ 1673 .name = "gcc_pcie_0_pipe_clk", 1674 .parent_hws = (const struct clk_hw *[]){ &pcie_0_pipe_clk_src.clkr.hw }, 1675 .num_parents = 1, 1676 .flags = CLK_SET_RATE_PARENT, 1677 .ops = &clk_branch2_ops, 1678 }, 1679 }, 1680 }; 1681 1682 static struct clk_branch gcc_pcie_0_slv_axi_clk = { 1683 .halt_reg = 0x1ac8, 1684 .halt_check = BRANCH_HALT_DELAY, 1685 .clkr = { 1686 .enable_reg = 0x1ac8, 1687 .enable_mask = BIT(0), 1688 .hw.init = &(struct clk_init_data){ 1689 .name = "gcc_pcie_0_slv_axi_clk", 1690 .ops = &clk_branch2_ops, 1691 }, 1692 }, 1693 }; 1694 1695 static struct clk_branch gcc_pcie_1_aux_clk = { 1696 .halt_reg = 0x1b54, 1697 .clkr = { 1698 .enable_reg = 0x1b54, 1699 .enable_mask = BIT(0), 1700 .hw.init = &(struct clk_init_data){ 1701 .name = "gcc_pcie_1_aux_clk", 1702 .parent_hws = (const struct clk_hw *[]){ &pcie_1_aux_clk_src.clkr.hw }, 1703 .num_parents = 1, 1704 .flags = CLK_SET_RATE_PARENT, 1705 .ops = &clk_branch2_ops, 1706 }, 1707 }, 1708 }; 1709 1710 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { 1711 .halt_reg = 0x1b54, 1712 .clkr = { 1713 .enable_reg = 0x1b54, 1714 .enable_mask = BIT(0), 1715 .hw.init = &(struct clk_init_data){ 1716 .name = "gcc_pcie_1_cfg_ahb_clk", 1717 .ops = &clk_branch2_ops, 1718 }, 1719 }, 1720 }; 1721 1722 static struct clk_branch gcc_pcie_1_mstr_axi_clk = { 1723 .halt_reg = 0x1b50, 1724 .clkr = { 1725 .enable_reg = 0x1b50, 1726 .enable_mask = BIT(0), 1727 .hw.init = &(struct clk_init_data){ 1728 .name = "gcc_pcie_1_mstr_axi_clk", 1729 .ops = &clk_branch2_ops, 1730 }, 1731 }, 1732 }; 1733 1734 static struct clk_branch gcc_pcie_1_pipe_clk = { 1735 .halt_reg = 0x1b58, 1736 .halt_check = BRANCH_HALT_DELAY, 1737 .clkr = { 1738 .enable_reg = 0x1b58, 1739 .enable_mask = BIT(0), 1740 .hw.init = &(struct clk_init_data){ 1741 .name = "gcc_pcie_1_pipe_clk", 1742 .parent_hws = (const struct clk_hw *[]){ &pcie_1_pipe_clk_src.clkr.hw }, 1743 .num_parents = 1, 1744 .flags = CLK_SET_RATE_PARENT, 1745 .ops = &clk_branch2_ops, 1746 }, 1747 }, 1748 }; 1749 1750 static struct clk_branch gcc_pcie_1_slv_axi_clk = { 1751 .halt_reg = 0x1b48, 1752 .clkr = { 1753 .enable_reg = 0x1b48, 1754 .enable_mask = BIT(0), 1755 .hw.init = &(struct clk_init_data){ 1756 .name = "gcc_pcie_1_slv_axi_clk", 1757 .ops = &clk_branch2_ops, 1758 }, 1759 }, 1760 }; 1761 1762 static struct clk_branch gcc_pdm2_clk = { 1763 .halt_reg = 0x0ccc, 1764 .clkr = { 1765 .enable_reg = 0x0ccc, 1766 .enable_mask = BIT(0), 1767 .hw.init = &(struct clk_init_data){ 1768 .name = "gcc_pdm2_clk", 1769 .parent_hws = (const struct clk_hw *[]){ &pdm2_clk_src.clkr.hw }, 1770 .num_parents = 1, 1771 .flags = CLK_SET_RATE_PARENT, 1772 .ops = &clk_branch2_ops, 1773 }, 1774 }, 1775 }; 1776 1777 static struct clk_branch gcc_pdm_ahb_clk = { 1778 .halt_reg = 0x0cc4, 1779 .clkr = { 1780 .enable_reg = 0x0cc4, 1781 .enable_mask = BIT(0), 1782 .hw.init = &(struct clk_init_data){ 1783 .name = "gcc_pdm_ahb_clk", 1784 .ops = &clk_branch2_ops, 1785 }, 1786 }, 1787 }; 1788 1789 static struct clk_branch gcc_sdcc1_apps_clk = { 1790 .halt_reg = 0x04c4, 1791 .clkr = { 1792 .enable_reg = 0x04c4, 1793 .enable_mask = BIT(0), 1794 .hw.init = &(struct clk_init_data){ 1795 .name = "gcc_sdcc1_apps_clk", 1796 .parent_hws = (const struct clk_hw *[]){ &sdcc1_apps_clk_src.clkr.hw }, 1797 .num_parents = 1, 1798 .flags = CLK_SET_RATE_PARENT, 1799 .ops = &clk_branch2_ops, 1800 }, 1801 }, 1802 }; 1803 1804 static struct clk_branch gcc_sdcc1_ahb_clk = { 1805 .halt_reg = 0x04c8, 1806 .clkr = { 1807 .enable_reg = 0x04c8, 1808 .enable_mask = BIT(0), 1809 .hw.init = &(struct clk_init_data){ 1810 .name = "gcc_sdcc1_ahb_clk", 1811 .parent_names = (const char *[]){ 1812 "periph_noc_clk_src", 1813 }, 1814 .num_parents = 1, 1815 .ops = &clk_branch2_ops, 1816 }, 1817 }, 1818 }; 1819 1820 static struct clk_branch gcc_sdcc2_ahb_clk = { 1821 .halt_reg = 0x0508, 1822 .clkr = { 1823 .enable_reg = 0x0508, 1824 .enable_mask = BIT(0), 1825 .hw.init = &(struct clk_init_data){ 1826 .name = "gcc_sdcc2_ahb_clk", 1827 .parent_names = (const char *[]){ 1828 "periph_noc_clk_src", 1829 }, 1830 .num_parents = 1, 1831 .ops = &clk_branch2_ops, 1832 }, 1833 }, 1834 }; 1835 1836 static struct clk_branch gcc_sdcc2_apps_clk = { 1837 .halt_reg = 0x0504, 1838 .clkr = { 1839 .enable_reg = 0x0504, 1840 .enable_mask = BIT(0), 1841 .hw.init = &(struct clk_init_data){ 1842 .name = "gcc_sdcc2_apps_clk", 1843 .parent_hws = (const struct clk_hw *[]){ &sdcc2_apps_clk_src.clkr.hw }, 1844 .num_parents = 1, 1845 .flags = CLK_SET_RATE_PARENT, 1846 .ops = &clk_branch2_ops, 1847 }, 1848 }, 1849 }; 1850 1851 static struct clk_branch gcc_sdcc3_ahb_clk = { 1852 .halt_reg = 0x0548, 1853 .clkr = { 1854 .enable_reg = 0x0548, 1855 .enable_mask = BIT(0), 1856 .hw.init = &(struct clk_init_data){ 1857 .name = "gcc_sdcc3_ahb_clk", 1858 .parent_names = (const char *[]){ 1859 "periph_noc_clk_src", 1860 }, 1861 .num_parents = 1, 1862 .ops = &clk_branch2_ops, 1863 }, 1864 }, 1865 }; 1866 1867 static struct clk_branch gcc_sdcc3_apps_clk = { 1868 .halt_reg = 0x0544, 1869 .clkr = { 1870 .enable_reg = 0x0544, 1871 .enable_mask = BIT(0), 1872 .hw.init = &(struct clk_init_data){ 1873 .name = "gcc_sdcc3_apps_clk", 1874 .parent_hws = (const struct clk_hw *[]){ &sdcc3_apps_clk_src.clkr.hw }, 1875 .num_parents = 1, 1876 .flags = CLK_SET_RATE_PARENT, 1877 .ops = &clk_branch2_ops, 1878 }, 1879 }, 1880 }; 1881 1882 static struct clk_branch gcc_sdcc4_ahb_clk = { 1883 .halt_reg = 0x0588, 1884 .clkr = { 1885 .enable_reg = 0x0588, 1886 .enable_mask = BIT(0), 1887 .hw.init = &(struct clk_init_data){ 1888 .name = "gcc_sdcc4_ahb_clk", 1889 .parent_names = (const char *[]){ 1890 "periph_noc_clk_src", 1891 }, 1892 .num_parents = 1, 1893 .ops = &clk_branch2_ops, 1894 }, 1895 }, 1896 }; 1897 1898 static struct clk_branch gcc_sdcc4_apps_clk = { 1899 .halt_reg = 0x0584, 1900 .clkr = { 1901 .enable_reg = 0x0584, 1902 .enable_mask = BIT(0), 1903 .hw.init = &(struct clk_init_data){ 1904 .name = "gcc_sdcc4_apps_clk", 1905 .parent_hws = (const struct clk_hw *[]){ &sdcc4_apps_clk_src.clkr.hw }, 1906 .num_parents = 1, 1907 .flags = CLK_SET_RATE_PARENT, 1908 .ops = &clk_branch2_ops, 1909 }, 1910 }, 1911 }; 1912 1913 static struct clk_branch gcc_sys_noc_ufs_axi_clk = { 1914 .halt_reg = 0x1d7c, 1915 .clkr = { 1916 .enable_reg = 0x1d7c, 1917 .enable_mask = BIT(0), 1918 .hw.init = &(struct clk_init_data){ 1919 .name = "gcc_sys_noc_ufs_axi_clk", 1920 .parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw }, 1921 .num_parents = 1, 1922 .flags = CLK_SET_RATE_PARENT, 1923 .ops = &clk_branch2_ops, 1924 }, 1925 }, 1926 }; 1927 1928 static struct clk_branch gcc_sys_noc_usb3_axi_clk = { 1929 .halt_reg = 0x03fc, 1930 .clkr = { 1931 .enable_reg = 0x03fc, 1932 .enable_mask = BIT(0), 1933 .hw.init = &(struct clk_init_data){ 1934 .name = "gcc_sys_noc_usb3_axi_clk", 1935 .parent_hws = (const struct clk_hw *[]){ &usb30_master_clk_src.clkr.hw }, 1936 .num_parents = 1, 1937 .flags = CLK_SET_RATE_PARENT, 1938 .ops = &clk_branch2_ops, 1939 }, 1940 }, 1941 }; 1942 1943 static struct clk_branch gcc_tsif_ahb_clk = { 1944 .halt_reg = 0x0d84, 1945 .clkr = { 1946 .enable_reg = 0x0d84, 1947 .enable_mask = BIT(0), 1948 .hw.init = &(struct clk_init_data){ 1949 .name = "gcc_tsif_ahb_clk", 1950 .ops = &clk_branch2_ops, 1951 }, 1952 }, 1953 }; 1954 1955 static struct clk_branch gcc_tsif_ref_clk = { 1956 .halt_reg = 0x0d88, 1957 .clkr = { 1958 .enable_reg = 0x0d88, 1959 .enable_mask = BIT(0), 1960 .hw.init = &(struct clk_init_data){ 1961 .name = "gcc_tsif_ref_clk", 1962 .parent_hws = (const struct clk_hw *[]){ &tsif_ref_clk_src.clkr.hw }, 1963 .num_parents = 1, 1964 .flags = CLK_SET_RATE_PARENT, 1965 .ops = &clk_branch2_ops, 1966 }, 1967 }, 1968 }; 1969 1970 static struct clk_branch gcc_ufs_ahb_clk = { 1971 .halt_reg = 0x1d4c, 1972 .clkr = { 1973 .enable_reg = 0x1d4c, 1974 .enable_mask = BIT(0), 1975 .hw.init = &(struct clk_init_data){ 1976 .name = "gcc_ufs_ahb_clk", 1977 .ops = &clk_branch2_ops, 1978 }, 1979 }, 1980 }; 1981 1982 static struct clk_branch gcc_ufs_axi_clk = { 1983 .halt_reg = 0x1d48, 1984 .clkr = { 1985 .enable_reg = 0x1d48, 1986 .enable_mask = BIT(0), 1987 .hw.init = &(struct clk_init_data){ 1988 .name = "gcc_ufs_axi_clk", 1989 .parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw }, 1990 .num_parents = 1, 1991 .flags = CLK_SET_RATE_PARENT, 1992 .ops = &clk_branch2_ops, 1993 }, 1994 }, 1995 }; 1996 1997 static struct clk_branch gcc_ufs_rx_cfg_clk = { 1998 .halt_reg = 0x1d54, 1999 .clkr = { 2000 .enable_reg = 0x1d54, 2001 .enable_mask = BIT(0), 2002 .hw.init = &(struct clk_init_data){ 2003 .name = "gcc_ufs_rx_cfg_clk", 2004 .parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw }, 2005 .num_parents = 1, 2006 .flags = CLK_SET_RATE_PARENT, 2007 .ops = &clk_branch2_ops, 2008 }, 2009 }, 2010 }; 2011 2012 static struct clk_branch gcc_ufs_rx_symbol_0_clk = { 2013 .halt_reg = 0x1d60, 2014 .halt_check = BRANCH_HALT_DELAY, 2015 .clkr = { 2016 .enable_reg = 0x1d60, 2017 .enable_mask = BIT(0), 2018 .hw.init = &(struct clk_init_data){ 2019 .name = "gcc_ufs_rx_symbol_0_clk", 2020 .ops = &clk_branch2_ops, 2021 }, 2022 }, 2023 }; 2024 2025 static struct clk_branch gcc_ufs_rx_symbol_1_clk = { 2026 .halt_reg = 0x1d64, 2027 .halt_check = BRANCH_HALT_DELAY, 2028 .clkr = { 2029 .enable_reg = 0x1d64, 2030 .enable_mask = BIT(0), 2031 .hw.init = &(struct clk_init_data){ 2032 .name = "gcc_ufs_rx_symbol_1_clk", 2033 .ops = &clk_branch2_ops, 2034 }, 2035 }, 2036 }; 2037 2038 static struct clk_branch gcc_ufs_tx_cfg_clk = { 2039 .halt_reg = 0x1d50, 2040 .clkr = { 2041 .enable_reg = 0x1d50, 2042 .enable_mask = BIT(0), 2043 .hw.init = &(struct clk_init_data){ 2044 .name = "gcc_ufs_tx_cfg_clk", 2045 .parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw }, 2046 .num_parents = 1, 2047 .flags = CLK_SET_RATE_PARENT, 2048 .ops = &clk_branch2_ops, 2049 }, 2050 }, 2051 }; 2052 2053 static struct clk_branch gcc_ufs_tx_symbol_0_clk = { 2054 .halt_reg = 0x1d58, 2055 .halt_check = BRANCH_HALT_DELAY, 2056 .clkr = { 2057 .enable_reg = 0x1d58, 2058 .enable_mask = BIT(0), 2059 .hw.init = &(struct clk_init_data){ 2060 .name = "gcc_ufs_tx_symbol_0_clk", 2061 .ops = &clk_branch2_ops, 2062 }, 2063 }, 2064 }; 2065 2066 static struct clk_branch gcc_ufs_tx_symbol_1_clk = { 2067 .halt_reg = 0x1d5c, 2068 .halt_check = BRANCH_HALT_DELAY, 2069 .clkr = { 2070 .enable_reg = 0x1d5c, 2071 .enable_mask = BIT(0), 2072 .hw.init = &(struct clk_init_data){ 2073 .name = "gcc_ufs_tx_symbol_1_clk", 2074 .ops = &clk_branch2_ops, 2075 }, 2076 }, 2077 }; 2078 2079 static struct clk_branch gcc_usb2_hs_phy_sleep_clk = { 2080 .halt_reg = 0x04ac, 2081 .clkr = { 2082 .enable_reg = 0x04ac, 2083 .enable_mask = BIT(0), 2084 .hw.init = &(struct clk_init_data){ 2085 .name = "gcc_usb2_hs_phy_sleep_clk", 2086 .parent_data = &(const struct clk_parent_data){ 2087 .fw_name = "sleep", 2088 .name = "sleep" 2089 }, 2090 .num_parents = 1, 2091 .ops = &clk_branch2_ops, 2092 }, 2093 }, 2094 }; 2095 2096 static struct clk_branch gcc_usb30_master_clk = { 2097 .halt_reg = 0x03c8, 2098 .clkr = { 2099 .enable_reg = 0x03c8, 2100 .enable_mask = BIT(0), 2101 .hw.init = &(struct clk_init_data){ 2102 .name = "gcc_usb30_master_clk", 2103 .parent_hws = (const struct clk_hw *[]){ &usb30_master_clk_src.clkr.hw }, 2104 .num_parents = 1, 2105 .flags = CLK_SET_RATE_PARENT, 2106 .ops = &clk_branch2_ops, 2107 }, 2108 }, 2109 }; 2110 2111 static struct clk_branch gcc_usb30_mock_utmi_clk = { 2112 .halt_reg = 0x03d0, 2113 .clkr = { 2114 .enable_reg = 0x03d0, 2115 .enable_mask = BIT(0), 2116 .hw.init = &(struct clk_init_data){ 2117 .name = "gcc_usb30_mock_utmi_clk", 2118 .parent_hws = (const struct clk_hw *[]){ &usb30_mock_utmi_clk_src.clkr.hw }, 2119 .num_parents = 1, 2120 .flags = CLK_SET_RATE_PARENT, 2121 .ops = &clk_branch2_ops, 2122 }, 2123 }, 2124 }; 2125 2126 static struct clk_branch gcc_usb30_sleep_clk = { 2127 .halt_reg = 0x03cc, 2128 .clkr = { 2129 .enable_reg = 0x03cc, 2130 .enable_mask = BIT(0), 2131 .hw.init = &(struct clk_init_data){ 2132 .name = "gcc_usb30_sleep_clk", 2133 .parent_data = &(const struct clk_parent_data){ 2134 .fw_name = "sleep", 2135 .name = "sleep" 2136 }, 2137 .num_parents = 1, 2138 .ops = &clk_branch2_ops, 2139 }, 2140 }, 2141 }; 2142 2143 static struct clk_branch gcc_usb3_phy_aux_clk = { 2144 .halt_reg = 0x1408, 2145 .clkr = { 2146 .enable_reg = 0x1408, 2147 .enable_mask = BIT(0), 2148 .hw.init = &(struct clk_init_data){ 2149 .name = "gcc_usb3_phy_aux_clk", 2150 .parent_hws = (const struct clk_hw *[]){ &usb3_phy_aux_clk_src.clkr.hw }, 2151 .num_parents = 1, 2152 .flags = CLK_SET_RATE_PARENT, 2153 .ops = &clk_branch2_ops, 2154 }, 2155 }, 2156 }; 2157 2158 static struct clk_branch gcc_usb_hs_ahb_clk = { 2159 .halt_reg = 0x0488, 2160 .clkr = { 2161 .enable_reg = 0x0488, 2162 .enable_mask = BIT(0), 2163 .hw.init = &(struct clk_init_data){ 2164 .name = "gcc_usb_hs_ahb_clk", 2165 .ops = &clk_branch2_ops, 2166 }, 2167 }, 2168 }; 2169 2170 static struct clk_branch gcc_usb_hs_system_clk = { 2171 .halt_reg = 0x0484, 2172 .clkr = { 2173 .enable_reg = 0x0484, 2174 .enable_mask = BIT(0), 2175 .hw.init = &(struct clk_init_data){ 2176 .name = "gcc_usb_hs_system_clk", 2177 .parent_hws = (const struct clk_hw *[]){ &usb_hs_system_clk_src.clkr.hw }, 2178 .num_parents = 1, 2179 .flags = CLK_SET_RATE_PARENT, 2180 .ops = &clk_branch2_ops, 2181 }, 2182 }, 2183 }; 2184 2185 static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = { 2186 .halt_reg = 0x1a84, 2187 .clkr = { 2188 .enable_reg = 0x1a84, 2189 .enable_mask = BIT(0), 2190 .hw.init = &(struct clk_init_data){ 2191 .name = "gcc_usb_phy_cfg_ahb2phy_clk", 2192 .ops = &clk_branch2_ops, 2193 }, 2194 }, 2195 }; 2196 2197 static struct gdsc pcie_gdsc = { 2198 .gdscr = 0x1e18, 2199 .pd = { 2200 .name = "pcie", 2201 }, 2202 .pwrsts = PWRSTS_OFF_ON, 2203 }; 2204 2205 static struct gdsc pcie_0_gdsc = { 2206 .gdscr = 0x1ac4, 2207 .pd = { 2208 .name = "pcie_0", 2209 }, 2210 .pwrsts = PWRSTS_OFF_ON, 2211 }; 2212 2213 static struct gdsc pcie_1_gdsc = { 2214 .gdscr = 0x1b44, 2215 .pd = { 2216 .name = "pcie_1", 2217 }, 2218 .pwrsts = PWRSTS_OFF_ON, 2219 }; 2220 2221 static struct gdsc usb30_gdsc = { 2222 .gdscr = 0x3c4, 2223 .pd = { 2224 .name = "usb30", 2225 }, 2226 .pwrsts = PWRSTS_OFF_ON, 2227 }; 2228 2229 static struct gdsc ufs_gdsc = { 2230 .gdscr = 0x1d44, 2231 .pd = { 2232 .name = "ufs", 2233 }, 2234 .pwrsts = PWRSTS_OFF_ON, 2235 }; 2236 2237 static struct clk_regmap *gcc_msm8994_clocks[] = { 2238 [GPLL0_EARLY] = &gpll0_early.clkr, 2239 [GPLL0] = &gpll0.clkr, 2240 [GPLL4_EARLY] = &gpll4_early.clkr, 2241 [GPLL4] = &gpll4.clkr, 2242 [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr, 2243 [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr, 2244 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr, 2245 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr, 2246 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr, 2247 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr, 2248 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr, 2249 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr, 2250 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr, 2251 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr, 2252 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr, 2253 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr, 2254 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr, 2255 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr, 2256 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr, 2257 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr, 2258 [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr, 2259 [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr, 2260 [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr, 2261 [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr, 2262 [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr, 2263 [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr, 2264 [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr, 2265 [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr, 2266 [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr, 2267 [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr, 2268 [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr, 2269 [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr, 2270 [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr, 2271 [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr, 2272 [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr, 2273 [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr, 2274 [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr, 2275 [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr, 2276 [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr, 2277 [BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr, 2278 [BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr, 2279 [BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr, 2280 [GP1_CLK_SRC] = &gp1_clk_src.clkr, 2281 [GP2_CLK_SRC] = &gp2_clk_src.clkr, 2282 [GP3_CLK_SRC] = &gp3_clk_src.clkr, 2283 [PCIE_0_AUX_CLK_SRC] = &pcie_0_aux_clk_src.clkr, 2284 [PCIE_0_PIPE_CLK_SRC] = &pcie_0_pipe_clk_src.clkr, 2285 [PCIE_1_AUX_CLK_SRC] = &pcie_1_aux_clk_src.clkr, 2286 [PCIE_1_PIPE_CLK_SRC] = &pcie_1_pipe_clk_src.clkr, 2287 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr, 2288 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr, 2289 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr, 2290 [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr, 2291 [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr, 2292 [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr, 2293 [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr, 2294 [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr, 2295 [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr, 2296 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr, 2297 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr, 2298 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr, 2299 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr, 2300 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr, 2301 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr, 2302 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr, 2303 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr, 2304 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr, 2305 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr, 2306 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr, 2307 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr, 2308 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr, 2309 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, 2310 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr, 2311 [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr, 2312 [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr, 2313 [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr, 2314 [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr, 2315 [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr, 2316 [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr, 2317 [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr, 2318 [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr, 2319 [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr, 2320 [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr, 2321 [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr, 2322 [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr, 2323 [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr, 2324 [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr, 2325 [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr, 2326 [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr, 2327 [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr, 2328 [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr, 2329 [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr, 2330 [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr, 2331 [GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr, 2332 [GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr, 2333 [GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr, 2334 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 2335 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 2336 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 2337 [GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr, 2338 [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr, 2339 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, 2340 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, 2341 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, 2342 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, 2343 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, 2344 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr, 2345 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr, 2346 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr, 2347 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr, 2348 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr, 2349 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 2350 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 2351 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, 2352 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, 2353 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 2354 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 2355 [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr, 2356 [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr, 2357 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, 2358 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, 2359 [GCC_SYS_NOC_UFS_AXI_CLK] = &gcc_sys_noc_ufs_axi_clk.clkr, 2360 [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr, 2361 [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr, 2362 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr, 2363 [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr, 2364 [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr, 2365 [GCC_UFS_RX_CFG_CLK] = &gcc_ufs_rx_cfg_clk.clkr, 2366 [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr, 2367 [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr, 2368 [GCC_UFS_TX_CFG_CLK] = &gcc_ufs_tx_cfg_clk.clkr, 2369 [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr, 2370 [GCC_UFS_TX_SYMBOL_1_CLK] = &gcc_ufs_tx_symbol_1_clk.clkr, 2371 [GCC_USB2_HS_PHY_SLEEP_CLK] = &gcc_usb2_hs_phy_sleep_clk.clkr, 2372 [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr, 2373 [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr, 2374 [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr, 2375 [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr, 2376 [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr, 2377 [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr, 2378 [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr, 2379 }; 2380 2381 static struct gdsc *gcc_msm8994_gdscs[] = { 2382 [PCIE_GDSC] = &pcie_gdsc, 2383 [PCIE_0_GDSC] = &pcie_0_gdsc, 2384 [PCIE_1_GDSC] = &pcie_1_gdsc, 2385 [USB30_GDSC] = &usb30_gdsc, 2386 [UFS_GDSC] = &ufs_gdsc, 2387 }; 2388 2389 static const struct qcom_reset_map gcc_msm8994_resets[] = { 2390 [USB3_PHY_RESET] = { 0x1400 }, 2391 [USB3PHY_PHY_RESET] = { 0x1404 }, 2392 [PCIE_PHY_0_RESET] = { 0x1b18 }, 2393 [PCIE_PHY_1_RESET] = { 0x1b98 }, 2394 [QUSB2_PHY_RESET] = { 0x04b8 }, 2395 }; 2396 2397 static const struct regmap_config gcc_msm8994_regmap_config = { 2398 .reg_bits = 32, 2399 .reg_stride = 4, 2400 .val_bits = 32, 2401 .max_register = 0x2000, 2402 .fast_io = true, 2403 }; 2404 2405 static const struct qcom_cc_desc gcc_msm8994_desc = { 2406 .config = &gcc_msm8994_regmap_config, 2407 .clks = gcc_msm8994_clocks, 2408 .num_clks = ARRAY_SIZE(gcc_msm8994_clocks), 2409 .resets = gcc_msm8994_resets, 2410 .num_resets = ARRAY_SIZE(gcc_msm8994_resets), 2411 .gdscs = gcc_msm8994_gdscs, 2412 .num_gdscs = ARRAY_SIZE(gcc_msm8994_gdscs), 2413 }; 2414 2415 static const struct of_device_id gcc_msm8994_match_table[] = { 2416 { .compatible = "qcom,gcc-msm8994" }, 2417 {} 2418 }; 2419 MODULE_DEVICE_TABLE(of, gcc_msm8994_match_table); 2420 2421 static int gcc_msm8994_probe(struct platform_device *pdev) 2422 { 2423 return qcom_cc_probe(pdev, &gcc_msm8994_desc); 2424 } 2425 2426 static struct platform_driver gcc_msm8994_driver = { 2427 .probe = gcc_msm8994_probe, 2428 .driver = { 2429 .name = "gcc-msm8994", 2430 .of_match_table = gcc_msm8994_match_table, 2431 }, 2432 }; 2433 2434 static int __init gcc_msm8994_init(void) 2435 { 2436 return platform_driver_register(&gcc_msm8994_driver); 2437 } 2438 core_initcall(gcc_msm8994_init); 2439 2440 static void __exit gcc_msm8994_exit(void) 2441 { 2442 platform_driver_unregister(&gcc_msm8994_driver); 2443 } 2444 module_exit(gcc_msm8994_exit); 2445 2446 MODULE_DESCRIPTION("Qualcomm GCC MSM8994 Driver"); 2447 MODULE_LICENSE("GPL v2"); 2448 MODULE_ALIAS("platform:gcc-msm8994"); 2449