1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2013, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/bitops.h> 8 #include <linux/err.h> 9 #include <linux/platform_device.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/of_device.h> 13 #include <linux/clk-provider.h> 14 #include <linux/regmap.h> 15 #include <linux/reset-controller.h> 16 17 #include <dt-bindings/clock/qcom,gcc-msm8974.h> 18 #include <dt-bindings/reset/qcom,gcc-msm8974.h> 19 20 #include "common.h" 21 #include "clk-regmap.h" 22 #include "clk-pll.h" 23 #include "clk-rcg.h" 24 #include "clk-branch.h" 25 #include "reset.h" 26 #include "gdsc.h" 27 28 enum { 29 P_XO, 30 P_GPLL0, 31 P_GPLL1, 32 P_GPLL4, 33 }; 34 35 static struct clk_pll gpll0 = { 36 .l_reg = 0x0004, 37 .m_reg = 0x0008, 38 .n_reg = 0x000c, 39 .config_reg = 0x0014, 40 .mode_reg = 0x0000, 41 .status_reg = 0x001c, 42 .status_bit = 17, 43 .clkr.hw.init = &(struct clk_init_data){ 44 .name = "gpll0", 45 .parent_data = &(const struct clk_parent_data){ 46 .fw_name = "xo", .name = "xo_board", 47 }, 48 .num_parents = 1, 49 .ops = &clk_pll_ops, 50 }, 51 }; 52 53 static struct clk_regmap gpll0_vote = { 54 .enable_reg = 0x1480, 55 .enable_mask = BIT(0), 56 .hw.init = &(struct clk_init_data){ 57 .name = "gpll0_vote", 58 .parent_hws = (const struct clk_hw*[]){ 59 &gpll0.clkr.hw, 60 }, 61 .num_parents = 1, 62 .ops = &clk_pll_vote_ops, 63 }, 64 }; 65 66 static struct clk_pll gpll4 = { 67 .l_reg = 0x1dc4, 68 .m_reg = 0x1dc8, 69 .n_reg = 0x1dcc, 70 .config_reg = 0x1dd4, 71 .mode_reg = 0x1dc0, 72 .status_reg = 0x1ddc, 73 .status_bit = 17, 74 .clkr.hw.init = &(struct clk_init_data){ 75 .name = "gpll4", 76 .parent_data = &(const struct clk_parent_data){ 77 .fw_name = "xo", .name = "xo_board", 78 }, 79 .num_parents = 1, 80 .ops = &clk_pll_ops, 81 }, 82 }; 83 84 static struct clk_regmap gpll4_vote = { 85 .enable_reg = 0x1480, 86 .enable_mask = BIT(4), 87 .hw.init = &(struct clk_init_data){ 88 .name = "gpll4_vote", 89 .parent_hws = (const struct clk_hw*[]){ 90 &gpll4.clkr.hw, 91 }, 92 .num_parents = 1, 93 .ops = &clk_pll_vote_ops, 94 }, 95 }; 96 97 static const struct parent_map gcc_xo_gpll0_map[] = { 98 { P_XO, 0 }, 99 { P_GPLL0, 1 } 100 }; 101 102 static const struct clk_parent_data gcc_xo_gpll0[] = { 103 { .fw_name = "xo", .name = "xo_board" }, 104 { .hw = &gpll0_vote.hw }, 105 }; 106 107 static const struct parent_map gcc_xo_gpll0_gpll4_map[] = { 108 { P_XO, 0 }, 109 { P_GPLL0, 1 }, 110 { P_GPLL4, 5 } 111 }; 112 113 static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = { 114 { .fw_name = "xo", .name = "xo_board" }, 115 { .hw = &gpll0_vote.hw }, 116 { .hw = &gpll4_vote.hw }, 117 }; 118 119 static struct clk_rcg2 config_noc_clk_src = { 120 .cmd_rcgr = 0x0150, 121 .hid_width = 5, 122 .parent_map = gcc_xo_gpll0_map, 123 .clkr.hw.init = &(struct clk_init_data){ 124 .name = "config_noc_clk_src", 125 .parent_data = gcc_xo_gpll0, 126 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 127 .ops = &clk_rcg2_ops, 128 }, 129 }; 130 131 static struct clk_rcg2 periph_noc_clk_src = { 132 .cmd_rcgr = 0x0190, 133 .hid_width = 5, 134 .parent_map = gcc_xo_gpll0_map, 135 .clkr.hw.init = &(struct clk_init_data){ 136 .name = "periph_noc_clk_src", 137 .parent_data = gcc_xo_gpll0, 138 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 139 .ops = &clk_rcg2_ops, 140 }, 141 }; 142 143 static struct clk_rcg2 system_noc_clk_src = { 144 .cmd_rcgr = 0x0120, 145 .hid_width = 5, 146 .parent_map = gcc_xo_gpll0_map, 147 .clkr.hw.init = &(struct clk_init_data){ 148 .name = "system_noc_clk_src", 149 .parent_data = gcc_xo_gpll0, 150 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 151 .ops = &clk_rcg2_ops, 152 }, 153 }; 154 155 static struct clk_pll gpll1 = { 156 .l_reg = 0x0044, 157 .m_reg = 0x0048, 158 .n_reg = 0x004c, 159 .config_reg = 0x0054, 160 .mode_reg = 0x0040, 161 .status_reg = 0x005c, 162 .status_bit = 17, 163 .clkr.hw.init = &(struct clk_init_data){ 164 .name = "gpll1", 165 .parent_data = &(const struct clk_parent_data){ 166 .fw_name = "xo", .name = "xo_board", 167 }, 168 .num_parents = 1, 169 .ops = &clk_pll_ops, 170 }, 171 }; 172 173 static struct clk_regmap gpll1_vote = { 174 .enable_reg = 0x1480, 175 .enable_mask = BIT(1), 176 .hw.init = &(struct clk_init_data){ 177 .name = "gpll1_vote", 178 .parent_hws = (const struct clk_hw*[]){ 179 &gpll1.clkr.hw, 180 }, 181 .num_parents = 1, 182 .ops = &clk_pll_vote_ops, 183 }, 184 }; 185 186 static const struct freq_tbl ftbl_gcc_usb30_master_clk[] = { 187 F(125000000, P_GPLL0, 1, 5, 24), 188 { } 189 }; 190 191 static struct clk_rcg2 usb30_master_clk_src = { 192 .cmd_rcgr = 0x03d4, 193 .mnd_width = 8, 194 .hid_width = 5, 195 .parent_map = gcc_xo_gpll0_map, 196 .freq_tbl = ftbl_gcc_usb30_master_clk, 197 .clkr.hw.init = &(struct clk_init_data){ 198 .name = "usb30_master_clk_src", 199 .parent_data = gcc_xo_gpll0, 200 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 201 .ops = &clk_rcg2_ops, 202 }, 203 }; 204 205 static const struct freq_tbl ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk[] = { 206 F(19200000, P_XO, 1, 0, 0), 207 F(37500000, P_GPLL0, 16, 0, 0), 208 F(50000000, P_GPLL0, 12, 0, 0), 209 { } 210 }; 211 212 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { 213 .cmd_rcgr = 0x0660, 214 .hid_width = 5, 215 .parent_map = gcc_xo_gpll0_map, 216 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, 217 .clkr.hw.init = &(struct clk_init_data){ 218 .name = "blsp1_qup1_i2c_apps_clk_src", 219 .parent_data = gcc_xo_gpll0, 220 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 221 .ops = &clk_rcg2_ops, 222 }, 223 }; 224 225 static const struct freq_tbl ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk[] = { 226 F(960000, P_XO, 10, 1, 2), 227 F(4800000, P_XO, 4, 0, 0), 228 F(9600000, P_XO, 2, 0, 0), 229 F(15000000, P_GPLL0, 10, 1, 4), 230 F(19200000, P_XO, 1, 0, 0), 231 F(25000000, P_GPLL0, 12, 1, 2), 232 F(50000000, P_GPLL0, 12, 0, 0), 233 { } 234 }; 235 236 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { 237 .cmd_rcgr = 0x064c, 238 .mnd_width = 8, 239 .hid_width = 5, 240 .parent_map = gcc_xo_gpll0_map, 241 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, 242 .clkr.hw.init = &(struct clk_init_data){ 243 .name = "blsp1_qup1_spi_apps_clk_src", 244 .parent_data = gcc_xo_gpll0, 245 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 246 .ops = &clk_rcg2_ops, 247 }, 248 }; 249 250 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { 251 .cmd_rcgr = 0x06e0, 252 .hid_width = 5, 253 .parent_map = gcc_xo_gpll0_map, 254 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, 255 .clkr.hw.init = &(struct clk_init_data){ 256 .name = "blsp1_qup2_i2c_apps_clk_src", 257 .parent_data = gcc_xo_gpll0, 258 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 259 .ops = &clk_rcg2_ops, 260 }, 261 }; 262 263 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { 264 .cmd_rcgr = 0x06cc, 265 .mnd_width = 8, 266 .hid_width = 5, 267 .parent_map = gcc_xo_gpll0_map, 268 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, 269 .clkr.hw.init = &(struct clk_init_data){ 270 .name = "blsp1_qup2_spi_apps_clk_src", 271 .parent_data = gcc_xo_gpll0, 272 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 273 .ops = &clk_rcg2_ops, 274 }, 275 }; 276 277 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { 278 .cmd_rcgr = 0x0760, 279 .hid_width = 5, 280 .parent_map = gcc_xo_gpll0_map, 281 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, 282 .clkr.hw.init = &(struct clk_init_data){ 283 .name = "blsp1_qup3_i2c_apps_clk_src", 284 .parent_data = gcc_xo_gpll0, 285 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 286 .ops = &clk_rcg2_ops, 287 }, 288 }; 289 290 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { 291 .cmd_rcgr = 0x074c, 292 .mnd_width = 8, 293 .hid_width = 5, 294 .parent_map = gcc_xo_gpll0_map, 295 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, 296 .clkr.hw.init = &(struct clk_init_data){ 297 .name = "blsp1_qup3_spi_apps_clk_src", 298 .parent_data = gcc_xo_gpll0, 299 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 300 .ops = &clk_rcg2_ops, 301 }, 302 }; 303 304 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { 305 .cmd_rcgr = 0x07e0, 306 .hid_width = 5, 307 .parent_map = gcc_xo_gpll0_map, 308 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, 309 .clkr.hw.init = &(struct clk_init_data){ 310 .name = "blsp1_qup4_i2c_apps_clk_src", 311 .parent_data = gcc_xo_gpll0, 312 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 313 .ops = &clk_rcg2_ops, 314 }, 315 }; 316 317 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { 318 .cmd_rcgr = 0x07cc, 319 .mnd_width = 8, 320 .hid_width = 5, 321 .parent_map = gcc_xo_gpll0_map, 322 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, 323 .clkr.hw.init = &(struct clk_init_data){ 324 .name = "blsp1_qup4_spi_apps_clk_src", 325 .parent_data = gcc_xo_gpll0, 326 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 327 .ops = &clk_rcg2_ops, 328 }, 329 }; 330 331 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = { 332 .cmd_rcgr = 0x0860, 333 .hid_width = 5, 334 .parent_map = gcc_xo_gpll0_map, 335 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, 336 .clkr.hw.init = &(struct clk_init_data){ 337 .name = "blsp1_qup5_i2c_apps_clk_src", 338 .parent_data = gcc_xo_gpll0, 339 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 340 .ops = &clk_rcg2_ops, 341 }, 342 }; 343 344 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = { 345 .cmd_rcgr = 0x084c, 346 .mnd_width = 8, 347 .hid_width = 5, 348 .parent_map = gcc_xo_gpll0_map, 349 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, 350 .clkr.hw.init = &(struct clk_init_data){ 351 .name = "blsp1_qup5_spi_apps_clk_src", 352 .parent_data = gcc_xo_gpll0, 353 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 354 .ops = &clk_rcg2_ops, 355 }, 356 }; 357 358 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = { 359 .cmd_rcgr = 0x08e0, 360 .hid_width = 5, 361 .parent_map = gcc_xo_gpll0_map, 362 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, 363 .clkr.hw.init = &(struct clk_init_data){ 364 .name = "blsp1_qup6_i2c_apps_clk_src", 365 .parent_data = gcc_xo_gpll0, 366 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 367 .ops = &clk_rcg2_ops, 368 }, 369 }; 370 371 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = { 372 .cmd_rcgr = 0x08cc, 373 .mnd_width = 8, 374 .hid_width = 5, 375 .parent_map = gcc_xo_gpll0_map, 376 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, 377 .clkr.hw.init = &(struct clk_init_data){ 378 .name = "blsp1_qup6_spi_apps_clk_src", 379 .parent_data = gcc_xo_gpll0, 380 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 381 .ops = &clk_rcg2_ops, 382 }, 383 }; 384 385 static const struct freq_tbl ftbl_gcc_blsp1_2_uart1_6_apps_clk[] = { 386 F(3686400, P_GPLL0, 1, 96, 15625), 387 F(7372800, P_GPLL0, 1, 192, 15625), 388 F(14745600, P_GPLL0, 1, 384, 15625), 389 F(16000000, P_GPLL0, 5, 2, 15), 390 F(19200000, P_XO, 1, 0, 0), 391 F(24000000, P_GPLL0, 5, 1, 5), 392 F(32000000, P_GPLL0, 1, 4, 75), 393 F(40000000, P_GPLL0, 15, 0, 0), 394 F(46400000, P_GPLL0, 1, 29, 375), 395 F(48000000, P_GPLL0, 12.5, 0, 0), 396 F(51200000, P_GPLL0, 1, 32, 375), 397 F(56000000, P_GPLL0, 1, 7, 75), 398 F(58982400, P_GPLL0, 1, 1536, 15625), 399 F(60000000, P_GPLL0, 10, 0, 0), 400 F(63160000, P_GPLL0, 9.5, 0, 0), 401 { } 402 }; 403 404 static struct clk_rcg2 blsp1_uart1_apps_clk_src = { 405 .cmd_rcgr = 0x068c, 406 .mnd_width = 16, 407 .hid_width = 5, 408 .parent_map = gcc_xo_gpll0_map, 409 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, 410 .clkr.hw.init = &(struct clk_init_data){ 411 .name = "blsp1_uart1_apps_clk_src", 412 .parent_data = gcc_xo_gpll0, 413 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 414 .ops = &clk_rcg2_ops, 415 }, 416 }; 417 418 static struct clk_rcg2 blsp1_uart2_apps_clk_src = { 419 .cmd_rcgr = 0x070c, 420 .mnd_width = 16, 421 .hid_width = 5, 422 .parent_map = gcc_xo_gpll0_map, 423 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, 424 .clkr.hw.init = &(struct clk_init_data){ 425 .name = "blsp1_uart2_apps_clk_src", 426 .parent_data = gcc_xo_gpll0, 427 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 428 .ops = &clk_rcg2_ops, 429 }, 430 }; 431 432 static struct clk_rcg2 blsp1_uart3_apps_clk_src = { 433 .cmd_rcgr = 0x078c, 434 .mnd_width = 16, 435 .hid_width = 5, 436 .parent_map = gcc_xo_gpll0_map, 437 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, 438 .clkr.hw.init = &(struct clk_init_data){ 439 .name = "blsp1_uart3_apps_clk_src", 440 .parent_data = gcc_xo_gpll0, 441 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 442 .ops = &clk_rcg2_ops, 443 }, 444 }; 445 446 static struct clk_rcg2 blsp1_uart4_apps_clk_src = { 447 .cmd_rcgr = 0x080c, 448 .mnd_width = 16, 449 .hid_width = 5, 450 .parent_map = gcc_xo_gpll0_map, 451 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, 452 .clkr.hw.init = &(struct clk_init_data){ 453 .name = "blsp1_uart4_apps_clk_src", 454 .parent_data = gcc_xo_gpll0, 455 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 456 .ops = &clk_rcg2_ops, 457 }, 458 }; 459 460 static struct clk_rcg2 blsp1_uart5_apps_clk_src = { 461 .cmd_rcgr = 0x088c, 462 .mnd_width = 16, 463 .hid_width = 5, 464 .parent_map = gcc_xo_gpll0_map, 465 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, 466 .clkr.hw.init = &(struct clk_init_data){ 467 .name = "blsp1_uart5_apps_clk_src", 468 .parent_data = gcc_xo_gpll0, 469 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 470 .ops = &clk_rcg2_ops, 471 }, 472 }; 473 474 static struct clk_rcg2 blsp1_uart6_apps_clk_src = { 475 .cmd_rcgr = 0x090c, 476 .mnd_width = 16, 477 .hid_width = 5, 478 .parent_map = gcc_xo_gpll0_map, 479 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, 480 .clkr.hw.init = &(struct clk_init_data){ 481 .name = "blsp1_uart6_apps_clk_src", 482 .parent_data = gcc_xo_gpll0, 483 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 484 .ops = &clk_rcg2_ops, 485 }, 486 }; 487 488 static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = { 489 .cmd_rcgr = 0x09a0, 490 .hid_width = 5, 491 .parent_map = gcc_xo_gpll0_map, 492 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, 493 .clkr.hw.init = &(struct clk_init_data){ 494 .name = "blsp2_qup1_i2c_apps_clk_src", 495 .parent_data = gcc_xo_gpll0, 496 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 497 .ops = &clk_rcg2_ops, 498 }, 499 }; 500 501 static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = { 502 .cmd_rcgr = 0x098c, 503 .mnd_width = 8, 504 .hid_width = 5, 505 .parent_map = gcc_xo_gpll0_map, 506 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, 507 .clkr.hw.init = &(struct clk_init_data){ 508 .name = "blsp2_qup1_spi_apps_clk_src", 509 .parent_data = gcc_xo_gpll0, 510 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 511 .ops = &clk_rcg2_ops, 512 }, 513 }; 514 515 static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = { 516 .cmd_rcgr = 0x0a20, 517 .hid_width = 5, 518 .parent_map = gcc_xo_gpll0_map, 519 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, 520 .clkr.hw.init = &(struct clk_init_data){ 521 .name = "blsp2_qup2_i2c_apps_clk_src", 522 .parent_data = gcc_xo_gpll0, 523 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 524 .ops = &clk_rcg2_ops, 525 }, 526 }; 527 528 static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = { 529 .cmd_rcgr = 0x0a0c, 530 .mnd_width = 8, 531 .hid_width = 5, 532 .parent_map = gcc_xo_gpll0_map, 533 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, 534 .clkr.hw.init = &(struct clk_init_data){ 535 .name = "blsp2_qup2_spi_apps_clk_src", 536 .parent_data = gcc_xo_gpll0, 537 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 538 .ops = &clk_rcg2_ops, 539 }, 540 }; 541 542 static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = { 543 .cmd_rcgr = 0x0aa0, 544 .hid_width = 5, 545 .parent_map = gcc_xo_gpll0_map, 546 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, 547 .clkr.hw.init = &(struct clk_init_data){ 548 .name = "blsp2_qup3_i2c_apps_clk_src", 549 .parent_data = gcc_xo_gpll0, 550 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 551 .ops = &clk_rcg2_ops, 552 }, 553 }; 554 555 static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = { 556 .cmd_rcgr = 0x0a8c, 557 .mnd_width = 8, 558 .hid_width = 5, 559 .parent_map = gcc_xo_gpll0_map, 560 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, 561 .clkr.hw.init = &(struct clk_init_data){ 562 .name = "blsp2_qup3_spi_apps_clk_src", 563 .parent_data = gcc_xo_gpll0, 564 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 565 .ops = &clk_rcg2_ops, 566 }, 567 }; 568 569 static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = { 570 .cmd_rcgr = 0x0b20, 571 .hid_width = 5, 572 .parent_map = gcc_xo_gpll0_map, 573 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, 574 .clkr.hw.init = &(struct clk_init_data){ 575 .name = "blsp2_qup4_i2c_apps_clk_src", 576 .parent_data = gcc_xo_gpll0, 577 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 578 .ops = &clk_rcg2_ops, 579 }, 580 }; 581 582 static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = { 583 .cmd_rcgr = 0x0b0c, 584 .mnd_width = 8, 585 .hid_width = 5, 586 .parent_map = gcc_xo_gpll0_map, 587 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, 588 .clkr.hw.init = &(struct clk_init_data){ 589 .name = "blsp2_qup4_spi_apps_clk_src", 590 .parent_data = gcc_xo_gpll0, 591 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 592 .ops = &clk_rcg2_ops, 593 }, 594 }; 595 596 static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = { 597 .cmd_rcgr = 0x0ba0, 598 .hid_width = 5, 599 .parent_map = gcc_xo_gpll0_map, 600 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, 601 .clkr.hw.init = &(struct clk_init_data){ 602 .name = "blsp2_qup5_i2c_apps_clk_src", 603 .parent_data = gcc_xo_gpll0, 604 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 605 .ops = &clk_rcg2_ops, 606 }, 607 }; 608 609 static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = { 610 .cmd_rcgr = 0x0b8c, 611 .mnd_width = 8, 612 .hid_width = 5, 613 .parent_map = gcc_xo_gpll0_map, 614 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, 615 .clkr.hw.init = &(struct clk_init_data){ 616 .name = "blsp2_qup5_spi_apps_clk_src", 617 .parent_data = gcc_xo_gpll0, 618 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 619 .ops = &clk_rcg2_ops, 620 }, 621 }; 622 623 static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = { 624 .cmd_rcgr = 0x0c20, 625 .hid_width = 5, 626 .parent_map = gcc_xo_gpll0_map, 627 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, 628 .clkr.hw.init = &(struct clk_init_data){ 629 .name = "blsp2_qup6_i2c_apps_clk_src", 630 .parent_data = gcc_xo_gpll0, 631 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 632 .ops = &clk_rcg2_ops, 633 }, 634 }; 635 636 static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = { 637 .cmd_rcgr = 0x0c0c, 638 .mnd_width = 8, 639 .hid_width = 5, 640 .parent_map = gcc_xo_gpll0_map, 641 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, 642 .clkr.hw.init = &(struct clk_init_data){ 643 .name = "blsp2_qup6_spi_apps_clk_src", 644 .parent_data = gcc_xo_gpll0, 645 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 646 .ops = &clk_rcg2_ops, 647 }, 648 }; 649 650 static struct clk_rcg2 blsp2_uart1_apps_clk_src = { 651 .cmd_rcgr = 0x09cc, 652 .mnd_width = 16, 653 .hid_width = 5, 654 .parent_map = gcc_xo_gpll0_map, 655 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, 656 .clkr.hw.init = &(struct clk_init_data){ 657 .name = "blsp2_uart1_apps_clk_src", 658 .parent_data = gcc_xo_gpll0, 659 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 660 .ops = &clk_rcg2_ops, 661 }, 662 }; 663 664 static struct clk_rcg2 blsp2_uart2_apps_clk_src = { 665 .cmd_rcgr = 0x0a4c, 666 .mnd_width = 16, 667 .hid_width = 5, 668 .parent_map = gcc_xo_gpll0_map, 669 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, 670 .clkr.hw.init = &(struct clk_init_data){ 671 .name = "blsp2_uart2_apps_clk_src", 672 .parent_data = gcc_xo_gpll0, 673 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 674 .ops = &clk_rcg2_ops, 675 }, 676 }; 677 678 static struct clk_rcg2 blsp2_uart3_apps_clk_src = { 679 .cmd_rcgr = 0x0acc, 680 .mnd_width = 16, 681 .hid_width = 5, 682 .parent_map = gcc_xo_gpll0_map, 683 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, 684 .clkr.hw.init = &(struct clk_init_data){ 685 .name = "blsp2_uart3_apps_clk_src", 686 .parent_data = gcc_xo_gpll0, 687 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 688 .ops = &clk_rcg2_ops, 689 }, 690 }; 691 692 static struct clk_rcg2 blsp2_uart4_apps_clk_src = { 693 .cmd_rcgr = 0x0b4c, 694 .mnd_width = 16, 695 .hid_width = 5, 696 .parent_map = gcc_xo_gpll0_map, 697 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, 698 .clkr.hw.init = &(struct clk_init_data){ 699 .name = "blsp2_uart4_apps_clk_src", 700 .parent_data = gcc_xo_gpll0, 701 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 702 .ops = &clk_rcg2_ops, 703 }, 704 }; 705 706 static struct clk_rcg2 blsp2_uart5_apps_clk_src = { 707 .cmd_rcgr = 0x0bcc, 708 .mnd_width = 16, 709 .hid_width = 5, 710 .parent_map = gcc_xo_gpll0_map, 711 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, 712 .clkr.hw.init = &(struct clk_init_data){ 713 .name = "blsp2_uart5_apps_clk_src", 714 .parent_data = gcc_xo_gpll0, 715 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 716 .ops = &clk_rcg2_ops, 717 }, 718 }; 719 720 static struct clk_rcg2 blsp2_uart6_apps_clk_src = { 721 .cmd_rcgr = 0x0c4c, 722 .mnd_width = 16, 723 .hid_width = 5, 724 .parent_map = gcc_xo_gpll0_map, 725 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, 726 .clkr.hw.init = &(struct clk_init_data){ 727 .name = "blsp2_uart6_apps_clk_src", 728 .parent_data = gcc_xo_gpll0, 729 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 730 .ops = &clk_rcg2_ops, 731 }, 732 }; 733 734 static const struct freq_tbl ftbl_gcc_ce1_clk_msm8226[] = { 735 F(50000000, P_GPLL0, 12, 0, 0), 736 F(100000000, P_GPLL0, 6, 0, 0), 737 { } 738 }; 739 740 static const struct freq_tbl ftbl_gcc_ce1_clk[] = { 741 F(50000000, P_GPLL0, 12, 0, 0), 742 F(75000000, P_GPLL0, 8, 0, 0), 743 F(100000000, P_GPLL0, 6, 0, 0), 744 F(150000000, P_GPLL0, 4, 0, 0), 745 { } 746 }; 747 748 static struct clk_rcg2 ce1_clk_src = { 749 .cmd_rcgr = 0x1050, 750 .hid_width = 5, 751 .parent_map = gcc_xo_gpll0_map, 752 .freq_tbl = ftbl_gcc_ce1_clk, 753 .clkr.hw.init = &(struct clk_init_data){ 754 .name = "ce1_clk_src", 755 .parent_data = gcc_xo_gpll0, 756 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 757 .ops = &clk_rcg2_ops, 758 }, 759 }; 760 761 static const struct freq_tbl ftbl_gcc_ce2_clk[] = { 762 F(50000000, P_GPLL0, 12, 0, 0), 763 F(75000000, P_GPLL0, 8, 0, 0), 764 F(100000000, P_GPLL0, 6, 0, 0), 765 F(150000000, P_GPLL0, 4, 0, 0), 766 { } 767 }; 768 769 static struct clk_rcg2 ce2_clk_src = { 770 .cmd_rcgr = 0x1090, 771 .hid_width = 5, 772 .parent_map = gcc_xo_gpll0_map, 773 .freq_tbl = ftbl_gcc_ce2_clk, 774 .clkr.hw.init = &(struct clk_init_data){ 775 .name = "ce2_clk_src", 776 .parent_data = gcc_xo_gpll0, 777 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 778 .ops = &clk_rcg2_ops, 779 }, 780 }; 781 782 static const struct freq_tbl ftbl_gcc_gp_clk_msm8226[] = { 783 F(19200000, P_XO, 1, 0, 0), 784 { } 785 }; 786 787 static const struct freq_tbl ftbl_gcc_gp_clk[] = { 788 F(4800000, P_XO, 4, 0, 0), 789 F(6000000, P_GPLL0, 10, 1, 10), 790 F(6750000, P_GPLL0, 1, 1, 89), 791 F(8000000, P_GPLL0, 15, 1, 5), 792 F(9600000, P_XO, 2, 0, 0), 793 F(16000000, P_GPLL0, 1, 2, 75), 794 F(19200000, P_XO, 1, 0, 0), 795 F(24000000, P_GPLL0, 5, 1, 5), 796 { } 797 }; 798 799 800 static struct clk_rcg2 gp1_clk_src = { 801 .cmd_rcgr = 0x1904, 802 .mnd_width = 8, 803 .hid_width = 5, 804 .parent_map = gcc_xo_gpll0_map, 805 .freq_tbl = ftbl_gcc_gp_clk, 806 .clkr.hw.init = &(struct clk_init_data){ 807 .name = "gp1_clk_src", 808 .parent_data = gcc_xo_gpll0, 809 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 810 .ops = &clk_rcg2_ops, 811 }, 812 }; 813 814 static struct clk_rcg2 gp2_clk_src = { 815 .cmd_rcgr = 0x1944, 816 .mnd_width = 8, 817 .hid_width = 5, 818 .parent_map = gcc_xo_gpll0_map, 819 .freq_tbl = ftbl_gcc_gp_clk, 820 .clkr.hw.init = &(struct clk_init_data){ 821 .name = "gp2_clk_src", 822 .parent_data = gcc_xo_gpll0, 823 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 824 .ops = &clk_rcg2_ops, 825 }, 826 }; 827 828 static struct clk_rcg2 gp3_clk_src = { 829 .cmd_rcgr = 0x1984, 830 .mnd_width = 8, 831 .hid_width = 5, 832 .parent_map = gcc_xo_gpll0_map, 833 .freq_tbl = ftbl_gcc_gp_clk, 834 .clkr.hw.init = &(struct clk_init_data){ 835 .name = "gp3_clk_src", 836 .parent_data = gcc_xo_gpll0, 837 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 838 .ops = &clk_rcg2_ops, 839 }, 840 }; 841 842 static const struct freq_tbl ftbl_gcc_pdm2_clk[] = { 843 F(60000000, P_GPLL0, 10, 0, 0), 844 { } 845 }; 846 847 static struct clk_rcg2 pdm2_clk_src = { 848 .cmd_rcgr = 0x0cd0, 849 .hid_width = 5, 850 .parent_map = gcc_xo_gpll0_map, 851 .freq_tbl = ftbl_gcc_pdm2_clk, 852 .clkr.hw.init = &(struct clk_init_data){ 853 .name = "pdm2_clk_src", 854 .parent_data = gcc_xo_gpll0, 855 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 856 .ops = &clk_rcg2_ops, 857 }, 858 }; 859 860 static const struct freq_tbl ftbl_gcc_sdcc1_4_apps_clk[] = { 861 F(144000, P_XO, 16, 3, 25), 862 F(400000, P_XO, 12, 1, 4), 863 F(20000000, P_GPLL0, 15, 1, 2), 864 F(25000000, P_GPLL0, 12, 1, 2), 865 F(50000000, P_GPLL0, 12, 0, 0), 866 F(100000000, P_GPLL0, 6, 0, 0), 867 F(200000000, P_GPLL0, 3, 0, 0), 868 { } 869 }; 870 871 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_pro[] = { 872 F(144000, P_XO, 16, 3, 25), 873 F(400000, P_XO, 12, 1, 4), 874 F(20000000, P_GPLL0, 15, 1, 2), 875 F(25000000, P_GPLL0, 12, 1, 2), 876 F(50000000, P_GPLL0, 12, 0, 0), 877 F(100000000, P_GPLL0, 6, 0, 0), 878 F(192000000, P_GPLL4, 4, 0, 0), 879 F(200000000, P_GPLL0, 3, 0, 0), 880 F(384000000, P_GPLL4, 2, 0, 0), 881 { } 882 }; 883 884 static struct clk_init_data sdcc1_apps_clk_src_init = { 885 .name = "sdcc1_apps_clk_src", 886 .parent_data = gcc_xo_gpll0, 887 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 888 .ops = &clk_rcg2_floor_ops, 889 }; 890 891 static struct clk_rcg2 sdcc1_apps_clk_src = { 892 .cmd_rcgr = 0x04d0, 893 .mnd_width = 8, 894 .hid_width = 5, 895 .parent_map = gcc_xo_gpll0_map, 896 .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk, 897 .clkr.hw.init = &sdcc1_apps_clk_src_init, 898 }; 899 900 static struct clk_rcg2 sdcc2_apps_clk_src = { 901 .cmd_rcgr = 0x0510, 902 .mnd_width = 8, 903 .hid_width = 5, 904 .parent_map = gcc_xo_gpll0_map, 905 .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk, 906 .clkr.hw.init = &(struct clk_init_data){ 907 .name = "sdcc2_apps_clk_src", 908 .parent_data = gcc_xo_gpll0, 909 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 910 .ops = &clk_rcg2_floor_ops, 911 }, 912 }; 913 914 static struct clk_rcg2 sdcc3_apps_clk_src = { 915 .cmd_rcgr = 0x0550, 916 .mnd_width = 8, 917 .hid_width = 5, 918 .parent_map = gcc_xo_gpll0_map, 919 .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk, 920 .clkr.hw.init = &(struct clk_init_data){ 921 .name = "sdcc3_apps_clk_src", 922 .parent_data = gcc_xo_gpll0, 923 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 924 .ops = &clk_rcg2_floor_ops, 925 }, 926 }; 927 928 static struct clk_rcg2 sdcc4_apps_clk_src = { 929 .cmd_rcgr = 0x0590, 930 .mnd_width = 8, 931 .hid_width = 5, 932 .parent_map = gcc_xo_gpll0_map, 933 .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk, 934 .clkr.hw.init = &(struct clk_init_data){ 935 .name = "sdcc4_apps_clk_src", 936 .parent_data = gcc_xo_gpll0, 937 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 938 .ops = &clk_rcg2_floor_ops, 939 }, 940 }; 941 942 static const struct freq_tbl ftbl_gcc_tsif_ref_clk[] = { 943 F(105000, P_XO, 2, 1, 91), 944 { } 945 }; 946 947 static struct clk_rcg2 tsif_ref_clk_src = { 948 .cmd_rcgr = 0x0d90, 949 .mnd_width = 8, 950 .hid_width = 5, 951 .parent_map = gcc_xo_gpll0_map, 952 .freq_tbl = ftbl_gcc_tsif_ref_clk, 953 .clkr.hw.init = &(struct clk_init_data){ 954 .name = "tsif_ref_clk_src", 955 .parent_data = gcc_xo_gpll0, 956 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 957 .ops = &clk_rcg2_ops, 958 }, 959 }; 960 961 static const struct freq_tbl ftbl_gcc_usb30_mock_utmi_clk[] = { 962 F(60000000, P_GPLL0, 10, 0, 0), 963 { } 964 }; 965 966 static struct clk_rcg2 usb30_mock_utmi_clk_src = { 967 .cmd_rcgr = 0x03e8, 968 .hid_width = 5, 969 .parent_map = gcc_xo_gpll0_map, 970 .freq_tbl = ftbl_gcc_usb30_mock_utmi_clk, 971 .clkr.hw.init = &(struct clk_init_data){ 972 .name = "usb30_mock_utmi_clk_src", 973 .parent_data = gcc_xo_gpll0, 974 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 975 .ops = &clk_rcg2_ops, 976 }, 977 }; 978 979 static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = { 980 F(60000000, P_GPLL0, 10, 0, 0), 981 F(75000000, P_GPLL0, 8, 0, 0), 982 { } 983 }; 984 985 static struct clk_rcg2 usb_hs_system_clk_src = { 986 .cmd_rcgr = 0x0490, 987 .hid_width = 5, 988 .parent_map = gcc_xo_gpll0_map, 989 .freq_tbl = ftbl_gcc_usb_hs_system_clk, 990 .clkr.hw.init = &(struct clk_init_data){ 991 .name = "usb_hs_system_clk_src", 992 .parent_data = gcc_xo_gpll0, 993 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 994 .ops = &clk_rcg2_ops, 995 }, 996 }; 997 998 static const struct freq_tbl ftbl_gcc_usb_hsic_clk[] = { 999 F(480000000, P_GPLL1, 1, 0, 0), 1000 { } 1001 }; 1002 1003 static const struct parent_map usb_hsic_clk_src_map[] = { 1004 { P_XO, 0 }, 1005 { P_GPLL1, 4 } 1006 }; 1007 1008 static struct clk_rcg2 usb_hsic_clk_src = { 1009 .cmd_rcgr = 0x0440, 1010 .hid_width = 5, 1011 .parent_map = usb_hsic_clk_src_map, 1012 .freq_tbl = ftbl_gcc_usb_hsic_clk, 1013 .clkr.hw.init = &(struct clk_init_data){ 1014 .name = "usb_hsic_clk_src", 1015 .parent_data = (const struct clk_parent_data[]){ 1016 { .fw_name = "xo", .name = "xo_board" }, 1017 { .hw = &gpll1_vote.hw }, 1018 }, 1019 .num_parents = 2, 1020 .ops = &clk_rcg2_ops, 1021 }, 1022 }; 1023 1024 static const struct freq_tbl ftbl_gcc_usb_hsic_io_cal_clk[] = { 1025 F(9600000, P_XO, 2, 0, 0), 1026 { } 1027 }; 1028 1029 static struct clk_rcg2 usb_hsic_io_cal_clk_src = { 1030 .cmd_rcgr = 0x0458, 1031 .hid_width = 5, 1032 .parent_map = gcc_xo_gpll0_map, 1033 .freq_tbl = ftbl_gcc_usb_hsic_io_cal_clk, 1034 .clkr.hw.init = &(struct clk_init_data){ 1035 .name = "usb_hsic_io_cal_clk_src", 1036 .parent_data = gcc_xo_gpll0, 1037 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1038 .ops = &clk_rcg2_ops, 1039 }, 1040 }; 1041 1042 static const struct freq_tbl ftbl_gcc_usb_hsic_system_clk[] = { 1043 F(60000000, P_GPLL0, 10, 0, 0), 1044 F(75000000, P_GPLL0, 8, 0, 0), 1045 { } 1046 }; 1047 1048 static struct clk_rcg2 usb_hsic_system_clk_src = { 1049 .cmd_rcgr = 0x041c, 1050 .hid_width = 5, 1051 .parent_map = gcc_xo_gpll0_map, 1052 .freq_tbl = ftbl_gcc_usb_hsic_system_clk, 1053 .clkr.hw.init = &(struct clk_init_data){ 1054 .name = "usb_hsic_system_clk_src", 1055 .parent_data = gcc_xo_gpll0, 1056 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1057 .ops = &clk_rcg2_ops, 1058 }, 1059 }; 1060 1061 static struct clk_regmap gcc_mmss_gpll0_clk_src = { 1062 .enable_reg = 0x1484, 1063 .enable_mask = BIT(26), 1064 .hw.init = &(struct clk_init_data){ 1065 .name = "mmss_gpll0_vote", 1066 .parent_hws = (const struct clk_hw*[]){ 1067 &gpll0_vote.hw, 1068 }, 1069 .num_parents = 1, 1070 .ops = &clk_branch_simple_ops, 1071 }, 1072 }; 1073 1074 static struct clk_branch gcc_bam_dma_ahb_clk = { 1075 .halt_reg = 0x0d44, 1076 .halt_check = BRANCH_HALT_VOTED, 1077 .clkr = { 1078 .enable_reg = 0x1484, 1079 .enable_mask = BIT(12), 1080 .hw.init = &(struct clk_init_data){ 1081 .name = "gcc_bam_dma_ahb_clk", 1082 .parent_hws = (const struct clk_hw*[]){ 1083 &periph_noc_clk_src.clkr.hw, 1084 }, 1085 .num_parents = 1, 1086 .ops = &clk_branch2_ops, 1087 }, 1088 }, 1089 }; 1090 1091 static struct clk_branch gcc_blsp1_ahb_clk = { 1092 .halt_reg = 0x05c4, 1093 .halt_check = BRANCH_HALT_VOTED, 1094 .clkr = { 1095 .enable_reg = 0x1484, 1096 .enable_mask = BIT(17), 1097 .hw.init = &(struct clk_init_data){ 1098 .name = "gcc_blsp1_ahb_clk", 1099 .parent_hws = (const struct clk_hw*[]){ 1100 &periph_noc_clk_src.clkr.hw, 1101 }, 1102 .num_parents = 1, 1103 .ops = &clk_branch2_ops, 1104 }, 1105 }, 1106 }; 1107 1108 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { 1109 .halt_reg = 0x0648, 1110 .clkr = { 1111 .enable_reg = 0x0648, 1112 .enable_mask = BIT(0), 1113 .hw.init = &(struct clk_init_data){ 1114 .name = "gcc_blsp1_qup1_i2c_apps_clk", 1115 .parent_hws = (const struct clk_hw*[]){ 1116 &blsp1_qup1_i2c_apps_clk_src.clkr.hw, 1117 }, 1118 .num_parents = 1, 1119 .flags = CLK_SET_RATE_PARENT, 1120 .ops = &clk_branch2_ops, 1121 }, 1122 }, 1123 }; 1124 1125 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { 1126 .halt_reg = 0x0644, 1127 .clkr = { 1128 .enable_reg = 0x0644, 1129 .enable_mask = BIT(0), 1130 .hw.init = &(struct clk_init_data){ 1131 .name = "gcc_blsp1_qup1_spi_apps_clk", 1132 .parent_hws = (const struct clk_hw*[]){ 1133 &blsp1_qup1_spi_apps_clk_src.clkr.hw, 1134 }, 1135 .num_parents = 1, 1136 .flags = CLK_SET_RATE_PARENT, 1137 .ops = &clk_branch2_ops, 1138 }, 1139 }, 1140 }; 1141 1142 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { 1143 .halt_reg = 0x06c8, 1144 .clkr = { 1145 .enable_reg = 0x06c8, 1146 .enable_mask = BIT(0), 1147 .hw.init = &(struct clk_init_data){ 1148 .name = "gcc_blsp1_qup2_i2c_apps_clk", 1149 .parent_hws = (const struct clk_hw*[]){ 1150 &blsp1_qup2_i2c_apps_clk_src.clkr.hw, 1151 }, 1152 .num_parents = 1, 1153 .flags = CLK_SET_RATE_PARENT, 1154 .ops = &clk_branch2_ops, 1155 }, 1156 }, 1157 }; 1158 1159 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { 1160 .halt_reg = 0x06c4, 1161 .clkr = { 1162 .enable_reg = 0x06c4, 1163 .enable_mask = BIT(0), 1164 .hw.init = &(struct clk_init_data){ 1165 .name = "gcc_blsp1_qup2_spi_apps_clk", 1166 .parent_hws = (const struct clk_hw*[]){ 1167 &blsp1_qup2_spi_apps_clk_src.clkr.hw, 1168 }, 1169 .num_parents = 1, 1170 .flags = CLK_SET_RATE_PARENT, 1171 .ops = &clk_branch2_ops, 1172 }, 1173 }, 1174 }; 1175 1176 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = { 1177 .halt_reg = 0x0748, 1178 .clkr = { 1179 .enable_reg = 0x0748, 1180 .enable_mask = BIT(0), 1181 .hw.init = &(struct clk_init_data){ 1182 .name = "gcc_blsp1_qup3_i2c_apps_clk", 1183 .parent_hws = (const struct clk_hw*[]){ 1184 &blsp1_qup3_i2c_apps_clk_src.clkr.hw, 1185 }, 1186 .num_parents = 1, 1187 .flags = CLK_SET_RATE_PARENT, 1188 .ops = &clk_branch2_ops, 1189 }, 1190 }, 1191 }; 1192 1193 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = { 1194 .halt_reg = 0x0744, 1195 .clkr = { 1196 .enable_reg = 0x0744, 1197 .enable_mask = BIT(0), 1198 .hw.init = &(struct clk_init_data){ 1199 .name = "gcc_blsp1_qup3_spi_apps_clk", 1200 .parent_hws = (const struct clk_hw*[]){ 1201 &blsp1_qup3_spi_apps_clk_src.clkr.hw, 1202 }, 1203 .num_parents = 1, 1204 .flags = CLK_SET_RATE_PARENT, 1205 .ops = &clk_branch2_ops, 1206 }, 1207 }, 1208 }; 1209 1210 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = { 1211 .halt_reg = 0x07c8, 1212 .clkr = { 1213 .enable_reg = 0x07c8, 1214 .enable_mask = BIT(0), 1215 .hw.init = &(struct clk_init_data){ 1216 .name = "gcc_blsp1_qup4_i2c_apps_clk", 1217 .parent_hws = (const struct clk_hw*[]){ 1218 &blsp1_qup4_i2c_apps_clk_src.clkr.hw, 1219 }, 1220 .num_parents = 1, 1221 .flags = CLK_SET_RATE_PARENT, 1222 .ops = &clk_branch2_ops, 1223 }, 1224 }, 1225 }; 1226 1227 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = { 1228 .halt_reg = 0x07c4, 1229 .clkr = { 1230 .enable_reg = 0x07c4, 1231 .enable_mask = BIT(0), 1232 .hw.init = &(struct clk_init_data){ 1233 .name = "gcc_blsp1_qup4_spi_apps_clk", 1234 .parent_hws = (const struct clk_hw*[]){ 1235 &blsp1_qup4_spi_apps_clk_src.clkr.hw, 1236 }, 1237 .num_parents = 1, 1238 .flags = CLK_SET_RATE_PARENT, 1239 .ops = &clk_branch2_ops, 1240 }, 1241 }, 1242 }; 1243 1244 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = { 1245 .halt_reg = 0x0848, 1246 .clkr = { 1247 .enable_reg = 0x0848, 1248 .enable_mask = BIT(0), 1249 .hw.init = &(struct clk_init_data){ 1250 .name = "gcc_blsp1_qup5_i2c_apps_clk", 1251 .parent_hws = (const struct clk_hw*[]){ 1252 &blsp1_qup5_i2c_apps_clk_src.clkr.hw, 1253 }, 1254 .num_parents = 1, 1255 .flags = CLK_SET_RATE_PARENT, 1256 .ops = &clk_branch2_ops, 1257 }, 1258 }, 1259 }; 1260 1261 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = { 1262 .halt_reg = 0x0844, 1263 .clkr = { 1264 .enable_reg = 0x0844, 1265 .enable_mask = BIT(0), 1266 .hw.init = &(struct clk_init_data){ 1267 .name = "gcc_blsp1_qup5_spi_apps_clk", 1268 .parent_hws = (const struct clk_hw*[]){ 1269 &blsp1_qup5_spi_apps_clk_src.clkr.hw, 1270 }, 1271 .num_parents = 1, 1272 .flags = CLK_SET_RATE_PARENT, 1273 .ops = &clk_branch2_ops, 1274 }, 1275 }, 1276 }; 1277 1278 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = { 1279 .halt_reg = 0x08c8, 1280 .clkr = { 1281 .enable_reg = 0x08c8, 1282 .enable_mask = BIT(0), 1283 .hw.init = &(struct clk_init_data){ 1284 .name = "gcc_blsp1_qup6_i2c_apps_clk", 1285 .parent_hws = (const struct clk_hw*[]){ 1286 &blsp1_qup6_i2c_apps_clk_src.clkr.hw, 1287 }, 1288 .num_parents = 1, 1289 .flags = CLK_SET_RATE_PARENT, 1290 .ops = &clk_branch2_ops, 1291 }, 1292 }, 1293 }; 1294 1295 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = { 1296 .halt_reg = 0x08c4, 1297 .clkr = { 1298 .enable_reg = 0x08c4, 1299 .enable_mask = BIT(0), 1300 .hw.init = &(struct clk_init_data){ 1301 .name = "gcc_blsp1_qup6_spi_apps_clk", 1302 .parent_hws = (const struct clk_hw*[]){ 1303 &blsp1_qup6_spi_apps_clk_src.clkr.hw, 1304 }, 1305 .num_parents = 1, 1306 .flags = CLK_SET_RATE_PARENT, 1307 .ops = &clk_branch2_ops, 1308 }, 1309 }, 1310 }; 1311 1312 static struct clk_branch gcc_blsp1_uart1_apps_clk = { 1313 .halt_reg = 0x0684, 1314 .clkr = { 1315 .enable_reg = 0x0684, 1316 .enable_mask = BIT(0), 1317 .hw.init = &(struct clk_init_data){ 1318 .name = "gcc_blsp1_uart1_apps_clk", 1319 .parent_hws = (const struct clk_hw*[]){ 1320 &blsp1_uart1_apps_clk_src.clkr.hw, 1321 }, 1322 .num_parents = 1, 1323 .flags = CLK_SET_RATE_PARENT, 1324 .ops = &clk_branch2_ops, 1325 }, 1326 }, 1327 }; 1328 1329 static struct clk_branch gcc_blsp1_uart2_apps_clk = { 1330 .halt_reg = 0x0704, 1331 .clkr = { 1332 .enable_reg = 0x0704, 1333 .enable_mask = BIT(0), 1334 .hw.init = &(struct clk_init_data){ 1335 .name = "gcc_blsp1_uart2_apps_clk", 1336 .parent_hws = (const struct clk_hw*[]){ 1337 &blsp1_uart2_apps_clk_src.clkr.hw, 1338 }, 1339 .num_parents = 1, 1340 .flags = CLK_SET_RATE_PARENT, 1341 .ops = &clk_branch2_ops, 1342 }, 1343 }, 1344 }; 1345 1346 static struct clk_branch gcc_blsp1_uart3_apps_clk = { 1347 .halt_reg = 0x0784, 1348 .clkr = { 1349 .enable_reg = 0x0784, 1350 .enable_mask = BIT(0), 1351 .hw.init = &(struct clk_init_data){ 1352 .name = "gcc_blsp1_uart3_apps_clk", 1353 .parent_hws = (const struct clk_hw*[]){ 1354 &blsp1_uart3_apps_clk_src.clkr.hw, 1355 }, 1356 .num_parents = 1, 1357 .flags = CLK_SET_RATE_PARENT, 1358 .ops = &clk_branch2_ops, 1359 }, 1360 }, 1361 }; 1362 1363 static struct clk_branch gcc_blsp1_uart4_apps_clk = { 1364 .halt_reg = 0x0804, 1365 .clkr = { 1366 .enable_reg = 0x0804, 1367 .enable_mask = BIT(0), 1368 .hw.init = &(struct clk_init_data){ 1369 .name = "gcc_blsp1_uart4_apps_clk", 1370 .parent_hws = (const struct clk_hw*[]){ 1371 &blsp1_uart4_apps_clk_src.clkr.hw, 1372 }, 1373 .num_parents = 1, 1374 .flags = CLK_SET_RATE_PARENT, 1375 .ops = &clk_branch2_ops, 1376 }, 1377 }, 1378 }; 1379 1380 static struct clk_branch gcc_blsp1_uart5_apps_clk = { 1381 .halt_reg = 0x0884, 1382 .clkr = { 1383 .enable_reg = 0x0884, 1384 .enable_mask = BIT(0), 1385 .hw.init = &(struct clk_init_data){ 1386 .name = "gcc_blsp1_uart5_apps_clk", 1387 .parent_hws = (const struct clk_hw*[]){ 1388 &blsp1_uart5_apps_clk_src.clkr.hw, 1389 }, 1390 .num_parents = 1, 1391 .flags = CLK_SET_RATE_PARENT, 1392 .ops = &clk_branch2_ops, 1393 }, 1394 }, 1395 }; 1396 1397 static struct clk_branch gcc_blsp1_uart6_apps_clk = { 1398 .halt_reg = 0x0904, 1399 .clkr = { 1400 .enable_reg = 0x0904, 1401 .enable_mask = BIT(0), 1402 .hw.init = &(struct clk_init_data){ 1403 .name = "gcc_blsp1_uart6_apps_clk", 1404 .parent_hws = (const struct clk_hw*[]){ 1405 &blsp1_uart6_apps_clk_src.clkr.hw, 1406 }, 1407 .num_parents = 1, 1408 .flags = CLK_SET_RATE_PARENT, 1409 .ops = &clk_branch2_ops, 1410 }, 1411 }, 1412 }; 1413 1414 static struct clk_branch gcc_blsp2_ahb_clk = { 1415 .halt_reg = 0x0944, 1416 .halt_check = BRANCH_HALT_VOTED, 1417 .clkr = { 1418 .enable_reg = 0x1484, 1419 .enable_mask = BIT(15), 1420 .hw.init = &(struct clk_init_data){ 1421 .name = "gcc_blsp2_ahb_clk", 1422 .parent_hws = (const struct clk_hw*[]){ 1423 &periph_noc_clk_src.clkr.hw, 1424 }, 1425 .num_parents = 1, 1426 .ops = &clk_branch2_ops, 1427 }, 1428 }, 1429 }; 1430 1431 static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = { 1432 .halt_reg = 0x0988, 1433 .clkr = { 1434 .enable_reg = 0x0988, 1435 .enable_mask = BIT(0), 1436 .hw.init = &(struct clk_init_data){ 1437 .name = "gcc_blsp2_qup1_i2c_apps_clk", 1438 .parent_hws = (const struct clk_hw*[]){ 1439 &blsp2_qup1_i2c_apps_clk_src.clkr.hw, 1440 }, 1441 .num_parents = 1, 1442 .flags = CLK_SET_RATE_PARENT, 1443 .ops = &clk_branch2_ops, 1444 }, 1445 }, 1446 }; 1447 1448 static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = { 1449 .halt_reg = 0x0984, 1450 .clkr = { 1451 .enable_reg = 0x0984, 1452 .enable_mask = BIT(0), 1453 .hw.init = &(struct clk_init_data){ 1454 .name = "gcc_blsp2_qup1_spi_apps_clk", 1455 .parent_hws = (const struct clk_hw*[]){ 1456 &blsp2_qup1_spi_apps_clk_src.clkr.hw, 1457 }, 1458 .num_parents = 1, 1459 .flags = CLK_SET_RATE_PARENT, 1460 .ops = &clk_branch2_ops, 1461 }, 1462 }, 1463 }; 1464 1465 static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = { 1466 .halt_reg = 0x0a08, 1467 .clkr = { 1468 .enable_reg = 0x0a08, 1469 .enable_mask = BIT(0), 1470 .hw.init = &(struct clk_init_data){ 1471 .name = "gcc_blsp2_qup2_i2c_apps_clk", 1472 .parent_hws = (const struct clk_hw*[]){ 1473 &blsp2_qup2_i2c_apps_clk_src.clkr.hw, 1474 }, 1475 .num_parents = 1, 1476 .flags = CLK_SET_RATE_PARENT, 1477 .ops = &clk_branch2_ops, 1478 }, 1479 }, 1480 }; 1481 1482 static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = { 1483 .halt_reg = 0x0a04, 1484 .clkr = { 1485 .enable_reg = 0x0a04, 1486 .enable_mask = BIT(0), 1487 .hw.init = &(struct clk_init_data){ 1488 .name = "gcc_blsp2_qup2_spi_apps_clk", 1489 .parent_hws = (const struct clk_hw*[]){ 1490 &blsp2_qup2_spi_apps_clk_src.clkr.hw, 1491 }, 1492 .num_parents = 1, 1493 .flags = CLK_SET_RATE_PARENT, 1494 .ops = &clk_branch2_ops, 1495 }, 1496 }, 1497 }; 1498 1499 static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = { 1500 .halt_reg = 0x0a88, 1501 .clkr = { 1502 .enable_reg = 0x0a88, 1503 .enable_mask = BIT(0), 1504 .hw.init = &(struct clk_init_data){ 1505 .name = "gcc_blsp2_qup3_i2c_apps_clk", 1506 .parent_hws = (const struct clk_hw*[]){ 1507 &blsp2_qup3_i2c_apps_clk_src.clkr.hw, 1508 }, 1509 .num_parents = 1, 1510 .flags = CLK_SET_RATE_PARENT, 1511 .ops = &clk_branch2_ops, 1512 }, 1513 }, 1514 }; 1515 1516 static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = { 1517 .halt_reg = 0x0a84, 1518 .clkr = { 1519 .enable_reg = 0x0a84, 1520 .enable_mask = BIT(0), 1521 .hw.init = &(struct clk_init_data){ 1522 .name = "gcc_blsp2_qup3_spi_apps_clk", 1523 .parent_hws = (const struct clk_hw*[]){ 1524 &blsp2_qup3_spi_apps_clk_src.clkr.hw, 1525 }, 1526 .num_parents = 1, 1527 .flags = CLK_SET_RATE_PARENT, 1528 .ops = &clk_branch2_ops, 1529 }, 1530 }, 1531 }; 1532 1533 static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = { 1534 .halt_reg = 0x0b08, 1535 .clkr = { 1536 .enable_reg = 0x0b08, 1537 .enable_mask = BIT(0), 1538 .hw.init = &(struct clk_init_data){ 1539 .name = "gcc_blsp2_qup4_i2c_apps_clk", 1540 .parent_hws = (const struct clk_hw*[]){ 1541 &blsp2_qup4_i2c_apps_clk_src.clkr.hw, 1542 }, 1543 .num_parents = 1, 1544 .flags = CLK_SET_RATE_PARENT, 1545 .ops = &clk_branch2_ops, 1546 }, 1547 }, 1548 }; 1549 1550 static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = { 1551 .halt_reg = 0x0b04, 1552 .clkr = { 1553 .enable_reg = 0x0b04, 1554 .enable_mask = BIT(0), 1555 .hw.init = &(struct clk_init_data){ 1556 .name = "gcc_blsp2_qup4_spi_apps_clk", 1557 .parent_hws = (const struct clk_hw*[]){ 1558 &blsp2_qup4_spi_apps_clk_src.clkr.hw, 1559 }, 1560 .num_parents = 1, 1561 .flags = CLK_SET_RATE_PARENT, 1562 .ops = &clk_branch2_ops, 1563 }, 1564 }, 1565 }; 1566 1567 static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = { 1568 .halt_reg = 0x0b88, 1569 .clkr = { 1570 .enable_reg = 0x0b88, 1571 .enable_mask = BIT(0), 1572 .hw.init = &(struct clk_init_data){ 1573 .name = "gcc_blsp2_qup5_i2c_apps_clk", 1574 .parent_hws = (const struct clk_hw*[]){ 1575 &blsp2_qup5_i2c_apps_clk_src.clkr.hw, 1576 }, 1577 .num_parents = 1, 1578 .flags = CLK_SET_RATE_PARENT, 1579 .ops = &clk_branch2_ops, 1580 }, 1581 }, 1582 }; 1583 1584 static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = { 1585 .halt_reg = 0x0b84, 1586 .clkr = { 1587 .enable_reg = 0x0b84, 1588 .enable_mask = BIT(0), 1589 .hw.init = &(struct clk_init_data){ 1590 .name = "gcc_blsp2_qup5_spi_apps_clk", 1591 .parent_hws = (const struct clk_hw*[]){ 1592 &blsp2_qup5_spi_apps_clk_src.clkr.hw, 1593 }, 1594 .num_parents = 1, 1595 .flags = CLK_SET_RATE_PARENT, 1596 .ops = &clk_branch2_ops, 1597 }, 1598 }, 1599 }; 1600 1601 static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = { 1602 .halt_reg = 0x0c08, 1603 .clkr = { 1604 .enable_reg = 0x0c08, 1605 .enable_mask = BIT(0), 1606 .hw.init = &(struct clk_init_data){ 1607 .name = "gcc_blsp2_qup6_i2c_apps_clk", 1608 .parent_hws = (const struct clk_hw*[]){ 1609 &blsp2_qup6_i2c_apps_clk_src.clkr.hw, 1610 }, 1611 .num_parents = 1, 1612 .flags = CLK_SET_RATE_PARENT, 1613 .ops = &clk_branch2_ops, 1614 }, 1615 }, 1616 }; 1617 1618 static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = { 1619 .halt_reg = 0x0c04, 1620 .clkr = { 1621 .enable_reg = 0x0c04, 1622 .enable_mask = BIT(0), 1623 .hw.init = &(struct clk_init_data){ 1624 .name = "gcc_blsp2_qup6_spi_apps_clk", 1625 .parent_hws = (const struct clk_hw*[]){ 1626 &blsp2_qup6_spi_apps_clk_src.clkr.hw, 1627 }, 1628 .num_parents = 1, 1629 .flags = CLK_SET_RATE_PARENT, 1630 .ops = &clk_branch2_ops, 1631 }, 1632 }, 1633 }; 1634 1635 static struct clk_branch gcc_blsp2_uart1_apps_clk = { 1636 .halt_reg = 0x09c4, 1637 .clkr = { 1638 .enable_reg = 0x09c4, 1639 .enable_mask = BIT(0), 1640 .hw.init = &(struct clk_init_data){ 1641 .name = "gcc_blsp2_uart1_apps_clk", 1642 .parent_hws = (const struct clk_hw*[]){ 1643 &blsp2_uart1_apps_clk_src.clkr.hw, 1644 }, 1645 .num_parents = 1, 1646 .flags = CLK_SET_RATE_PARENT, 1647 .ops = &clk_branch2_ops, 1648 }, 1649 }, 1650 }; 1651 1652 static struct clk_branch gcc_blsp2_uart2_apps_clk = { 1653 .halt_reg = 0x0a44, 1654 .clkr = { 1655 .enable_reg = 0x0a44, 1656 .enable_mask = BIT(0), 1657 .hw.init = &(struct clk_init_data){ 1658 .name = "gcc_blsp2_uart2_apps_clk", 1659 .parent_hws = (const struct clk_hw*[]){ 1660 &blsp2_uart2_apps_clk_src.clkr.hw, 1661 }, 1662 .num_parents = 1, 1663 .flags = CLK_SET_RATE_PARENT, 1664 .ops = &clk_branch2_ops, 1665 }, 1666 }, 1667 }; 1668 1669 static struct clk_branch gcc_blsp2_uart3_apps_clk = { 1670 .halt_reg = 0x0ac4, 1671 .clkr = { 1672 .enable_reg = 0x0ac4, 1673 .enable_mask = BIT(0), 1674 .hw.init = &(struct clk_init_data){ 1675 .name = "gcc_blsp2_uart3_apps_clk", 1676 .parent_hws = (const struct clk_hw*[]){ 1677 &blsp2_uart3_apps_clk_src.clkr.hw, 1678 }, 1679 .num_parents = 1, 1680 .flags = CLK_SET_RATE_PARENT, 1681 .ops = &clk_branch2_ops, 1682 }, 1683 }, 1684 }; 1685 1686 static struct clk_branch gcc_blsp2_uart4_apps_clk = { 1687 .halt_reg = 0x0b44, 1688 .clkr = { 1689 .enable_reg = 0x0b44, 1690 .enable_mask = BIT(0), 1691 .hw.init = &(struct clk_init_data){ 1692 .name = "gcc_blsp2_uart4_apps_clk", 1693 .parent_hws = (const struct clk_hw*[]){ 1694 &blsp2_uart4_apps_clk_src.clkr.hw, 1695 }, 1696 .num_parents = 1, 1697 .flags = CLK_SET_RATE_PARENT, 1698 .ops = &clk_branch2_ops, 1699 }, 1700 }, 1701 }; 1702 1703 static struct clk_branch gcc_blsp2_uart5_apps_clk = { 1704 .halt_reg = 0x0bc4, 1705 .clkr = { 1706 .enable_reg = 0x0bc4, 1707 .enable_mask = BIT(0), 1708 .hw.init = &(struct clk_init_data){ 1709 .name = "gcc_blsp2_uart5_apps_clk", 1710 .parent_hws = (const struct clk_hw*[]){ 1711 &blsp2_uart5_apps_clk_src.clkr.hw, 1712 }, 1713 .num_parents = 1, 1714 .flags = CLK_SET_RATE_PARENT, 1715 .ops = &clk_branch2_ops, 1716 }, 1717 }, 1718 }; 1719 1720 static struct clk_branch gcc_blsp2_uart6_apps_clk = { 1721 .halt_reg = 0x0c44, 1722 .clkr = { 1723 .enable_reg = 0x0c44, 1724 .enable_mask = BIT(0), 1725 .hw.init = &(struct clk_init_data){ 1726 .name = "gcc_blsp2_uart6_apps_clk", 1727 .parent_hws = (const struct clk_hw*[]){ 1728 &blsp2_uart6_apps_clk_src.clkr.hw, 1729 }, 1730 .num_parents = 1, 1731 .flags = CLK_SET_RATE_PARENT, 1732 .ops = &clk_branch2_ops, 1733 }, 1734 }, 1735 }; 1736 1737 static struct clk_branch gcc_boot_rom_ahb_clk = { 1738 .halt_reg = 0x0e04, 1739 .halt_check = BRANCH_HALT_VOTED, 1740 .clkr = { 1741 .enable_reg = 0x1484, 1742 .enable_mask = BIT(10), 1743 .hw.init = &(struct clk_init_data){ 1744 .name = "gcc_boot_rom_ahb_clk", 1745 .parent_hws = (const struct clk_hw*[]){ 1746 &config_noc_clk_src.clkr.hw, 1747 }, 1748 .num_parents = 1, 1749 .ops = &clk_branch2_ops, 1750 }, 1751 }, 1752 }; 1753 1754 static struct clk_branch gcc_ce1_ahb_clk = { 1755 .halt_reg = 0x104c, 1756 .halt_check = BRANCH_HALT_VOTED, 1757 .clkr = { 1758 .enable_reg = 0x1484, 1759 .enable_mask = BIT(3), 1760 .hw.init = &(struct clk_init_data){ 1761 .name = "gcc_ce1_ahb_clk", 1762 .parent_hws = (const struct clk_hw*[]){ 1763 &config_noc_clk_src.clkr.hw, 1764 }, 1765 .num_parents = 1, 1766 .ops = &clk_branch2_ops, 1767 }, 1768 }, 1769 }; 1770 1771 static struct clk_branch gcc_ce1_axi_clk = { 1772 .halt_reg = 0x1048, 1773 .halt_check = BRANCH_HALT_VOTED, 1774 .clkr = { 1775 .enable_reg = 0x1484, 1776 .enable_mask = BIT(4), 1777 .hw.init = &(struct clk_init_data){ 1778 .name = "gcc_ce1_axi_clk", 1779 .parent_hws = (const struct clk_hw*[]){ 1780 &system_noc_clk_src.clkr.hw, 1781 }, 1782 .num_parents = 1, 1783 .ops = &clk_branch2_ops, 1784 }, 1785 }, 1786 }; 1787 1788 static struct clk_branch gcc_ce1_clk = { 1789 .halt_reg = 0x1050, 1790 .halt_check = BRANCH_HALT_VOTED, 1791 .clkr = { 1792 .enable_reg = 0x1484, 1793 .enable_mask = BIT(5), 1794 .hw.init = &(struct clk_init_data){ 1795 .name = "gcc_ce1_clk", 1796 .parent_hws = (const struct clk_hw*[]){ 1797 &ce1_clk_src.clkr.hw, 1798 }, 1799 .num_parents = 1, 1800 .flags = CLK_SET_RATE_PARENT, 1801 .ops = &clk_branch2_ops, 1802 }, 1803 }, 1804 }; 1805 1806 static struct clk_branch gcc_ce2_ahb_clk = { 1807 .halt_reg = 0x108c, 1808 .halt_check = BRANCH_HALT_VOTED, 1809 .clkr = { 1810 .enable_reg = 0x1484, 1811 .enable_mask = BIT(0), 1812 .hw.init = &(struct clk_init_data){ 1813 .name = "gcc_ce2_ahb_clk", 1814 .parent_hws = (const struct clk_hw*[]){ 1815 &config_noc_clk_src.clkr.hw, 1816 }, 1817 .num_parents = 1, 1818 .ops = &clk_branch2_ops, 1819 }, 1820 }, 1821 }; 1822 1823 static struct clk_branch gcc_ce2_axi_clk = { 1824 .halt_reg = 0x1088, 1825 .halt_check = BRANCH_HALT_VOTED, 1826 .clkr = { 1827 .enable_reg = 0x1484, 1828 .enable_mask = BIT(1), 1829 .hw.init = &(struct clk_init_data){ 1830 .name = "gcc_ce2_axi_clk", 1831 .parent_hws = (const struct clk_hw*[]){ 1832 &system_noc_clk_src.clkr.hw, 1833 }, 1834 .num_parents = 1, 1835 .ops = &clk_branch2_ops, 1836 }, 1837 }, 1838 }; 1839 1840 static struct clk_branch gcc_ce2_clk = { 1841 .halt_reg = 0x1090, 1842 .halt_check = BRANCH_HALT_VOTED, 1843 .clkr = { 1844 .enable_reg = 0x1484, 1845 .enable_mask = BIT(2), 1846 .hw.init = &(struct clk_init_data){ 1847 .name = "gcc_ce2_clk", 1848 .parent_hws = (const struct clk_hw*[]){ 1849 &ce2_clk_src.clkr.hw, 1850 }, 1851 .num_parents = 1, 1852 .flags = CLK_SET_RATE_PARENT, 1853 .ops = &clk_branch2_ops, 1854 }, 1855 }, 1856 }; 1857 1858 static struct clk_branch gcc_gp1_clk = { 1859 .halt_reg = 0x1900, 1860 .clkr = { 1861 .enable_reg = 0x1900, 1862 .enable_mask = BIT(0), 1863 .hw.init = &(struct clk_init_data){ 1864 .name = "gcc_gp1_clk", 1865 .parent_hws = (const struct clk_hw*[]){ 1866 &gp1_clk_src.clkr.hw, 1867 }, 1868 .num_parents = 1, 1869 .flags = CLK_SET_RATE_PARENT, 1870 .ops = &clk_branch2_ops, 1871 }, 1872 }, 1873 }; 1874 1875 static struct clk_branch gcc_gp2_clk = { 1876 .halt_reg = 0x1940, 1877 .clkr = { 1878 .enable_reg = 0x1940, 1879 .enable_mask = BIT(0), 1880 .hw.init = &(struct clk_init_data){ 1881 .name = "gcc_gp2_clk", 1882 .parent_hws = (const struct clk_hw*[]){ 1883 &gp2_clk_src.clkr.hw, 1884 }, 1885 .num_parents = 1, 1886 .flags = CLK_SET_RATE_PARENT, 1887 .ops = &clk_branch2_ops, 1888 }, 1889 }, 1890 }; 1891 1892 static struct clk_branch gcc_gp3_clk = { 1893 .halt_reg = 0x1980, 1894 .clkr = { 1895 .enable_reg = 0x1980, 1896 .enable_mask = BIT(0), 1897 .hw.init = &(struct clk_init_data){ 1898 .name = "gcc_gp3_clk", 1899 .parent_hws = (const struct clk_hw*[]){ 1900 &gp3_clk_src.clkr.hw, 1901 }, 1902 .num_parents = 1, 1903 .flags = CLK_SET_RATE_PARENT, 1904 .ops = &clk_branch2_ops, 1905 }, 1906 }, 1907 }; 1908 1909 static struct clk_branch gcc_lpass_q6_axi_clk = { 1910 .halt_reg = 0x11c0, 1911 .clkr = { 1912 .enable_reg = 0x11c0, 1913 .enable_mask = BIT(0), 1914 .hw.init = &(struct clk_init_data){ 1915 .name = "gcc_lpass_q6_axi_clk", 1916 .parent_hws = (const struct clk_hw*[]){ 1917 &system_noc_clk_src.clkr.hw, 1918 }, 1919 .num_parents = 1, 1920 .ops = &clk_branch2_ops, 1921 }, 1922 }, 1923 }; 1924 1925 static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = { 1926 .halt_reg = 0x024c, 1927 .clkr = { 1928 .enable_reg = 0x024c, 1929 .enable_mask = BIT(0), 1930 .hw.init = &(struct clk_init_data){ 1931 .name = "gcc_mmss_noc_cfg_ahb_clk", 1932 .parent_hws = (const struct clk_hw*[]){ 1933 &config_noc_clk_src.clkr.hw, 1934 }, 1935 .num_parents = 1, 1936 .ops = &clk_branch2_ops, 1937 .flags = CLK_IGNORE_UNUSED, 1938 }, 1939 }, 1940 }; 1941 1942 static struct clk_branch gcc_ocmem_noc_cfg_ahb_clk = { 1943 .halt_reg = 0x0248, 1944 .clkr = { 1945 .enable_reg = 0x0248, 1946 .enable_mask = BIT(0), 1947 .hw.init = &(struct clk_init_data){ 1948 .name = "gcc_ocmem_noc_cfg_ahb_clk", 1949 .parent_hws = (const struct clk_hw*[]){ 1950 &config_noc_clk_src.clkr.hw, 1951 }, 1952 .num_parents = 1, 1953 .ops = &clk_branch2_ops, 1954 }, 1955 }, 1956 }; 1957 1958 static struct clk_branch gcc_mss_cfg_ahb_clk = { 1959 .halt_reg = 0x0280, 1960 .clkr = { 1961 .enable_reg = 0x0280, 1962 .enable_mask = BIT(0), 1963 .hw.init = &(struct clk_init_data){ 1964 .name = "gcc_mss_cfg_ahb_clk", 1965 .parent_hws = (const struct clk_hw*[]){ 1966 &config_noc_clk_src.clkr.hw, 1967 }, 1968 .num_parents = 1, 1969 .ops = &clk_branch2_ops, 1970 }, 1971 }, 1972 }; 1973 1974 static struct clk_branch gcc_mss_q6_bimc_axi_clk = { 1975 .halt_reg = 0x0284, 1976 .clkr = { 1977 .enable_reg = 0x0284, 1978 .enable_mask = BIT(0), 1979 .hw.init = &(struct clk_init_data){ 1980 .name = "gcc_mss_q6_bimc_axi_clk", 1981 .parent_hws = (const struct clk_hw*[]){ 1982 &system_noc_clk_src.clkr.hw, 1983 }, 1984 .num_parents = 1, 1985 .ops = &clk_branch2_ops, 1986 }, 1987 }, 1988 }; 1989 1990 static struct clk_branch gcc_pdm2_clk = { 1991 .halt_reg = 0x0ccc, 1992 .clkr = { 1993 .enable_reg = 0x0ccc, 1994 .enable_mask = BIT(0), 1995 .hw.init = &(struct clk_init_data){ 1996 .name = "gcc_pdm2_clk", 1997 .parent_hws = (const struct clk_hw*[]){ 1998 &pdm2_clk_src.clkr.hw, 1999 }, 2000 .num_parents = 1, 2001 .flags = CLK_SET_RATE_PARENT, 2002 .ops = &clk_branch2_ops, 2003 }, 2004 }, 2005 }; 2006 2007 static struct clk_branch gcc_pdm_ahb_clk = { 2008 .halt_reg = 0x0cc4, 2009 .clkr = { 2010 .enable_reg = 0x0cc4, 2011 .enable_mask = BIT(0), 2012 .hw.init = &(struct clk_init_data){ 2013 .name = "gcc_pdm_ahb_clk", 2014 .parent_hws = (const struct clk_hw*[]){ 2015 &periph_noc_clk_src.clkr.hw, 2016 }, 2017 .num_parents = 1, 2018 .ops = &clk_branch2_ops, 2019 }, 2020 }, 2021 }; 2022 2023 static struct clk_branch gcc_pdm_xo4_clk = { 2024 .halt_reg = 0x0cc8, 2025 .clkr = { 2026 .enable_reg = 0x0cc8, 2027 .enable_mask = BIT(0), 2028 .hw.init = &(struct clk_init_data){ 2029 .name = "gcc_pdm_xo4_clk", 2030 .parent_data = &(const struct clk_parent_data){ 2031 .fw_name = "xo", .name = "xo_board", 2032 }, 2033 .num_parents = 1, 2034 .ops = &clk_branch2_ops, 2035 }, 2036 }, 2037 }; 2038 2039 static struct clk_branch gcc_prng_ahb_clk = { 2040 .halt_reg = 0x0d04, 2041 .halt_check = BRANCH_HALT_VOTED, 2042 .clkr = { 2043 .enable_reg = 0x1484, 2044 .enable_mask = BIT(13), 2045 .hw.init = &(struct clk_init_data){ 2046 .name = "gcc_prng_ahb_clk", 2047 .parent_hws = (const struct clk_hw*[]){ 2048 &periph_noc_clk_src.clkr.hw, 2049 }, 2050 .num_parents = 1, 2051 .ops = &clk_branch2_ops, 2052 }, 2053 }, 2054 }; 2055 2056 static struct clk_branch gcc_sdcc1_ahb_clk = { 2057 .halt_reg = 0x04c8, 2058 .clkr = { 2059 .enable_reg = 0x04c8, 2060 .enable_mask = BIT(0), 2061 .hw.init = &(struct clk_init_data){ 2062 .name = "gcc_sdcc1_ahb_clk", 2063 .parent_hws = (const struct clk_hw*[]){ 2064 &periph_noc_clk_src.clkr.hw, 2065 }, 2066 .num_parents = 1, 2067 .ops = &clk_branch2_ops, 2068 }, 2069 }, 2070 }; 2071 2072 static struct clk_branch gcc_sdcc1_apps_clk = { 2073 .halt_reg = 0x04c4, 2074 .clkr = { 2075 .enable_reg = 0x04c4, 2076 .enable_mask = BIT(0), 2077 .hw.init = &(struct clk_init_data){ 2078 .name = "gcc_sdcc1_apps_clk", 2079 .parent_hws = (const struct clk_hw*[]){ 2080 &sdcc1_apps_clk_src.clkr.hw, 2081 }, 2082 .num_parents = 1, 2083 .flags = CLK_SET_RATE_PARENT, 2084 .ops = &clk_branch2_ops, 2085 }, 2086 }, 2087 }; 2088 2089 static struct clk_branch gcc_sdcc1_cdccal_ff_clk = { 2090 .halt_reg = 0x04e8, 2091 .clkr = { 2092 .enable_reg = 0x04e8, 2093 .enable_mask = BIT(0), 2094 .hw.init = &(struct clk_init_data){ 2095 .name = "gcc_sdcc1_cdccal_ff_clk", 2096 .parent_data = (const struct clk_parent_data[]){ 2097 { .fw_name = "xo", .name = "xo_board" } 2098 }, 2099 .num_parents = 1, 2100 .ops = &clk_branch2_ops, 2101 }, 2102 }, 2103 }; 2104 2105 static struct clk_branch gcc_sdcc1_cdccal_sleep_clk = { 2106 .halt_reg = 0x04e4, 2107 .clkr = { 2108 .enable_reg = 0x04e4, 2109 .enable_mask = BIT(0), 2110 .hw.init = &(struct clk_init_data){ 2111 .name = "gcc_sdcc1_cdccal_sleep_clk", 2112 .parent_data = (const struct clk_parent_data[]){ 2113 { .fw_name = "sleep_clk", .name = "sleep_clk" } 2114 }, 2115 .num_parents = 1, 2116 .ops = &clk_branch2_ops, 2117 }, 2118 }, 2119 }; 2120 2121 static struct clk_branch gcc_sdcc2_ahb_clk = { 2122 .halt_reg = 0x0508, 2123 .clkr = { 2124 .enable_reg = 0x0508, 2125 .enable_mask = BIT(0), 2126 .hw.init = &(struct clk_init_data){ 2127 .name = "gcc_sdcc2_ahb_clk", 2128 .parent_hws = (const struct clk_hw*[]){ 2129 &periph_noc_clk_src.clkr.hw, 2130 }, 2131 .num_parents = 1, 2132 .ops = &clk_branch2_ops, 2133 }, 2134 }, 2135 }; 2136 2137 static struct clk_branch gcc_sdcc2_apps_clk = { 2138 .halt_reg = 0x0504, 2139 .clkr = { 2140 .enable_reg = 0x0504, 2141 .enable_mask = BIT(0), 2142 .hw.init = &(struct clk_init_data){ 2143 .name = "gcc_sdcc2_apps_clk", 2144 .parent_hws = (const struct clk_hw*[]){ 2145 &sdcc2_apps_clk_src.clkr.hw, 2146 }, 2147 .num_parents = 1, 2148 .flags = CLK_SET_RATE_PARENT, 2149 .ops = &clk_branch2_ops, 2150 }, 2151 }, 2152 }; 2153 2154 static struct clk_branch gcc_sdcc3_ahb_clk = { 2155 .halt_reg = 0x0548, 2156 .clkr = { 2157 .enable_reg = 0x0548, 2158 .enable_mask = BIT(0), 2159 .hw.init = &(struct clk_init_data){ 2160 .name = "gcc_sdcc3_ahb_clk", 2161 .parent_hws = (const struct clk_hw*[]){ 2162 &periph_noc_clk_src.clkr.hw, 2163 }, 2164 .num_parents = 1, 2165 .ops = &clk_branch2_ops, 2166 }, 2167 }, 2168 }; 2169 2170 static struct clk_branch gcc_sdcc3_apps_clk = { 2171 .halt_reg = 0x0544, 2172 .clkr = { 2173 .enable_reg = 0x0544, 2174 .enable_mask = BIT(0), 2175 .hw.init = &(struct clk_init_data){ 2176 .name = "gcc_sdcc3_apps_clk", 2177 .parent_hws = (const struct clk_hw*[]){ 2178 &sdcc3_apps_clk_src.clkr.hw, 2179 }, 2180 .num_parents = 1, 2181 .flags = CLK_SET_RATE_PARENT, 2182 .ops = &clk_branch2_ops, 2183 }, 2184 }, 2185 }; 2186 2187 static struct clk_branch gcc_sdcc4_ahb_clk = { 2188 .halt_reg = 0x0588, 2189 .clkr = { 2190 .enable_reg = 0x0588, 2191 .enable_mask = BIT(0), 2192 .hw.init = &(struct clk_init_data){ 2193 .name = "gcc_sdcc4_ahb_clk", 2194 .parent_hws = (const struct clk_hw*[]){ 2195 &periph_noc_clk_src.clkr.hw, 2196 }, 2197 .num_parents = 1, 2198 .ops = &clk_branch2_ops, 2199 }, 2200 }, 2201 }; 2202 2203 static struct clk_branch gcc_sdcc4_apps_clk = { 2204 .halt_reg = 0x0584, 2205 .clkr = { 2206 .enable_reg = 0x0584, 2207 .enable_mask = BIT(0), 2208 .hw.init = &(struct clk_init_data){ 2209 .name = "gcc_sdcc4_apps_clk", 2210 .parent_hws = (const struct clk_hw*[]){ 2211 &sdcc4_apps_clk_src.clkr.hw, 2212 }, 2213 .num_parents = 1, 2214 .flags = CLK_SET_RATE_PARENT, 2215 .ops = &clk_branch2_ops, 2216 }, 2217 }, 2218 }; 2219 2220 static struct clk_branch gcc_sys_noc_usb3_axi_clk = { 2221 .halt_reg = 0x0108, 2222 .clkr = { 2223 .enable_reg = 0x0108, 2224 .enable_mask = BIT(0), 2225 .hw.init = &(struct clk_init_data){ 2226 .name = "gcc_sys_noc_usb3_axi_clk", 2227 .parent_hws = (const struct clk_hw*[]){ 2228 &usb30_master_clk_src.clkr.hw, 2229 }, 2230 .num_parents = 1, 2231 .flags = CLK_SET_RATE_PARENT, 2232 .ops = &clk_branch2_ops, 2233 }, 2234 }, 2235 }; 2236 2237 static struct clk_branch gcc_tsif_ahb_clk = { 2238 .halt_reg = 0x0d84, 2239 .clkr = { 2240 .enable_reg = 0x0d84, 2241 .enable_mask = BIT(0), 2242 .hw.init = &(struct clk_init_data){ 2243 .name = "gcc_tsif_ahb_clk", 2244 .parent_hws = (const struct clk_hw*[]){ 2245 &periph_noc_clk_src.clkr.hw, 2246 }, 2247 .num_parents = 1, 2248 .ops = &clk_branch2_ops, 2249 }, 2250 }, 2251 }; 2252 2253 static struct clk_branch gcc_tsif_ref_clk = { 2254 .halt_reg = 0x0d88, 2255 .clkr = { 2256 .enable_reg = 0x0d88, 2257 .enable_mask = BIT(0), 2258 .hw.init = &(struct clk_init_data){ 2259 .name = "gcc_tsif_ref_clk", 2260 .parent_hws = (const struct clk_hw*[]){ 2261 &tsif_ref_clk_src.clkr.hw, 2262 }, 2263 .num_parents = 1, 2264 .flags = CLK_SET_RATE_PARENT, 2265 .ops = &clk_branch2_ops, 2266 }, 2267 }, 2268 }; 2269 2270 static struct clk_branch gcc_usb2a_phy_sleep_clk = { 2271 .halt_reg = 0x04ac, 2272 .clkr = { 2273 .enable_reg = 0x04ac, 2274 .enable_mask = BIT(0), 2275 .hw.init = &(struct clk_init_data){ 2276 .name = "gcc_usb2a_phy_sleep_clk", 2277 .parent_data = &(const struct clk_parent_data){ 2278 .fw_name = "sleep_clk", .name = "sleep_clk", 2279 }, 2280 .num_parents = 1, 2281 .ops = &clk_branch2_ops, 2282 }, 2283 }, 2284 }; 2285 2286 static struct clk_branch gcc_usb2b_phy_sleep_clk = { 2287 .halt_reg = 0x04b4, 2288 .clkr = { 2289 .enable_reg = 0x04b4, 2290 .enable_mask = BIT(0), 2291 .hw.init = &(struct clk_init_data){ 2292 .name = "gcc_usb2b_phy_sleep_clk", 2293 .parent_data = &(const struct clk_parent_data){ 2294 .fw_name = "sleep_clk", .name = "sleep_clk", 2295 }, 2296 .num_parents = 1, 2297 .ops = &clk_branch2_ops, 2298 }, 2299 }, 2300 }; 2301 2302 static struct clk_branch gcc_usb30_master_clk = { 2303 .halt_reg = 0x03c8, 2304 .clkr = { 2305 .enable_reg = 0x03c8, 2306 .enable_mask = BIT(0), 2307 .hw.init = &(struct clk_init_data){ 2308 .name = "gcc_usb30_master_clk", 2309 .parent_hws = (const struct clk_hw*[]){ 2310 &usb30_master_clk_src.clkr.hw, 2311 }, 2312 .num_parents = 1, 2313 .flags = CLK_SET_RATE_PARENT, 2314 .ops = &clk_branch2_ops, 2315 }, 2316 }, 2317 }; 2318 2319 static struct clk_branch gcc_usb30_mock_utmi_clk = { 2320 .halt_reg = 0x03d0, 2321 .clkr = { 2322 .enable_reg = 0x03d0, 2323 .enable_mask = BIT(0), 2324 .hw.init = &(struct clk_init_data){ 2325 .name = "gcc_usb30_mock_utmi_clk", 2326 .parent_hws = (const struct clk_hw*[]){ 2327 &usb30_mock_utmi_clk_src.clkr.hw, 2328 }, 2329 .num_parents = 1, 2330 .flags = CLK_SET_RATE_PARENT, 2331 .ops = &clk_branch2_ops, 2332 }, 2333 }, 2334 }; 2335 2336 static struct clk_branch gcc_usb30_sleep_clk = { 2337 .halt_reg = 0x03cc, 2338 .clkr = { 2339 .enable_reg = 0x03cc, 2340 .enable_mask = BIT(0), 2341 .hw.init = &(struct clk_init_data){ 2342 .name = "gcc_usb30_sleep_clk", 2343 .parent_data = &(const struct clk_parent_data){ 2344 .fw_name = "sleep_clk", .name = "sleep_clk", 2345 }, 2346 .num_parents = 1, 2347 .ops = &clk_branch2_ops, 2348 }, 2349 }, 2350 }; 2351 2352 static struct clk_branch gcc_usb_hs_ahb_clk = { 2353 .halt_reg = 0x0488, 2354 .clkr = { 2355 .enable_reg = 0x0488, 2356 .enable_mask = BIT(0), 2357 .hw.init = &(struct clk_init_data){ 2358 .name = "gcc_usb_hs_ahb_clk", 2359 .parent_hws = (const struct clk_hw*[]){ 2360 &periph_noc_clk_src.clkr.hw, 2361 }, 2362 .num_parents = 1, 2363 .ops = &clk_branch2_ops, 2364 }, 2365 }, 2366 }; 2367 2368 static struct clk_branch gcc_usb_hs_system_clk = { 2369 .halt_reg = 0x0484, 2370 .clkr = { 2371 .enable_reg = 0x0484, 2372 .enable_mask = BIT(0), 2373 .hw.init = &(struct clk_init_data){ 2374 .name = "gcc_usb_hs_system_clk", 2375 .parent_hws = (const struct clk_hw*[]){ 2376 &usb_hs_system_clk_src.clkr.hw, 2377 }, 2378 .num_parents = 1, 2379 .flags = CLK_SET_RATE_PARENT, 2380 .ops = &clk_branch2_ops, 2381 }, 2382 }, 2383 }; 2384 2385 static struct clk_branch gcc_usb_hsic_ahb_clk = { 2386 .halt_reg = 0x0408, 2387 .clkr = { 2388 .enable_reg = 0x0408, 2389 .enable_mask = BIT(0), 2390 .hw.init = &(struct clk_init_data){ 2391 .name = "gcc_usb_hsic_ahb_clk", 2392 .parent_hws = (const struct clk_hw*[]){ 2393 &periph_noc_clk_src.clkr.hw, 2394 }, 2395 .num_parents = 1, 2396 .ops = &clk_branch2_ops, 2397 }, 2398 }, 2399 }; 2400 2401 static struct clk_branch gcc_usb_hsic_clk = { 2402 .halt_reg = 0x0410, 2403 .clkr = { 2404 .enable_reg = 0x0410, 2405 .enable_mask = BIT(0), 2406 .hw.init = &(struct clk_init_data){ 2407 .name = "gcc_usb_hsic_clk", 2408 .parent_hws = (const struct clk_hw*[]){ 2409 &usb_hsic_clk_src.clkr.hw, 2410 }, 2411 .num_parents = 1, 2412 .flags = CLK_SET_RATE_PARENT, 2413 .ops = &clk_branch2_ops, 2414 }, 2415 }, 2416 }; 2417 2418 static struct clk_branch gcc_usb_hsic_io_cal_clk = { 2419 .halt_reg = 0x0414, 2420 .clkr = { 2421 .enable_reg = 0x0414, 2422 .enable_mask = BIT(0), 2423 .hw.init = &(struct clk_init_data){ 2424 .name = "gcc_usb_hsic_io_cal_clk", 2425 .parent_hws = (const struct clk_hw*[]){ 2426 &usb_hsic_io_cal_clk_src.clkr.hw, 2427 }, 2428 .num_parents = 1, 2429 .flags = CLK_SET_RATE_PARENT, 2430 .ops = &clk_branch2_ops, 2431 }, 2432 }, 2433 }; 2434 2435 static struct clk_branch gcc_usb_hsic_io_cal_sleep_clk = { 2436 .halt_reg = 0x0418, 2437 .clkr = { 2438 .enable_reg = 0x0418, 2439 .enable_mask = BIT(0), 2440 .hw.init = &(struct clk_init_data){ 2441 .name = "gcc_usb_hsic_io_cal_sleep_clk", 2442 .parent_data = &(const struct clk_parent_data){ 2443 .fw_name = "sleep_clk", .name = "sleep_clk", 2444 }, 2445 .num_parents = 1, 2446 .ops = &clk_branch2_ops, 2447 }, 2448 }, 2449 }; 2450 2451 static struct clk_branch gcc_usb_hsic_system_clk = { 2452 .halt_reg = 0x040c, 2453 .clkr = { 2454 .enable_reg = 0x040c, 2455 .enable_mask = BIT(0), 2456 .hw.init = &(struct clk_init_data){ 2457 .name = "gcc_usb_hsic_system_clk", 2458 .parent_hws = (const struct clk_hw*[]){ 2459 &usb_hsic_system_clk_src.clkr.hw, 2460 }, 2461 .num_parents = 1, 2462 .flags = CLK_SET_RATE_PARENT, 2463 .ops = &clk_branch2_ops, 2464 }, 2465 }, 2466 }; 2467 2468 static struct gdsc usb_hs_hsic_gdsc = { 2469 .gdscr = 0x404, 2470 .pd = { 2471 .name = "usb_hs_hsic", 2472 }, 2473 .pwrsts = PWRSTS_OFF_ON, 2474 }; 2475 2476 static struct clk_regmap *gcc_msm8226_clocks[] = { 2477 [GPLL0] = &gpll0.clkr, 2478 [GPLL0_VOTE] = &gpll0_vote, 2479 [GPLL1] = &gpll1.clkr, 2480 [GPLL1_VOTE] = &gpll1_vote, 2481 [CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr, 2482 [PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr, 2483 [SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr, 2484 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr, 2485 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr, 2486 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr, 2487 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr, 2488 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr, 2489 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr, 2490 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr, 2491 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr, 2492 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr, 2493 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr, 2494 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr, 2495 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr, 2496 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr, 2497 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr, 2498 [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr, 2499 [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr, 2500 [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr, 2501 [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr, 2502 [CE1_CLK_SRC] = &ce1_clk_src.clkr, 2503 [GP1_CLK_SRC] = &gp1_clk_src.clkr, 2504 [GP2_CLK_SRC] = &gp2_clk_src.clkr, 2505 [GP3_CLK_SRC] = &gp3_clk_src.clkr, 2506 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr, 2507 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr, 2508 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr, 2509 [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr, 2510 [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr, 2511 [USB_HSIC_CLK_SRC] = &usb_hsic_clk_src.clkr, 2512 [USB_HSIC_IO_CAL_CLK_SRC] = &usb_hsic_io_cal_clk_src.clkr, 2513 [USB_HSIC_SYSTEM_CLK_SRC] = &usb_hsic_system_clk_src.clkr, 2514 [GCC_BAM_DMA_AHB_CLK] = &gcc_bam_dma_ahb_clk.clkr, 2515 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr, 2516 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr, 2517 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr, 2518 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr, 2519 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr, 2520 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr, 2521 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr, 2522 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr, 2523 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr, 2524 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr, 2525 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr, 2526 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr, 2527 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr, 2528 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, 2529 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr, 2530 [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr, 2531 [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr, 2532 [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr, 2533 [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr, 2534 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 2535 [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr, 2536 [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr, 2537 [GCC_CE1_CLK] = &gcc_ce1_clk.clkr, 2538 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 2539 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 2540 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 2541 [GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr, 2542 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr, 2543 [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr, 2544 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 2545 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 2546 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 2547 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, 2548 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, 2549 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, 2550 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 2551 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 2552 [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr, 2553 [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr, 2554 [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr, 2555 [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr, 2556 [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr, 2557 [GCC_USB_HSIC_AHB_CLK] = &gcc_usb_hsic_ahb_clk.clkr, 2558 [GCC_USB_HSIC_CLK] = &gcc_usb_hsic_clk.clkr, 2559 [GCC_USB_HSIC_IO_CAL_CLK] = &gcc_usb_hsic_io_cal_clk.clkr, 2560 [GCC_USB_HSIC_SYSTEM_CLK] = &gcc_usb_hsic_system_clk.clkr, 2561 }; 2562 2563 static const struct qcom_reset_map gcc_msm8226_resets[] = { 2564 [GCC_USB_HS_HSIC_BCR] = { 0x0400 }, 2565 [GCC_USB_HS_BCR] = { 0x0480 }, 2566 [GCC_USB2A_PHY_BCR] = { 0x04a8 }, 2567 }; 2568 2569 static struct gdsc *gcc_msm8226_gdscs[] = { 2570 [USB_HS_HSIC_GDSC] = &usb_hs_hsic_gdsc, 2571 }; 2572 2573 static const struct regmap_config gcc_msm8226_regmap_config = { 2574 .reg_bits = 32, 2575 .reg_stride = 4, 2576 .val_bits = 32, 2577 .max_register = 0x1a80, 2578 .fast_io = true, 2579 }; 2580 2581 static const struct qcom_cc_desc gcc_msm8226_desc = { 2582 .config = &gcc_msm8226_regmap_config, 2583 .clks = gcc_msm8226_clocks, 2584 .num_clks = ARRAY_SIZE(gcc_msm8226_clocks), 2585 .resets = gcc_msm8226_resets, 2586 .num_resets = ARRAY_SIZE(gcc_msm8226_resets), 2587 .gdscs = gcc_msm8226_gdscs, 2588 .num_gdscs = ARRAY_SIZE(gcc_msm8226_gdscs), 2589 }; 2590 2591 static struct clk_regmap *gcc_msm8974_clocks[] = { 2592 [GPLL0] = &gpll0.clkr, 2593 [GPLL0_VOTE] = &gpll0_vote, 2594 [CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr, 2595 [PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr, 2596 [SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr, 2597 [GPLL1] = &gpll1.clkr, 2598 [GPLL1_VOTE] = &gpll1_vote, 2599 [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr, 2600 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr, 2601 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr, 2602 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr, 2603 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr, 2604 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr, 2605 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr, 2606 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr, 2607 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr, 2608 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr, 2609 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr, 2610 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr, 2611 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr, 2612 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr, 2613 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr, 2614 [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr, 2615 [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr, 2616 [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr, 2617 [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr, 2618 [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr, 2619 [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr, 2620 [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr, 2621 [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr, 2622 [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr, 2623 [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr, 2624 [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr, 2625 [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr, 2626 [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr, 2627 [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr, 2628 [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr, 2629 [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr, 2630 [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr, 2631 [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr, 2632 [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr, 2633 [BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr, 2634 [BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr, 2635 [BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr, 2636 [CE1_CLK_SRC] = &ce1_clk_src.clkr, 2637 [CE2_CLK_SRC] = &ce2_clk_src.clkr, 2638 [GP1_CLK_SRC] = &gp1_clk_src.clkr, 2639 [GP2_CLK_SRC] = &gp2_clk_src.clkr, 2640 [GP3_CLK_SRC] = &gp3_clk_src.clkr, 2641 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr, 2642 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr, 2643 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr, 2644 [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr, 2645 [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr, 2646 [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr, 2647 [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr, 2648 [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr, 2649 [USB_HSIC_CLK_SRC] = &usb_hsic_clk_src.clkr, 2650 [USB_HSIC_IO_CAL_CLK_SRC] = &usb_hsic_io_cal_clk_src.clkr, 2651 [USB_HSIC_SYSTEM_CLK_SRC] = &usb_hsic_system_clk_src.clkr, 2652 [GCC_BAM_DMA_AHB_CLK] = &gcc_bam_dma_ahb_clk.clkr, 2653 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr, 2654 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr, 2655 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr, 2656 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr, 2657 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr, 2658 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr, 2659 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr, 2660 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr, 2661 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr, 2662 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr, 2663 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr, 2664 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr, 2665 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr, 2666 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, 2667 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr, 2668 [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr, 2669 [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr, 2670 [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr, 2671 [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr, 2672 [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr, 2673 [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr, 2674 [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr, 2675 [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr, 2676 [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr, 2677 [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr, 2678 [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr, 2679 [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr, 2680 [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr, 2681 [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr, 2682 [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr, 2683 [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr, 2684 [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr, 2685 [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr, 2686 [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr, 2687 [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr, 2688 [GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr, 2689 [GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr, 2690 [GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr, 2691 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 2692 [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr, 2693 [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr, 2694 [GCC_CE1_CLK] = &gcc_ce1_clk.clkr, 2695 [GCC_CE2_AHB_CLK] = &gcc_ce2_ahb_clk.clkr, 2696 [GCC_CE2_AXI_CLK] = &gcc_ce2_axi_clk.clkr, 2697 [GCC_CE2_CLK] = &gcc_ce2_clk.clkr, 2698 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 2699 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 2700 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 2701 [GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr, 2702 [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr, 2703 [GCC_OCMEM_NOC_CFG_AHB_CLK] = &gcc_ocmem_noc_cfg_ahb_clk.clkr, 2704 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr, 2705 [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr, 2706 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 2707 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 2708 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, 2709 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, 2710 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, 2711 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 2712 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 2713 [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr, 2714 [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr, 2715 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, 2716 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, 2717 [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr, 2718 [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr, 2719 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr, 2720 [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr, 2721 [GCC_USB2B_PHY_SLEEP_CLK] = &gcc_usb2b_phy_sleep_clk.clkr, 2722 [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr, 2723 [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr, 2724 [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr, 2725 [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr, 2726 [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr, 2727 [GCC_USB_HSIC_AHB_CLK] = &gcc_usb_hsic_ahb_clk.clkr, 2728 [GCC_USB_HSIC_CLK] = &gcc_usb_hsic_clk.clkr, 2729 [GCC_USB_HSIC_IO_CAL_CLK] = &gcc_usb_hsic_io_cal_clk.clkr, 2730 [GCC_USB_HSIC_IO_CAL_SLEEP_CLK] = &gcc_usb_hsic_io_cal_sleep_clk.clkr, 2731 [GCC_USB_HSIC_SYSTEM_CLK] = &gcc_usb_hsic_system_clk.clkr, 2732 [GCC_MMSS_GPLL0_CLK_SRC] = &gcc_mmss_gpll0_clk_src, 2733 [GPLL4] = NULL, 2734 [GPLL4_VOTE] = NULL, 2735 [GCC_SDCC1_CDCCAL_SLEEP_CLK] = NULL, 2736 [GCC_SDCC1_CDCCAL_FF_CLK] = NULL, 2737 }; 2738 2739 static const struct qcom_reset_map gcc_msm8974_resets[] = { 2740 [GCC_SYSTEM_NOC_BCR] = { 0x0100 }, 2741 [GCC_CONFIG_NOC_BCR] = { 0x0140 }, 2742 [GCC_PERIPH_NOC_BCR] = { 0x0180 }, 2743 [GCC_IMEM_BCR] = { 0x0200 }, 2744 [GCC_MMSS_BCR] = { 0x0240 }, 2745 [GCC_QDSS_BCR] = { 0x0300 }, 2746 [GCC_USB_30_BCR] = { 0x03c0 }, 2747 [GCC_USB3_PHY_BCR] = { 0x03fc }, 2748 [GCC_USB_HS_HSIC_BCR] = { 0x0400 }, 2749 [GCC_USB_HS_BCR] = { 0x0480 }, 2750 [GCC_USB2A_PHY_BCR] = { 0x04a8 }, 2751 [GCC_USB2B_PHY_BCR] = { 0x04b0 }, 2752 [GCC_SDCC1_BCR] = { 0x04c0 }, 2753 [GCC_SDCC2_BCR] = { 0x0500 }, 2754 [GCC_SDCC3_BCR] = { 0x0540 }, 2755 [GCC_SDCC4_BCR] = { 0x0580 }, 2756 [GCC_BLSP1_BCR] = { 0x05c0 }, 2757 [GCC_BLSP1_QUP1_BCR] = { 0x0640 }, 2758 [GCC_BLSP1_UART1_BCR] = { 0x0680 }, 2759 [GCC_BLSP1_QUP2_BCR] = { 0x06c0 }, 2760 [GCC_BLSP1_UART2_BCR] = { 0x0700 }, 2761 [GCC_BLSP1_QUP3_BCR] = { 0x0740 }, 2762 [GCC_BLSP1_UART3_BCR] = { 0x0780 }, 2763 [GCC_BLSP1_QUP4_BCR] = { 0x07c0 }, 2764 [GCC_BLSP1_UART4_BCR] = { 0x0800 }, 2765 [GCC_BLSP1_QUP5_BCR] = { 0x0840 }, 2766 [GCC_BLSP1_UART5_BCR] = { 0x0880 }, 2767 [GCC_BLSP1_QUP6_BCR] = { 0x08c0 }, 2768 [GCC_BLSP1_UART6_BCR] = { 0x0900 }, 2769 [GCC_BLSP2_BCR] = { 0x0940 }, 2770 [GCC_BLSP2_QUP1_BCR] = { 0x0980 }, 2771 [GCC_BLSP2_UART1_BCR] = { 0x09c0 }, 2772 [GCC_BLSP2_QUP2_BCR] = { 0x0a00 }, 2773 [GCC_BLSP2_UART2_BCR] = { 0x0a40 }, 2774 [GCC_BLSP2_QUP3_BCR] = { 0x0a80 }, 2775 [GCC_BLSP2_UART3_BCR] = { 0x0ac0 }, 2776 [GCC_BLSP2_QUP4_BCR] = { 0x0b00 }, 2777 [GCC_BLSP2_UART4_BCR] = { 0x0b40 }, 2778 [GCC_BLSP2_QUP5_BCR] = { 0x0b80 }, 2779 [GCC_BLSP2_UART5_BCR] = { 0x0bc0 }, 2780 [GCC_BLSP2_QUP6_BCR] = { 0x0c00 }, 2781 [GCC_BLSP2_UART6_BCR] = { 0x0c40 }, 2782 [GCC_PDM_BCR] = { 0x0cc0 }, 2783 [GCC_BAM_DMA_BCR] = { 0x0d40 }, 2784 [GCC_TSIF_BCR] = { 0x0d80 }, 2785 [GCC_TCSR_BCR] = { 0x0dc0 }, 2786 [GCC_BOOT_ROM_BCR] = { 0x0e00 }, 2787 [GCC_MSG_RAM_BCR] = { 0x0e40 }, 2788 [GCC_TLMM_BCR] = { 0x0e80 }, 2789 [GCC_MPM_BCR] = { 0x0ec0 }, 2790 [GCC_SEC_CTRL_BCR] = { 0x0f40 }, 2791 [GCC_SPMI_BCR] = { 0x0fc0 }, 2792 [GCC_SPDM_BCR] = { 0x1000 }, 2793 [GCC_CE1_BCR] = { 0x1040 }, 2794 [GCC_CE2_BCR] = { 0x1080 }, 2795 [GCC_BIMC_BCR] = { 0x1100 }, 2796 [GCC_MPM_NON_AHB_RESET] = { 0x0ec4, 2 }, 2797 [GCC_MPM_AHB_RESET] = { 0x0ec4, 1 }, 2798 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x1240 }, 2799 [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x1248 }, 2800 [GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x1280 }, 2801 [GCC_PNOC_BUS_TIMEOUT1_BCR] = { 0x1288 }, 2802 [GCC_PNOC_BUS_TIMEOUT2_BCR] = { 0x1290 }, 2803 [GCC_PNOC_BUS_TIMEOUT3_BCR] = { 0x1298 }, 2804 [GCC_PNOC_BUS_TIMEOUT4_BCR] = { 0x12a0 }, 2805 [GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x12c0 }, 2806 [GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x12c8 }, 2807 [GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x12d0 }, 2808 [GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x12d8 }, 2809 [GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x12e0 }, 2810 [GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x12e8 }, 2811 [GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x12f0 }, 2812 [GCC_DEHR_BCR] = { 0x1300 }, 2813 [GCC_RBCPR_BCR] = { 0x1380 }, 2814 [GCC_MSS_RESTART] = { 0x1680 }, 2815 [GCC_LPASS_RESTART] = { 0x16c0 }, 2816 [GCC_WCSS_RESTART] = { 0x1700 }, 2817 [GCC_VENUS_RESTART] = { 0x1740 }, 2818 }; 2819 2820 static struct gdsc *gcc_msm8974_gdscs[] = { 2821 [USB_HS_HSIC_GDSC] = &usb_hs_hsic_gdsc, 2822 }; 2823 2824 static const struct regmap_config gcc_msm8974_regmap_config = { 2825 .reg_bits = 32, 2826 .reg_stride = 4, 2827 .val_bits = 32, 2828 .max_register = 0x1fc0, 2829 .fast_io = true, 2830 }; 2831 2832 static const struct qcom_cc_desc gcc_msm8974_desc = { 2833 .config = &gcc_msm8974_regmap_config, 2834 .clks = gcc_msm8974_clocks, 2835 .num_clks = ARRAY_SIZE(gcc_msm8974_clocks), 2836 .resets = gcc_msm8974_resets, 2837 .num_resets = ARRAY_SIZE(gcc_msm8974_resets), 2838 .gdscs = gcc_msm8974_gdscs, 2839 .num_gdscs = ARRAY_SIZE(gcc_msm8974_gdscs), 2840 }; 2841 2842 static const struct of_device_id gcc_msm8974_match_table[] = { 2843 { .compatible = "qcom,gcc-msm8226", .data = &gcc_msm8226_desc }, 2844 { .compatible = "qcom,gcc-msm8974", .data = &gcc_msm8974_desc }, 2845 { .compatible = "qcom,gcc-msm8974pro", .data = &gcc_msm8974_desc }, 2846 { .compatible = "qcom,gcc-msm8974pro-ac", .data = &gcc_msm8974_desc }, 2847 { } 2848 }; 2849 MODULE_DEVICE_TABLE(of, gcc_msm8974_match_table); 2850 2851 static void msm8226_clock_override(void) 2852 { 2853 ce1_clk_src.freq_tbl = ftbl_gcc_ce1_clk_msm8226; 2854 gp1_clk_src.freq_tbl = ftbl_gcc_gp_clk_msm8226; 2855 gp2_clk_src.freq_tbl = ftbl_gcc_gp_clk_msm8226; 2856 gp3_clk_src.freq_tbl = ftbl_gcc_gp_clk_msm8226; 2857 } 2858 2859 static void msm8974_pro_clock_override(void) 2860 { 2861 sdcc1_apps_clk_src_init.parent_data = gcc_xo_gpll0_gpll4; 2862 sdcc1_apps_clk_src_init.num_parents = 3; 2863 sdcc1_apps_clk_src.freq_tbl = ftbl_gcc_sdcc1_apps_clk_pro; 2864 sdcc1_apps_clk_src.parent_map = gcc_xo_gpll0_gpll4_map; 2865 2866 gcc_msm8974_clocks[GPLL4] = &gpll4.clkr; 2867 gcc_msm8974_clocks[GPLL4_VOTE] = &gpll4_vote; 2868 gcc_msm8974_clocks[GCC_SDCC1_CDCCAL_SLEEP_CLK] = 2869 &gcc_sdcc1_cdccal_sleep_clk.clkr; 2870 gcc_msm8974_clocks[GCC_SDCC1_CDCCAL_FF_CLK] = 2871 &gcc_sdcc1_cdccal_ff_clk.clkr; 2872 } 2873 2874 static int gcc_msm8974_probe(struct platform_device *pdev) 2875 { 2876 int ret; 2877 struct device *dev = &pdev->dev; 2878 const struct of_device_id *id; 2879 2880 id = of_match_device(gcc_msm8974_match_table, dev); 2881 if (!id) 2882 return -ENODEV; 2883 2884 if (!of_device_is_compatible(dev->of_node, "qcom,gcc-msm8974")) { 2885 if (id->data == &gcc_msm8226_desc) 2886 msm8226_clock_override(); 2887 else 2888 msm8974_pro_clock_override(); 2889 } 2890 2891 ret = qcom_cc_register_board_clk(dev, "xo_board", "xo", 19200000); 2892 if (ret) 2893 return ret; 2894 2895 ret = qcom_cc_register_sleep_clk(dev); 2896 if (ret) 2897 return ret; 2898 2899 return qcom_cc_probe(pdev, &gcc_msm8974_desc); 2900 } 2901 2902 static struct platform_driver gcc_msm8974_driver = { 2903 .probe = gcc_msm8974_probe, 2904 .driver = { 2905 .name = "gcc-msm8974", 2906 .of_match_table = gcc_msm8974_match_table, 2907 }, 2908 }; 2909 2910 static int __init gcc_msm8974_init(void) 2911 { 2912 return platform_driver_register(&gcc_msm8974_driver); 2913 } 2914 core_initcall(gcc_msm8974_init); 2915 2916 static void __exit gcc_msm8974_exit(void) 2917 { 2918 platform_driver_unregister(&gcc_msm8974_driver); 2919 } 2920 module_exit(gcc_msm8974_exit); 2921 2922 MODULE_DESCRIPTION("QCOM GCC MSM8974 Driver"); 2923 MODULE_LICENSE("GPL v2"); 2924 MODULE_ALIAS("platform:gcc-msm8974"); 2925