1 /* 2 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include <linux/kernel.h> 15 #include <linux/bitops.h> 16 #include <linux/err.h> 17 #include <linux/platform_device.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/of_device.h> 21 #include <linux/clk-provider.h> 22 #include <linux/regmap.h> 23 #include <linux/reset-controller.h> 24 25 #include <dt-bindings/clock/qcom,gcc-msm8960.h> 26 #include <dt-bindings/reset/qcom,gcc-msm8960.h> 27 28 #include "common.h" 29 #include "clk-regmap.h" 30 #include "clk-pll.h" 31 #include "clk-rcg.h" 32 #include "clk-branch.h" 33 #include "reset.h" 34 35 static struct clk_pll pll3 = { 36 .l_reg = 0x3164, 37 .m_reg = 0x3168, 38 .n_reg = 0x316c, 39 .config_reg = 0x3174, 40 .mode_reg = 0x3160, 41 .status_reg = 0x3178, 42 .status_bit = 16, 43 .clkr.hw.init = &(struct clk_init_data){ 44 .name = "pll3", 45 .parent_names = (const char *[]){ "pxo" }, 46 .num_parents = 1, 47 .ops = &clk_pll_ops, 48 }, 49 }; 50 51 static struct clk_regmap pll4_vote = { 52 .enable_reg = 0x34c0, 53 .enable_mask = BIT(4), 54 .hw.init = &(struct clk_init_data){ 55 .name = "pll4_vote", 56 .parent_names = (const char *[]){ "pll4" }, 57 .num_parents = 1, 58 .ops = &clk_pll_vote_ops, 59 }, 60 }; 61 62 static struct clk_pll pll8 = { 63 .l_reg = 0x3144, 64 .m_reg = 0x3148, 65 .n_reg = 0x314c, 66 .config_reg = 0x3154, 67 .mode_reg = 0x3140, 68 .status_reg = 0x3158, 69 .status_bit = 16, 70 .clkr.hw.init = &(struct clk_init_data){ 71 .name = "pll8", 72 .parent_names = (const char *[]){ "pxo" }, 73 .num_parents = 1, 74 .ops = &clk_pll_ops, 75 }, 76 }; 77 78 static struct clk_regmap pll8_vote = { 79 .enable_reg = 0x34c0, 80 .enable_mask = BIT(8), 81 .hw.init = &(struct clk_init_data){ 82 .name = "pll8_vote", 83 .parent_names = (const char *[]){ "pll8" }, 84 .num_parents = 1, 85 .ops = &clk_pll_vote_ops, 86 }, 87 }; 88 89 static struct clk_pll pll14 = { 90 .l_reg = 0x31c4, 91 .m_reg = 0x31c8, 92 .n_reg = 0x31cc, 93 .config_reg = 0x31d4, 94 .mode_reg = 0x31c0, 95 .status_reg = 0x31d8, 96 .status_bit = 16, 97 .clkr.hw.init = &(struct clk_init_data){ 98 .name = "pll14", 99 .parent_names = (const char *[]){ "pxo" }, 100 .num_parents = 1, 101 .ops = &clk_pll_ops, 102 }, 103 }; 104 105 static struct clk_regmap pll14_vote = { 106 .enable_reg = 0x34c0, 107 .enable_mask = BIT(14), 108 .hw.init = &(struct clk_init_data){ 109 .name = "pll14_vote", 110 .parent_names = (const char *[]){ "pll14" }, 111 .num_parents = 1, 112 .ops = &clk_pll_vote_ops, 113 }, 114 }; 115 116 #define P_PXO 0 117 #define P_PLL8 1 118 #define P_PLL3 2 119 #define P_CXO 2 120 121 static const u8 gcc_pxo_pll8_map[] = { 122 [P_PXO] = 0, 123 [P_PLL8] = 3, 124 }; 125 126 static const char *gcc_pxo_pll8[] = { 127 "pxo", 128 "pll8_vote", 129 }; 130 131 static const u8 gcc_pxo_pll8_cxo_map[] = { 132 [P_PXO] = 0, 133 [P_PLL8] = 3, 134 [P_CXO] = 5, 135 }; 136 137 static const char *gcc_pxo_pll8_cxo[] = { 138 "pxo", 139 "pll8_vote", 140 "cxo", 141 }; 142 143 static const u8 gcc_pxo_pll8_pll3_map[] = { 144 [P_PXO] = 0, 145 [P_PLL8] = 3, 146 [P_PLL3] = 6, 147 }; 148 149 static const char *gcc_pxo_pll8_pll3[] = { 150 "pxo", 151 "pll8_vote", 152 "pll3", 153 }; 154 155 static struct freq_tbl clk_tbl_gsbi_uart[] = { 156 { 1843200, P_PLL8, 2, 6, 625 }, 157 { 3686400, P_PLL8, 2, 12, 625 }, 158 { 7372800, P_PLL8, 2, 24, 625 }, 159 { 14745600, P_PLL8, 2, 48, 625 }, 160 { 16000000, P_PLL8, 4, 1, 6 }, 161 { 24000000, P_PLL8, 4, 1, 4 }, 162 { 32000000, P_PLL8, 4, 1, 3 }, 163 { 40000000, P_PLL8, 1, 5, 48 }, 164 { 46400000, P_PLL8, 1, 29, 240 }, 165 { 48000000, P_PLL8, 4, 1, 2 }, 166 { 51200000, P_PLL8, 1, 2, 15 }, 167 { 56000000, P_PLL8, 1, 7, 48 }, 168 { 58982400, P_PLL8, 1, 96, 625 }, 169 { 64000000, P_PLL8, 2, 1, 3 }, 170 { } 171 }; 172 173 static struct clk_rcg gsbi1_uart_src = { 174 .ns_reg = 0x29d4, 175 .md_reg = 0x29d0, 176 .mn = { 177 .mnctr_en_bit = 8, 178 .mnctr_reset_bit = 7, 179 .mnctr_mode_shift = 5, 180 .n_val_shift = 16, 181 .m_val_shift = 16, 182 .width = 16, 183 }, 184 .p = { 185 .pre_div_shift = 3, 186 .pre_div_width = 2, 187 }, 188 .s = { 189 .src_sel_shift = 0, 190 .parent_map = gcc_pxo_pll8_map, 191 }, 192 .freq_tbl = clk_tbl_gsbi_uart, 193 .clkr = { 194 .enable_reg = 0x29d4, 195 .enable_mask = BIT(11), 196 .hw.init = &(struct clk_init_data){ 197 .name = "gsbi1_uart_src", 198 .parent_names = gcc_pxo_pll8, 199 .num_parents = 2, 200 .ops = &clk_rcg_ops, 201 .flags = CLK_SET_PARENT_GATE, 202 }, 203 }, 204 }; 205 206 static struct clk_branch gsbi1_uart_clk = { 207 .halt_reg = 0x2fcc, 208 .halt_bit = 10, 209 .clkr = { 210 .enable_reg = 0x29d4, 211 .enable_mask = BIT(9), 212 .hw.init = &(struct clk_init_data){ 213 .name = "gsbi1_uart_clk", 214 .parent_names = (const char *[]){ 215 "gsbi1_uart_src", 216 }, 217 .num_parents = 1, 218 .ops = &clk_branch_ops, 219 .flags = CLK_SET_RATE_PARENT, 220 }, 221 }, 222 }; 223 224 static struct clk_rcg gsbi2_uart_src = { 225 .ns_reg = 0x29f4, 226 .md_reg = 0x29f0, 227 .mn = { 228 .mnctr_en_bit = 8, 229 .mnctr_reset_bit = 7, 230 .mnctr_mode_shift = 5, 231 .n_val_shift = 16, 232 .m_val_shift = 16, 233 .width = 16, 234 }, 235 .p = { 236 .pre_div_shift = 3, 237 .pre_div_width = 2, 238 }, 239 .s = { 240 .src_sel_shift = 0, 241 .parent_map = gcc_pxo_pll8_map, 242 }, 243 .freq_tbl = clk_tbl_gsbi_uart, 244 .clkr = { 245 .enable_reg = 0x29f4, 246 .enable_mask = BIT(11), 247 .hw.init = &(struct clk_init_data){ 248 .name = "gsbi2_uart_src", 249 .parent_names = gcc_pxo_pll8, 250 .num_parents = 2, 251 .ops = &clk_rcg_ops, 252 .flags = CLK_SET_PARENT_GATE, 253 }, 254 }, 255 }; 256 257 static struct clk_branch gsbi2_uart_clk = { 258 .halt_reg = 0x2fcc, 259 .halt_bit = 6, 260 .clkr = { 261 .enable_reg = 0x29f4, 262 .enable_mask = BIT(9), 263 .hw.init = &(struct clk_init_data){ 264 .name = "gsbi2_uart_clk", 265 .parent_names = (const char *[]){ 266 "gsbi2_uart_src", 267 }, 268 .num_parents = 1, 269 .ops = &clk_branch_ops, 270 .flags = CLK_SET_RATE_PARENT, 271 }, 272 }, 273 }; 274 275 static struct clk_rcg gsbi3_uart_src = { 276 .ns_reg = 0x2a14, 277 .md_reg = 0x2a10, 278 .mn = { 279 .mnctr_en_bit = 8, 280 .mnctr_reset_bit = 7, 281 .mnctr_mode_shift = 5, 282 .n_val_shift = 16, 283 .m_val_shift = 16, 284 .width = 16, 285 }, 286 .p = { 287 .pre_div_shift = 3, 288 .pre_div_width = 2, 289 }, 290 .s = { 291 .src_sel_shift = 0, 292 .parent_map = gcc_pxo_pll8_map, 293 }, 294 .freq_tbl = clk_tbl_gsbi_uart, 295 .clkr = { 296 .enable_reg = 0x2a14, 297 .enable_mask = BIT(11), 298 .hw.init = &(struct clk_init_data){ 299 .name = "gsbi3_uart_src", 300 .parent_names = gcc_pxo_pll8, 301 .num_parents = 2, 302 .ops = &clk_rcg_ops, 303 .flags = CLK_SET_PARENT_GATE, 304 }, 305 }, 306 }; 307 308 static struct clk_branch gsbi3_uart_clk = { 309 .halt_reg = 0x2fcc, 310 .halt_bit = 2, 311 .clkr = { 312 .enable_reg = 0x2a14, 313 .enable_mask = BIT(9), 314 .hw.init = &(struct clk_init_data){ 315 .name = "gsbi3_uart_clk", 316 .parent_names = (const char *[]){ 317 "gsbi3_uart_src", 318 }, 319 .num_parents = 1, 320 .ops = &clk_branch_ops, 321 .flags = CLK_SET_RATE_PARENT, 322 }, 323 }, 324 }; 325 326 static struct clk_rcg gsbi4_uart_src = { 327 .ns_reg = 0x2a34, 328 .md_reg = 0x2a30, 329 .mn = { 330 .mnctr_en_bit = 8, 331 .mnctr_reset_bit = 7, 332 .mnctr_mode_shift = 5, 333 .n_val_shift = 16, 334 .m_val_shift = 16, 335 .width = 16, 336 }, 337 .p = { 338 .pre_div_shift = 3, 339 .pre_div_width = 2, 340 }, 341 .s = { 342 .src_sel_shift = 0, 343 .parent_map = gcc_pxo_pll8_map, 344 }, 345 .freq_tbl = clk_tbl_gsbi_uart, 346 .clkr = { 347 .enable_reg = 0x2a34, 348 .enable_mask = BIT(11), 349 .hw.init = &(struct clk_init_data){ 350 .name = "gsbi4_uart_src", 351 .parent_names = gcc_pxo_pll8, 352 .num_parents = 2, 353 .ops = &clk_rcg_ops, 354 .flags = CLK_SET_PARENT_GATE, 355 }, 356 }, 357 }; 358 359 static struct clk_branch gsbi4_uart_clk = { 360 .halt_reg = 0x2fd0, 361 .halt_bit = 26, 362 .clkr = { 363 .enable_reg = 0x2a34, 364 .enable_mask = BIT(9), 365 .hw.init = &(struct clk_init_data){ 366 .name = "gsbi4_uart_clk", 367 .parent_names = (const char *[]){ 368 "gsbi4_uart_src", 369 }, 370 .num_parents = 1, 371 .ops = &clk_branch_ops, 372 .flags = CLK_SET_RATE_PARENT, 373 }, 374 }, 375 }; 376 377 static struct clk_rcg gsbi5_uart_src = { 378 .ns_reg = 0x2a54, 379 .md_reg = 0x2a50, 380 .mn = { 381 .mnctr_en_bit = 8, 382 .mnctr_reset_bit = 7, 383 .mnctr_mode_shift = 5, 384 .n_val_shift = 16, 385 .m_val_shift = 16, 386 .width = 16, 387 }, 388 .p = { 389 .pre_div_shift = 3, 390 .pre_div_width = 2, 391 }, 392 .s = { 393 .src_sel_shift = 0, 394 .parent_map = gcc_pxo_pll8_map, 395 }, 396 .freq_tbl = clk_tbl_gsbi_uart, 397 .clkr = { 398 .enable_reg = 0x2a54, 399 .enable_mask = BIT(11), 400 .hw.init = &(struct clk_init_data){ 401 .name = "gsbi5_uart_src", 402 .parent_names = gcc_pxo_pll8, 403 .num_parents = 2, 404 .ops = &clk_rcg_ops, 405 .flags = CLK_SET_PARENT_GATE, 406 }, 407 }, 408 }; 409 410 static struct clk_branch gsbi5_uart_clk = { 411 .halt_reg = 0x2fd0, 412 .halt_bit = 22, 413 .clkr = { 414 .enable_reg = 0x2a54, 415 .enable_mask = BIT(9), 416 .hw.init = &(struct clk_init_data){ 417 .name = "gsbi5_uart_clk", 418 .parent_names = (const char *[]){ 419 "gsbi5_uart_src", 420 }, 421 .num_parents = 1, 422 .ops = &clk_branch_ops, 423 .flags = CLK_SET_RATE_PARENT, 424 }, 425 }, 426 }; 427 428 static struct clk_rcg gsbi6_uart_src = { 429 .ns_reg = 0x2a74, 430 .md_reg = 0x2a70, 431 .mn = { 432 .mnctr_en_bit = 8, 433 .mnctr_reset_bit = 7, 434 .mnctr_mode_shift = 5, 435 .n_val_shift = 16, 436 .m_val_shift = 16, 437 .width = 16, 438 }, 439 .p = { 440 .pre_div_shift = 3, 441 .pre_div_width = 2, 442 }, 443 .s = { 444 .src_sel_shift = 0, 445 .parent_map = gcc_pxo_pll8_map, 446 }, 447 .freq_tbl = clk_tbl_gsbi_uart, 448 .clkr = { 449 .enable_reg = 0x2a74, 450 .enable_mask = BIT(11), 451 .hw.init = &(struct clk_init_data){ 452 .name = "gsbi6_uart_src", 453 .parent_names = gcc_pxo_pll8, 454 .num_parents = 2, 455 .ops = &clk_rcg_ops, 456 .flags = CLK_SET_PARENT_GATE, 457 }, 458 }, 459 }; 460 461 static struct clk_branch gsbi6_uart_clk = { 462 .halt_reg = 0x2fd0, 463 .halt_bit = 18, 464 .clkr = { 465 .enable_reg = 0x2a74, 466 .enable_mask = BIT(9), 467 .hw.init = &(struct clk_init_data){ 468 .name = "gsbi6_uart_clk", 469 .parent_names = (const char *[]){ 470 "gsbi6_uart_src", 471 }, 472 .num_parents = 1, 473 .ops = &clk_branch_ops, 474 .flags = CLK_SET_RATE_PARENT, 475 }, 476 }, 477 }; 478 479 static struct clk_rcg gsbi7_uart_src = { 480 .ns_reg = 0x2a94, 481 .md_reg = 0x2a90, 482 .mn = { 483 .mnctr_en_bit = 8, 484 .mnctr_reset_bit = 7, 485 .mnctr_mode_shift = 5, 486 .n_val_shift = 16, 487 .m_val_shift = 16, 488 .width = 16, 489 }, 490 .p = { 491 .pre_div_shift = 3, 492 .pre_div_width = 2, 493 }, 494 .s = { 495 .src_sel_shift = 0, 496 .parent_map = gcc_pxo_pll8_map, 497 }, 498 .freq_tbl = clk_tbl_gsbi_uart, 499 .clkr = { 500 .enable_reg = 0x2a94, 501 .enable_mask = BIT(11), 502 .hw.init = &(struct clk_init_data){ 503 .name = "gsbi7_uart_src", 504 .parent_names = gcc_pxo_pll8, 505 .num_parents = 2, 506 .ops = &clk_rcg_ops, 507 .flags = CLK_SET_PARENT_GATE, 508 }, 509 }, 510 }; 511 512 static struct clk_branch gsbi7_uart_clk = { 513 .halt_reg = 0x2fd0, 514 .halt_bit = 14, 515 .clkr = { 516 .enable_reg = 0x2a94, 517 .enable_mask = BIT(9), 518 .hw.init = &(struct clk_init_data){ 519 .name = "gsbi7_uart_clk", 520 .parent_names = (const char *[]){ 521 "gsbi7_uart_src", 522 }, 523 .num_parents = 1, 524 .ops = &clk_branch_ops, 525 .flags = CLK_SET_RATE_PARENT, 526 }, 527 }, 528 }; 529 530 static struct clk_rcg gsbi8_uart_src = { 531 .ns_reg = 0x2ab4, 532 .md_reg = 0x2ab0, 533 .mn = { 534 .mnctr_en_bit = 8, 535 .mnctr_reset_bit = 7, 536 .mnctr_mode_shift = 5, 537 .n_val_shift = 16, 538 .m_val_shift = 16, 539 .width = 16, 540 }, 541 .p = { 542 .pre_div_shift = 3, 543 .pre_div_width = 2, 544 }, 545 .s = { 546 .src_sel_shift = 0, 547 .parent_map = gcc_pxo_pll8_map, 548 }, 549 .freq_tbl = clk_tbl_gsbi_uart, 550 .clkr = { 551 .enable_reg = 0x2ab4, 552 .enable_mask = BIT(11), 553 .hw.init = &(struct clk_init_data){ 554 .name = "gsbi8_uart_src", 555 .parent_names = gcc_pxo_pll8, 556 .num_parents = 2, 557 .ops = &clk_rcg_ops, 558 .flags = CLK_SET_PARENT_GATE, 559 }, 560 }, 561 }; 562 563 static struct clk_branch gsbi8_uart_clk = { 564 .halt_reg = 0x2fd0, 565 .halt_bit = 10, 566 .clkr = { 567 .enable_reg = 0x2ab4, 568 .enable_mask = BIT(9), 569 .hw.init = &(struct clk_init_data){ 570 .name = "gsbi8_uart_clk", 571 .parent_names = (const char *[]){ "gsbi8_uart_src" }, 572 .num_parents = 1, 573 .ops = &clk_branch_ops, 574 .flags = CLK_SET_RATE_PARENT, 575 }, 576 }, 577 }; 578 579 static struct clk_rcg gsbi9_uart_src = { 580 .ns_reg = 0x2ad4, 581 .md_reg = 0x2ad0, 582 .mn = { 583 .mnctr_en_bit = 8, 584 .mnctr_reset_bit = 7, 585 .mnctr_mode_shift = 5, 586 .n_val_shift = 16, 587 .m_val_shift = 16, 588 .width = 16, 589 }, 590 .p = { 591 .pre_div_shift = 3, 592 .pre_div_width = 2, 593 }, 594 .s = { 595 .src_sel_shift = 0, 596 .parent_map = gcc_pxo_pll8_map, 597 }, 598 .freq_tbl = clk_tbl_gsbi_uart, 599 .clkr = { 600 .enable_reg = 0x2ad4, 601 .enable_mask = BIT(11), 602 .hw.init = &(struct clk_init_data){ 603 .name = "gsbi9_uart_src", 604 .parent_names = gcc_pxo_pll8, 605 .num_parents = 2, 606 .ops = &clk_rcg_ops, 607 .flags = CLK_SET_PARENT_GATE, 608 }, 609 }, 610 }; 611 612 static struct clk_branch gsbi9_uart_clk = { 613 .halt_reg = 0x2fd0, 614 .halt_bit = 6, 615 .clkr = { 616 .enable_reg = 0x2ad4, 617 .enable_mask = BIT(9), 618 .hw.init = &(struct clk_init_data){ 619 .name = "gsbi9_uart_clk", 620 .parent_names = (const char *[]){ "gsbi9_uart_src" }, 621 .num_parents = 1, 622 .ops = &clk_branch_ops, 623 .flags = CLK_SET_RATE_PARENT, 624 }, 625 }, 626 }; 627 628 static struct clk_rcg gsbi10_uart_src = { 629 .ns_reg = 0x2af4, 630 .md_reg = 0x2af0, 631 .mn = { 632 .mnctr_en_bit = 8, 633 .mnctr_reset_bit = 7, 634 .mnctr_mode_shift = 5, 635 .n_val_shift = 16, 636 .m_val_shift = 16, 637 .width = 16, 638 }, 639 .p = { 640 .pre_div_shift = 3, 641 .pre_div_width = 2, 642 }, 643 .s = { 644 .src_sel_shift = 0, 645 .parent_map = gcc_pxo_pll8_map, 646 }, 647 .freq_tbl = clk_tbl_gsbi_uart, 648 .clkr = { 649 .enable_reg = 0x2af4, 650 .enable_mask = BIT(11), 651 .hw.init = &(struct clk_init_data){ 652 .name = "gsbi10_uart_src", 653 .parent_names = gcc_pxo_pll8, 654 .num_parents = 2, 655 .ops = &clk_rcg_ops, 656 .flags = CLK_SET_PARENT_GATE, 657 }, 658 }, 659 }; 660 661 static struct clk_branch gsbi10_uart_clk = { 662 .halt_reg = 0x2fd0, 663 .halt_bit = 2, 664 .clkr = { 665 .enable_reg = 0x2af4, 666 .enable_mask = BIT(9), 667 .hw.init = &(struct clk_init_data){ 668 .name = "gsbi10_uart_clk", 669 .parent_names = (const char *[]){ "gsbi10_uart_src" }, 670 .num_parents = 1, 671 .ops = &clk_branch_ops, 672 .flags = CLK_SET_RATE_PARENT, 673 }, 674 }, 675 }; 676 677 static struct clk_rcg gsbi11_uart_src = { 678 .ns_reg = 0x2b14, 679 .md_reg = 0x2b10, 680 .mn = { 681 .mnctr_en_bit = 8, 682 .mnctr_reset_bit = 7, 683 .mnctr_mode_shift = 5, 684 .n_val_shift = 16, 685 .m_val_shift = 16, 686 .width = 16, 687 }, 688 .p = { 689 .pre_div_shift = 3, 690 .pre_div_width = 2, 691 }, 692 .s = { 693 .src_sel_shift = 0, 694 .parent_map = gcc_pxo_pll8_map, 695 }, 696 .freq_tbl = clk_tbl_gsbi_uart, 697 .clkr = { 698 .enable_reg = 0x2b14, 699 .enable_mask = BIT(11), 700 .hw.init = &(struct clk_init_data){ 701 .name = "gsbi11_uart_src", 702 .parent_names = gcc_pxo_pll8, 703 .num_parents = 2, 704 .ops = &clk_rcg_ops, 705 .flags = CLK_SET_PARENT_GATE, 706 }, 707 }, 708 }; 709 710 static struct clk_branch gsbi11_uart_clk = { 711 .halt_reg = 0x2fd4, 712 .halt_bit = 17, 713 .clkr = { 714 .enable_reg = 0x2b14, 715 .enable_mask = BIT(9), 716 .hw.init = &(struct clk_init_data){ 717 .name = "gsbi11_uart_clk", 718 .parent_names = (const char *[]){ "gsbi11_uart_src" }, 719 .num_parents = 1, 720 .ops = &clk_branch_ops, 721 .flags = CLK_SET_RATE_PARENT, 722 }, 723 }, 724 }; 725 726 static struct clk_rcg gsbi12_uart_src = { 727 .ns_reg = 0x2b34, 728 .md_reg = 0x2b30, 729 .mn = { 730 .mnctr_en_bit = 8, 731 .mnctr_reset_bit = 7, 732 .mnctr_mode_shift = 5, 733 .n_val_shift = 16, 734 .m_val_shift = 16, 735 .width = 16, 736 }, 737 .p = { 738 .pre_div_shift = 3, 739 .pre_div_width = 2, 740 }, 741 .s = { 742 .src_sel_shift = 0, 743 .parent_map = gcc_pxo_pll8_map, 744 }, 745 .freq_tbl = clk_tbl_gsbi_uart, 746 .clkr = { 747 .enable_reg = 0x2b34, 748 .enable_mask = BIT(11), 749 .hw.init = &(struct clk_init_data){ 750 .name = "gsbi12_uart_src", 751 .parent_names = gcc_pxo_pll8, 752 .num_parents = 2, 753 .ops = &clk_rcg_ops, 754 .flags = CLK_SET_PARENT_GATE, 755 }, 756 }, 757 }; 758 759 static struct clk_branch gsbi12_uart_clk = { 760 .halt_reg = 0x2fd4, 761 .halt_bit = 13, 762 .clkr = { 763 .enable_reg = 0x2b34, 764 .enable_mask = BIT(9), 765 .hw.init = &(struct clk_init_data){ 766 .name = "gsbi12_uart_clk", 767 .parent_names = (const char *[]){ "gsbi12_uart_src" }, 768 .num_parents = 1, 769 .ops = &clk_branch_ops, 770 .flags = CLK_SET_RATE_PARENT, 771 }, 772 }, 773 }; 774 775 static struct freq_tbl clk_tbl_gsbi_qup[] = { 776 { 1100000, P_PXO, 1, 2, 49 }, 777 { 5400000, P_PXO, 1, 1, 5 }, 778 { 10800000, P_PXO, 1, 2, 5 }, 779 { 15060000, P_PLL8, 1, 2, 51 }, 780 { 24000000, P_PLL8, 4, 1, 4 }, 781 { 25600000, P_PLL8, 1, 1, 15 }, 782 { 27000000, P_PXO, 1, 0, 0 }, 783 { 48000000, P_PLL8, 4, 1, 2 }, 784 { 51200000, P_PLL8, 1, 2, 15 }, 785 { } 786 }; 787 788 static struct clk_rcg gsbi1_qup_src = { 789 .ns_reg = 0x29cc, 790 .md_reg = 0x29c8, 791 .mn = { 792 .mnctr_en_bit = 8, 793 .mnctr_reset_bit = 7, 794 .mnctr_mode_shift = 5, 795 .n_val_shift = 16, 796 .m_val_shift = 16, 797 .width = 8, 798 }, 799 .p = { 800 .pre_div_shift = 3, 801 .pre_div_width = 2, 802 }, 803 .s = { 804 .src_sel_shift = 0, 805 .parent_map = gcc_pxo_pll8_map, 806 }, 807 .freq_tbl = clk_tbl_gsbi_qup, 808 .clkr = { 809 .enable_reg = 0x29cc, 810 .enable_mask = BIT(11), 811 .hw.init = &(struct clk_init_data){ 812 .name = "gsbi1_qup_src", 813 .parent_names = gcc_pxo_pll8, 814 .num_parents = 2, 815 .ops = &clk_rcg_ops, 816 .flags = CLK_SET_PARENT_GATE, 817 }, 818 }, 819 }; 820 821 static struct clk_branch gsbi1_qup_clk = { 822 .halt_reg = 0x2fcc, 823 .halt_bit = 9, 824 .clkr = { 825 .enable_reg = 0x29cc, 826 .enable_mask = BIT(9), 827 .hw.init = &(struct clk_init_data){ 828 .name = "gsbi1_qup_clk", 829 .parent_names = (const char *[]){ "gsbi1_qup_src" }, 830 .num_parents = 1, 831 .ops = &clk_branch_ops, 832 .flags = CLK_SET_RATE_PARENT, 833 }, 834 }, 835 }; 836 837 static struct clk_rcg gsbi2_qup_src = { 838 .ns_reg = 0x29ec, 839 .md_reg = 0x29e8, 840 .mn = { 841 .mnctr_en_bit = 8, 842 .mnctr_reset_bit = 7, 843 .mnctr_mode_shift = 5, 844 .n_val_shift = 16, 845 .m_val_shift = 16, 846 .width = 8, 847 }, 848 .p = { 849 .pre_div_shift = 3, 850 .pre_div_width = 2, 851 }, 852 .s = { 853 .src_sel_shift = 0, 854 .parent_map = gcc_pxo_pll8_map, 855 }, 856 .freq_tbl = clk_tbl_gsbi_qup, 857 .clkr = { 858 .enable_reg = 0x29ec, 859 .enable_mask = BIT(11), 860 .hw.init = &(struct clk_init_data){ 861 .name = "gsbi2_qup_src", 862 .parent_names = gcc_pxo_pll8, 863 .num_parents = 2, 864 .ops = &clk_rcg_ops, 865 .flags = CLK_SET_PARENT_GATE, 866 }, 867 }, 868 }; 869 870 static struct clk_branch gsbi2_qup_clk = { 871 .halt_reg = 0x2fcc, 872 .halt_bit = 4, 873 .clkr = { 874 .enable_reg = 0x29ec, 875 .enable_mask = BIT(9), 876 .hw.init = &(struct clk_init_data){ 877 .name = "gsbi2_qup_clk", 878 .parent_names = (const char *[]){ "gsbi2_qup_src" }, 879 .num_parents = 1, 880 .ops = &clk_branch_ops, 881 .flags = CLK_SET_RATE_PARENT, 882 }, 883 }, 884 }; 885 886 static struct clk_rcg gsbi3_qup_src = { 887 .ns_reg = 0x2a0c, 888 .md_reg = 0x2a08, 889 .mn = { 890 .mnctr_en_bit = 8, 891 .mnctr_reset_bit = 7, 892 .mnctr_mode_shift = 5, 893 .n_val_shift = 16, 894 .m_val_shift = 16, 895 .width = 8, 896 }, 897 .p = { 898 .pre_div_shift = 3, 899 .pre_div_width = 2, 900 }, 901 .s = { 902 .src_sel_shift = 0, 903 .parent_map = gcc_pxo_pll8_map, 904 }, 905 .freq_tbl = clk_tbl_gsbi_qup, 906 .clkr = { 907 .enable_reg = 0x2a0c, 908 .enable_mask = BIT(11), 909 .hw.init = &(struct clk_init_data){ 910 .name = "gsbi3_qup_src", 911 .parent_names = gcc_pxo_pll8, 912 .num_parents = 2, 913 .ops = &clk_rcg_ops, 914 .flags = CLK_SET_PARENT_GATE, 915 }, 916 }, 917 }; 918 919 static struct clk_branch gsbi3_qup_clk = { 920 .halt_reg = 0x2fcc, 921 .halt_bit = 0, 922 .clkr = { 923 .enable_reg = 0x2a0c, 924 .enable_mask = BIT(9), 925 .hw.init = &(struct clk_init_data){ 926 .name = "gsbi3_qup_clk", 927 .parent_names = (const char *[]){ "gsbi3_qup_src" }, 928 .num_parents = 1, 929 .ops = &clk_branch_ops, 930 .flags = CLK_SET_RATE_PARENT, 931 }, 932 }, 933 }; 934 935 static struct clk_rcg gsbi4_qup_src = { 936 .ns_reg = 0x2a2c, 937 .md_reg = 0x2a28, 938 .mn = { 939 .mnctr_en_bit = 8, 940 .mnctr_reset_bit = 7, 941 .mnctr_mode_shift = 5, 942 .n_val_shift = 16, 943 .m_val_shift = 16, 944 .width = 8, 945 }, 946 .p = { 947 .pre_div_shift = 3, 948 .pre_div_width = 2, 949 }, 950 .s = { 951 .src_sel_shift = 0, 952 .parent_map = gcc_pxo_pll8_map, 953 }, 954 .freq_tbl = clk_tbl_gsbi_qup, 955 .clkr = { 956 .enable_reg = 0x2a2c, 957 .enable_mask = BIT(11), 958 .hw.init = &(struct clk_init_data){ 959 .name = "gsbi4_qup_src", 960 .parent_names = gcc_pxo_pll8, 961 .num_parents = 2, 962 .ops = &clk_rcg_ops, 963 .flags = CLK_SET_PARENT_GATE, 964 }, 965 }, 966 }; 967 968 static struct clk_branch gsbi4_qup_clk = { 969 .halt_reg = 0x2fd0, 970 .halt_bit = 24, 971 .clkr = { 972 .enable_reg = 0x2a2c, 973 .enable_mask = BIT(9), 974 .hw.init = &(struct clk_init_data){ 975 .name = "gsbi4_qup_clk", 976 .parent_names = (const char *[]){ "gsbi4_qup_src" }, 977 .num_parents = 1, 978 .ops = &clk_branch_ops, 979 .flags = CLK_SET_RATE_PARENT, 980 }, 981 }, 982 }; 983 984 static struct clk_rcg gsbi5_qup_src = { 985 .ns_reg = 0x2a4c, 986 .md_reg = 0x2a48, 987 .mn = { 988 .mnctr_en_bit = 8, 989 .mnctr_reset_bit = 7, 990 .mnctr_mode_shift = 5, 991 .n_val_shift = 16, 992 .m_val_shift = 16, 993 .width = 8, 994 }, 995 .p = { 996 .pre_div_shift = 3, 997 .pre_div_width = 2, 998 }, 999 .s = { 1000 .src_sel_shift = 0, 1001 .parent_map = gcc_pxo_pll8_map, 1002 }, 1003 .freq_tbl = clk_tbl_gsbi_qup, 1004 .clkr = { 1005 .enable_reg = 0x2a4c, 1006 .enable_mask = BIT(11), 1007 .hw.init = &(struct clk_init_data){ 1008 .name = "gsbi5_qup_src", 1009 .parent_names = gcc_pxo_pll8, 1010 .num_parents = 2, 1011 .ops = &clk_rcg_ops, 1012 .flags = CLK_SET_PARENT_GATE, 1013 }, 1014 }, 1015 }; 1016 1017 static struct clk_branch gsbi5_qup_clk = { 1018 .halt_reg = 0x2fd0, 1019 .halt_bit = 20, 1020 .clkr = { 1021 .enable_reg = 0x2a4c, 1022 .enable_mask = BIT(9), 1023 .hw.init = &(struct clk_init_data){ 1024 .name = "gsbi5_qup_clk", 1025 .parent_names = (const char *[]){ "gsbi5_qup_src" }, 1026 .num_parents = 1, 1027 .ops = &clk_branch_ops, 1028 .flags = CLK_SET_RATE_PARENT, 1029 }, 1030 }, 1031 }; 1032 1033 static struct clk_rcg gsbi6_qup_src = { 1034 .ns_reg = 0x2a6c, 1035 .md_reg = 0x2a68, 1036 .mn = { 1037 .mnctr_en_bit = 8, 1038 .mnctr_reset_bit = 7, 1039 .mnctr_mode_shift = 5, 1040 .n_val_shift = 16, 1041 .m_val_shift = 16, 1042 .width = 8, 1043 }, 1044 .p = { 1045 .pre_div_shift = 3, 1046 .pre_div_width = 2, 1047 }, 1048 .s = { 1049 .src_sel_shift = 0, 1050 .parent_map = gcc_pxo_pll8_map, 1051 }, 1052 .freq_tbl = clk_tbl_gsbi_qup, 1053 .clkr = { 1054 .enable_reg = 0x2a6c, 1055 .enable_mask = BIT(11), 1056 .hw.init = &(struct clk_init_data){ 1057 .name = "gsbi6_qup_src", 1058 .parent_names = gcc_pxo_pll8, 1059 .num_parents = 2, 1060 .ops = &clk_rcg_ops, 1061 .flags = CLK_SET_PARENT_GATE, 1062 }, 1063 }, 1064 }; 1065 1066 static struct clk_branch gsbi6_qup_clk = { 1067 .halt_reg = 0x2fd0, 1068 .halt_bit = 16, 1069 .clkr = { 1070 .enable_reg = 0x2a6c, 1071 .enable_mask = BIT(9), 1072 .hw.init = &(struct clk_init_data){ 1073 .name = "gsbi6_qup_clk", 1074 .parent_names = (const char *[]){ "gsbi6_qup_src" }, 1075 .num_parents = 1, 1076 .ops = &clk_branch_ops, 1077 .flags = CLK_SET_RATE_PARENT, 1078 }, 1079 }, 1080 }; 1081 1082 static struct clk_rcg gsbi7_qup_src = { 1083 .ns_reg = 0x2a8c, 1084 .md_reg = 0x2a88, 1085 .mn = { 1086 .mnctr_en_bit = 8, 1087 .mnctr_reset_bit = 7, 1088 .mnctr_mode_shift = 5, 1089 .n_val_shift = 16, 1090 .m_val_shift = 16, 1091 .width = 8, 1092 }, 1093 .p = { 1094 .pre_div_shift = 3, 1095 .pre_div_width = 2, 1096 }, 1097 .s = { 1098 .src_sel_shift = 0, 1099 .parent_map = gcc_pxo_pll8_map, 1100 }, 1101 .freq_tbl = clk_tbl_gsbi_qup, 1102 .clkr = { 1103 .enable_reg = 0x2a8c, 1104 .enable_mask = BIT(11), 1105 .hw.init = &(struct clk_init_data){ 1106 .name = "gsbi7_qup_src", 1107 .parent_names = gcc_pxo_pll8, 1108 .num_parents = 2, 1109 .ops = &clk_rcg_ops, 1110 .flags = CLK_SET_PARENT_GATE, 1111 }, 1112 }, 1113 }; 1114 1115 static struct clk_branch gsbi7_qup_clk = { 1116 .halt_reg = 0x2fd0, 1117 .halt_bit = 12, 1118 .clkr = { 1119 .enable_reg = 0x2a8c, 1120 .enable_mask = BIT(9), 1121 .hw.init = &(struct clk_init_data){ 1122 .name = "gsbi7_qup_clk", 1123 .parent_names = (const char *[]){ "gsbi7_qup_src" }, 1124 .num_parents = 1, 1125 .ops = &clk_branch_ops, 1126 .flags = CLK_SET_RATE_PARENT, 1127 }, 1128 }, 1129 }; 1130 1131 static struct clk_rcg gsbi8_qup_src = { 1132 .ns_reg = 0x2aac, 1133 .md_reg = 0x2aa8, 1134 .mn = { 1135 .mnctr_en_bit = 8, 1136 .mnctr_reset_bit = 7, 1137 .mnctr_mode_shift = 5, 1138 .n_val_shift = 16, 1139 .m_val_shift = 16, 1140 .width = 8, 1141 }, 1142 .p = { 1143 .pre_div_shift = 3, 1144 .pre_div_width = 2, 1145 }, 1146 .s = { 1147 .src_sel_shift = 0, 1148 .parent_map = gcc_pxo_pll8_map, 1149 }, 1150 .freq_tbl = clk_tbl_gsbi_qup, 1151 .clkr = { 1152 .enable_reg = 0x2aac, 1153 .enable_mask = BIT(11), 1154 .hw.init = &(struct clk_init_data){ 1155 .name = "gsbi8_qup_src", 1156 .parent_names = gcc_pxo_pll8, 1157 .num_parents = 2, 1158 .ops = &clk_rcg_ops, 1159 .flags = CLK_SET_PARENT_GATE, 1160 }, 1161 }, 1162 }; 1163 1164 static struct clk_branch gsbi8_qup_clk = { 1165 .halt_reg = 0x2fd0, 1166 .halt_bit = 8, 1167 .clkr = { 1168 .enable_reg = 0x2aac, 1169 .enable_mask = BIT(9), 1170 .hw.init = &(struct clk_init_data){ 1171 .name = "gsbi8_qup_clk", 1172 .parent_names = (const char *[]){ "gsbi8_qup_src" }, 1173 .num_parents = 1, 1174 .ops = &clk_branch_ops, 1175 .flags = CLK_SET_RATE_PARENT, 1176 }, 1177 }, 1178 }; 1179 1180 static struct clk_rcg gsbi9_qup_src = { 1181 .ns_reg = 0x2acc, 1182 .md_reg = 0x2ac8, 1183 .mn = { 1184 .mnctr_en_bit = 8, 1185 .mnctr_reset_bit = 7, 1186 .mnctr_mode_shift = 5, 1187 .n_val_shift = 16, 1188 .m_val_shift = 16, 1189 .width = 8, 1190 }, 1191 .p = { 1192 .pre_div_shift = 3, 1193 .pre_div_width = 2, 1194 }, 1195 .s = { 1196 .src_sel_shift = 0, 1197 .parent_map = gcc_pxo_pll8_map, 1198 }, 1199 .freq_tbl = clk_tbl_gsbi_qup, 1200 .clkr = { 1201 .enable_reg = 0x2acc, 1202 .enable_mask = BIT(11), 1203 .hw.init = &(struct clk_init_data){ 1204 .name = "gsbi9_qup_src", 1205 .parent_names = gcc_pxo_pll8, 1206 .num_parents = 2, 1207 .ops = &clk_rcg_ops, 1208 .flags = CLK_SET_PARENT_GATE, 1209 }, 1210 }, 1211 }; 1212 1213 static struct clk_branch gsbi9_qup_clk = { 1214 .halt_reg = 0x2fd0, 1215 .halt_bit = 4, 1216 .clkr = { 1217 .enable_reg = 0x2acc, 1218 .enable_mask = BIT(9), 1219 .hw.init = &(struct clk_init_data){ 1220 .name = "gsbi9_qup_clk", 1221 .parent_names = (const char *[]){ "gsbi9_qup_src" }, 1222 .num_parents = 1, 1223 .ops = &clk_branch_ops, 1224 .flags = CLK_SET_RATE_PARENT, 1225 }, 1226 }, 1227 }; 1228 1229 static struct clk_rcg gsbi10_qup_src = { 1230 .ns_reg = 0x2aec, 1231 .md_reg = 0x2ae8, 1232 .mn = { 1233 .mnctr_en_bit = 8, 1234 .mnctr_reset_bit = 7, 1235 .mnctr_mode_shift = 5, 1236 .n_val_shift = 16, 1237 .m_val_shift = 16, 1238 .width = 8, 1239 }, 1240 .p = { 1241 .pre_div_shift = 3, 1242 .pre_div_width = 2, 1243 }, 1244 .s = { 1245 .src_sel_shift = 0, 1246 .parent_map = gcc_pxo_pll8_map, 1247 }, 1248 .freq_tbl = clk_tbl_gsbi_qup, 1249 .clkr = { 1250 .enable_reg = 0x2aec, 1251 .enable_mask = BIT(11), 1252 .hw.init = &(struct clk_init_data){ 1253 .name = "gsbi10_qup_src", 1254 .parent_names = gcc_pxo_pll8, 1255 .num_parents = 2, 1256 .ops = &clk_rcg_ops, 1257 .flags = CLK_SET_PARENT_GATE, 1258 }, 1259 }, 1260 }; 1261 1262 static struct clk_branch gsbi10_qup_clk = { 1263 .halt_reg = 0x2fd0, 1264 .halt_bit = 0, 1265 .clkr = { 1266 .enable_reg = 0x2aec, 1267 .enable_mask = BIT(9), 1268 .hw.init = &(struct clk_init_data){ 1269 .name = "gsbi10_qup_clk", 1270 .parent_names = (const char *[]){ "gsbi10_qup_src" }, 1271 .num_parents = 1, 1272 .ops = &clk_branch_ops, 1273 .flags = CLK_SET_RATE_PARENT, 1274 }, 1275 }, 1276 }; 1277 1278 static struct clk_rcg gsbi11_qup_src = { 1279 .ns_reg = 0x2b0c, 1280 .md_reg = 0x2b08, 1281 .mn = { 1282 .mnctr_en_bit = 8, 1283 .mnctr_reset_bit = 7, 1284 .mnctr_mode_shift = 5, 1285 .n_val_shift = 16, 1286 .m_val_shift = 16, 1287 .width = 8, 1288 }, 1289 .p = { 1290 .pre_div_shift = 3, 1291 .pre_div_width = 2, 1292 }, 1293 .s = { 1294 .src_sel_shift = 0, 1295 .parent_map = gcc_pxo_pll8_map, 1296 }, 1297 .freq_tbl = clk_tbl_gsbi_qup, 1298 .clkr = { 1299 .enable_reg = 0x2b0c, 1300 .enable_mask = BIT(11), 1301 .hw.init = &(struct clk_init_data){ 1302 .name = "gsbi11_qup_src", 1303 .parent_names = gcc_pxo_pll8, 1304 .num_parents = 2, 1305 .ops = &clk_rcg_ops, 1306 .flags = CLK_SET_PARENT_GATE, 1307 }, 1308 }, 1309 }; 1310 1311 static struct clk_branch gsbi11_qup_clk = { 1312 .halt_reg = 0x2fd4, 1313 .halt_bit = 15, 1314 .clkr = { 1315 .enable_reg = 0x2b0c, 1316 .enable_mask = BIT(9), 1317 .hw.init = &(struct clk_init_data){ 1318 .name = "gsbi11_qup_clk", 1319 .parent_names = (const char *[]){ "gsbi11_qup_src" }, 1320 .num_parents = 1, 1321 .ops = &clk_branch_ops, 1322 .flags = CLK_SET_RATE_PARENT, 1323 }, 1324 }, 1325 }; 1326 1327 static struct clk_rcg gsbi12_qup_src = { 1328 .ns_reg = 0x2b2c, 1329 .md_reg = 0x2b28, 1330 .mn = { 1331 .mnctr_en_bit = 8, 1332 .mnctr_reset_bit = 7, 1333 .mnctr_mode_shift = 5, 1334 .n_val_shift = 16, 1335 .m_val_shift = 16, 1336 .width = 8, 1337 }, 1338 .p = { 1339 .pre_div_shift = 3, 1340 .pre_div_width = 2, 1341 }, 1342 .s = { 1343 .src_sel_shift = 0, 1344 .parent_map = gcc_pxo_pll8_map, 1345 }, 1346 .freq_tbl = clk_tbl_gsbi_qup, 1347 .clkr = { 1348 .enable_reg = 0x2b2c, 1349 .enable_mask = BIT(11), 1350 .hw.init = &(struct clk_init_data){ 1351 .name = "gsbi12_qup_src", 1352 .parent_names = gcc_pxo_pll8, 1353 .num_parents = 2, 1354 .ops = &clk_rcg_ops, 1355 .flags = CLK_SET_PARENT_GATE, 1356 }, 1357 }, 1358 }; 1359 1360 static struct clk_branch gsbi12_qup_clk = { 1361 .halt_reg = 0x2fd4, 1362 .halt_bit = 11, 1363 .clkr = { 1364 .enable_reg = 0x2b2c, 1365 .enable_mask = BIT(9), 1366 .hw.init = &(struct clk_init_data){ 1367 .name = "gsbi12_qup_clk", 1368 .parent_names = (const char *[]){ "gsbi12_qup_src" }, 1369 .num_parents = 1, 1370 .ops = &clk_branch_ops, 1371 .flags = CLK_SET_RATE_PARENT, 1372 }, 1373 }, 1374 }; 1375 1376 static const struct freq_tbl clk_tbl_gp[] = { 1377 { 9600000, P_CXO, 2, 0, 0 }, 1378 { 13500000, P_PXO, 2, 0, 0 }, 1379 { 19200000, P_CXO, 1, 0, 0 }, 1380 { 27000000, P_PXO, 1, 0, 0 }, 1381 { 64000000, P_PLL8, 2, 1, 3 }, 1382 { 76800000, P_PLL8, 1, 1, 5 }, 1383 { 96000000, P_PLL8, 4, 0, 0 }, 1384 { 128000000, P_PLL8, 3, 0, 0 }, 1385 { 192000000, P_PLL8, 2, 0, 0 }, 1386 { } 1387 }; 1388 1389 static struct clk_rcg gp0_src = { 1390 .ns_reg = 0x2d24, 1391 .md_reg = 0x2d00, 1392 .mn = { 1393 .mnctr_en_bit = 8, 1394 .mnctr_reset_bit = 7, 1395 .mnctr_mode_shift = 5, 1396 .n_val_shift = 16, 1397 .m_val_shift = 16, 1398 .width = 8, 1399 }, 1400 .p = { 1401 .pre_div_shift = 3, 1402 .pre_div_width = 2, 1403 }, 1404 .s = { 1405 .src_sel_shift = 0, 1406 .parent_map = gcc_pxo_pll8_cxo_map, 1407 }, 1408 .freq_tbl = clk_tbl_gp, 1409 .clkr = { 1410 .enable_reg = 0x2d24, 1411 .enable_mask = BIT(11), 1412 .hw.init = &(struct clk_init_data){ 1413 .name = "gp0_src", 1414 .parent_names = gcc_pxo_pll8_cxo, 1415 .num_parents = 3, 1416 .ops = &clk_rcg_ops, 1417 .flags = CLK_SET_PARENT_GATE, 1418 }, 1419 } 1420 }; 1421 1422 static struct clk_branch gp0_clk = { 1423 .halt_reg = 0x2fd8, 1424 .halt_bit = 7, 1425 .clkr = { 1426 .enable_reg = 0x2d24, 1427 .enable_mask = BIT(9), 1428 .hw.init = &(struct clk_init_data){ 1429 .name = "gp0_clk", 1430 .parent_names = (const char *[]){ "gp0_src" }, 1431 .num_parents = 1, 1432 .ops = &clk_branch_ops, 1433 .flags = CLK_SET_RATE_PARENT, 1434 }, 1435 }, 1436 }; 1437 1438 static struct clk_rcg gp1_src = { 1439 .ns_reg = 0x2d44, 1440 .md_reg = 0x2d40, 1441 .mn = { 1442 .mnctr_en_bit = 8, 1443 .mnctr_reset_bit = 7, 1444 .mnctr_mode_shift = 5, 1445 .n_val_shift = 16, 1446 .m_val_shift = 16, 1447 .width = 8, 1448 }, 1449 .p = { 1450 .pre_div_shift = 3, 1451 .pre_div_width = 2, 1452 }, 1453 .s = { 1454 .src_sel_shift = 0, 1455 .parent_map = gcc_pxo_pll8_cxo_map, 1456 }, 1457 .freq_tbl = clk_tbl_gp, 1458 .clkr = { 1459 .enable_reg = 0x2d44, 1460 .enable_mask = BIT(11), 1461 .hw.init = &(struct clk_init_data){ 1462 .name = "gp1_src", 1463 .parent_names = gcc_pxo_pll8_cxo, 1464 .num_parents = 3, 1465 .ops = &clk_rcg_ops, 1466 .flags = CLK_SET_RATE_GATE, 1467 }, 1468 } 1469 }; 1470 1471 static struct clk_branch gp1_clk = { 1472 .halt_reg = 0x2fd8, 1473 .halt_bit = 6, 1474 .clkr = { 1475 .enable_reg = 0x2d44, 1476 .enable_mask = BIT(9), 1477 .hw.init = &(struct clk_init_data){ 1478 .name = "gp1_clk", 1479 .parent_names = (const char *[]){ "gp1_src" }, 1480 .num_parents = 1, 1481 .ops = &clk_branch_ops, 1482 .flags = CLK_SET_RATE_PARENT, 1483 }, 1484 }, 1485 }; 1486 1487 static struct clk_rcg gp2_src = { 1488 .ns_reg = 0x2d64, 1489 .md_reg = 0x2d60, 1490 .mn = { 1491 .mnctr_en_bit = 8, 1492 .mnctr_reset_bit = 7, 1493 .mnctr_mode_shift = 5, 1494 .n_val_shift = 16, 1495 .m_val_shift = 16, 1496 .width = 8, 1497 }, 1498 .p = { 1499 .pre_div_shift = 3, 1500 .pre_div_width = 2, 1501 }, 1502 .s = { 1503 .src_sel_shift = 0, 1504 .parent_map = gcc_pxo_pll8_cxo_map, 1505 }, 1506 .freq_tbl = clk_tbl_gp, 1507 .clkr = { 1508 .enable_reg = 0x2d64, 1509 .enable_mask = BIT(11), 1510 .hw.init = &(struct clk_init_data){ 1511 .name = "gp2_src", 1512 .parent_names = gcc_pxo_pll8_cxo, 1513 .num_parents = 3, 1514 .ops = &clk_rcg_ops, 1515 .flags = CLK_SET_RATE_GATE, 1516 }, 1517 } 1518 }; 1519 1520 static struct clk_branch gp2_clk = { 1521 .halt_reg = 0x2fd8, 1522 .halt_bit = 5, 1523 .clkr = { 1524 .enable_reg = 0x2d64, 1525 .enable_mask = BIT(9), 1526 .hw.init = &(struct clk_init_data){ 1527 .name = "gp2_clk", 1528 .parent_names = (const char *[]){ "gp2_src" }, 1529 .num_parents = 1, 1530 .ops = &clk_branch_ops, 1531 .flags = CLK_SET_RATE_PARENT, 1532 }, 1533 }, 1534 }; 1535 1536 static struct clk_branch pmem_clk = { 1537 .hwcg_reg = 0x25a0, 1538 .hwcg_bit = 6, 1539 .halt_reg = 0x2fc8, 1540 .halt_bit = 20, 1541 .clkr = { 1542 .enable_reg = 0x25a0, 1543 .enable_mask = BIT(4), 1544 .hw.init = &(struct clk_init_data){ 1545 .name = "pmem_clk", 1546 .ops = &clk_branch_ops, 1547 .flags = CLK_IS_ROOT, 1548 }, 1549 }, 1550 }; 1551 1552 static struct clk_rcg prng_src = { 1553 .ns_reg = 0x2e80, 1554 .p = { 1555 .pre_div_shift = 3, 1556 .pre_div_width = 4, 1557 }, 1558 .s = { 1559 .src_sel_shift = 0, 1560 .parent_map = gcc_pxo_pll8_map, 1561 }, 1562 .clkr = { 1563 .hw.init = &(struct clk_init_data){ 1564 .name = "prng_src", 1565 .parent_names = gcc_pxo_pll8, 1566 .num_parents = 2, 1567 .ops = &clk_rcg_ops, 1568 }, 1569 }, 1570 }; 1571 1572 static struct clk_branch prng_clk = { 1573 .halt_reg = 0x2fd8, 1574 .halt_check = BRANCH_HALT_VOTED, 1575 .halt_bit = 10, 1576 .clkr = { 1577 .enable_reg = 0x3080, 1578 .enable_mask = BIT(10), 1579 .hw.init = &(struct clk_init_data){ 1580 .name = "prng_clk", 1581 .parent_names = (const char *[]){ "prng_src" }, 1582 .num_parents = 1, 1583 .ops = &clk_branch_ops, 1584 }, 1585 }, 1586 }; 1587 1588 static const struct freq_tbl clk_tbl_sdc[] = { 1589 { 144000, P_PXO, 3, 2, 125 }, 1590 { 400000, P_PLL8, 4, 1, 240 }, 1591 { 16000000, P_PLL8, 4, 1, 6 }, 1592 { 17070000, P_PLL8, 1, 2, 45 }, 1593 { 20210000, P_PLL8, 1, 1, 19 }, 1594 { 24000000, P_PLL8, 4, 1, 4 }, 1595 { 48000000, P_PLL8, 4, 1, 2 }, 1596 { 64000000, P_PLL8, 3, 1, 2 }, 1597 { 96000000, P_PLL8, 4, 0, 0 }, 1598 { 192000000, P_PLL8, 2, 0, 0 }, 1599 { } 1600 }; 1601 1602 static struct clk_rcg sdc1_src = { 1603 .ns_reg = 0x282c, 1604 .md_reg = 0x2828, 1605 .mn = { 1606 .mnctr_en_bit = 8, 1607 .mnctr_reset_bit = 7, 1608 .mnctr_mode_shift = 5, 1609 .n_val_shift = 16, 1610 .m_val_shift = 16, 1611 .width = 8, 1612 }, 1613 .p = { 1614 .pre_div_shift = 3, 1615 .pre_div_width = 2, 1616 }, 1617 .s = { 1618 .src_sel_shift = 0, 1619 .parent_map = gcc_pxo_pll8_map, 1620 }, 1621 .freq_tbl = clk_tbl_sdc, 1622 .clkr = { 1623 .enable_reg = 0x282c, 1624 .enable_mask = BIT(11), 1625 .hw.init = &(struct clk_init_data){ 1626 .name = "sdc1_src", 1627 .parent_names = gcc_pxo_pll8, 1628 .num_parents = 2, 1629 .ops = &clk_rcg_ops, 1630 .flags = CLK_SET_RATE_GATE, 1631 }, 1632 } 1633 }; 1634 1635 static struct clk_branch sdc1_clk = { 1636 .halt_reg = 0x2fc8, 1637 .halt_bit = 6, 1638 .clkr = { 1639 .enable_reg = 0x282c, 1640 .enable_mask = BIT(9), 1641 .hw.init = &(struct clk_init_data){ 1642 .name = "sdc1_clk", 1643 .parent_names = (const char *[]){ "sdc1_src" }, 1644 .num_parents = 1, 1645 .ops = &clk_branch_ops, 1646 .flags = CLK_SET_RATE_PARENT, 1647 }, 1648 }, 1649 }; 1650 1651 static struct clk_rcg sdc2_src = { 1652 .ns_reg = 0x284c, 1653 .md_reg = 0x2848, 1654 .mn = { 1655 .mnctr_en_bit = 8, 1656 .mnctr_reset_bit = 7, 1657 .mnctr_mode_shift = 5, 1658 .n_val_shift = 16, 1659 .m_val_shift = 16, 1660 .width = 8, 1661 }, 1662 .p = { 1663 .pre_div_shift = 3, 1664 .pre_div_width = 2, 1665 }, 1666 .s = { 1667 .src_sel_shift = 0, 1668 .parent_map = gcc_pxo_pll8_map, 1669 }, 1670 .freq_tbl = clk_tbl_sdc, 1671 .clkr = { 1672 .enable_reg = 0x284c, 1673 .enable_mask = BIT(11), 1674 .hw.init = &(struct clk_init_data){ 1675 .name = "sdc2_src", 1676 .parent_names = gcc_pxo_pll8, 1677 .num_parents = 2, 1678 .ops = &clk_rcg_ops, 1679 .flags = CLK_SET_RATE_GATE, 1680 }, 1681 } 1682 }; 1683 1684 static struct clk_branch sdc2_clk = { 1685 .halt_reg = 0x2fc8, 1686 .halt_bit = 5, 1687 .clkr = { 1688 .enable_reg = 0x284c, 1689 .enable_mask = BIT(9), 1690 .hw.init = &(struct clk_init_data){ 1691 .name = "sdc2_clk", 1692 .parent_names = (const char *[]){ "sdc2_src" }, 1693 .num_parents = 1, 1694 .ops = &clk_branch_ops, 1695 .flags = CLK_SET_RATE_PARENT, 1696 }, 1697 }, 1698 }; 1699 1700 static struct clk_rcg sdc3_src = { 1701 .ns_reg = 0x286c, 1702 .md_reg = 0x2868, 1703 .mn = { 1704 .mnctr_en_bit = 8, 1705 .mnctr_reset_bit = 7, 1706 .mnctr_mode_shift = 5, 1707 .n_val_shift = 16, 1708 .m_val_shift = 16, 1709 .width = 8, 1710 }, 1711 .p = { 1712 .pre_div_shift = 3, 1713 .pre_div_width = 2, 1714 }, 1715 .s = { 1716 .src_sel_shift = 0, 1717 .parent_map = gcc_pxo_pll8_map, 1718 }, 1719 .freq_tbl = clk_tbl_sdc, 1720 .clkr = { 1721 .enable_reg = 0x286c, 1722 .enable_mask = BIT(11), 1723 .hw.init = &(struct clk_init_data){ 1724 .name = "sdc3_src", 1725 .parent_names = gcc_pxo_pll8, 1726 .num_parents = 2, 1727 .ops = &clk_rcg_ops, 1728 .flags = CLK_SET_RATE_GATE, 1729 }, 1730 } 1731 }; 1732 1733 static struct clk_branch sdc3_clk = { 1734 .halt_reg = 0x2fc8, 1735 .halt_bit = 4, 1736 .clkr = { 1737 .enable_reg = 0x286c, 1738 .enable_mask = BIT(9), 1739 .hw.init = &(struct clk_init_data){ 1740 .name = "sdc3_clk", 1741 .parent_names = (const char *[]){ "sdc3_src" }, 1742 .num_parents = 1, 1743 .ops = &clk_branch_ops, 1744 .flags = CLK_SET_RATE_PARENT, 1745 }, 1746 }, 1747 }; 1748 1749 static struct clk_rcg sdc4_src = { 1750 .ns_reg = 0x288c, 1751 .md_reg = 0x2888, 1752 .mn = { 1753 .mnctr_en_bit = 8, 1754 .mnctr_reset_bit = 7, 1755 .mnctr_mode_shift = 5, 1756 .n_val_shift = 16, 1757 .m_val_shift = 16, 1758 .width = 8, 1759 }, 1760 .p = { 1761 .pre_div_shift = 3, 1762 .pre_div_width = 2, 1763 }, 1764 .s = { 1765 .src_sel_shift = 0, 1766 .parent_map = gcc_pxo_pll8_map, 1767 }, 1768 .freq_tbl = clk_tbl_sdc, 1769 .clkr = { 1770 .enable_reg = 0x288c, 1771 .enable_mask = BIT(11), 1772 .hw.init = &(struct clk_init_data){ 1773 .name = "sdc4_src", 1774 .parent_names = gcc_pxo_pll8, 1775 .num_parents = 2, 1776 .ops = &clk_rcg_ops, 1777 .flags = CLK_SET_RATE_GATE, 1778 }, 1779 } 1780 }; 1781 1782 static struct clk_branch sdc4_clk = { 1783 .halt_reg = 0x2fc8, 1784 .halt_bit = 3, 1785 .clkr = { 1786 .enable_reg = 0x288c, 1787 .enable_mask = BIT(9), 1788 .hw.init = &(struct clk_init_data){ 1789 .name = "sdc4_clk", 1790 .parent_names = (const char *[]){ "sdc4_src" }, 1791 .num_parents = 1, 1792 .ops = &clk_branch_ops, 1793 .flags = CLK_SET_RATE_PARENT, 1794 }, 1795 }, 1796 }; 1797 1798 static struct clk_rcg sdc5_src = { 1799 .ns_reg = 0x28ac, 1800 .md_reg = 0x28a8, 1801 .mn = { 1802 .mnctr_en_bit = 8, 1803 .mnctr_reset_bit = 7, 1804 .mnctr_mode_shift = 5, 1805 .n_val_shift = 16, 1806 .m_val_shift = 16, 1807 .width = 8, 1808 }, 1809 .p = { 1810 .pre_div_shift = 3, 1811 .pre_div_width = 2, 1812 }, 1813 .s = { 1814 .src_sel_shift = 0, 1815 .parent_map = gcc_pxo_pll8_map, 1816 }, 1817 .freq_tbl = clk_tbl_sdc, 1818 .clkr = { 1819 .enable_reg = 0x28ac, 1820 .enable_mask = BIT(11), 1821 .hw.init = &(struct clk_init_data){ 1822 .name = "sdc5_src", 1823 .parent_names = gcc_pxo_pll8, 1824 .num_parents = 2, 1825 .ops = &clk_rcg_ops, 1826 .flags = CLK_SET_RATE_GATE, 1827 }, 1828 } 1829 }; 1830 1831 static struct clk_branch sdc5_clk = { 1832 .halt_reg = 0x2fc8, 1833 .halt_bit = 2, 1834 .clkr = { 1835 .enable_reg = 0x28ac, 1836 .enable_mask = BIT(9), 1837 .hw.init = &(struct clk_init_data){ 1838 .name = "sdc5_clk", 1839 .parent_names = (const char *[]){ "sdc5_src" }, 1840 .num_parents = 1, 1841 .ops = &clk_branch_ops, 1842 .flags = CLK_SET_RATE_PARENT, 1843 }, 1844 }, 1845 }; 1846 1847 static const struct freq_tbl clk_tbl_tsif_ref[] = { 1848 { 105000, P_PXO, 1, 1, 256 }, 1849 { } 1850 }; 1851 1852 static struct clk_rcg tsif_ref_src = { 1853 .ns_reg = 0x2710, 1854 .md_reg = 0x270c, 1855 .mn = { 1856 .mnctr_en_bit = 8, 1857 .mnctr_reset_bit = 7, 1858 .mnctr_mode_shift = 5, 1859 .n_val_shift = 16, 1860 .m_val_shift = 16, 1861 .width = 16, 1862 }, 1863 .p = { 1864 .pre_div_shift = 3, 1865 .pre_div_width = 2, 1866 }, 1867 .s = { 1868 .src_sel_shift = 0, 1869 .parent_map = gcc_pxo_pll8_map, 1870 }, 1871 .freq_tbl = clk_tbl_tsif_ref, 1872 .clkr = { 1873 .enable_reg = 0x2710, 1874 .enable_mask = BIT(11), 1875 .hw.init = &(struct clk_init_data){ 1876 .name = "tsif_ref_src", 1877 .parent_names = gcc_pxo_pll8, 1878 .num_parents = 2, 1879 .ops = &clk_rcg_ops, 1880 .flags = CLK_SET_RATE_GATE, 1881 }, 1882 } 1883 }; 1884 1885 static struct clk_branch tsif_ref_clk = { 1886 .halt_reg = 0x2fd4, 1887 .halt_bit = 5, 1888 .clkr = { 1889 .enable_reg = 0x2710, 1890 .enable_mask = BIT(9), 1891 .hw.init = &(struct clk_init_data){ 1892 .name = "tsif_ref_clk", 1893 .parent_names = (const char *[]){ "tsif_ref_src" }, 1894 .num_parents = 1, 1895 .ops = &clk_branch_ops, 1896 .flags = CLK_SET_RATE_PARENT, 1897 }, 1898 }, 1899 }; 1900 1901 static const struct freq_tbl clk_tbl_usb[] = { 1902 { 60000000, P_PLL8, 1, 5, 32 }, 1903 { } 1904 }; 1905 1906 static struct clk_rcg usb_hs1_xcvr_src = { 1907 .ns_reg = 0x290c, 1908 .md_reg = 0x2908, 1909 .mn = { 1910 .mnctr_en_bit = 8, 1911 .mnctr_reset_bit = 7, 1912 .mnctr_mode_shift = 5, 1913 .n_val_shift = 16, 1914 .m_val_shift = 16, 1915 .width = 8, 1916 }, 1917 .p = { 1918 .pre_div_shift = 3, 1919 .pre_div_width = 2, 1920 }, 1921 .s = { 1922 .src_sel_shift = 0, 1923 .parent_map = gcc_pxo_pll8_map, 1924 }, 1925 .freq_tbl = clk_tbl_usb, 1926 .clkr = { 1927 .enable_reg = 0x290c, 1928 .enable_mask = BIT(11), 1929 .hw.init = &(struct clk_init_data){ 1930 .name = "usb_hs1_xcvr_src", 1931 .parent_names = gcc_pxo_pll8, 1932 .num_parents = 2, 1933 .ops = &clk_rcg_ops, 1934 .flags = CLK_SET_RATE_GATE, 1935 }, 1936 } 1937 }; 1938 1939 static struct clk_branch usb_hs1_xcvr_clk = { 1940 .halt_reg = 0x2fc8, 1941 .halt_bit = 0, 1942 .clkr = { 1943 .enable_reg = 0x290c, 1944 .enable_mask = BIT(9), 1945 .hw.init = &(struct clk_init_data){ 1946 .name = "usb_hs1_xcvr_clk", 1947 .parent_names = (const char *[]){ "usb_hs1_xcvr_src" }, 1948 .num_parents = 1, 1949 .ops = &clk_branch_ops, 1950 .flags = CLK_SET_RATE_PARENT, 1951 }, 1952 }, 1953 }; 1954 1955 static struct clk_rcg usb_hs3_xcvr_src = { 1956 .ns_reg = 0x370c, 1957 .md_reg = 0x3708, 1958 .mn = { 1959 .mnctr_en_bit = 8, 1960 .mnctr_reset_bit = 7, 1961 .mnctr_mode_shift = 5, 1962 .n_val_shift = 16, 1963 .m_val_shift = 16, 1964 .width = 8, 1965 }, 1966 .p = { 1967 .pre_div_shift = 3, 1968 .pre_div_width = 2, 1969 }, 1970 .s = { 1971 .src_sel_shift = 0, 1972 .parent_map = gcc_pxo_pll8_map, 1973 }, 1974 .freq_tbl = clk_tbl_usb, 1975 .clkr = { 1976 .enable_reg = 0x370c, 1977 .enable_mask = BIT(11), 1978 .hw.init = &(struct clk_init_data){ 1979 .name = "usb_hs3_xcvr_src", 1980 .parent_names = gcc_pxo_pll8, 1981 .num_parents = 2, 1982 .ops = &clk_rcg_ops, 1983 .flags = CLK_SET_RATE_GATE, 1984 }, 1985 } 1986 }; 1987 1988 static struct clk_branch usb_hs3_xcvr_clk = { 1989 .halt_reg = 0x2fc8, 1990 .halt_bit = 30, 1991 .clkr = { 1992 .enable_reg = 0x370c, 1993 .enable_mask = BIT(9), 1994 .hw.init = &(struct clk_init_data){ 1995 .name = "usb_hs3_xcvr_clk", 1996 .parent_names = (const char *[]){ "usb_hs3_xcvr_src" }, 1997 .num_parents = 1, 1998 .ops = &clk_branch_ops, 1999 .flags = CLK_SET_RATE_PARENT, 2000 }, 2001 }, 2002 }; 2003 2004 static struct clk_rcg usb_hs4_xcvr_src = { 2005 .ns_reg = 0x372c, 2006 .md_reg = 0x3728, 2007 .mn = { 2008 .mnctr_en_bit = 8, 2009 .mnctr_reset_bit = 7, 2010 .mnctr_mode_shift = 5, 2011 .n_val_shift = 16, 2012 .m_val_shift = 16, 2013 .width = 8, 2014 }, 2015 .p = { 2016 .pre_div_shift = 3, 2017 .pre_div_width = 2, 2018 }, 2019 .s = { 2020 .src_sel_shift = 0, 2021 .parent_map = gcc_pxo_pll8_map, 2022 }, 2023 .freq_tbl = clk_tbl_usb, 2024 .clkr = { 2025 .enable_reg = 0x372c, 2026 .enable_mask = BIT(11), 2027 .hw.init = &(struct clk_init_data){ 2028 .name = "usb_hs4_xcvr_src", 2029 .parent_names = gcc_pxo_pll8, 2030 .num_parents = 2, 2031 .ops = &clk_rcg_ops, 2032 .flags = CLK_SET_RATE_GATE, 2033 }, 2034 } 2035 }; 2036 2037 static struct clk_branch usb_hs4_xcvr_clk = { 2038 .halt_reg = 0x2fc8, 2039 .halt_bit = 2, 2040 .clkr = { 2041 .enable_reg = 0x372c, 2042 .enable_mask = BIT(9), 2043 .hw.init = &(struct clk_init_data){ 2044 .name = "usb_hs4_xcvr_clk", 2045 .parent_names = (const char *[]){ "usb_hs4_xcvr_src" }, 2046 .num_parents = 1, 2047 .ops = &clk_branch_ops, 2048 .flags = CLK_SET_RATE_PARENT, 2049 }, 2050 }, 2051 }; 2052 2053 static struct clk_rcg usb_hsic_xcvr_fs_src = { 2054 .ns_reg = 0x2928, 2055 .md_reg = 0x2924, 2056 .mn = { 2057 .mnctr_en_bit = 8, 2058 .mnctr_reset_bit = 7, 2059 .mnctr_mode_shift = 5, 2060 .n_val_shift = 16, 2061 .m_val_shift = 16, 2062 .width = 8, 2063 }, 2064 .p = { 2065 .pre_div_shift = 3, 2066 .pre_div_width = 2, 2067 }, 2068 .s = { 2069 .src_sel_shift = 0, 2070 .parent_map = gcc_pxo_pll8_map, 2071 }, 2072 .freq_tbl = clk_tbl_usb, 2073 .clkr = { 2074 .enable_reg = 0x2928, 2075 .enable_mask = BIT(11), 2076 .hw.init = &(struct clk_init_data){ 2077 .name = "usb_hsic_xcvr_fs_src", 2078 .parent_names = gcc_pxo_pll8, 2079 .num_parents = 2, 2080 .ops = &clk_rcg_ops, 2081 .flags = CLK_SET_RATE_GATE, 2082 }, 2083 } 2084 }; 2085 2086 static const char *usb_hsic_xcvr_fs_src_p[] = { "usb_hsic_xcvr_fs_src" }; 2087 2088 static struct clk_branch usb_hsic_xcvr_fs_clk = { 2089 .halt_reg = 0x2fc8, 2090 .halt_bit = 2, 2091 .clkr = { 2092 .enable_reg = 0x2928, 2093 .enable_mask = BIT(9), 2094 .hw.init = &(struct clk_init_data){ 2095 .name = "usb_hsic_xcvr_fs_clk", 2096 .parent_names = usb_hsic_xcvr_fs_src_p, 2097 .num_parents = 1, 2098 .ops = &clk_branch_ops, 2099 .flags = CLK_SET_RATE_PARENT, 2100 }, 2101 }, 2102 }; 2103 2104 static struct clk_branch usb_hsic_system_clk = { 2105 .halt_reg = 0x2fcc, 2106 .halt_bit = 24, 2107 .clkr = { 2108 .enable_reg = 0x292c, 2109 .enable_mask = BIT(4), 2110 .hw.init = &(struct clk_init_data){ 2111 .parent_names = usb_hsic_xcvr_fs_src_p, 2112 .num_parents = 1, 2113 .name = "usb_hsic_system_clk", 2114 .ops = &clk_branch_ops, 2115 .flags = CLK_SET_RATE_PARENT, 2116 }, 2117 }, 2118 }; 2119 2120 static struct clk_branch usb_hsic_hsic_clk = { 2121 .halt_reg = 0x2fcc, 2122 .halt_bit = 19, 2123 .clkr = { 2124 .enable_reg = 0x2b44, 2125 .enable_mask = BIT(0), 2126 .hw.init = &(struct clk_init_data){ 2127 .parent_names = (const char *[]){ "pll14_vote" }, 2128 .num_parents = 1, 2129 .name = "usb_hsic_hsic_clk", 2130 .ops = &clk_branch_ops, 2131 }, 2132 }, 2133 }; 2134 2135 static struct clk_branch usb_hsic_hsio_cal_clk = { 2136 .halt_reg = 0x2fcc, 2137 .halt_bit = 23, 2138 .clkr = { 2139 .enable_reg = 0x2b48, 2140 .enable_mask = BIT(0), 2141 .hw.init = &(struct clk_init_data){ 2142 .name = "usb_hsic_hsio_cal_clk", 2143 .ops = &clk_branch_ops, 2144 .flags = CLK_IS_ROOT, 2145 }, 2146 }, 2147 }; 2148 2149 static struct clk_rcg usb_fs1_xcvr_fs_src = { 2150 .ns_reg = 0x2968, 2151 .md_reg = 0x2964, 2152 .mn = { 2153 .mnctr_en_bit = 8, 2154 .mnctr_reset_bit = 7, 2155 .mnctr_mode_shift = 5, 2156 .n_val_shift = 16, 2157 .m_val_shift = 16, 2158 .width = 8, 2159 }, 2160 .p = { 2161 .pre_div_shift = 3, 2162 .pre_div_width = 2, 2163 }, 2164 .s = { 2165 .src_sel_shift = 0, 2166 .parent_map = gcc_pxo_pll8_map, 2167 }, 2168 .freq_tbl = clk_tbl_usb, 2169 .clkr = { 2170 .enable_reg = 0x2968, 2171 .enable_mask = BIT(11), 2172 .hw.init = &(struct clk_init_data){ 2173 .name = "usb_fs1_xcvr_fs_src", 2174 .parent_names = gcc_pxo_pll8, 2175 .num_parents = 2, 2176 .ops = &clk_rcg_ops, 2177 .flags = CLK_SET_RATE_GATE, 2178 }, 2179 } 2180 }; 2181 2182 static const char *usb_fs1_xcvr_fs_src_p[] = { "usb_fs1_xcvr_fs_src" }; 2183 2184 static struct clk_branch usb_fs1_xcvr_fs_clk = { 2185 .halt_reg = 0x2fcc, 2186 .halt_bit = 15, 2187 .clkr = { 2188 .enable_reg = 0x2968, 2189 .enable_mask = BIT(9), 2190 .hw.init = &(struct clk_init_data){ 2191 .name = "usb_fs1_xcvr_fs_clk", 2192 .parent_names = usb_fs1_xcvr_fs_src_p, 2193 .num_parents = 1, 2194 .ops = &clk_branch_ops, 2195 .flags = CLK_SET_RATE_PARENT, 2196 }, 2197 }, 2198 }; 2199 2200 static struct clk_branch usb_fs1_system_clk = { 2201 .halt_reg = 0x2fcc, 2202 .halt_bit = 16, 2203 .clkr = { 2204 .enable_reg = 0x296c, 2205 .enable_mask = BIT(4), 2206 .hw.init = &(struct clk_init_data){ 2207 .parent_names = usb_fs1_xcvr_fs_src_p, 2208 .num_parents = 1, 2209 .name = "usb_fs1_system_clk", 2210 .ops = &clk_branch_ops, 2211 .flags = CLK_SET_RATE_PARENT, 2212 }, 2213 }, 2214 }; 2215 2216 static struct clk_rcg usb_fs2_xcvr_fs_src = { 2217 .ns_reg = 0x2988, 2218 .md_reg = 0x2984, 2219 .mn = { 2220 .mnctr_en_bit = 8, 2221 .mnctr_reset_bit = 7, 2222 .mnctr_mode_shift = 5, 2223 .n_val_shift = 16, 2224 .m_val_shift = 16, 2225 .width = 8, 2226 }, 2227 .p = { 2228 .pre_div_shift = 3, 2229 .pre_div_width = 2, 2230 }, 2231 .s = { 2232 .src_sel_shift = 0, 2233 .parent_map = gcc_pxo_pll8_map, 2234 }, 2235 .freq_tbl = clk_tbl_usb, 2236 .clkr = { 2237 .enable_reg = 0x2988, 2238 .enable_mask = BIT(11), 2239 .hw.init = &(struct clk_init_data){ 2240 .name = "usb_fs2_xcvr_fs_src", 2241 .parent_names = gcc_pxo_pll8, 2242 .num_parents = 2, 2243 .ops = &clk_rcg_ops, 2244 .flags = CLK_SET_RATE_GATE, 2245 }, 2246 } 2247 }; 2248 2249 static const char *usb_fs2_xcvr_fs_src_p[] = { "usb_fs2_xcvr_fs_src" }; 2250 2251 static struct clk_branch usb_fs2_xcvr_fs_clk = { 2252 .halt_reg = 0x2fcc, 2253 .halt_bit = 12, 2254 .clkr = { 2255 .enable_reg = 0x2988, 2256 .enable_mask = BIT(9), 2257 .hw.init = &(struct clk_init_data){ 2258 .name = "usb_fs2_xcvr_fs_clk", 2259 .parent_names = usb_fs2_xcvr_fs_src_p, 2260 .num_parents = 1, 2261 .ops = &clk_branch_ops, 2262 .flags = CLK_SET_RATE_PARENT, 2263 }, 2264 }, 2265 }; 2266 2267 static struct clk_branch usb_fs2_system_clk = { 2268 .halt_reg = 0x2fcc, 2269 .halt_bit = 13, 2270 .clkr = { 2271 .enable_reg = 0x298c, 2272 .enable_mask = BIT(4), 2273 .hw.init = &(struct clk_init_data){ 2274 .name = "usb_fs2_system_clk", 2275 .parent_names = usb_fs2_xcvr_fs_src_p, 2276 .num_parents = 1, 2277 .ops = &clk_branch_ops, 2278 .flags = CLK_SET_RATE_PARENT, 2279 }, 2280 }, 2281 }; 2282 2283 static struct clk_branch ce1_core_clk = { 2284 .hwcg_reg = 0x2724, 2285 .hwcg_bit = 6, 2286 .halt_reg = 0x2fd4, 2287 .halt_bit = 27, 2288 .clkr = { 2289 .enable_reg = 0x2724, 2290 .enable_mask = BIT(4), 2291 .hw.init = &(struct clk_init_data){ 2292 .name = "ce1_core_clk", 2293 .ops = &clk_branch_ops, 2294 .flags = CLK_IS_ROOT, 2295 }, 2296 }, 2297 }; 2298 2299 static struct clk_branch ce1_h_clk = { 2300 .halt_reg = 0x2fd4, 2301 .halt_bit = 1, 2302 .clkr = { 2303 .enable_reg = 0x2720, 2304 .enable_mask = BIT(4), 2305 .hw.init = &(struct clk_init_data){ 2306 .name = "ce1_h_clk", 2307 .ops = &clk_branch_ops, 2308 .flags = CLK_IS_ROOT, 2309 }, 2310 }, 2311 }; 2312 2313 static struct clk_branch dma_bam_h_clk = { 2314 .hwcg_reg = 0x25c0, 2315 .hwcg_bit = 6, 2316 .halt_reg = 0x2fc8, 2317 .halt_bit = 12, 2318 .clkr = { 2319 .enable_reg = 0x25c0, 2320 .enable_mask = BIT(4), 2321 .hw.init = &(struct clk_init_data){ 2322 .name = "dma_bam_h_clk", 2323 .ops = &clk_branch_ops, 2324 .flags = CLK_IS_ROOT, 2325 }, 2326 }, 2327 }; 2328 2329 static struct clk_branch gsbi1_h_clk = { 2330 .hwcg_reg = 0x29c0, 2331 .hwcg_bit = 6, 2332 .halt_reg = 0x2fcc, 2333 .halt_bit = 11, 2334 .clkr = { 2335 .enable_reg = 0x29c0, 2336 .enable_mask = BIT(4), 2337 .hw.init = &(struct clk_init_data){ 2338 .name = "gsbi1_h_clk", 2339 .ops = &clk_branch_ops, 2340 .flags = CLK_IS_ROOT, 2341 }, 2342 }, 2343 }; 2344 2345 static struct clk_branch gsbi2_h_clk = { 2346 .hwcg_reg = 0x29e0, 2347 .hwcg_bit = 6, 2348 .halt_reg = 0x2fcc, 2349 .halt_bit = 7, 2350 .clkr = { 2351 .enable_reg = 0x29e0, 2352 .enable_mask = BIT(4), 2353 .hw.init = &(struct clk_init_data){ 2354 .name = "gsbi2_h_clk", 2355 .ops = &clk_branch_ops, 2356 .flags = CLK_IS_ROOT, 2357 }, 2358 }, 2359 }; 2360 2361 static struct clk_branch gsbi3_h_clk = { 2362 .hwcg_reg = 0x2a00, 2363 .hwcg_bit = 6, 2364 .halt_reg = 0x2fcc, 2365 .halt_bit = 3, 2366 .clkr = { 2367 .enable_reg = 0x2a00, 2368 .enable_mask = BIT(4), 2369 .hw.init = &(struct clk_init_data){ 2370 .name = "gsbi3_h_clk", 2371 .ops = &clk_branch_ops, 2372 .flags = CLK_IS_ROOT, 2373 }, 2374 }, 2375 }; 2376 2377 static struct clk_branch gsbi4_h_clk = { 2378 .hwcg_reg = 0x2a20, 2379 .hwcg_bit = 6, 2380 .halt_reg = 0x2fd0, 2381 .halt_bit = 27, 2382 .clkr = { 2383 .enable_reg = 0x2a20, 2384 .enable_mask = BIT(4), 2385 .hw.init = &(struct clk_init_data){ 2386 .name = "gsbi4_h_clk", 2387 .ops = &clk_branch_ops, 2388 .flags = CLK_IS_ROOT, 2389 }, 2390 }, 2391 }; 2392 2393 static struct clk_branch gsbi5_h_clk = { 2394 .hwcg_reg = 0x2a40, 2395 .hwcg_bit = 6, 2396 .halt_reg = 0x2fd0, 2397 .halt_bit = 23, 2398 .clkr = { 2399 .enable_reg = 0x2a40, 2400 .enable_mask = BIT(4), 2401 .hw.init = &(struct clk_init_data){ 2402 .name = "gsbi5_h_clk", 2403 .ops = &clk_branch_ops, 2404 .flags = CLK_IS_ROOT, 2405 }, 2406 }, 2407 }; 2408 2409 static struct clk_branch gsbi6_h_clk = { 2410 .hwcg_reg = 0x2a60, 2411 .hwcg_bit = 6, 2412 .halt_reg = 0x2fd0, 2413 .halt_bit = 19, 2414 .clkr = { 2415 .enable_reg = 0x2a60, 2416 .enable_mask = BIT(4), 2417 .hw.init = &(struct clk_init_data){ 2418 .name = "gsbi6_h_clk", 2419 .ops = &clk_branch_ops, 2420 .flags = CLK_IS_ROOT, 2421 }, 2422 }, 2423 }; 2424 2425 static struct clk_branch gsbi7_h_clk = { 2426 .hwcg_reg = 0x2a80, 2427 .hwcg_bit = 6, 2428 .halt_reg = 0x2fd0, 2429 .halt_bit = 15, 2430 .clkr = { 2431 .enable_reg = 0x2a80, 2432 .enable_mask = BIT(4), 2433 .hw.init = &(struct clk_init_data){ 2434 .name = "gsbi7_h_clk", 2435 .ops = &clk_branch_ops, 2436 .flags = CLK_IS_ROOT, 2437 }, 2438 }, 2439 }; 2440 2441 static struct clk_branch gsbi8_h_clk = { 2442 .hwcg_reg = 0x2aa0, 2443 .hwcg_bit = 6, 2444 .halt_reg = 0x2fd0, 2445 .halt_bit = 11, 2446 .clkr = { 2447 .enable_reg = 0x2aa0, 2448 .enable_mask = BIT(4), 2449 .hw.init = &(struct clk_init_data){ 2450 .name = "gsbi8_h_clk", 2451 .ops = &clk_branch_ops, 2452 .flags = CLK_IS_ROOT, 2453 }, 2454 }, 2455 }; 2456 2457 static struct clk_branch gsbi9_h_clk = { 2458 .hwcg_reg = 0x2ac0, 2459 .hwcg_bit = 6, 2460 .halt_reg = 0x2fd0, 2461 .halt_bit = 7, 2462 .clkr = { 2463 .enable_reg = 0x2ac0, 2464 .enable_mask = BIT(4), 2465 .hw.init = &(struct clk_init_data){ 2466 .name = "gsbi9_h_clk", 2467 .ops = &clk_branch_ops, 2468 .flags = CLK_IS_ROOT, 2469 }, 2470 }, 2471 }; 2472 2473 static struct clk_branch gsbi10_h_clk = { 2474 .hwcg_reg = 0x2ae0, 2475 .hwcg_bit = 6, 2476 .halt_reg = 0x2fd0, 2477 .halt_bit = 3, 2478 .clkr = { 2479 .enable_reg = 0x2ae0, 2480 .enable_mask = BIT(4), 2481 .hw.init = &(struct clk_init_data){ 2482 .name = "gsbi10_h_clk", 2483 .ops = &clk_branch_ops, 2484 .flags = CLK_IS_ROOT, 2485 }, 2486 }, 2487 }; 2488 2489 static struct clk_branch gsbi11_h_clk = { 2490 .hwcg_reg = 0x2b00, 2491 .hwcg_bit = 6, 2492 .halt_reg = 0x2fd4, 2493 .halt_bit = 18, 2494 .clkr = { 2495 .enable_reg = 0x2b00, 2496 .enable_mask = BIT(4), 2497 .hw.init = &(struct clk_init_data){ 2498 .name = "gsbi11_h_clk", 2499 .ops = &clk_branch_ops, 2500 .flags = CLK_IS_ROOT, 2501 }, 2502 }, 2503 }; 2504 2505 static struct clk_branch gsbi12_h_clk = { 2506 .hwcg_reg = 0x2b20, 2507 .hwcg_bit = 6, 2508 .halt_reg = 0x2fd4, 2509 .halt_bit = 14, 2510 .clkr = { 2511 .enable_reg = 0x2b20, 2512 .enable_mask = BIT(4), 2513 .hw.init = &(struct clk_init_data){ 2514 .name = "gsbi12_h_clk", 2515 .ops = &clk_branch_ops, 2516 .flags = CLK_IS_ROOT, 2517 }, 2518 }, 2519 }; 2520 2521 static struct clk_branch tsif_h_clk = { 2522 .hwcg_reg = 0x2700, 2523 .hwcg_bit = 6, 2524 .halt_reg = 0x2fd4, 2525 .halt_bit = 7, 2526 .clkr = { 2527 .enable_reg = 0x2700, 2528 .enable_mask = BIT(4), 2529 .hw.init = &(struct clk_init_data){ 2530 .name = "tsif_h_clk", 2531 .ops = &clk_branch_ops, 2532 .flags = CLK_IS_ROOT, 2533 }, 2534 }, 2535 }; 2536 2537 static struct clk_branch usb_fs1_h_clk = { 2538 .halt_reg = 0x2fcc, 2539 .halt_bit = 17, 2540 .clkr = { 2541 .enable_reg = 0x2960, 2542 .enable_mask = BIT(4), 2543 .hw.init = &(struct clk_init_data){ 2544 .name = "usb_fs1_h_clk", 2545 .ops = &clk_branch_ops, 2546 .flags = CLK_IS_ROOT, 2547 }, 2548 }, 2549 }; 2550 2551 static struct clk_branch usb_fs2_h_clk = { 2552 .halt_reg = 0x2fcc, 2553 .halt_bit = 14, 2554 .clkr = { 2555 .enable_reg = 0x2980, 2556 .enable_mask = BIT(4), 2557 .hw.init = &(struct clk_init_data){ 2558 .name = "usb_fs2_h_clk", 2559 .ops = &clk_branch_ops, 2560 .flags = CLK_IS_ROOT, 2561 }, 2562 }, 2563 }; 2564 2565 static struct clk_branch usb_hs1_h_clk = { 2566 .hwcg_reg = 0x2900, 2567 .hwcg_bit = 6, 2568 .halt_reg = 0x2fc8, 2569 .halt_bit = 1, 2570 .clkr = { 2571 .enable_reg = 0x2900, 2572 .enable_mask = BIT(4), 2573 .hw.init = &(struct clk_init_data){ 2574 .name = "usb_hs1_h_clk", 2575 .ops = &clk_branch_ops, 2576 .flags = CLK_IS_ROOT, 2577 }, 2578 }, 2579 }; 2580 2581 static struct clk_branch usb_hs3_h_clk = { 2582 .halt_reg = 0x2fc8, 2583 .halt_bit = 31, 2584 .clkr = { 2585 .enable_reg = 0x3700, 2586 .enable_mask = BIT(4), 2587 .hw.init = &(struct clk_init_data){ 2588 .name = "usb_hs3_h_clk", 2589 .ops = &clk_branch_ops, 2590 .flags = CLK_IS_ROOT, 2591 }, 2592 }, 2593 }; 2594 2595 static struct clk_branch usb_hs4_h_clk = { 2596 .halt_reg = 0x2fc8, 2597 .halt_bit = 7, 2598 .clkr = { 2599 .enable_reg = 0x3720, 2600 .enable_mask = BIT(4), 2601 .hw.init = &(struct clk_init_data){ 2602 .name = "usb_hs4_h_clk", 2603 .ops = &clk_branch_ops, 2604 .flags = CLK_IS_ROOT, 2605 }, 2606 }, 2607 }; 2608 2609 static struct clk_branch usb_hsic_h_clk = { 2610 .halt_reg = 0x2fcc, 2611 .halt_bit = 28, 2612 .clkr = { 2613 .enable_reg = 0x2920, 2614 .enable_mask = BIT(4), 2615 .hw.init = &(struct clk_init_data){ 2616 .name = "usb_hsic_h_clk", 2617 .ops = &clk_branch_ops, 2618 .flags = CLK_IS_ROOT, 2619 }, 2620 }, 2621 }; 2622 2623 static struct clk_branch sdc1_h_clk = { 2624 .hwcg_reg = 0x2820, 2625 .hwcg_bit = 6, 2626 .halt_reg = 0x2fc8, 2627 .halt_bit = 11, 2628 .clkr = { 2629 .enable_reg = 0x2820, 2630 .enable_mask = BIT(4), 2631 .hw.init = &(struct clk_init_data){ 2632 .name = "sdc1_h_clk", 2633 .ops = &clk_branch_ops, 2634 .flags = CLK_IS_ROOT, 2635 }, 2636 }, 2637 }; 2638 2639 static struct clk_branch sdc2_h_clk = { 2640 .hwcg_reg = 0x2840, 2641 .hwcg_bit = 6, 2642 .halt_reg = 0x2fc8, 2643 .halt_bit = 10, 2644 .clkr = { 2645 .enable_reg = 0x2840, 2646 .enable_mask = BIT(4), 2647 .hw.init = &(struct clk_init_data){ 2648 .name = "sdc2_h_clk", 2649 .ops = &clk_branch_ops, 2650 .flags = CLK_IS_ROOT, 2651 }, 2652 }, 2653 }; 2654 2655 static struct clk_branch sdc3_h_clk = { 2656 .hwcg_reg = 0x2860, 2657 .hwcg_bit = 6, 2658 .halt_reg = 0x2fc8, 2659 .halt_bit = 9, 2660 .clkr = { 2661 .enable_reg = 0x2860, 2662 .enable_mask = BIT(4), 2663 .hw.init = &(struct clk_init_data){ 2664 .name = "sdc3_h_clk", 2665 .ops = &clk_branch_ops, 2666 .flags = CLK_IS_ROOT, 2667 }, 2668 }, 2669 }; 2670 2671 static struct clk_branch sdc4_h_clk = { 2672 .hwcg_reg = 0x2880, 2673 .hwcg_bit = 6, 2674 .halt_reg = 0x2fc8, 2675 .halt_bit = 8, 2676 .clkr = { 2677 .enable_reg = 0x2880, 2678 .enable_mask = BIT(4), 2679 .hw.init = &(struct clk_init_data){ 2680 .name = "sdc4_h_clk", 2681 .ops = &clk_branch_ops, 2682 .flags = CLK_IS_ROOT, 2683 }, 2684 }, 2685 }; 2686 2687 static struct clk_branch sdc5_h_clk = { 2688 .hwcg_reg = 0x28a0, 2689 .hwcg_bit = 6, 2690 .halt_reg = 0x2fc8, 2691 .halt_bit = 7, 2692 .clkr = { 2693 .enable_reg = 0x28a0, 2694 .enable_mask = BIT(4), 2695 .hw.init = &(struct clk_init_data){ 2696 .name = "sdc5_h_clk", 2697 .ops = &clk_branch_ops, 2698 .flags = CLK_IS_ROOT, 2699 }, 2700 }, 2701 }; 2702 2703 static struct clk_branch adm0_clk = { 2704 .halt_reg = 0x2fdc, 2705 .halt_check = BRANCH_HALT_VOTED, 2706 .halt_bit = 14, 2707 .clkr = { 2708 .enable_reg = 0x3080, 2709 .enable_mask = BIT(2), 2710 .hw.init = &(struct clk_init_data){ 2711 .name = "adm0_clk", 2712 .ops = &clk_branch_ops, 2713 .flags = CLK_IS_ROOT, 2714 }, 2715 }, 2716 }; 2717 2718 static struct clk_branch adm0_pbus_clk = { 2719 .hwcg_reg = 0x2208, 2720 .hwcg_bit = 6, 2721 .halt_reg = 0x2fdc, 2722 .halt_check = BRANCH_HALT_VOTED, 2723 .halt_bit = 13, 2724 .clkr = { 2725 .enable_reg = 0x3080, 2726 .enable_mask = BIT(3), 2727 .hw.init = &(struct clk_init_data){ 2728 .name = "adm0_pbus_clk", 2729 .ops = &clk_branch_ops, 2730 .flags = CLK_IS_ROOT, 2731 }, 2732 }, 2733 }; 2734 2735 static struct freq_tbl clk_tbl_ce3[] = { 2736 { 48000000, P_PLL8, 8 }, 2737 { 100000000, P_PLL3, 12 }, 2738 { 120000000, P_PLL3, 10 }, 2739 { } 2740 }; 2741 2742 static struct clk_rcg ce3_src = { 2743 .ns_reg = 0x36c0, 2744 .p = { 2745 .pre_div_shift = 3, 2746 .pre_div_width = 4, 2747 }, 2748 .s = { 2749 .src_sel_shift = 0, 2750 .parent_map = gcc_pxo_pll8_pll3_map, 2751 }, 2752 .freq_tbl = clk_tbl_ce3, 2753 .clkr = { 2754 .enable_reg = 0x2c08, 2755 .enable_mask = BIT(7), 2756 .hw.init = &(struct clk_init_data){ 2757 .name = "ce3_src", 2758 .parent_names = gcc_pxo_pll8_pll3, 2759 .num_parents = 3, 2760 .ops = &clk_rcg_ops, 2761 .flags = CLK_SET_RATE_GATE, 2762 }, 2763 }, 2764 }; 2765 2766 static struct clk_branch ce3_core_clk = { 2767 .halt_reg = 0x2fdc, 2768 .halt_bit = 5, 2769 .clkr = { 2770 .enable_reg = 0x36c4, 2771 .enable_mask = BIT(4), 2772 .hw.init = &(struct clk_init_data){ 2773 .name = "ce3_core_clk", 2774 .parent_names = (const char *[]){ "ce3_src" }, 2775 .num_parents = 1, 2776 .ops = &clk_branch_ops, 2777 .flags = CLK_SET_RATE_PARENT, 2778 }, 2779 }, 2780 }; 2781 2782 static struct clk_branch ce3_h_clk = { 2783 .halt_reg = 0x2fc4, 2784 .halt_bit = 16, 2785 .clkr = { 2786 .enable_reg = 0x36c4, 2787 .enable_mask = BIT(4), 2788 .hw.init = &(struct clk_init_data){ 2789 .name = "ce3_h_clk", 2790 .parent_names = (const char *[]){ "ce3_src" }, 2791 .num_parents = 1, 2792 .ops = &clk_branch_ops, 2793 .flags = CLK_SET_RATE_PARENT, 2794 }, 2795 }, 2796 }; 2797 2798 static const struct freq_tbl clk_tbl_sata_ref[] = { 2799 { 48000000, P_PLL8, 8, 0, 0 }, 2800 { 100000000, P_PLL3, 12, 0, 0 }, 2801 { } 2802 }; 2803 2804 static struct clk_rcg sata_clk_src = { 2805 .ns_reg = 0x2c08, 2806 .p = { 2807 .pre_div_shift = 3, 2808 .pre_div_width = 4, 2809 }, 2810 .s = { 2811 .src_sel_shift = 0, 2812 .parent_map = gcc_pxo_pll8_pll3_map, 2813 }, 2814 .freq_tbl = clk_tbl_sata_ref, 2815 .clkr = { 2816 .enable_reg = 0x2c08, 2817 .enable_mask = BIT(7), 2818 .hw.init = &(struct clk_init_data){ 2819 .name = "sata_clk_src", 2820 .parent_names = gcc_pxo_pll8_pll3, 2821 .num_parents = 3, 2822 .ops = &clk_rcg_ops, 2823 .flags = CLK_SET_RATE_GATE, 2824 }, 2825 }, 2826 }; 2827 2828 static struct clk_branch sata_rxoob_clk = { 2829 .halt_reg = 0x2fdc, 2830 .halt_bit = 26, 2831 .clkr = { 2832 .enable_reg = 0x2c0c, 2833 .enable_mask = BIT(4), 2834 .hw.init = &(struct clk_init_data){ 2835 .name = "sata_rxoob_clk", 2836 .parent_names = (const char *[]){ "sata_clk_src" }, 2837 .num_parents = 1, 2838 .ops = &clk_branch_ops, 2839 .flags = CLK_SET_RATE_PARENT, 2840 }, 2841 }, 2842 }; 2843 2844 static struct clk_branch sata_pmalive_clk = { 2845 .halt_reg = 0x2fdc, 2846 .halt_bit = 25, 2847 .clkr = { 2848 .enable_reg = 0x2c10, 2849 .enable_mask = BIT(4), 2850 .hw.init = &(struct clk_init_data){ 2851 .name = "sata_pmalive_clk", 2852 .parent_names = (const char *[]){ "sata_clk_src" }, 2853 .num_parents = 1, 2854 .ops = &clk_branch_ops, 2855 .flags = CLK_SET_RATE_PARENT, 2856 }, 2857 }, 2858 }; 2859 2860 static struct clk_branch sata_phy_ref_clk = { 2861 .halt_reg = 0x2fdc, 2862 .halt_bit = 24, 2863 .clkr = { 2864 .enable_reg = 0x2c14, 2865 .enable_mask = BIT(4), 2866 .hw.init = &(struct clk_init_data){ 2867 .name = "sata_phy_ref_clk", 2868 .parent_names = (const char *[]){ "pxo" }, 2869 .num_parents = 1, 2870 .ops = &clk_branch_ops, 2871 }, 2872 }, 2873 }; 2874 2875 static struct clk_branch sata_a_clk = { 2876 .halt_reg = 0x2fc0, 2877 .halt_bit = 12, 2878 .clkr = { 2879 .enable_reg = 0x2c20, 2880 .enable_mask = BIT(4), 2881 .hw.init = &(struct clk_init_data){ 2882 .name = "sata_a_clk", 2883 .ops = &clk_branch_ops, 2884 .flags = CLK_IS_ROOT, 2885 }, 2886 }, 2887 }; 2888 2889 static struct clk_branch sata_h_clk = { 2890 .halt_reg = 0x2fdc, 2891 .halt_bit = 27, 2892 .clkr = { 2893 .enable_reg = 0x2c00, 2894 .enable_mask = BIT(4), 2895 .hw.init = &(struct clk_init_data){ 2896 .name = "sata_h_clk", 2897 .ops = &clk_branch_ops, 2898 .flags = CLK_IS_ROOT, 2899 }, 2900 }, 2901 }; 2902 2903 static struct clk_branch sfab_sata_s_h_clk = { 2904 .halt_reg = 0x2fc4, 2905 .halt_bit = 14, 2906 .clkr = { 2907 .enable_reg = 0x2480, 2908 .enable_mask = BIT(4), 2909 .hw.init = &(struct clk_init_data){ 2910 .name = "sfab_sata_s_h_clk", 2911 .ops = &clk_branch_ops, 2912 .flags = CLK_IS_ROOT, 2913 }, 2914 }, 2915 }; 2916 2917 static struct clk_branch sata_phy_cfg_clk = { 2918 .halt_reg = 0x2fcc, 2919 .halt_bit = 12, 2920 .clkr = { 2921 .enable_reg = 0x2c40, 2922 .enable_mask = BIT(4), 2923 .hw.init = &(struct clk_init_data){ 2924 .name = "sata_phy_cfg_clk", 2925 .ops = &clk_branch_ops, 2926 .flags = CLK_IS_ROOT, 2927 }, 2928 }, 2929 }; 2930 2931 static struct clk_branch pcie_phy_ref_clk = { 2932 .halt_reg = 0x2fdc, 2933 .halt_bit = 29, 2934 .clkr = { 2935 .enable_reg = 0x22d0, 2936 .enable_mask = BIT(4), 2937 .hw.init = &(struct clk_init_data){ 2938 .name = "pcie_phy_ref_clk", 2939 .ops = &clk_branch_ops, 2940 .flags = CLK_IS_ROOT, 2941 }, 2942 }, 2943 }; 2944 2945 static struct clk_branch pcie_h_clk = { 2946 .halt_reg = 0x2fd4, 2947 .halt_bit = 8, 2948 .clkr = { 2949 .enable_reg = 0x22cc, 2950 .enable_mask = BIT(4), 2951 .hw.init = &(struct clk_init_data){ 2952 .name = "pcie_h_clk", 2953 .ops = &clk_branch_ops, 2954 .flags = CLK_IS_ROOT, 2955 }, 2956 }, 2957 }; 2958 2959 static struct clk_branch pcie_a_clk = { 2960 .halt_reg = 0x2fc0, 2961 .halt_bit = 13, 2962 .clkr = { 2963 .enable_reg = 0x22c0, 2964 .enable_mask = BIT(4), 2965 .hw.init = &(struct clk_init_data){ 2966 .name = "pcie_a_clk", 2967 .ops = &clk_branch_ops, 2968 .flags = CLK_IS_ROOT, 2969 }, 2970 }, 2971 }; 2972 2973 static struct clk_branch pmic_arb0_h_clk = { 2974 .halt_reg = 0x2fd8, 2975 .halt_check = BRANCH_HALT_VOTED, 2976 .halt_bit = 22, 2977 .clkr = { 2978 .enable_reg = 0x3080, 2979 .enable_mask = BIT(8), 2980 .hw.init = &(struct clk_init_data){ 2981 .name = "pmic_arb0_h_clk", 2982 .ops = &clk_branch_ops, 2983 .flags = CLK_IS_ROOT, 2984 }, 2985 }, 2986 }; 2987 2988 static struct clk_branch pmic_arb1_h_clk = { 2989 .halt_reg = 0x2fd8, 2990 .halt_check = BRANCH_HALT_VOTED, 2991 .halt_bit = 21, 2992 .clkr = { 2993 .enable_reg = 0x3080, 2994 .enable_mask = BIT(9), 2995 .hw.init = &(struct clk_init_data){ 2996 .name = "pmic_arb1_h_clk", 2997 .ops = &clk_branch_ops, 2998 .flags = CLK_IS_ROOT, 2999 }, 3000 }, 3001 }; 3002 3003 static struct clk_branch pmic_ssbi2_clk = { 3004 .halt_reg = 0x2fd8, 3005 .halt_check = BRANCH_HALT_VOTED, 3006 .halt_bit = 23, 3007 .clkr = { 3008 .enable_reg = 0x3080, 3009 .enable_mask = BIT(7), 3010 .hw.init = &(struct clk_init_data){ 3011 .name = "pmic_ssbi2_clk", 3012 .ops = &clk_branch_ops, 3013 .flags = CLK_IS_ROOT, 3014 }, 3015 }, 3016 }; 3017 3018 static struct clk_branch rpm_msg_ram_h_clk = { 3019 .hwcg_reg = 0x27e0, 3020 .hwcg_bit = 6, 3021 .halt_reg = 0x2fd8, 3022 .halt_check = BRANCH_HALT_VOTED, 3023 .halt_bit = 12, 3024 .clkr = { 3025 .enable_reg = 0x3080, 3026 .enable_mask = BIT(6), 3027 .hw.init = &(struct clk_init_data){ 3028 .name = "rpm_msg_ram_h_clk", 3029 .ops = &clk_branch_ops, 3030 .flags = CLK_IS_ROOT, 3031 }, 3032 }, 3033 }; 3034 3035 static struct clk_regmap *gcc_msm8960_clks[] = { 3036 [PLL3] = &pll3.clkr, 3037 [PLL4_VOTE] = &pll4_vote, 3038 [PLL8] = &pll8.clkr, 3039 [PLL8_VOTE] = &pll8_vote, 3040 [PLL14] = &pll14.clkr, 3041 [PLL14_VOTE] = &pll14_vote, 3042 [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr, 3043 [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr, 3044 [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr, 3045 [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr, 3046 [GSBI3_UART_SRC] = &gsbi3_uart_src.clkr, 3047 [GSBI3_UART_CLK] = &gsbi3_uart_clk.clkr, 3048 [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr, 3049 [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr, 3050 [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr, 3051 [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr, 3052 [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr, 3053 [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr, 3054 [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr, 3055 [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr, 3056 [GSBI8_UART_SRC] = &gsbi8_uart_src.clkr, 3057 [GSBI8_UART_CLK] = &gsbi8_uart_clk.clkr, 3058 [GSBI9_UART_SRC] = &gsbi9_uart_src.clkr, 3059 [GSBI9_UART_CLK] = &gsbi9_uart_clk.clkr, 3060 [GSBI10_UART_SRC] = &gsbi10_uart_src.clkr, 3061 [GSBI10_UART_CLK] = &gsbi10_uart_clk.clkr, 3062 [GSBI11_UART_SRC] = &gsbi11_uart_src.clkr, 3063 [GSBI11_UART_CLK] = &gsbi11_uart_clk.clkr, 3064 [GSBI12_UART_SRC] = &gsbi12_uart_src.clkr, 3065 [GSBI12_UART_CLK] = &gsbi12_uart_clk.clkr, 3066 [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr, 3067 [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr, 3068 [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr, 3069 [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr, 3070 [GSBI3_QUP_SRC] = &gsbi3_qup_src.clkr, 3071 [GSBI3_QUP_CLK] = &gsbi3_qup_clk.clkr, 3072 [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr, 3073 [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr, 3074 [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr, 3075 [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr, 3076 [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr, 3077 [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr, 3078 [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr, 3079 [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr, 3080 [GSBI8_QUP_SRC] = &gsbi8_qup_src.clkr, 3081 [GSBI8_QUP_CLK] = &gsbi8_qup_clk.clkr, 3082 [GSBI9_QUP_SRC] = &gsbi9_qup_src.clkr, 3083 [GSBI9_QUP_CLK] = &gsbi9_qup_clk.clkr, 3084 [GSBI10_QUP_SRC] = &gsbi10_qup_src.clkr, 3085 [GSBI10_QUP_CLK] = &gsbi10_qup_clk.clkr, 3086 [GSBI11_QUP_SRC] = &gsbi11_qup_src.clkr, 3087 [GSBI11_QUP_CLK] = &gsbi11_qup_clk.clkr, 3088 [GSBI12_QUP_SRC] = &gsbi12_qup_src.clkr, 3089 [GSBI12_QUP_CLK] = &gsbi12_qup_clk.clkr, 3090 [GP0_SRC] = &gp0_src.clkr, 3091 [GP0_CLK] = &gp0_clk.clkr, 3092 [GP1_SRC] = &gp1_src.clkr, 3093 [GP1_CLK] = &gp1_clk.clkr, 3094 [GP2_SRC] = &gp2_src.clkr, 3095 [GP2_CLK] = &gp2_clk.clkr, 3096 [PMEM_A_CLK] = &pmem_clk.clkr, 3097 [PRNG_SRC] = &prng_src.clkr, 3098 [PRNG_CLK] = &prng_clk.clkr, 3099 [SDC1_SRC] = &sdc1_src.clkr, 3100 [SDC1_CLK] = &sdc1_clk.clkr, 3101 [SDC2_SRC] = &sdc2_src.clkr, 3102 [SDC2_CLK] = &sdc2_clk.clkr, 3103 [SDC3_SRC] = &sdc3_src.clkr, 3104 [SDC3_CLK] = &sdc3_clk.clkr, 3105 [SDC4_SRC] = &sdc4_src.clkr, 3106 [SDC4_CLK] = &sdc4_clk.clkr, 3107 [SDC5_SRC] = &sdc5_src.clkr, 3108 [SDC5_CLK] = &sdc5_clk.clkr, 3109 [TSIF_REF_SRC] = &tsif_ref_src.clkr, 3110 [TSIF_REF_CLK] = &tsif_ref_clk.clkr, 3111 [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_src.clkr, 3112 [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr, 3113 [USB_HSIC_XCVR_FS_SRC] = &usb_hsic_xcvr_fs_src.clkr, 3114 [USB_HSIC_XCVR_FS_CLK] = &usb_hsic_xcvr_fs_clk.clkr, 3115 [USB_HSIC_SYSTEM_CLK] = &usb_hsic_system_clk.clkr, 3116 [USB_HSIC_HSIC_CLK] = &usb_hsic_hsic_clk.clkr, 3117 [USB_HSIC_HSIO_CAL_CLK] = &usb_hsic_hsio_cal_clk.clkr, 3118 [USB_FS1_XCVR_FS_SRC] = &usb_fs1_xcvr_fs_src.clkr, 3119 [USB_FS1_XCVR_FS_CLK] = &usb_fs1_xcvr_fs_clk.clkr, 3120 [USB_FS1_SYSTEM_CLK] = &usb_fs1_system_clk.clkr, 3121 [USB_FS2_XCVR_FS_SRC] = &usb_fs2_xcvr_fs_src.clkr, 3122 [USB_FS2_XCVR_FS_CLK] = &usb_fs2_xcvr_fs_clk.clkr, 3123 [USB_FS2_SYSTEM_CLK] = &usb_fs2_system_clk.clkr, 3124 [CE1_CORE_CLK] = &ce1_core_clk.clkr, 3125 [CE1_H_CLK] = &ce1_h_clk.clkr, 3126 [DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr, 3127 [GSBI1_H_CLK] = &gsbi1_h_clk.clkr, 3128 [GSBI2_H_CLK] = &gsbi2_h_clk.clkr, 3129 [GSBI3_H_CLK] = &gsbi3_h_clk.clkr, 3130 [GSBI4_H_CLK] = &gsbi4_h_clk.clkr, 3131 [GSBI5_H_CLK] = &gsbi5_h_clk.clkr, 3132 [GSBI6_H_CLK] = &gsbi6_h_clk.clkr, 3133 [GSBI7_H_CLK] = &gsbi7_h_clk.clkr, 3134 [GSBI8_H_CLK] = &gsbi8_h_clk.clkr, 3135 [GSBI9_H_CLK] = &gsbi9_h_clk.clkr, 3136 [GSBI10_H_CLK] = &gsbi10_h_clk.clkr, 3137 [GSBI11_H_CLK] = &gsbi11_h_clk.clkr, 3138 [GSBI12_H_CLK] = &gsbi12_h_clk.clkr, 3139 [TSIF_H_CLK] = &tsif_h_clk.clkr, 3140 [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr, 3141 [USB_FS2_H_CLK] = &usb_fs2_h_clk.clkr, 3142 [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr, 3143 [USB_HSIC_H_CLK] = &usb_hsic_h_clk.clkr, 3144 [SDC1_H_CLK] = &sdc1_h_clk.clkr, 3145 [SDC2_H_CLK] = &sdc2_h_clk.clkr, 3146 [SDC3_H_CLK] = &sdc3_h_clk.clkr, 3147 [SDC4_H_CLK] = &sdc4_h_clk.clkr, 3148 [SDC5_H_CLK] = &sdc5_h_clk.clkr, 3149 [ADM0_CLK] = &adm0_clk.clkr, 3150 [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr, 3151 [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr, 3152 [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr, 3153 [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr, 3154 [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr, 3155 }; 3156 3157 static const struct qcom_reset_map gcc_msm8960_resets[] = { 3158 [SFAB_MSS_Q6_SW_RESET] = { 0x2040, 7 }, 3159 [SFAB_MSS_Q6_FW_RESET] = { 0x2044, 7 }, 3160 [QDSS_STM_RESET] = { 0x2060, 6 }, 3161 [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 }, 3162 [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 }, 3163 [AFAB_SMPSS_M0_RESET] = { 0x20b8 }, 3164 [AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 }, 3165 [AFAB_EBI1_CH1_RESET] = { 0x20c4, 7}, 3166 [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 }, 3167 [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 }, 3168 [SFAB_ADM0_M2_RESET] = { 0x21e8, 7 }, 3169 [ADM0_C2_RESET] = { 0x220c, 4}, 3170 [ADM0_C1_RESET] = { 0x220c, 3}, 3171 [ADM0_C0_RESET] = { 0x220c, 2}, 3172 [ADM0_PBUS_RESET] = { 0x220c, 1 }, 3173 [ADM0_RESET] = { 0x220c }, 3174 [QDSS_CLKS_SW_RESET] = { 0x2260, 5 }, 3175 [QDSS_POR_RESET] = { 0x2260, 4 }, 3176 [QDSS_TSCTR_RESET] = { 0x2260, 3 }, 3177 [QDSS_HRESET_RESET] = { 0x2260, 2 }, 3178 [QDSS_AXI_RESET] = { 0x2260, 1 }, 3179 [QDSS_DBG_RESET] = { 0x2260 }, 3180 [PCIE_A_RESET] = { 0x22c0, 7 }, 3181 [PCIE_AUX_RESET] = { 0x22c8, 7 }, 3182 [PCIE_H_RESET] = { 0x22d0, 7 }, 3183 [SFAB_PCIE_M_RESET] = { 0x22d4, 1 }, 3184 [SFAB_PCIE_S_RESET] = { 0x22d4 }, 3185 [SFAB_MSS_M_RESET] = { 0x2340, 7 }, 3186 [SFAB_USB3_M_RESET] = { 0x2360, 7 }, 3187 [SFAB_RIVA_M_RESET] = { 0x2380, 7 }, 3188 [SFAB_LPASS_RESET] = { 0x23a0, 7 }, 3189 [SFAB_AFAB_M_RESET] = { 0x23e0, 7 }, 3190 [AFAB_SFAB_M0_RESET] = { 0x2420, 7 }, 3191 [AFAB_SFAB_M1_RESET] = { 0x2424, 7 }, 3192 [SFAB_SATA_S_RESET] = { 0x2480, 7 }, 3193 [SFAB_DFAB_M_RESET] = { 0x2500, 7 }, 3194 [DFAB_SFAB_M_RESET] = { 0x2520, 7 }, 3195 [DFAB_SWAY0_RESET] = { 0x2540, 7 }, 3196 [DFAB_SWAY1_RESET] = { 0x2544, 7 }, 3197 [DFAB_ARB0_RESET] = { 0x2560, 7 }, 3198 [DFAB_ARB1_RESET] = { 0x2564, 7 }, 3199 [PPSS_PROC_RESET] = { 0x2594, 1 }, 3200 [PPSS_RESET] = { 0x2594}, 3201 [DMA_BAM_RESET] = { 0x25c0, 7 }, 3202 [SPS_TIC_H_RESET] = { 0x2600, 7 }, 3203 [SLIMBUS_H_RESET] = { 0x2620, 7 }, 3204 [SFAB_CFPB_M_RESET] = { 0x2680, 7 }, 3205 [SFAB_CFPB_S_RESET] = { 0x26c0, 7 }, 3206 [TSIF_H_RESET] = { 0x2700, 7 }, 3207 [CE1_H_RESET] = { 0x2720, 7 }, 3208 [CE1_CORE_RESET] = { 0x2724, 7 }, 3209 [CE1_SLEEP_RESET] = { 0x2728, 7 }, 3210 [CE2_H_RESET] = { 0x2740, 7 }, 3211 [CE2_CORE_RESET] = { 0x2744, 7 }, 3212 [SFAB_SFPB_M_RESET] = { 0x2780, 7 }, 3213 [SFAB_SFPB_S_RESET] = { 0x27a0, 7 }, 3214 [RPM_PROC_RESET] = { 0x27c0, 7 }, 3215 [PMIC_SSBI2_RESET] = { 0x280c, 12 }, 3216 [SDC1_RESET] = { 0x2830 }, 3217 [SDC2_RESET] = { 0x2850 }, 3218 [SDC3_RESET] = { 0x2870 }, 3219 [SDC4_RESET] = { 0x2890 }, 3220 [SDC5_RESET] = { 0x28b0 }, 3221 [DFAB_A2_RESET] = { 0x28c0, 7 }, 3222 [USB_HS1_RESET] = { 0x2910 }, 3223 [USB_HSIC_RESET] = { 0x2934 }, 3224 [USB_FS1_XCVR_RESET] = { 0x2974, 1 }, 3225 [USB_FS1_RESET] = { 0x2974 }, 3226 [USB_FS2_XCVR_RESET] = { 0x2994, 1 }, 3227 [USB_FS2_RESET] = { 0x2994 }, 3228 [GSBI1_RESET] = { 0x29dc }, 3229 [GSBI2_RESET] = { 0x29fc }, 3230 [GSBI3_RESET] = { 0x2a1c }, 3231 [GSBI4_RESET] = { 0x2a3c }, 3232 [GSBI5_RESET] = { 0x2a5c }, 3233 [GSBI6_RESET] = { 0x2a7c }, 3234 [GSBI7_RESET] = { 0x2a9c }, 3235 [GSBI8_RESET] = { 0x2abc }, 3236 [GSBI9_RESET] = { 0x2adc }, 3237 [GSBI10_RESET] = { 0x2afc }, 3238 [GSBI11_RESET] = { 0x2b1c }, 3239 [GSBI12_RESET] = { 0x2b3c }, 3240 [SPDM_RESET] = { 0x2b6c }, 3241 [TLMM_H_RESET] = { 0x2ba0, 7 }, 3242 [SFAB_MSS_S_RESET] = { 0x2c00, 7 }, 3243 [MSS_SLP_RESET] = { 0x2c60, 7 }, 3244 [MSS_Q6SW_JTAG_RESET] = { 0x2c68, 7 }, 3245 [MSS_Q6FW_JTAG_RESET] = { 0x2c6c, 7 }, 3246 [MSS_RESET] = { 0x2c64 }, 3247 [SATA_H_RESET] = { 0x2c80, 7 }, 3248 [SATA_RXOOB_RESE] = { 0x2c8c, 7 }, 3249 [SATA_PMALIVE_RESET] = { 0x2c90, 7 }, 3250 [SATA_SFAB_M_RESET] = { 0x2c98, 7 }, 3251 [TSSC_RESET] = { 0x2ca0, 7 }, 3252 [PDM_RESET] = { 0x2cc0, 12 }, 3253 [MPM_H_RESET] = { 0x2da0, 7 }, 3254 [MPM_RESET] = { 0x2da4 }, 3255 [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 }, 3256 [PRNG_RESET] = { 0x2e80, 12 }, 3257 [RIVA_RESET] = { 0x35e0 }, 3258 }; 3259 3260 static struct clk_regmap *gcc_apq8064_clks[] = { 3261 [PLL3] = &pll3.clkr, 3262 [PLL4_VOTE] = &pll4_vote, 3263 [PLL8] = &pll8.clkr, 3264 [PLL8_VOTE] = &pll8_vote, 3265 [PLL14] = &pll14.clkr, 3266 [PLL14_VOTE] = &pll14_vote, 3267 [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr, 3268 [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr, 3269 [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr, 3270 [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr, 3271 [GSBI3_UART_SRC] = &gsbi3_uart_src.clkr, 3272 [GSBI3_UART_CLK] = &gsbi3_uart_clk.clkr, 3273 [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr, 3274 [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr, 3275 [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr, 3276 [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr, 3277 [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr, 3278 [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr, 3279 [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr, 3280 [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr, 3281 [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr, 3282 [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr, 3283 [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr, 3284 [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr, 3285 [GSBI3_QUP_SRC] = &gsbi3_qup_src.clkr, 3286 [GSBI3_QUP_CLK] = &gsbi3_qup_clk.clkr, 3287 [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr, 3288 [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr, 3289 [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr, 3290 [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr, 3291 [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr, 3292 [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr, 3293 [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr, 3294 [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr, 3295 [GP0_SRC] = &gp0_src.clkr, 3296 [GP0_CLK] = &gp0_clk.clkr, 3297 [GP1_SRC] = &gp1_src.clkr, 3298 [GP1_CLK] = &gp1_clk.clkr, 3299 [GP2_SRC] = &gp2_src.clkr, 3300 [GP2_CLK] = &gp2_clk.clkr, 3301 [PMEM_A_CLK] = &pmem_clk.clkr, 3302 [PRNG_SRC] = &prng_src.clkr, 3303 [PRNG_CLK] = &prng_clk.clkr, 3304 [SDC1_SRC] = &sdc1_src.clkr, 3305 [SDC1_CLK] = &sdc1_clk.clkr, 3306 [SDC2_SRC] = &sdc2_src.clkr, 3307 [SDC2_CLK] = &sdc2_clk.clkr, 3308 [SDC3_SRC] = &sdc3_src.clkr, 3309 [SDC3_CLK] = &sdc3_clk.clkr, 3310 [SDC4_SRC] = &sdc4_src.clkr, 3311 [SDC4_CLK] = &sdc4_clk.clkr, 3312 [TSIF_REF_SRC] = &tsif_ref_src.clkr, 3313 [TSIF_REF_CLK] = &tsif_ref_clk.clkr, 3314 [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_src.clkr, 3315 [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr, 3316 [USB_HS3_XCVR_SRC] = &usb_hs3_xcvr_src.clkr, 3317 [USB_HS3_XCVR_CLK] = &usb_hs3_xcvr_clk.clkr, 3318 [USB_HS4_XCVR_SRC] = &usb_hs4_xcvr_src.clkr, 3319 [USB_HS4_XCVR_CLK] = &usb_hs4_xcvr_clk.clkr, 3320 [USB_HSIC_XCVR_FS_SRC] = &usb_hsic_xcvr_fs_src.clkr, 3321 [USB_HSIC_XCVR_FS_CLK] = &usb_hsic_xcvr_fs_clk.clkr, 3322 [USB_HSIC_SYSTEM_CLK] = &usb_hsic_system_clk.clkr, 3323 [USB_HSIC_HSIC_CLK] = &usb_hsic_hsic_clk.clkr, 3324 [USB_HSIC_HSIO_CAL_CLK] = &usb_hsic_hsio_cal_clk.clkr, 3325 [USB_FS1_XCVR_FS_SRC] = &usb_fs1_xcvr_fs_src.clkr, 3326 [USB_FS1_XCVR_FS_CLK] = &usb_fs1_xcvr_fs_clk.clkr, 3327 [USB_FS1_SYSTEM_CLK] = &usb_fs1_system_clk.clkr, 3328 [SATA_H_CLK] = &sata_h_clk.clkr, 3329 [SATA_CLK_SRC] = &sata_clk_src.clkr, 3330 [SATA_RXOOB_CLK] = &sata_rxoob_clk.clkr, 3331 [SATA_PMALIVE_CLK] = &sata_pmalive_clk.clkr, 3332 [SATA_PHY_REF_CLK] = &sata_phy_ref_clk.clkr, 3333 [SATA_PHY_CFG_CLK] = &sata_phy_cfg_clk.clkr, 3334 [SATA_A_CLK] = &sata_a_clk.clkr, 3335 [SFAB_SATA_S_H_CLK] = &sfab_sata_s_h_clk.clkr, 3336 [CE3_SRC] = &ce3_src.clkr, 3337 [CE3_CORE_CLK] = &ce3_core_clk.clkr, 3338 [CE3_H_CLK] = &ce3_h_clk.clkr, 3339 [DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr, 3340 [GSBI1_H_CLK] = &gsbi1_h_clk.clkr, 3341 [GSBI2_H_CLK] = &gsbi2_h_clk.clkr, 3342 [GSBI3_H_CLK] = &gsbi3_h_clk.clkr, 3343 [GSBI4_H_CLK] = &gsbi4_h_clk.clkr, 3344 [GSBI5_H_CLK] = &gsbi5_h_clk.clkr, 3345 [GSBI6_H_CLK] = &gsbi6_h_clk.clkr, 3346 [GSBI7_H_CLK] = &gsbi7_h_clk.clkr, 3347 [TSIF_H_CLK] = &tsif_h_clk.clkr, 3348 [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr, 3349 [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr, 3350 [USB_HSIC_H_CLK] = &usb_hsic_h_clk.clkr, 3351 [USB_HS3_H_CLK] = &usb_hs3_h_clk.clkr, 3352 [USB_HS4_H_CLK] = &usb_hs4_h_clk.clkr, 3353 [SDC1_H_CLK] = &sdc1_h_clk.clkr, 3354 [SDC2_H_CLK] = &sdc2_h_clk.clkr, 3355 [SDC3_H_CLK] = &sdc3_h_clk.clkr, 3356 [SDC4_H_CLK] = &sdc4_h_clk.clkr, 3357 [ADM0_CLK] = &adm0_clk.clkr, 3358 [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr, 3359 [PCIE_A_CLK] = &pcie_a_clk.clkr, 3360 [PCIE_PHY_REF_CLK] = &pcie_phy_ref_clk.clkr, 3361 [PCIE_H_CLK] = &pcie_h_clk.clkr, 3362 [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr, 3363 [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr, 3364 [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr, 3365 [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr, 3366 }; 3367 3368 static const struct qcom_reset_map gcc_apq8064_resets[] = { 3369 [QDSS_STM_RESET] = { 0x2060, 6 }, 3370 [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 }, 3371 [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 }, 3372 [AFAB_SMPSS_M0_RESET] = { 0x20b8 }, 3373 [AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 }, 3374 [AFAB_EBI1_CH1_RESET] = { 0x20c4, 7}, 3375 [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 }, 3376 [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 }, 3377 [SFAB_ADM0_M2_RESET] = { 0x21e8, 7 }, 3378 [ADM0_C2_RESET] = { 0x220c, 4}, 3379 [ADM0_C1_RESET] = { 0x220c, 3}, 3380 [ADM0_C0_RESET] = { 0x220c, 2}, 3381 [ADM0_PBUS_RESET] = { 0x220c, 1 }, 3382 [ADM0_RESET] = { 0x220c }, 3383 [QDSS_CLKS_SW_RESET] = { 0x2260, 5 }, 3384 [QDSS_POR_RESET] = { 0x2260, 4 }, 3385 [QDSS_TSCTR_RESET] = { 0x2260, 3 }, 3386 [QDSS_HRESET_RESET] = { 0x2260, 2 }, 3387 [QDSS_AXI_RESET] = { 0x2260, 1 }, 3388 [QDSS_DBG_RESET] = { 0x2260 }, 3389 [SFAB_PCIE_M_RESET] = { 0x22d8, 1 }, 3390 [SFAB_PCIE_S_RESET] = { 0x22d8 }, 3391 [PCIE_EXT_PCI_RESET] = { 0x22dc, 6 }, 3392 [PCIE_PHY_RESET] = { 0x22dc, 5 }, 3393 [PCIE_PCI_RESET] = { 0x22dc, 4 }, 3394 [PCIE_POR_RESET] = { 0x22dc, 3 }, 3395 [PCIE_HCLK_RESET] = { 0x22dc, 2 }, 3396 [PCIE_ACLK_RESET] = { 0x22dc }, 3397 [SFAB_USB3_M_RESET] = { 0x2360, 7 }, 3398 [SFAB_RIVA_M_RESET] = { 0x2380, 7 }, 3399 [SFAB_LPASS_RESET] = { 0x23a0, 7 }, 3400 [SFAB_AFAB_M_RESET] = { 0x23e0, 7 }, 3401 [AFAB_SFAB_M0_RESET] = { 0x2420, 7 }, 3402 [AFAB_SFAB_M1_RESET] = { 0x2424, 7 }, 3403 [SFAB_SATA_S_RESET] = { 0x2480, 7 }, 3404 [SFAB_DFAB_M_RESET] = { 0x2500, 7 }, 3405 [DFAB_SFAB_M_RESET] = { 0x2520, 7 }, 3406 [DFAB_SWAY0_RESET] = { 0x2540, 7 }, 3407 [DFAB_SWAY1_RESET] = { 0x2544, 7 }, 3408 [DFAB_ARB0_RESET] = { 0x2560, 7 }, 3409 [DFAB_ARB1_RESET] = { 0x2564, 7 }, 3410 [PPSS_PROC_RESET] = { 0x2594, 1 }, 3411 [PPSS_RESET] = { 0x2594}, 3412 [DMA_BAM_RESET] = { 0x25c0, 7 }, 3413 [SPS_TIC_H_RESET] = { 0x2600, 7 }, 3414 [SFAB_CFPB_M_RESET] = { 0x2680, 7 }, 3415 [SFAB_CFPB_S_RESET] = { 0x26c0, 7 }, 3416 [TSIF_H_RESET] = { 0x2700, 7 }, 3417 [CE1_H_RESET] = { 0x2720, 7 }, 3418 [CE1_CORE_RESET] = { 0x2724, 7 }, 3419 [CE1_SLEEP_RESET] = { 0x2728, 7 }, 3420 [CE2_H_RESET] = { 0x2740, 7 }, 3421 [CE2_CORE_RESET] = { 0x2744, 7 }, 3422 [SFAB_SFPB_M_RESET] = { 0x2780, 7 }, 3423 [SFAB_SFPB_S_RESET] = { 0x27a0, 7 }, 3424 [RPM_PROC_RESET] = { 0x27c0, 7 }, 3425 [PMIC_SSBI2_RESET] = { 0x280c, 12 }, 3426 [SDC1_RESET] = { 0x2830 }, 3427 [SDC2_RESET] = { 0x2850 }, 3428 [SDC3_RESET] = { 0x2870 }, 3429 [SDC4_RESET] = { 0x2890 }, 3430 [USB_HS1_RESET] = { 0x2910 }, 3431 [USB_HSIC_RESET] = { 0x2934 }, 3432 [USB_FS1_XCVR_RESET] = { 0x2974, 1 }, 3433 [USB_FS1_RESET] = { 0x2974 }, 3434 [GSBI1_RESET] = { 0x29dc }, 3435 [GSBI2_RESET] = { 0x29fc }, 3436 [GSBI3_RESET] = { 0x2a1c }, 3437 [GSBI4_RESET] = { 0x2a3c }, 3438 [GSBI5_RESET] = { 0x2a5c }, 3439 [GSBI6_RESET] = { 0x2a7c }, 3440 [GSBI7_RESET] = { 0x2a9c }, 3441 [SPDM_RESET] = { 0x2b6c }, 3442 [TLMM_H_RESET] = { 0x2ba0, 7 }, 3443 [SATA_SFAB_M_RESET] = { 0x2c18 }, 3444 [SATA_RESET] = { 0x2c1c }, 3445 [GSS_SLP_RESET] = { 0x2c60, 7 }, 3446 [GSS_RESET] = { 0x2c64 }, 3447 [TSSC_RESET] = { 0x2ca0, 7 }, 3448 [PDM_RESET] = { 0x2cc0, 12 }, 3449 [MPM_H_RESET] = { 0x2da0, 7 }, 3450 [MPM_RESET] = { 0x2da4 }, 3451 [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 }, 3452 [PRNG_RESET] = { 0x2e80, 12 }, 3453 [RIVA_RESET] = { 0x35e0 }, 3454 [CE3_H_RESET] = { 0x36c4, 7 }, 3455 [SFAB_CE3_M_RESET] = { 0x36c8, 1 }, 3456 [SFAB_CE3_S_RESET] = { 0x36c8 }, 3457 [CE3_RESET] = { 0x36cc, 7 }, 3458 [CE3_SLEEP_RESET] = { 0x36d0, 7 }, 3459 [USB_HS3_RESET] = { 0x3710 }, 3460 [USB_HS4_RESET] = { 0x3730 }, 3461 }; 3462 3463 static const struct regmap_config gcc_msm8960_regmap_config = { 3464 .reg_bits = 32, 3465 .reg_stride = 4, 3466 .val_bits = 32, 3467 .max_register = 0x3660, 3468 .fast_io = true, 3469 }; 3470 3471 static const struct regmap_config gcc_apq8064_regmap_config = { 3472 .reg_bits = 32, 3473 .reg_stride = 4, 3474 .val_bits = 32, 3475 .max_register = 0x3880, 3476 .fast_io = true, 3477 }; 3478 3479 static const struct qcom_cc_desc gcc_msm8960_desc = { 3480 .config = &gcc_msm8960_regmap_config, 3481 .clks = gcc_msm8960_clks, 3482 .num_clks = ARRAY_SIZE(gcc_msm8960_clks), 3483 .resets = gcc_msm8960_resets, 3484 .num_resets = ARRAY_SIZE(gcc_msm8960_resets), 3485 }; 3486 3487 static const struct qcom_cc_desc gcc_apq8064_desc = { 3488 .config = &gcc_apq8064_regmap_config, 3489 .clks = gcc_apq8064_clks, 3490 .num_clks = ARRAY_SIZE(gcc_apq8064_clks), 3491 .resets = gcc_apq8064_resets, 3492 .num_resets = ARRAY_SIZE(gcc_apq8064_resets), 3493 }; 3494 3495 static const struct of_device_id gcc_msm8960_match_table[] = { 3496 { .compatible = "qcom,gcc-msm8960", .data = &gcc_msm8960_desc }, 3497 { .compatible = "qcom,gcc-apq8064", .data = &gcc_apq8064_desc }, 3498 { } 3499 }; 3500 MODULE_DEVICE_TABLE(of, gcc_msm8960_match_table); 3501 3502 static int gcc_msm8960_probe(struct platform_device *pdev) 3503 { 3504 struct clk *clk; 3505 struct device *dev = &pdev->dev; 3506 const struct of_device_id *match; 3507 3508 match = of_match_device(gcc_msm8960_match_table, &pdev->dev); 3509 if (!match) 3510 return -EINVAL; 3511 3512 /* Temporary until RPM clocks supported */ 3513 clk = clk_register_fixed_rate(dev, "cxo", NULL, CLK_IS_ROOT, 19200000); 3514 if (IS_ERR(clk)) 3515 return PTR_ERR(clk); 3516 3517 clk = clk_register_fixed_rate(dev, "pxo", NULL, CLK_IS_ROOT, 27000000); 3518 if (IS_ERR(clk)) 3519 return PTR_ERR(clk); 3520 3521 return qcom_cc_probe(pdev, match->data); 3522 } 3523 3524 static int gcc_msm8960_remove(struct platform_device *pdev) 3525 { 3526 qcom_cc_remove(pdev); 3527 return 0; 3528 } 3529 3530 static struct platform_driver gcc_msm8960_driver = { 3531 .probe = gcc_msm8960_probe, 3532 .remove = gcc_msm8960_remove, 3533 .driver = { 3534 .name = "gcc-msm8960", 3535 .of_match_table = gcc_msm8960_match_table, 3536 }, 3537 }; 3538 3539 static int __init gcc_msm8960_init(void) 3540 { 3541 return platform_driver_register(&gcc_msm8960_driver); 3542 } 3543 core_initcall(gcc_msm8960_init); 3544 3545 static void __exit gcc_msm8960_exit(void) 3546 { 3547 platform_driver_unregister(&gcc_msm8960_driver); 3548 } 3549 module_exit(gcc_msm8960_exit); 3550 3551 MODULE_DESCRIPTION("QCOM GCC MSM8960 Driver"); 3552 MODULE_LICENSE("GPL v2"); 3553 MODULE_ALIAS("platform:gcc-msm8960"); 3554