1 /* 2 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include <linux/kernel.h> 15 #include <linux/bitops.h> 16 #include <linux/err.h> 17 #include <linux/platform_device.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/of_device.h> 21 #include <linux/clk-provider.h> 22 #include <linux/regmap.h> 23 #include <linux/reset-controller.h> 24 25 #include <dt-bindings/clock/qcom,gcc-msm8960.h> 26 #include <dt-bindings/reset/qcom,gcc-msm8960.h> 27 28 #include "common.h" 29 #include "clk-regmap.h" 30 #include "clk-pll.h" 31 #include "clk-rcg.h" 32 #include "clk-branch.h" 33 #include "reset.h" 34 35 static struct clk_pll pll3 = { 36 .l_reg = 0x3164, 37 .m_reg = 0x3168, 38 .n_reg = 0x316c, 39 .config_reg = 0x3174, 40 .mode_reg = 0x3160, 41 .status_reg = 0x3178, 42 .status_bit = 16, 43 .clkr.hw.init = &(struct clk_init_data){ 44 .name = "pll3", 45 .parent_names = (const char *[]){ "pxo" }, 46 .num_parents = 1, 47 .ops = &clk_pll_ops, 48 }, 49 }; 50 51 static struct clk_pll pll8 = { 52 .l_reg = 0x3144, 53 .m_reg = 0x3148, 54 .n_reg = 0x314c, 55 .config_reg = 0x3154, 56 .mode_reg = 0x3140, 57 .status_reg = 0x3158, 58 .status_bit = 16, 59 .clkr.hw.init = &(struct clk_init_data){ 60 .name = "pll8", 61 .parent_names = (const char *[]){ "pxo" }, 62 .num_parents = 1, 63 .ops = &clk_pll_ops, 64 }, 65 }; 66 67 static struct clk_regmap pll8_vote = { 68 .enable_reg = 0x34c0, 69 .enable_mask = BIT(8), 70 .hw.init = &(struct clk_init_data){ 71 .name = "pll8_vote", 72 .parent_names = (const char *[]){ "pll8" }, 73 .num_parents = 1, 74 .ops = &clk_pll_vote_ops, 75 }, 76 }; 77 78 static struct clk_pll pll14 = { 79 .l_reg = 0x31c4, 80 .m_reg = 0x31c8, 81 .n_reg = 0x31cc, 82 .config_reg = 0x31d4, 83 .mode_reg = 0x31c0, 84 .status_reg = 0x31d8, 85 .status_bit = 16, 86 .clkr.hw.init = &(struct clk_init_data){ 87 .name = "pll14", 88 .parent_names = (const char *[]){ "pxo" }, 89 .num_parents = 1, 90 .ops = &clk_pll_ops, 91 }, 92 }; 93 94 static struct clk_regmap pll14_vote = { 95 .enable_reg = 0x34c0, 96 .enable_mask = BIT(14), 97 .hw.init = &(struct clk_init_data){ 98 .name = "pll14_vote", 99 .parent_names = (const char *[]){ "pll14" }, 100 .num_parents = 1, 101 .ops = &clk_pll_vote_ops, 102 }, 103 }; 104 105 #define P_PXO 0 106 #define P_PLL8 1 107 #define P_CXO 2 108 109 static const u8 gcc_pxo_pll8_map[] = { 110 [P_PXO] = 0, 111 [P_PLL8] = 3, 112 }; 113 114 static const char *gcc_pxo_pll8[] = { 115 "pxo", 116 "pll8_vote", 117 }; 118 119 static const u8 gcc_pxo_pll8_cxo_map[] = { 120 [P_PXO] = 0, 121 [P_PLL8] = 3, 122 [P_CXO] = 5, 123 }; 124 125 static const char *gcc_pxo_pll8_cxo[] = { 126 "pxo", 127 "pll8_vote", 128 "cxo", 129 }; 130 131 static struct freq_tbl clk_tbl_gsbi_uart[] = { 132 { 1843200, P_PLL8, 2, 6, 625 }, 133 { 3686400, P_PLL8, 2, 12, 625 }, 134 { 7372800, P_PLL8, 2, 24, 625 }, 135 { 14745600, P_PLL8, 2, 48, 625 }, 136 { 16000000, P_PLL8, 4, 1, 6 }, 137 { 24000000, P_PLL8, 4, 1, 4 }, 138 { 32000000, P_PLL8, 4, 1, 3 }, 139 { 40000000, P_PLL8, 1, 5, 48 }, 140 { 46400000, P_PLL8, 1, 29, 240 }, 141 { 48000000, P_PLL8, 4, 1, 2 }, 142 { 51200000, P_PLL8, 1, 2, 15 }, 143 { 56000000, P_PLL8, 1, 7, 48 }, 144 { 58982400, P_PLL8, 1, 96, 625 }, 145 { 64000000, P_PLL8, 2, 1, 3 }, 146 { } 147 }; 148 149 static struct clk_rcg gsbi1_uart_src = { 150 .ns_reg = 0x29d4, 151 .md_reg = 0x29d0, 152 .mn = { 153 .mnctr_en_bit = 8, 154 .mnctr_reset_bit = 7, 155 .mnctr_mode_shift = 5, 156 .n_val_shift = 16, 157 .m_val_shift = 16, 158 .width = 16, 159 }, 160 .p = { 161 .pre_div_shift = 3, 162 .pre_div_width = 2, 163 }, 164 .s = { 165 .src_sel_shift = 0, 166 .parent_map = gcc_pxo_pll8_map, 167 }, 168 .freq_tbl = clk_tbl_gsbi_uart, 169 .clkr = { 170 .enable_reg = 0x29d4, 171 .enable_mask = BIT(11), 172 .hw.init = &(struct clk_init_data){ 173 .name = "gsbi1_uart_src", 174 .parent_names = gcc_pxo_pll8, 175 .num_parents = 2, 176 .ops = &clk_rcg_ops, 177 .flags = CLK_SET_PARENT_GATE, 178 }, 179 }, 180 }; 181 182 static struct clk_branch gsbi1_uart_clk = { 183 .halt_reg = 0x2fcc, 184 .halt_bit = 10, 185 .clkr = { 186 .enable_reg = 0x29d4, 187 .enable_mask = BIT(9), 188 .hw.init = &(struct clk_init_data){ 189 .name = "gsbi1_uart_clk", 190 .parent_names = (const char *[]){ 191 "gsbi1_uart_src", 192 }, 193 .num_parents = 1, 194 .ops = &clk_branch_ops, 195 .flags = CLK_SET_RATE_PARENT, 196 }, 197 }, 198 }; 199 200 static struct clk_rcg gsbi2_uart_src = { 201 .ns_reg = 0x29f4, 202 .md_reg = 0x29f0, 203 .mn = { 204 .mnctr_en_bit = 8, 205 .mnctr_reset_bit = 7, 206 .mnctr_mode_shift = 5, 207 .n_val_shift = 16, 208 .m_val_shift = 16, 209 .width = 16, 210 }, 211 .p = { 212 .pre_div_shift = 3, 213 .pre_div_width = 2, 214 }, 215 .s = { 216 .src_sel_shift = 0, 217 .parent_map = gcc_pxo_pll8_map, 218 }, 219 .freq_tbl = clk_tbl_gsbi_uart, 220 .clkr = { 221 .enable_reg = 0x29f4, 222 .enable_mask = BIT(11), 223 .hw.init = &(struct clk_init_data){ 224 .name = "gsbi2_uart_src", 225 .parent_names = gcc_pxo_pll8, 226 .num_parents = 2, 227 .ops = &clk_rcg_ops, 228 .flags = CLK_SET_PARENT_GATE, 229 }, 230 }, 231 }; 232 233 static struct clk_branch gsbi2_uart_clk = { 234 .halt_reg = 0x2fcc, 235 .halt_bit = 6, 236 .clkr = { 237 .enable_reg = 0x29f4, 238 .enable_mask = BIT(9), 239 .hw.init = &(struct clk_init_data){ 240 .name = "gsbi2_uart_clk", 241 .parent_names = (const char *[]){ 242 "gsbi2_uart_src", 243 }, 244 .num_parents = 1, 245 .ops = &clk_branch_ops, 246 .flags = CLK_SET_RATE_PARENT, 247 }, 248 }, 249 }; 250 251 static struct clk_rcg gsbi3_uart_src = { 252 .ns_reg = 0x2a14, 253 .md_reg = 0x2a10, 254 .mn = { 255 .mnctr_en_bit = 8, 256 .mnctr_reset_bit = 7, 257 .mnctr_mode_shift = 5, 258 .n_val_shift = 16, 259 .m_val_shift = 16, 260 .width = 16, 261 }, 262 .p = { 263 .pre_div_shift = 3, 264 .pre_div_width = 2, 265 }, 266 .s = { 267 .src_sel_shift = 0, 268 .parent_map = gcc_pxo_pll8_map, 269 }, 270 .freq_tbl = clk_tbl_gsbi_uart, 271 .clkr = { 272 .enable_reg = 0x2a14, 273 .enable_mask = BIT(11), 274 .hw.init = &(struct clk_init_data){ 275 .name = "gsbi3_uart_src", 276 .parent_names = gcc_pxo_pll8, 277 .num_parents = 2, 278 .ops = &clk_rcg_ops, 279 .flags = CLK_SET_PARENT_GATE, 280 }, 281 }, 282 }; 283 284 static struct clk_branch gsbi3_uart_clk = { 285 .halt_reg = 0x2fcc, 286 .halt_bit = 2, 287 .clkr = { 288 .enable_reg = 0x2a14, 289 .enable_mask = BIT(9), 290 .hw.init = &(struct clk_init_data){ 291 .name = "gsbi3_uart_clk", 292 .parent_names = (const char *[]){ 293 "gsbi3_uart_src", 294 }, 295 .num_parents = 1, 296 .ops = &clk_branch_ops, 297 .flags = CLK_SET_RATE_PARENT, 298 }, 299 }, 300 }; 301 302 static struct clk_rcg gsbi4_uart_src = { 303 .ns_reg = 0x2a34, 304 .md_reg = 0x2a30, 305 .mn = { 306 .mnctr_en_bit = 8, 307 .mnctr_reset_bit = 7, 308 .mnctr_mode_shift = 5, 309 .n_val_shift = 16, 310 .m_val_shift = 16, 311 .width = 16, 312 }, 313 .p = { 314 .pre_div_shift = 3, 315 .pre_div_width = 2, 316 }, 317 .s = { 318 .src_sel_shift = 0, 319 .parent_map = gcc_pxo_pll8_map, 320 }, 321 .freq_tbl = clk_tbl_gsbi_uart, 322 .clkr = { 323 .enable_reg = 0x2a34, 324 .enable_mask = BIT(11), 325 .hw.init = &(struct clk_init_data){ 326 .name = "gsbi4_uart_src", 327 .parent_names = gcc_pxo_pll8, 328 .num_parents = 2, 329 .ops = &clk_rcg_ops, 330 .flags = CLK_SET_PARENT_GATE, 331 }, 332 }, 333 }; 334 335 static struct clk_branch gsbi4_uart_clk = { 336 .halt_reg = 0x2fd0, 337 .halt_bit = 26, 338 .clkr = { 339 .enable_reg = 0x2a34, 340 .enable_mask = BIT(9), 341 .hw.init = &(struct clk_init_data){ 342 .name = "gsbi4_uart_clk", 343 .parent_names = (const char *[]){ 344 "gsbi4_uart_src", 345 }, 346 .num_parents = 1, 347 .ops = &clk_branch_ops, 348 .flags = CLK_SET_RATE_PARENT, 349 }, 350 }, 351 }; 352 353 static struct clk_rcg gsbi5_uart_src = { 354 .ns_reg = 0x2a54, 355 .md_reg = 0x2a50, 356 .mn = { 357 .mnctr_en_bit = 8, 358 .mnctr_reset_bit = 7, 359 .mnctr_mode_shift = 5, 360 .n_val_shift = 16, 361 .m_val_shift = 16, 362 .width = 16, 363 }, 364 .p = { 365 .pre_div_shift = 3, 366 .pre_div_width = 2, 367 }, 368 .s = { 369 .src_sel_shift = 0, 370 .parent_map = gcc_pxo_pll8_map, 371 }, 372 .freq_tbl = clk_tbl_gsbi_uart, 373 .clkr = { 374 .enable_reg = 0x2a54, 375 .enable_mask = BIT(11), 376 .hw.init = &(struct clk_init_data){ 377 .name = "gsbi5_uart_src", 378 .parent_names = gcc_pxo_pll8, 379 .num_parents = 2, 380 .ops = &clk_rcg_ops, 381 .flags = CLK_SET_PARENT_GATE, 382 }, 383 }, 384 }; 385 386 static struct clk_branch gsbi5_uart_clk = { 387 .halt_reg = 0x2fd0, 388 .halt_bit = 22, 389 .clkr = { 390 .enable_reg = 0x2a54, 391 .enable_mask = BIT(9), 392 .hw.init = &(struct clk_init_data){ 393 .name = "gsbi5_uart_clk", 394 .parent_names = (const char *[]){ 395 "gsbi5_uart_src", 396 }, 397 .num_parents = 1, 398 .ops = &clk_branch_ops, 399 .flags = CLK_SET_RATE_PARENT, 400 }, 401 }, 402 }; 403 404 static struct clk_rcg gsbi6_uart_src = { 405 .ns_reg = 0x2a74, 406 .md_reg = 0x2a70, 407 .mn = { 408 .mnctr_en_bit = 8, 409 .mnctr_reset_bit = 7, 410 .mnctr_mode_shift = 5, 411 .n_val_shift = 16, 412 .m_val_shift = 16, 413 .width = 16, 414 }, 415 .p = { 416 .pre_div_shift = 3, 417 .pre_div_width = 2, 418 }, 419 .s = { 420 .src_sel_shift = 0, 421 .parent_map = gcc_pxo_pll8_map, 422 }, 423 .freq_tbl = clk_tbl_gsbi_uart, 424 .clkr = { 425 .enable_reg = 0x2a74, 426 .enable_mask = BIT(11), 427 .hw.init = &(struct clk_init_data){ 428 .name = "gsbi6_uart_src", 429 .parent_names = gcc_pxo_pll8, 430 .num_parents = 2, 431 .ops = &clk_rcg_ops, 432 .flags = CLK_SET_PARENT_GATE, 433 }, 434 }, 435 }; 436 437 static struct clk_branch gsbi6_uart_clk = { 438 .halt_reg = 0x2fd0, 439 .halt_bit = 18, 440 .clkr = { 441 .enable_reg = 0x2a74, 442 .enable_mask = BIT(9), 443 .hw.init = &(struct clk_init_data){ 444 .name = "gsbi6_uart_clk", 445 .parent_names = (const char *[]){ 446 "gsbi6_uart_src", 447 }, 448 .num_parents = 1, 449 .ops = &clk_branch_ops, 450 .flags = CLK_SET_RATE_PARENT, 451 }, 452 }, 453 }; 454 455 static struct clk_rcg gsbi7_uart_src = { 456 .ns_reg = 0x2a94, 457 .md_reg = 0x2a90, 458 .mn = { 459 .mnctr_en_bit = 8, 460 .mnctr_reset_bit = 7, 461 .mnctr_mode_shift = 5, 462 .n_val_shift = 16, 463 .m_val_shift = 16, 464 .width = 16, 465 }, 466 .p = { 467 .pre_div_shift = 3, 468 .pre_div_width = 2, 469 }, 470 .s = { 471 .src_sel_shift = 0, 472 .parent_map = gcc_pxo_pll8_map, 473 }, 474 .freq_tbl = clk_tbl_gsbi_uart, 475 .clkr = { 476 .enable_reg = 0x2a94, 477 .enable_mask = BIT(11), 478 .hw.init = &(struct clk_init_data){ 479 .name = "gsbi7_uart_src", 480 .parent_names = gcc_pxo_pll8, 481 .num_parents = 2, 482 .ops = &clk_rcg_ops, 483 .flags = CLK_SET_PARENT_GATE, 484 }, 485 }, 486 }; 487 488 static struct clk_branch gsbi7_uart_clk = { 489 .halt_reg = 0x2fd0, 490 .halt_bit = 14, 491 .clkr = { 492 .enable_reg = 0x2a94, 493 .enable_mask = BIT(9), 494 .hw.init = &(struct clk_init_data){ 495 .name = "gsbi7_uart_clk", 496 .parent_names = (const char *[]){ 497 "gsbi7_uart_src", 498 }, 499 .num_parents = 1, 500 .ops = &clk_branch_ops, 501 .flags = CLK_SET_RATE_PARENT, 502 }, 503 }, 504 }; 505 506 static struct clk_rcg gsbi8_uart_src = { 507 .ns_reg = 0x2ab4, 508 .md_reg = 0x2ab0, 509 .mn = { 510 .mnctr_en_bit = 8, 511 .mnctr_reset_bit = 7, 512 .mnctr_mode_shift = 5, 513 .n_val_shift = 16, 514 .m_val_shift = 16, 515 .width = 16, 516 }, 517 .p = { 518 .pre_div_shift = 3, 519 .pre_div_width = 2, 520 }, 521 .s = { 522 .src_sel_shift = 0, 523 .parent_map = gcc_pxo_pll8_map, 524 }, 525 .freq_tbl = clk_tbl_gsbi_uart, 526 .clkr = { 527 .enable_reg = 0x2ab4, 528 .enable_mask = BIT(11), 529 .hw.init = &(struct clk_init_data){ 530 .name = "gsbi8_uart_src", 531 .parent_names = gcc_pxo_pll8, 532 .num_parents = 2, 533 .ops = &clk_rcg_ops, 534 .flags = CLK_SET_PARENT_GATE, 535 }, 536 }, 537 }; 538 539 static struct clk_branch gsbi8_uart_clk = { 540 .halt_reg = 0x2fd0, 541 .halt_bit = 10, 542 .clkr = { 543 .enable_reg = 0x2ab4, 544 .enable_mask = BIT(9), 545 .hw.init = &(struct clk_init_data){ 546 .name = "gsbi8_uart_clk", 547 .parent_names = (const char *[]){ "gsbi8_uart_src" }, 548 .num_parents = 1, 549 .ops = &clk_branch_ops, 550 .flags = CLK_SET_RATE_PARENT, 551 }, 552 }, 553 }; 554 555 static struct clk_rcg gsbi9_uart_src = { 556 .ns_reg = 0x2ad4, 557 .md_reg = 0x2ad0, 558 .mn = { 559 .mnctr_en_bit = 8, 560 .mnctr_reset_bit = 7, 561 .mnctr_mode_shift = 5, 562 .n_val_shift = 16, 563 .m_val_shift = 16, 564 .width = 16, 565 }, 566 .p = { 567 .pre_div_shift = 3, 568 .pre_div_width = 2, 569 }, 570 .s = { 571 .src_sel_shift = 0, 572 .parent_map = gcc_pxo_pll8_map, 573 }, 574 .freq_tbl = clk_tbl_gsbi_uart, 575 .clkr = { 576 .enable_reg = 0x2ad4, 577 .enable_mask = BIT(11), 578 .hw.init = &(struct clk_init_data){ 579 .name = "gsbi9_uart_src", 580 .parent_names = gcc_pxo_pll8, 581 .num_parents = 2, 582 .ops = &clk_rcg_ops, 583 .flags = CLK_SET_PARENT_GATE, 584 }, 585 }, 586 }; 587 588 static struct clk_branch gsbi9_uart_clk = { 589 .halt_reg = 0x2fd0, 590 .halt_bit = 6, 591 .clkr = { 592 .enable_reg = 0x2ad4, 593 .enable_mask = BIT(9), 594 .hw.init = &(struct clk_init_data){ 595 .name = "gsbi9_uart_clk", 596 .parent_names = (const char *[]){ "gsbi9_uart_src" }, 597 .num_parents = 1, 598 .ops = &clk_branch_ops, 599 .flags = CLK_SET_RATE_PARENT, 600 }, 601 }, 602 }; 603 604 static struct clk_rcg gsbi10_uart_src = { 605 .ns_reg = 0x2af4, 606 .md_reg = 0x2af0, 607 .mn = { 608 .mnctr_en_bit = 8, 609 .mnctr_reset_bit = 7, 610 .mnctr_mode_shift = 5, 611 .n_val_shift = 16, 612 .m_val_shift = 16, 613 .width = 16, 614 }, 615 .p = { 616 .pre_div_shift = 3, 617 .pre_div_width = 2, 618 }, 619 .s = { 620 .src_sel_shift = 0, 621 .parent_map = gcc_pxo_pll8_map, 622 }, 623 .freq_tbl = clk_tbl_gsbi_uart, 624 .clkr = { 625 .enable_reg = 0x2af4, 626 .enable_mask = BIT(11), 627 .hw.init = &(struct clk_init_data){ 628 .name = "gsbi10_uart_src", 629 .parent_names = gcc_pxo_pll8, 630 .num_parents = 2, 631 .ops = &clk_rcg_ops, 632 .flags = CLK_SET_PARENT_GATE, 633 }, 634 }, 635 }; 636 637 static struct clk_branch gsbi10_uart_clk = { 638 .halt_reg = 0x2fd0, 639 .halt_bit = 2, 640 .clkr = { 641 .enable_reg = 0x2af4, 642 .enable_mask = BIT(9), 643 .hw.init = &(struct clk_init_data){ 644 .name = "gsbi10_uart_clk", 645 .parent_names = (const char *[]){ "gsbi10_uart_src" }, 646 .num_parents = 1, 647 .ops = &clk_branch_ops, 648 .flags = CLK_SET_RATE_PARENT, 649 }, 650 }, 651 }; 652 653 static struct clk_rcg gsbi11_uart_src = { 654 .ns_reg = 0x2b14, 655 .md_reg = 0x2b10, 656 .mn = { 657 .mnctr_en_bit = 8, 658 .mnctr_reset_bit = 7, 659 .mnctr_mode_shift = 5, 660 .n_val_shift = 16, 661 .m_val_shift = 16, 662 .width = 16, 663 }, 664 .p = { 665 .pre_div_shift = 3, 666 .pre_div_width = 2, 667 }, 668 .s = { 669 .src_sel_shift = 0, 670 .parent_map = gcc_pxo_pll8_map, 671 }, 672 .freq_tbl = clk_tbl_gsbi_uart, 673 .clkr = { 674 .enable_reg = 0x2b14, 675 .enable_mask = BIT(11), 676 .hw.init = &(struct clk_init_data){ 677 .name = "gsbi11_uart_src", 678 .parent_names = gcc_pxo_pll8, 679 .num_parents = 2, 680 .ops = &clk_rcg_ops, 681 .flags = CLK_SET_PARENT_GATE, 682 }, 683 }, 684 }; 685 686 static struct clk_branch gsbi11_uart_clk = { 687 .halt_reg = 0x2fd4, 688 .halt_bit = 17, 689 .clkr = { 690 .enable_reg = 0x2b14, 691 .enable_mask = BIT(9), 692 .hw.init = &(struct clk_init_data){ 693 .name = "gsbi11_uart_clk", 694 .parent_names = (const char *[]){ "gsbi11_uart_src" }, 695 .num_parents = 1, 696 .ops = &clk_branch_ops, 697 .flags = CLK_SET_RATE_PARENT, 698 }, 699 }, 700 }; 701 702 static struct clk_rcg gsbi12_uart_src = { 703 .ns_reg = 0x2b34, 704 .md_reg = 0x2b30, 705 .mn = { 706 .mnctr_en_bit = 8, 707 .mnctr_reset_bit = 7, 708 .mnctr_mode_shift = 5, 709 .n_val_shift = 16, 710 .m_val_shift = 16, 711 .width = 16, 712 }, 713 .p = { 714 .pre_div_shift = 3, 715 .pre_div_width = 2, 716 }, 717 .s = { 718 .src_sel_shift = 0, 719 .parent_map = gcc_pxo_pll8_map, 720 }, 721 .freq_tbl = clk_tbl_gsbi_uart, 722 .clkr = { 723 .enable_reg = 0x2b34, 724 .enable_mask = BIT(11), 725 .hw.init = &(struct clk_init_data){ 726 .name = "gsbi12_uart_src", 727 .parent_names = gcc_pxo_pll8, 728 .num_parents = 2, 729 .ops = &clk_rcg_ops, 730 .flags = CLK_SET_PARENT_GATE, 731 }, 732 }, 733 }; 734 735 static struct clk_branch gsbi12_uart_clk = { 736 .halt_reg = 0x2fd4, 737 .halt_bit = 13, 738 .clkr = { 739 .enable_reg = 0x2b34, 740 .enable_mask = BIT(9), 741 .hw.init = &(struct clk_init_data){ 742 .name = "gsbi12_uart_clk", 743 .parent_names = (const char *[]){ "gsbi12_uart_src" }, 744 .num_parents = 1, 745 .ops = &clk_branch_ops, 746 .flags = CLK_SET_RATE_PARENT, 747 }, 748 }, 749 }; 750 751 static struct freq_tbl clk_tbl_gsbi_qup[] = { 752 { 1100000, P_PXO, 1, 2, 49 }, 753 { 5400000, P_PXO, 1, 1, 5 }, 754 { 10800000, P_PXO, 1, 2, 5 }, 755 { 15060000, P_PLL8, 1, 2, 51 }, 756 { 24000000, P_PLL8, 4, 1, 4 }, 757 { 25600000, P_PLL8, 1, 1, 15 }, 758 { 27000000, P_PXO, 1, 0, 0 }, 759 { 48000000, P_PLL8, 4, 1, 2 }, 760 { 51200000, P_PLL8, 1, 2, 15 }, 761 { } 762 }; 763 764 static struct clk_rcg gsbi1_qup_src = { 765 .ns_reg = 0x29cc, 766 .md_reg = 0x29c8, 767 .mn = { 768 .mnctr_en_bit = 8, 769 .mnctr_reset_bit = 7, 770 .mnctr_mode_shift = 5, 771 .n_val_shift = 16, 772 .m_val_shift = 16, 773 .width = 8, 774 }, 775 .p = { 776 .pre_div_shift = 3, 777 .pre_div_width = 2, 778 }, 779 .s = { 780 .src_sel_shift = 0, 781 .parent_map = gcc_pxo_pll8_map, 782 }, 783 .freq_tbl = clk_tbl_gsbi_qup, 784 .clkr = { 785 .enable_reg = 0x29cc, 786 .enable_mask = BIT(11), 787 .hw.init = &(struct clk_init_data){ 788 .name = "gsbi1_qup_src", 789 .parent_names = gcc_pxo_pll8, 790 .num_parents = 2, 791 .ops = &clk_rcg_ops, 792 .flags = CLK_SET_PARENT_GATE, 793 }, 794 }, 795 }; 796 797 static struct clk_branch gsbi1_qup_clk = { 798 .halt_reg = 0x2fcc, 799 .halt_bit = 9, 800 .clkr = { 801 .enable_reg = 0x29cc, 802 .enable_mask = BIT(9), 803 .hw.init = &(struct clk_init_data){ 804 .name = "gsbi1_qup_clk", 805 .parent_names = (const char *[]){ "gsbi1_qup_src" }, 806 .num_parents = 1, 807 .ops = &clk_branch_ops, 808 .flags = CLK_SET_RATE_PARENT, 809 }, 810 }, 811 }; 812 813 static struct clk_rcg gsbi2_qup_src = { 814 .ns_reg = 0x29ec, 815 .md_reg = 0x29e8, 816 .mn = { 817 .mnctr_en_bit = 8, 818 .mnctr_reset_bit = 7, 819 .mnctr_mode_shift = 5, 820 .n_val_shift = 16, 821 .m_val_shift = 16, 822 .width = 8, 823 }, 824 .p = { 825 .pre_div_shift = 3, 826 .pre_div_width = 2, 827 }, 828 .s = { 829 .src_sel_shift = 0, 830 .parent_map = gcc_pxo_pll8_map, 831 }, 832 .freq_tbl = clk_tbl_gsbi_qup, 833 .clkr = { 834 .enable_reg = 0x29ec, 835 .enable_mask = BIT(11), 836 .hw.init = &(struct clk_init_data){ 837 .name = "gsbi2_qup_src", 838 .parent_names = gcc_pxo_pll8, 839 .num_parents = 2, 840 .ops = &clk_rcg_ops, 841 .flags = CLK_SET_PARENT_GATE, 842 }, 843 }, 844 }; 845 846 static struct clk_branch gsbi2_qup_clk = { 847 .halt_reg = 0x2fcc, 848 .halt_bit = 4, 849 .clkr = { 850 .enable_reg = 0x29ec, 851 .enable_mask = BIT(9), 852 .hw.init = &(struct clk_init_data){ 853 .name = "gsbi2_qup_clk", 854 .parent_names = (const char *[]){ "gsbi2_qup_src" }, 855 .num_parents = 1, 856 .ops = &clk_branch_ops, 857 .flags = CLK_SET_RATE_PARENT, 858 }, 859 }, 860 }; 861 862 static struct clk_rcg gsbi3_qup_src = { 863 .ns_reg = 0x2a0c, 864 .md_reg = 0x2a08, 865 .mn = { 866 .mnctr_en_bit = 8, 867 .mnctr_reset_bit = 7, 868 .mnctr_mode_shift = 5, 869 .n_val_shift = 16, 870 .m_val_shift = 16, 871 .width = 8, 872 }, 873 .p = { 874 .pre_div_shift = 3, 875 .pre_div_width = 2, 876 }, 877 .s = { 878 .src_sel_shift = 0, 879 .parent_map = gcc_pxo_pll8_map, 880 }, 881 .freq_tbl = clk_tbl_gsbi_qup, 882 .clkr = { 883 .enable_reg = 0x2a0c, 884 .enable_mask = BIT(11), 885 .hw.init = &(struct clk_init_data){ 886 .name = "gsbi3_qup_src", 887 .parent_names = gcc_pxo_pll8, 888 .num_parents = 2, 889 .ops = &clk_rcg_ops, 890 .flags = CLK_SET_PARENT_GATE, 891 }, 892 }, 893 }; 894 895 static struct clk_branch gsbi3_qup_clk = { 896 .halt_reg = 0x2fcc, 897 .halt_bit = 0, 898 .clkr = { 899 .enable_reg = 0x2a0c, 900 .enable_mask = BIT(9), 901 .hw.init = &(struct clk_init_data){ 902 .name = "gsbi3_qup_clk", 903 .parent_names = (const char *[]){ "gsbi3_qup_src" }, 904 .num_parents = 1, 905 .ops = &clk_branch_ops, 906 .flags = CLK_SET_RATE_PARENT, 907 }, 908 }, 909 }; 910 911 static struct clk_rcg gsbi4_qup_src = { 912 .ns_reg = 0x2a2c, 913 .md_reg = 0x2a28, 914 .mn = { 915 .mnctr_en_bit = 8, 916 .mnctr_reset_bit = 7, 917 .mnctr_mode_shift = 5, 918 .n_val_shift = 16, 919 .m_val_shift = 16, 920 .width = 8, 921 }, 922 .p = { 923 .pre_div_shift = 3, 924 .pre_div_width = 2, 925 }, 926 .s = { 927 .src_sel_shift = 0, 928 .parent_map = gcc_pxo_pll8_map, 929 }, 930 .freq_tbl = clk_tbl_gsbi_qup, 931 .clkr = { 932 .enable_reg = 0x2a2c, 933 .enable_mask = BIT(11), 934 .hw.init = &(struct clk_init_data){ 935 .name = "gsbi4_qup_src", 936 .parent_names = gcc_pxo_pll8, 937 .num_parents = 2, 938 .ops = &clk_rcg_ops, 939 .flags = CLK_SET_PARENT_GATE, 940 }, 941 }, 942 }; 943 944 static struct clk_branch gsbi4_qup_clk = { 945 .halt_reg = 0x2fd0, 946 .halt_bit = 24, 947 .clkr = { 948 .enable_reg = 0x2a2c, 949 .enable_mask = BIT(9), 950 .hw.init = &(struct clk_init_data){ 951 .name = "gsbi4_qup_clk", 952 .parent_names = (const char *[]){ "gsbi4_qup_src" }, 953 .num_parents = 1, 954 .ops = &clk_branch_ops, 955 .flags = CLK_SET_RATE_PARENT, 956 }, 957 }, 958 }; 959 960 static struct clk_rcg gsbi5_qup_src = { 961 .ns_reg = 0x2a4c, 962 .md_reg = 0x2a48, 963 .mn = { 964 .mnctr_en_bit = 8, 965 .mnctr_reset_bit = 7, 966 .mnctr_mode_shift = 5, 967 .n_val_shift = 16, 968 .m_val_shift = 16, 969 .width = 8, 970 }, 971 .p = { 972 .pre_div_shift = 3, 973 .pre_div_width = 2, 974 }, 975 .s = { 976 .src_sel_shift = 0, 977 .parent_map = gcc_pxo_pll8_map, 978 }, 979 .freq_tbl = clk_tbl_gsbi_qup, 980 .clkr = { 981 .enable_reg = 0x2a4c, 982 .enable_mask = BIT(11), 983 .hw.init = &(struct clk_init_data){ 984 .name = "gsbi5_qup_src", 985 .parent_names = gcc_pxo_pll8, 986 .num_parents = 2, 987 .ops = &clk_rcg_ops, 988 .flags = CLK_SET_PARENT_GATE, 989 }, 990 }, 991 }; 992 993 static struct clk_branch gsbi5_qup_clk = { 994 .halt_reg = 0x2fd0, 995 .halt_bit = 20, 996 .clkr = { 997 .enable_reg = 0x2a4c, 998 .enable_mask = BIT(9), 999 .hw.init = &(struct clk_init_data){ 1000 .name = "gsbi5_qup_clk", 1001 .parent_names = (const char *[]){ "gsbi5_qup_src" }, 1002 .num_parents = 1, 1003 .ops = &clk_branch_ops, 1004 .flags = CLK_SET_RATE_PARENT, 1005 }, 1006 }, 1007 }; 1008 1009 static struct clk_rcg gsbi6_qup_src = { 1010 .ns_reg = 0x2a6c, 1011 .md_reg = 0x2a68, 1012 .mn = { 1013 .mnctr_en_bit = 8, 1014 .mnctr_reset_bit = 7, 1015 .mnctr_mode_shift = 5, 1016 .n_val_shift = 16, 1017 .m_val_shift = 16, 1018 .width = 8, 1019 }, 1020 .p = { 1021 .pre_div_shift = 3, 1022 .pre_div_width = 2, 1023 }, 1024 .s = { 1025 .src_sel_shift = 0, 1026 .parent_map = gcc_pxo_pll8_map, 1027 }, 1028 .freq_tbl = clk_tbl_gsbi_qup, 1029 .clkr = { 1030 .enable_reg = 0x2a6c, 1031 .enable_mask = BIT(11), 1032 .hw.init = &(struct clk_init_data){ 1033 .name = "gsbi6_qup_src", 1034 .parent_names = gcc_pxo_pll8, 1035 .num_parents = 2, 1036 .ops = &clk_rcg_ops, 1037 .flags = CLK_SET_PARENT_GATE, 1038 }, 1039 }, 1040 }; 1041 1042 static struct clk_branch gsbi6_qup_clk = { 1043 .halt_reg = 0x2fd0, 1044 .halt_bit = 16, 1045 .clkr = { 1046 .enable_reg = 0x2a6c, 1047 .enable_mask = BIT(9), 1048 .hw.init = &(struct clk_init_data){ 1049 .name = "gsbi6_qup_clk", 1050 .parent_names = (const char *[]){ "gsbi6_qup_src" }, 1051 .num_parents = 1, 1052 .ops = &clk_branch_ops, 1053 .flags = CLK_SET_RATE_PARENT, 1054 }, 1055 }, 1056 }; 1057 1058 static struct clk_rcg gsbi7_qup_src = { 1059 .ns_reg = 0x2a8c, 1060 .md_reg = 0x2a88, 1061 .mn = { 1062 .mnctr_en_bit = 8, 1063 .mnctr_reset_bit = 7, 1064 .mnctr_mode_shift = 5, 1065 .n_val_shift = 16, 1066 .m_val_shift = 16, 1067 .width = 8, 1068 }, 1069 .p = { 1070 .pre_div_shift = 3, 1071 .pre_div_width = 2, 1072 }, 1073 .s = { 1074 .src_sel_shift = 0, 1075 .parent_map = gcc_pxo_pll8_map, 1076 }, 1077 .freq_tbl = clk_tbl_gsbi_qup, 1078 .clkr = { 1079 .enable_reg = 0x2a8c, 1080 .enable_mask = BIT(11), 1081 .hw.init = &(struct clk_init_data){ 1082 .name = "gsbi7_qup_src", 1083 .parent_names = gcc_pxo_pll8, 1084 .num_parents = 2, 1085 .ops = &clk_rcg_ops, 1086 .flags = CLK_SET_PARENT_GATE, 1087 }, 1088 }, 1089 }; 1090 1091 static struct clk_branch gsbi7_qup_clk = { 1092 .halt_reg = 0x2fd0, 1093 .halt_bit = 12, 1094 .clkr = { 1095 .enable_reg = 0x2a8c, 1096 .enable_mask = BIT(9), 1097 .hw.init = &(struct clk_init_data){ 1098 .name = "gsbi7_qup_clk", 1099 .parent_names = (const char *[]){ "gsbi7_qup_src" }, 1100 .num_parents = 1, 1101 .ops = &clk_branch_ops, 1102 .flags = CLK_SET_RATE_PARENT, 1103 }, 1104 }, 1105 }; 1106 1107 static struct clk_rcg gsbi8_qup_src = { 1108 .ns_reg = 0x2aac, 1109 .md_reg = 0x2aa8, 1110 .mn = { 1111 .mnctr_en_bit = 8, 1112 .mnctr_reset_bit = 7, 1113 .mnctr_mode_shift = 5, 1114 .n_val_shift = 16, 1115 .m_val_shift = 16, 1116 .width = 8, 1117 }, 1118 .p = { 1119 .pre_div_shift = 3, 1120 .pre_div_width = 2, 1121 }, 1122 .s = { 1123 .src_sel_shift = 0, 1124 .parent_map = gcc_pxo_pll8_map, 1125 }, 1126 .freq_tbl = clk_tbl_gsbi_qup, 1127 .clkr = { 1128 .enable_reg = 0x2aac, 1129 .enable_mask = BIT(11), 1130 .hw.init = &(struct clk_init_data){ 1131 .name = "gsbi8_qup_src", 1132 .parent_names = gcc_pxo_pll8, 1133 .num_parents = 2, 1134 .ops = &clk_rcg_ops, 1135 .flags = CLK_SET_PARENT_GATE, 1136 }, 1137 }, 1138 }; 1139 1140 static struct clk_branch gsbi8_qup_clk = { 1141 .halt_reg = 0x2fd0, 1142 .halt_bit = 8, 1143 .clkr = { 1144 .enable_reg = 0x2aac, 1145 .enable_mask = BIT(9), 1146 .hw.init = &(struct clk_init_data){ 1147 .name = "gsbi8_qup_clk", 1148 .parent_names = (const char *[]){ "gsbi8_qup_src" }, 1149 .num_parents = 1, 1150 .ops = &clk_branch_ops, 1151 .flags = CLK_SET_RATE_PARENT, 1152 }, 1153 }, 1154 }; 1155 1156 static struct clk_rcg gsbi9_qup_src = { 1157 .ns_reg = 0x2acc, 1158 .md_reg = 0x2ac8, 1159 .mn = { 1160 .mnctr_en_bit = 8, 1161 .mnctr_reset_bit = 7, 1162 .mnctr_mode_shift = 5, 1163 .n_val_shift = 16, 1164 .m_val_shift = 16, 1165 .width = 8, 1166 }, 1167 .p = { 1168 .pre_div_shift = 3, 1169 .pre_div_width = 2, 1170 }, 1171 .s = { 1172 .src_sel_shift = 0, 1173 .parent_map = gcc_pxo_pll8_map, 1174 }, 1175 .freq_tbl = clk_tbl_gsbi_qup, 1176 .clkr = { 1177 .enable_reg = 0x2acc, 1178 .enable_mask = BIT(11), 1179 .hw.init = &(struct clk_init_data){ 1180 .name = "gsbi9_qup_src", 1181 .parent_names = gcc_pxo_pll8, 1182 .num_parents = 2, 1183 .ops = &clk_rcg_ops, 1184 .flags = CLK_SET_PARENT_GATE, 1185 }, 1186 }, 1187 }; 1188 1189 static struct clk_branch gsbi9_qup_clk = { 1190 .halt_reg = 0x2fd0, 1191 .halt_bit = 4, 1192 .clkr = { 1193 .enable_reg = 0x2acc, 1194 .enable_mask = BIT(9), 1195 .hw.init = &(struct clk_init_data){ 1196 .name = "gsbi9_qup_clk", 1197 .parent_names = (const char *[]){ "gsbi9_qup_src" }, 1198 .num_parents = 1, 1199 .ops = &clk_branch_ops, 1200 .flags = CLK_SET_RATE_PARENT, 1201 }, 1202 }, 1203 }; 1204 1205 static struct clk_rcg gsbi10_qup_src = { 1206 .ns_reg = 0x2aec, 1207 .md_reg = 0x2ae8, 1208 .mn = { 1209 .mnctr_en_bit = 8, 1210 .mnctr_reset_bit = 7, 1211 .mnctr_mode_shift = 5, 1212 .n_val_shift = 16, 1213 .m_val_shift = 16, 1214 .width = 8, 1215 }, 1216 .p = { 1217 .pre_div_shift = 3, 1218 .pre_div_width = 2, 1219 }, 1220 .s = { 1221 .src_sel_shift = 0, 1222 .parent_map = gcc_pxo_pll8_map, 1223 }, 1224 .freq_tbl = clk_tbl_gsbi_qup, 1225 .clkr = { 1226 .enable_reg = 0x2aec, 1227 .enable_mask = BIT(11), 1228 .hw.init = &(struct clk_init_data){ 1229 .name = "gsbi10_qup_src", 1230 .parent_names = gcc_pxo_pll8, 1231 .num_parents = 2, 1232 .ops = &clk_rcg_ops, 1233 .flags = CLK_SET_PARENT_GATE, 1234 }, 1235 }, 1236 }; 1237 1238 static struct clk_branch gsbi10_qup_clk = { 1239 .halt_reg = 0x2fd0, 1240 .halt_bit = 0, 1241 .clkr = { 1242 .enable_reg = 0x2aec, 1243 .enable_mask = BIT(9), 1244 .hw.init = &(struct clk_init_data){ 1245 .name = "gsbi10_qup_clk", 1246 .parent_names = (const char *[]){ "gsbi10_qup_src" }, 1247 .num_parents = 1, 1248 .ops = &clk_branch_ops, 1249 .flags = CLK_SET_RATE_PARENT, 1250 }, 1251 }, 1252 }; 1253 1254 static struct clk_rcg gsbi11_qup_src = { 1255 .ns_reg = 0x2b0c, 1256 .md_reg = 0x2b08, 1257 .mn = { 1258 .mnctr_en_bit = 8, 1259 .mnctr_reset_bit = 7, 1260 .mnctr_mode_shift = 5, 1261 .n_val_shift = 16, 1262 .m_val_shift = 16, 1263 .width = 8, 1264 }, 1265 .p = { 1266 .pre_div_shift = 3, 1267 .pre_div_width = 2, 1268 }, 1269 .s = { 1270 .src_sel_shift = 0, 1271 .parent_map = gcc_pxo_pll8_map, 1272 }, 1273 .freq_tbl = clk_tbl_gsbi_qup, 1274 .clkr = { 1275 .enable_reg = 0x2b0c, 1276 .enable_mask = BIT(11), 1277 .hw.init = &(struct clk_init_data){ 1278 .name = "gsbi11_qup_src", 1279 .parent_names = gcc_pxo_pll8, 1280 .num_parents = 2, 1281 .ops = &clk_rcg_ops, 1282 .flags = CLK_SET_PARENT_GATE, 1283 }, 1284 }, 1285 }; 1286 1287 static struct clk_branch gsbi11_qup_clk = { 1288 .halt_reg = 0x2fd4, 1289 .halt_bit = 15, 1290 .clkr = { 1291 .enable_reg = 0x2b0c, 1292 .enable_mask = BIT(9), 1293 .hw.init = &(struct clk_init_data){ 1294 .name = "gsbi11_qup_clk", 1295 .parent_names = (const char *[]){ "gsbi11_qup_src" }, 1296 .num_parents = 1, 1297 .ops = &clk_branch_ops, 1298 .flags = CLK_SET_RATE_PARENT, 1299 }, 1300 }, 1301 }; 1302 1303 static struct clk_rcg gsbi12_qup_src = { 1304 .ns_reg = 0x2b2c, 1305 .md_reg = 0x2b28, 1306 .mn = { 1307 .mnctr_en_bit = 8, 1308 .mnctr_reset_bit = 7, 1309 .mnctr_mode_shift = 5, 1310 .n_val_shift = 16, 1311 .m_val_shift = 16, 1312 .width = 8, 1313 }, 1314 .p = { 1315 .pre_div_shift = 3, 1316 .pre_div_width = 2, 1317 }, 1318 .s = { 1319 .src_sel_shift = 0, 1320 .parent_map = gcc_pxo_pll8_map, 1321 }, 1322 .freq_tbl = clk_tbl_gsbi_qup, 1323 .clkr = { 1324 .enable_reg = 0x2b2c, 1325 .enable_mask = BIT(11), 1326 .hw.init = &(struct clk_init_data){ 1327 .name = "gsbi12_qup_src", 1328 .parent_names = gcc_pxo_pll8, 1329 .num_parents = 2, 1330 .ops = &clk_rcg_ops, 1331 .flags = CLK_SET_PARENT_GATE, 1332 }, 1333 }, 1334 }; 1335 1336 static struct clk_branch gsbi12_qup_clk = { 1337 .halt_reg = 0x2fd4, 1338 .halt_bit = 11, 1339 .clkr = { 1340 .enable_reg = 0x2b2c, 1341 .enable_mask = BIT(9), 1342 .hw.init = &(struct clk_init_data){ 1343 .name = "gsbi12_qup_clk", 1344 .parent_names = (const char *[]){ "gsbi12_qup_src" }, 1345 .num_parents = 1, 1346 .ops = &clk_branch_ops, 1347 .flags = CLK_SET_RATE_PARENT, 1348 }, 1349 }, 1350 }; 1351 1352 static const struct freq_tbl clk_tbl_gp[] = { 1353 { 9600000, P_CXO, 2, 0, 0 }, 1354 { 13500000, P_PXO, 2, 0, 0 }, 1355 { 19200000, P_CXO, 1, 0, 0 }, 1356 { 27000000, P_PXO, 1, 0, 0 }, 1357 { 64000000, P_PLL8, 2, 1, 3 }, 1358 { 76800000, P_PLL8, 1, 1, 5 }, 1359 { 96000000, P_PLL8, 4, 0, 0 }, 1360 { 128000000, P_PLL8, 3, 0, 0 }, 1361 { 192000000, P_PLL8, 2, 0, 0 }, 1362 { } 1363 }; 1364 1365 static struct clk_rcg gp0_src = { 1366 .ns_reg = 0x2d24, 1367 .md_reg = 0x2d00, 1368 .mn = { 1369 .mnctr_en_bit = 8, 1370 .mnctr_reset_bit = 7, 1371 .mnctr_mode_shift = 5, 1372 .n_val_shift = 16, 1373 .m_val_shift = 16, 1374 .width = 8, 1375 }, 1376 .p = { 1377 .pre_div_shift = 3, 1378 .pre_div_width = 2, 1379 }, 1380 .s = { 1381 .src_sel_shift = 0, 1382 .parent_map = gcc_pxo_pll8_cxo_map, 1383 }, 1384 .freq_tbl = clk_tbl_gp, 1385 .clkr = { 1386 .enable_reg = 0x2d24, 1387 .enable_mask = BIT(11), 1388 .hw.init = &(struct clk_init_data){ 1389 .name = "gp0_src", 1390 .parent_names = gcc_pxo_pll8_cxo, 1391 .num_parents = 3, 1392 .ops = &clk_rcg_ops, 1393 .flags = CLK_SET_PARENT_GATE, 1394 }, 1395 } 1396 }; 1397 1398 static struct clk_branch gp0_clk = { 1399 .halt_reg = 0x2fd8, 1400 .halt_bit = 7, 1401 .clkr = { 1402 .enable_reg = 0x2d24, 1403 .enable_mask = BIT(9), 1404 .hw.init = &(struct clk_init_data){ 1405 .name = "gp0_clk", 1406 .parent_names = (const char *[]){ "gp0_src" }, 1407 .num_parents = 1, 1408 .ops = &clk_branch_ops, 1409 .flags = CLK_SET_RATE_PARENT, 1410 }, 1411 }, 1412 }; 1413 1414 static struct clk_rcg gp1_src = { 1415 .ns_reg = 0x2d44, 1416 .md_reg = 0x2d40, 1417 .mn = { 1418 .mnctr_en_bit = 8, 1419 .mnctr_reset_bit = 7, 1420 .mnctr_mode_shift = 5, 1421 .n_val_shift = 16, 1422 .m_val_shift = 16, 1423 .width = 8, 1424 }, 1425 .p = { 1426 .pre_div_shift = 3, 1427 .pre_div_width = 2, 1428 }, 1429 .s = { 1430 .src_sel_shift = 0, 1431 .parent_map = gcc_pxo_pll8_cxo_map, 1432 }, 1433 .freq_tbl = clk_tbl_gp, 1434 .clkr = { 1435 .enable_reg = 0x2d44, 1436 .enable_mask = BIT(11), 1437 .hw.init = &(struct clk_init_data){ 1438 .name = "gp1_src", 1439 .parent_names = gcc_pxo_pll8_cxo, 1440 .num_parents = 3, 1441 .ops = &clk_rcg_ops, 1442 .flags = CLK_SET_RATE_GATE, 1443 }, 1444 } 1445 }; 1446 1447 static struct clk_branch gp1_clk = { 1448 .halt_reg = 0x2fd8, 1449 .halt_bit = 6, 1450 .clkr = { 1451 .enable_reg = 0x2d44, 1452 .enable_mask = BIT(9), 1453 .hw.init = &(struct clk_init_data){ 1454 .name = "gp1_clk", 1455 .parent_names = (const char *[]){ "gp1_src" }, 1456 .num_parents = 1, 1457 .ops = &clk_branch_ops, 1458 .flags = CLK_SET_RATE_PARENT, 1459 }, 1460 }, 1461 }; 1462 1463 static struct clk_rcg gp2_src = { 1464 .ns_reg = 0x2d64, 1465 .md_reg = 0x2d60, 1466 .mn = { 1467 .mnctr_en_bit = 8, 1468 .mnctr_reset_bit = 7, 1469 .mnctr_mode_shift = 5, 1470 .n_val_shift = 16, 1471 .m_val_shift = 16, 1472 .width = 8, 1473 }, 1474 .p = { 1475 .pre_div_shift = 3, 1476 .pre_div_width = 2, 1477 }, 1478 .s = { 1479 .src_sel_shift = 0, 1480 .parent_map = gcc_pxo_pll8_cxo_map, 1481 }, 1482 .freq_tbl = clk_tbl_gp, 1483 .clkr = { 1484 .enable_reg = 0x2d64, 1485 .enable_mask = BIT(11), 1486 .hw.init = &(struct clk_init_data){ 1487 .name = "gp2_src", 1488 .parent_names = gcc_pxo_pll8_cxo, 1489 .num_parents = 3, 1490 .ops = &clk_rcg_ops, 1491 .flags = CLK_SET_RATE_GATE, 1492 }, 1493 } 1494 }; 1495 1496 static struct clk_branch gp2_clk = { 1497 .halt_reg = 0x2fd8, 1498 .halt_bit = 5, 1499 .clkr = { 1500 .enable_reg = 0x2d64, 1501 .enable_mask = BIT(9), 1502 .hw.init = &(struct clk_init_data){ 1503 .name = "gp2_clk", 1504 .parent_names = (const char *[]){ "gp2_src" }, 1505 .num_parents = 1, 1506 .ops = &clk_branch_ops, 1507 .flags = CLK_SET_RATE_PARENT, 1508 }, 1509 }, 1510 }; 1511 1512 static struct clk_branch pmem_clk = { 1513 .hwcg_reg = 0x25a0, 1514 .hwcg_bit = 6, 1515 .halt_reg = 0x2fc8, 1516 .halt_bit = 20, 1517 .clkr = { 1518 .enable_reg = 0x25a0, 1519 .enable_mask = BIT(4), 1520 .hw.init = &(struct clk_init_data){ 1521 .name = "pmem_clk", 1522 .ops = &clk_branch_ops, 1523 .flags = CLK_IS_ROOT, 1524 }, 1525 }, 1526 }; 1527 1528 static struct clk_rcg prng_src = { 1529 .ns_reg = 0x2e80, 1530 .p = { 1531 .pre_div_shift = 3, 1532 .pre_div_width = 4, 1533 }, 1534 .s = { 1535 .src_sel_shift = 0, 1536 .parent_map = gcc_pxo_pll8_map, 1537 }, 1538 .clkr = { 1539 .hw.init = &(struct clk_init_data){ 1540 .name = "prng_src", 1541 .parent_names = gcc_pxo_pll8, 1542 .num_parents = 2, 1543 .ops = &clk_rcg_ops, 1544 }, 1545 }, 1546 }; 1547 1548 static struct clk_branch prng_clk = { 1549 .halt_reg = 0x2fd8, 1550 .halt_check = BRANCH_HALT_VOTED, 1551 .halt_bit = 10, 1552 .clkr = { 1553 .enable_reg = 0x3080, 1554 .enable_mask = BIT(10), 1555 .hw.init = &(struct clk_init_data){ 1556 .name = "prng_clk", 1557 .parent_names = (const char *[]){ "prng_src" }, 1558 .num_parents = 1, 1559 .ops = &clk_branch_ops, 1560 }, 1561 }, 1562 }; 1563 1564 static const struct freq_tbl clk_tbl_sdc[] = { 1565 { 144000, P_PXO, 3, 2, 125 }, 1566 { 400000, P_PLL8, 4, 1, 240 }, 1567 { 16000000, P_PLL8, 4, 1, 6 }, 1568 { 17070000, P_PLL8, 1, 2, 45 }, 1569 { 20210000, P_PLL8, 1, 1, 19 }, 1570 { 24000000, P_PLL8, 4, 1, 4 }, 1571 { 48000000, P_PLL8, 4, 1, 2 }, 1572 { 64000000, P_PLL8, 3, 1, 2 }, 1573 { 96000000, P_PLL8, 4, 0, 0 }, 1574 { 192000000, P_PLL8, 2, 0, 0 }, 1575 { } 1576 }; 1577 1578 static struct clk_rcg sdc1_src = { 1579 .ns_reg = 0x282c, 1580 .md_reg = 0x2828, 1581 .mn = { 1582 .mnctr_en_bit = 8, 1583 .mnctr_reset_bit = 7, 1584 .mnctr_mode_shift = 5, 1585 .n_val_shift = 16, 1586 .m_val_shift = 16, 1587 .width = 8, 1588 }, 1589 .p = { 1590 .pre_div_shift = 3, 1591 .pre_div_width = 2, 1592 }, 1593 .s = { 1594 .src_sel_shift = 0, 1595 .parent_map = gcc_pxo_pll8_map, 1596 }, 1597 .freq_tbl = clk_tbl_sdc, 1598 .clkr = { 1599 .enable_reg = 0x282c, 1600 .enable_mask = BIT(11), 1601 .hw.init = &(struct clk_init_data){ 1602 .name = "sdc1_src", 1603 .parent_names = gcc_pxo_pll8, 1604 .num_parents = 2, 1605 .ops = &clk_rcg_ops, 1606 .flags = CLK_SET_RATE_GATE, 1607 }, 1608 } 1609 }; 1610 1611 static struct clk_branch sdc1_clk = { 1612 .halt_reg = 0x2fc8, 1613 .halt_bit = 6, 1614 .clkr = { 1615 .enable_reg = 0x282c, 1616 .enable_mask = BIT(9), 1617 .hw.init = &(struct clk_init_data){ 1618 .name = "sdc1_clk", 1619 .parent_names = (const char *[]){ "sdc1_src" }, 1620 .num_parents = 1, 1621 .ops = &clk_branch_ops, 1622 .flags = CLK_SET_RATE_PARENT, 1623 }, 1624 }, 1625 }; 1626 1627 static struct clk_rcg sdc2_src = { 1628 .ns_reg = 0x284c, 1629 .md_reg = 0x2848, 1630 .mn = { 1631 .mnctr_en_bit = 8, 1632 .mnctr_reset_bit = 7, 1633 .mnctr_mode_shift = 5, 1634 .n_val_shift = 16, 1635 .m_val_shift = 16, 1636 .width = 8, 1637 }, 1638 .p = { 1639 .pre_div_shift = 3, 1640 .pre_div_width = 2, 1641 }, 1642 .s = { 1643 .src_sel_shift = 0, 1644 .parent_map = gcc_pxo_pll8_map, 1645 }, 1646 .freq_tbl = clk_tbl_sdc, 1647 .clkr = { 1648 .enable_reg = 0x284c, 1649 .enable_mask = BIT(11), 1650 .hw.init = &(struct clk_init_data){ 1651 .name = "sdc2_src", 1652 .parent_names = gcc_pxo_pll8, 1653 .num_parents = 2, 1654 .ops = &clk_rcg_ops, 1655 .flags = CLK_SET_RATE_GATE, 1656 }, 1657 } 1658 }; 1659 1660 static struct clk_branch sdc2_clk = { 1661 .halt_reg = 0x2fc8, 1662 .halt_bit = 5, 1663 .clkr = { 1664 .enable_reg = 0x284c, 1665 .enable_mask = BIT(9), 1666 .hw.init = &(struct clk_init_data){ 1667 .name = "sdc2_clk", 1668 .parent_names = (const char *[]){ "sdc2_src" }, 1669 .num_parents = 1, 1670 .ops = &clk_branch_ops, 1671 .flags = CLK_SET_RATE_PARENT, 1672 }, 1673 }, 1674 }; 1675 1676 static struct clk_rcg sdc3_src = { 1677 .ns_reg = 0x286c, 1678 .md_reg = 0x2868, 1679 .mn = { 1680 .mnctr_en_bit = 8, 1681 .mnctr_reset_bit = 7, 1682 .mnctr_mode_shift = 5, 1683 .n_val_shift = 16, 1684 .m_val_shift = 16, 1685 .width = 8, 1686 }, 1687 .p = { 1688 .pre_div_shift = 3, 1689 .pre_div_width = 2, 1690 }, 1691 .s = { 1692 .src_sel_shift = 0, 1693 .parent_map = gcc_pxo_pll8_map, 1694 }, 1695 .freq_tbl = clk_tbl_sdc, 1696 .clkr = { 1697 .enable_reg = 0x286c, 1698 .enable_mask = BIT(11), 1699 .hw.init = &(struct clk_init_data){ 1700 .name = "sdc3_src", 1701 .parent_names = gcc_pxo_pll8, 1702 .num_parents = 2, 1703 .ops = &clk_rcg_ops, 1704 .flags = CLK_SET_RATE_GATE, 1705 }, 1706 } 1707 }; 1708 1709 static struct clk_branch sdc3_clk = { 1710 .halt_reg = 0x2fc8, 1711 .halt_bit = 4, 1712 .clkr = { 1713 .enable_reg = 0x286c, 1714 .enable_mask = BIT(9), 1715 .hw.init = &(struct clk_init_data){ 1716 .name = "sdc3_clk", 1717 .parent_names = (const char *[]){ "sdc3_src" }, 1718 .num_parents = 1, 1719 .ops = &clk_branch_ops, 1720 .flags = CLK_SET_RATE_PARENT, 1721 }, 1722 }, 1723 }; 1724 1725 static struct clk_rcg sdc4_src = { 1726 .ns_reg = 0x288c, 1727 .md_reg = 0x2888, 1728 .mn = { 1729 .mnctr_en_bit = 8, 1730 .mnctr_reset_bit = 7, 1731 .mnctr_mode_shift = 5, 1732 .n_val_shift = 16, 1733 .m_val_shift = 16, 1734 .width = 8, 1735 }, 1736 .p = { 1737 .pre_div_shift = 3, 1738 .pre_div_width = 2, 1739 }, 1740 .s = { 1741 .src_sel_shift = 0, 1742 .parent_map = gcc_pxo_pll8_map, 1743 }, 1744 .freq_tbl = clk_tbl_sdc, 1745 .clkr = { 1746 .enable_reg = 0x288c, 1747 .enable_mask = BIT(11), 1748 .hw.init = &(struct clk_init_data){ 1749 .name = "sdc4_src", 1750 .parent_names = gcc_pxo_pll8, 1751 .num_parents = 2, 1752 .ops = &clk_rcg_ops, 1753 .flags = CLK_SET_RATE_GATE, 1754 }, 1755 } 1756 }; 1757 1758 static struct clk_branch sdc4_clk = { 1759 .halt_reg = 0x2fc8, 1760 .halt_bit = 3, 1761 .clkr = { 1762 .enable_reg = 0x288c, 1763 .enable_mask = BIT(9), 1764 .hw.init = &(struct clk_init_data){ 1765 .name = "sdc4_clk", 1766 .parent_names = (const char *[]){ "sdc4_src" }, 1767 .num_parents = 1, 1768 .ops = &clk_branch_ops, 1769 .flags = CLK_SET_RATE_PARENT, 1770 }, 1771 }, 1772 }; 1773 1774 static struct clk_rcg sdc5_src = { 1775 .ns_reg = 0x28ac, 1776 .md_reg = 0x28a8, 1777 .mn = { 1778 .mnctr_en_bit = 8, 1779 .mnctr_reset_bit = 7, 1780 .mnctr_mode_shift = 5, 1781 .n_val_shift = 16, 1782 .m_val_shift = 16, 1783 .width = 8, 1784 }, 1785 .p = { 1786 .pre_div_shift = 3, 1787 .pre_div_width = 2, 1788 }, 1789 .s = { 1790 .src_sel_shift = 0, 1791 .parent_map = gcc_pxo_pll8_map, 1792 }, 1793 .freq_tbl = clk_tbl_sdc, 1794 .clkr = { 1795 .enable_reg = 0x28ac, 1796 .enable_mask = BIT(11), 1797 .hw.init = &(struct clk_init_data){ 1798 .name = "sdc5_src", 1799 .parent_names = gcc_pxo_pll8, 1800 .num_parents = 2, 1801 .ops = &clk_rcg_ops, 1802 .flags = CLK_SET_RATE_GATE, 1803 }, 1804 } 1805 }; 1806 1807 static struct clk_branch sdc5_clk = { 1808 .halt_reg = 0x2fc8, 1809 .halt_bit = 2, 1810 .clkr = { 1811 .enable_reg = 0x28ac, 1812 .enable_mask = BIT(9), 1813 .hw.init = &(struct clk_init_data){ 1814 .name = "sdc5_clk", 1815 .parent_names = (const char *[]){ "sdc5_src" }, 1816 .num_parents = 1, 1817 .ops = &clk_branch_ops, 1818 .flags = CLK_SET_RATE_PARENT, 1819 }, 1820 }, 1821 }; 1822 1823 static const struct freq_tbl clk_tbl_tsif_ref[] = { 1824 { 105000, P_PXO, 1, 1, 256 }, 1825 { } 1826 }; 1827 1828 static struct clk_rcg tsif_ref_src = { 1829 .ns_reg = 0x2710, 1830 .md_reg = 0x270c, 1831 .mn = { 1832 .mnctr_en_bit = 8, 1833 .mnctr_reset_bit = 7, 1834 .mnctr_mode_shift = 5, 1835 .n_val_shift = 16, 1836 .m_val_shift = 16, 1837 .width = 16, 1838 }, 1839 .p = { 1840 .pre_div_shift = 3, 1841 .pre_div_width = 2, 1842 }, 1843 .s = { 1844 .src_sel_shift = 0, 1845 .parent_map = gcc_pxo_pll8_map, 1846 }, 1847 .freq_tbl = clk_tbl_tsif_ref, 1848 .clkr = { 1849 .enable_reg = 0x2710, 1850 .enable_mask = BIT(11), 1851 .hw.init = &(struct clk_init_data){ 1852 .name = "tsif_ref_src", 1853 .parent_names = gcc_pxo_pll8, 1854 .num_parents = 2, 1855 .ops = &clk_rcg_ops, 1856 .flags = CLK_SET_RATE_GATE, 1857 }, 1858 } 1859 }; 1860 1861 static struct clk_branch tsif_ref_clk = { 1862 .halt_reg = 0x2fd4, 1863 .halt_bit = 5, 1864 .clkr = { 1865 .enable_reg = 0x2710, 1866 .enable_mask = BIT(9), 1867 .hw.init = &(struct clk_init_data){ 1868 .name = "tsif_ref_clk", 1869 .parent_names = (const char *[]){ "tsif_ref_src" }, 1870 .num_parents = 1, 1871 .ops = &clk_branch_ops, 1872 .flags = CLK_SET_RATE_PARENT, 1873 }, 1874 }, 1875 }; 1876 1877 static const struct freq_tbl clk_tbl_usb[] = { 1878 { 60000000, P_PLL8, 1, 5, 32 }, 1879 { } 1880 }; 1881 1882 static struct clk_rcg usb_hs1_xcvr_src = { 1883 .ns_reg = 0x290c, 1884 .md_reg = 0x2908, 1885 .mn = { 1886 .mnctr_en_bit = 8, 1887 .mnctr_reset_bit = 7, 1888 .mnctr_mode_shift = 5, 1889 .n_val_shift = 16, 1890 .m_val_shift = 16, 1891 .width = 8, 1892 }, 1893 .p = { 1894 .pre_div_shift = 3, 1895 .pre_div_width = 2, 1896 }, 1897 .s = { 1898 .src_sel_shift = 0, 1899 .parent_map = gcc_pxo_pll8_map, 1900 }, 1901 .freq_tbl = clk_tbl_usb, 1902 .clkr = { 1903 .enable_reg = 0x290c, 1904 .enable_mask = BIT(11), 1905 .hw.init = &(struct clk_init_data){ 1906 .name = "usb_hs1_xcvr_src", 1907 .parent_names = gcc_pxo_pll8, 1908 .num_parents = 2, 1909 .ops = &clk_rcg_ops, 1910 .flags = CLK_SET_RATE_GATE, 1911 }, 1912 } 1913 }; 1914 1915 static struct clk_branch usb_hs1_xcvr_clk = { 1916 .halt_reg = 0x2fc8, 1917 .halt_bit = 0, 1918 .clkr = { 1919 .enable_reg = 0x290c, 1920 .enable_mask = BIT(9), 1921 .hw.init = &(struct clk_init_data){ 1922 .name = "usb_hs1_xcvr_clk", 1923 .parent_names = (const char *[]){ "usb_hs1_xcvr_src" }, 1924 .num_parents = 1, 1925 .ops = &clk_branch_ops, 1926 .flags = CLK_SET_RATE_PARENT, 1927 }, 1928 }, 1929 }; 1930 1931 static struct clk_rcg usb_hsic_xcvr_fs_src = { 1932 .ns_reg = 0x2928, 1933 .md_reg = 0x2924, 1934 .mn = { 1935 .mnctr_en_bit = 8, 1936 .mnctr_reset_bit = 7, 1937 .mnctr_mode_shift = 5, 1938 .n_val_shift = 16, 1939 .m_val_shift = 16, 1940 .width = 8, 1941 }, 1942 .p = { 1943 .pre_div_shift = 3, 1944 .pre_div_width = 2, 1945 }, 1946 .s = { 1947 .src_sel_shift = 0, 1948 .parent_map = gcc_pxo_pll8_map, 1949 }, 1950 .freq_tbl = clk_tbl_usb, 1951 .clkr = { 1952 .enable_reg = 0x2928, 1953 .enable_mask = BIT(11), 1954 .hw.init = &(struct clk_init_data){ 1955 .name = "usb_hsic_xcvr_fs_src", 1956 .parent_names = gcc_pxo_pll8, 1957 .num_parents = 2, 1958 .ops = &clk_rcg_ops, 1959 .flags = CLK_SET_RATE_GATE, 1960 }, 1961 } 1962 }; 1963 1964 static const char *usb_hsic_xcvr_fs_src_p[] = { "usb_hsic_xcvr_fs_src" }; 1965 1966 static struct clk_branch usb_hsic_xcvr_fs_clk = { 1967 .halt_reg = 0x2fc8, 1968 .halt_bit = 2, 1969 .clkr = { 1970 .enable_reg = 0x2928, 1971 .enable_mask = BIT(9), 1972 .hw.init = &(struct clk_init_data){ 1973 .name = "usb_hsic_xcvr_fs_clk", 1974 .parent_names = usb_hsic_xcvr_fs_src_p, 1975 .num_parents = 1, 1976 .ops = &clk_branch_ops, 1977 .flags = CLK_SET_RATE_PARENT, 1978 }, 1979 }, 1980 }; 1981 1982 static struct clk_branch usb_hsic_system_clk = { 1983 .halt_reg = 0x2fcc, 1984 .halt_bit = 24, 1985 .clkr = { 1986 .enable_reg = 0x292c, 1987 .enable_mask = BIT(4), 1988 .hw.init = &(struct clk_init_data){ 1989 .parent_names = usb_hsic_xcvr_fs_src_p, 1990 .num_parents = 1, 1991 .name = "usb_hsic_system_clk", 1992 .ops = &clk_branch_ops, 1993 .flags = CLK_SET_RATE_PARENT, 1994 }, 1995 }, 1996 }; 1997 1998 static struct clk_branch usb_hsic_hsic_clk = { 1999 .halt_reg = 0x2fcc, 2000 .halt_bit = 19, 2001 .clkr = { 2002 .enable_reg = 0x2b44, 2003 .enable_mask = BIT(0), 2004 .hw.init = &(struct clk_init_data){ 2005 .parent_names = (const char *[]){ "pll14_vote" }, 2006 .num_parents = 1, 2007 .name = "usb_hsic_hsic_clk", 2008 .ops = &clk_branch_ops, 2009 }, 2010 }, 2011 }; 2012 2013 static struct clk_branch usb_hsic_hsio_cal_clk = { 2014 .halt_reg = 0x2fcc, 2015 .halt_bit = 23, 2016 .clkr = { 2017 .enable_reg = 0x2b48, 2018 .enable_mask = BIT(0), 2019 .hw.init = &(struct clk_init_data){ 2020 .name = "usb_hsic_hsio_cal_clk", 2021 .ops = &clk_branch_ops, 2022 .flags = CLK_IS_ROOT, 2023 }, 2024 }, 2025 }; 2026 2027 static struct clk_rcg usb_fs1_xcvr_fs_src = { 2028 .ns_reg = 0x2968, 2029 .md_reg = 0x2964, 2030 .mn = { 2031 .mnctr_en_bit = 8, 2032 .mnctr_reset_bit = 7, 2033 .mnctr_mode_shift = 5, 2034 .n_val_shift = 16, 2035 .m_val_shift = 16, 2036 .width = 8, 2037 }, 2038 .p = { 2039 .pre_div_shift = 3, 2040 .pre_div_width = 2, 2041 }, 2042 .s = { 2043 .src_sel_shift = 0, 2044 .parent_map = gcc_pxo_pll8_map, 2045 }, 2046 .freq_tbl = clk_tbl_usb, 2047 .clkr = { 2048 .enable_reg = 0x2968, 2049 .enable_mask = BIT(11), 2050 .hw.init = &(struct clk_init_data){ 2051 .name = "usb_fs1_xcvr_fs_src", 2052 .parent_names = gcc_pxo_pll8, 2053 .num_parents = 2, 2054 .ops = &clk_rcg_ops, 2055 .flags = CLK_SET_RATE_GATE, 2056 }, 2057 } 2058 }; 2059 2060 static const char *usb_fs1_xcvr_fs_src_p[] = { "usb_fs1_xcvr_fs_src" }; 2061 2062 static struct clk_branch usb_fs1_xcvr_fs_clk = { 2063 .halt_reg = 0x2fcc, 2064 .halt_bit = 15, 2065 .clkr = { 2066 .enable_reg = 0x2968, 2067 .enable_mask = BIT(9), 2068 .hw.init = &(struct clk_init_data){ 2069 .name = "usb_fs1_xcvr_fs_clk", 2070 .parent_names = usb_fs1_xcvr_fs_src_p, 2071 .num_parents = 1, 2072 .ops = &clk_branch_ops, 2073 .flags = CLK_SET_RATE_PARENT, 2074 }, 2075 }, 2076 }; 2077 2078 static struct clk_branch usb_fs1_system_clk = { 2079 .halt_reg = 0x2fcc, 2080 .halt_bit = 16, 2081 .clkr = { 2082 .enable_reg = 0x296c, 2083 .enable_mask = BIT(4), 2084 .hw.init = &(struct clk_init_data){ 2085 .parent_names = usb_fs1_xcvr_fs_src_p, 2086 .num_parents = 1, 2087 .name = "usb_fs1_system_clk", 2088 .ops = &clk_branch_ops, 2089 .flags = CLK_SET_RATE_PARENT, 2090 }, 2091 }, 2092 }; 2093 2094 static struct clk_rcg usb_fs2_xcvr_fs_src = { 2095 .ns_reg = 0x2988, 2096 .md_reg = 0x2984, 2097 .mn = { 2098 .mnctr_en_bit = 8, 2099 .mnctr_reset_bit = 7, 2100 .mnctr_mode_shift = 5, 2101 .n_val_shift = 16, 2102 .m_val_shift = 16, 2103 .width = 8, 2104 }, 2105 .p = { 2106 .pre_div_shift = 3, 2107 .pre_div_width = 2, 2108 }, 2109 .s = { 2110 .src_sel_shift = 0, 2111 .parent_map = gcc_pxo_pll8_map, 2112 }, 2113 .freq_tbl = clk_tbl_usb, 2114 .clkr = { 2115 .enable_reg = 0x2988, 2116 .enable_mask = BIT(11), 2117 .hw.init = &(struct clk_init_data){ 2118 .name = "usb_fs2_xcvr_fs_src", 2119 .parent_names = gcc_pxo_pll8, 2120 .num_parents = 2, 2121 .ops = &clk_rcg_ops, 2122 .flags = CLK_SET_RATE_GATE, 2123 }, 2124 } 2125 }; 2126 2127 static const char *usb_fs2_xcvr_fs_src_p[] = { "usb_fs2_xcvr_fs_src" }; 2128 2129 static struct clk_branch usb_fs2_xcvr_fs_clk = { 2130 .halt_reg = 0x2fcc, 2131 .halt_bit = 12, 2132 .clkr = { 2133 .enable_reg = 0x2988, 2134 .enable_mask = BIT(9), 2135 .hw.init = &(struct clk_init_data){ 2136 .name = "usb_fs2_xcvr_fs_clk", 2137 .parent_names = usb_fs2_xcvr_fs_src_p, 2138 .num_parents = 1, 2139 .ops = &clk_branch_ops, 2140 .flags = CLK_SET_RATE_PARENT, 2141 }, 2142 }, 2143 }; 2144 2145 static struct clk_branch usb_fs2_system_clk = { 2146 .halt_reg = 0x2fcc, 2147 .halt_bit = 13, 2148 .clkr = { 2149 .enable_reg = 0x298c, 2150 .enable_mask = BIT(4), 2151 .hw.init = &(struct clk_init_data){ 2152 .name = "usb_fs2_system_clk", 2153 .parent_names = usb_fs2_xcvr_fs_src_p, 2154 .num_parents = 1, 2155 .ops = &clk_branch_ops, 2156 .flags = CLK_SET_RATE_PARENT, 2157 }, 2158 }, 2159 }; 2160 2161 static struct clk_branch ce1_core_clk = { 2162 .hwcg_reg = 0x2724, 2163 .hwcg_bit = 6, 2164 .halt_reg = 0x2fd4, 2165 .halt_bit = 27, 2166 .clkr = { 2167 .enable_reg = 0x2724, 2168 .enable_mask = BIT(4), 2169 .hw.init = &(struct clk_init_data){ 2170 .name = "ce1_core_clk", 2171 .ops = &clk_branch_ops, 2172 .flags = CLK_IS_ROOT, 2173 }, 2174 }, 2175 }; 2176 2177 static struct clk_branch ce1_h_clk = { 2178 .halt_reg = 0x2fd4, 2179 .halt_bit = 1, 2180 .clkr = { 2181 .enable_reg = 0x2720, 2182 .enable_mask = BIT(4), 2183 .hw.init = &(struct clk_init_data){ 2184 .name = "ce1_h_clk", 2185 .ops = &clk_branch_ops, 2186 .flags = CLK_IS_ROOT, 2187 }, 2188 }, 2189 }; 2190 2191 static struct clk_branch dma_bam_h_clk = { 2192 .hwcg_reg = 0x25c0, 2193 .hwcg_bit = 6, 2194 .halt_reg = 0x2fc8, 2195 .halt_bit = 12, 2196 .clkr = { 2197 .enable_reg = 0x25c0, 2198 .enable_mask = BIT(4), 2199 .hw.init = &(struct clk_init_data){ 2200 .name = "dma_bam_h_clk", 2201 .ops = &clk_branch_ops, 2202 .flags = CLK_IS_ROOT, 2203 }, 2204 }, 2205 }; 2206 2207 static struct clk_branch gsbi1_h_clk = { 2208 .hwcg_reg = 0x29c0, 2209 .hwcg_bit = 6, 2210 .halt_reg = 0x2fcc, 2211 .halt_bit = 11, 2212 .clkr = { 2213 .enable_reg = 0x29c0, 2214 .enable_mask = BIT(4), 2215 .hw.init = &(struct clk_init_data){ 2216 .name = "gsbi1_h_clk", 2217 .ops = &clk_branch_ops, 2218 .flags = CLK_IS_ROOT, 2219 }, 2220 }, 2221 }; 2222 2223 static struct clk_branch gsbi2_h_clk = { 2224 .hwcg_reg = 0x29e0, 2225 .hwcg_bit = 6, 2226 .halt_reg = 0x2fcc, 2227 .halt_bit = 7, 2228 .clkr = { 2229 .enable_reg = 0x29e0, 2230 .enable_mask = BIT(4), 2231 .hw.init = &(struct clk_init_data){ 2232 .name = "gsbi2_h_clk", 2233 .ops = &clk_branch_ops, 2234 .flags = CLK_IS_ROOT, 2235 }, 2236 }, 2237 }; 2238 2239 static struct clk_branch gsbi3_h_clk = { 2240 .hwcg_reg = 0x2a00, 2241 .hwcg_bit = 6, 2242 .halt_reg = 0x2fcc, 2243 .halt_bit = 3, 2244 .clkr = { 2245 .enable_reg = 0x2a00, 2246 .enable_mask = BIT(4), 2247 .hw.init = &(struct clk_init_data){ 2248 .name = "gsbi3_h_clk", 2249 .ops = &clk_branch_ops, 2250 .flags = CLK_IS_ROOT, 2251 }, 2252 }, 2253 }; 2254 2255 static struct clk_branch gsbi4_h_clk = { 2256 .hwcg_reg = 0x2a20, 2257 .hwcg_bit = 6, 2258 .halt_reg = 0x2fd0, 2259 .halt_bit = 27, 2260 .clkr = { 2261 .enable_reg = 0x2a20, 2262 .enable_mask = BIT(4), 2263 .hw.init = &(struct clk_init_data){ 2264 .name = "gsbi4_h_clk", 2265 .ops = &clk_branch_ops, 2266 .flags = CLK_IS_ROOT, 2267 }, 2268 }, 2269 }; 2270 2271 static struct clk_branch gsbi5_h_clk = { 2272 .hwcg_reg = 0x2a40, 2273 .hwcg_bit = 6, 2274 .halt_reg = 0x2fd0, 2275 .halt_bit = 23, 2276 .clkr = { 2277 .enable_reg = 0x2a40, 2278 .enable_mask = BIT(4), 2279 .hw.init = &(struct clk_init_data){ 2280 .name = "gsbi5_h_clk", 2281 .ops = &clk_branch_ops, 2282 .flags = CLK_IS_ROOT, 2283 }, 2284 }, 2285 }; 2286 2287 static struct clk_branch gsbi6_h_clk = { 2288 .hwcg_reg = 0x2a60, 2289 .hwcg_bit = 6, 2290 .halt_reg = 0x2fd0, 2291 .halt_bit = 19, 2292 .clkr = { 2293 .enable_reg = 0x2a60, 2294 .enable_mask = BIT(4), 2295 .hw.init = &(struct clk_init_data){ 2296 .name = "gsbi6_h_clk", 2297 .ops = &clk_branch_ops, 2298 .flags = CLK_IS_ROOT, 2299 }, 2300 }, 2301 }; 2302 2303 static struct clk_branch gsbi7_h_clk = { 2304 .hwcg_reg = 0x2a80, 2305 .hwcg_bit = 6, 2306 .halt_reg = 0x2fd0, 2307 .halt_bit = 15, 2308 .clkr = { 2309 .enable_reg = 0x2a80, 2310 .enable_mask = BIT(4), 2311 .hw.init = &(struct clk_init_data){ 2312 .name = "gsbi7_h_clk", 2313 .ops = &clk_branch_ops, 2314 .flags = CLK_IS_ROOT, 2315 }, 2316 }, 2317 }; 2318 2319 static struct clk_branch gsbi8_h_clk = { 2320 .hwcg_reg = 0x2aa0, 2321 .hwcg_bit = 6, 2322 .halt_reg = 0x2fd0, 2323 .halt_bit = 11, 2324 .clkr = { 2325 .enable_reg = 0x2aa0, 2326 .enable_mask = BIT(4), 2327 .hw.init = &(struct clk_init_data){ 2328 .name = "gsbi8_h_clk", 2329 .ops = &clk_branch_ops, 2330 .flags = CLK_IS_ROOT, 2331 }, 2332 }, 2333 }; 2334 2335 static struct clk_branch gsbi9_h_clk = { 2336 .hwcg_reg = 0x2ac0, 2337 .hwcg_bit = 6, 2338 .halt_reg = 0x2fd0, 2339 .halt_bit = 7, 2340 .clkr = { 2341 .enable_reg = 0x2ac0, 2342 .enable_mask = BIT(4), 2343 .hw.init = &(struct clk_init_data){ 2344 .name = "gsbi9_h_clk", 2345 .ops = &clk_branch_ops, 2346 .flags = CLK_IS_ROOT, 2347 }, 2348 }, 2349 }; 2350 2351 static struct clk_branch gsbi10_h_clk = { 2352 .hwcg_reg = 0x2ae0, 2353 .hwcg_bit = 6, 2354 .halt_reg = 0x2fd0, 2355 .halt_bit = 3, 2356 .clkr = { 2357 .enable_reg = 0x2ae0, 2358 .enable_mask = BIT(4), 2359 .hw.init = &(struct clk_init_data){ 2360 .name = "gsbi10_h_clk", 2361 .ops = &clk_branch_ops, 2362 .flags = CLK_IS_ROOT, 2363 }, 2364 }, 2365 }; 2366 2367 static struct clk_branch gsbi11_h_clk = { 2368 .hwcg_reg = 0x2b00, 2369 .hwcg_bit = 6, 2370 .halt_reg = 0x2fd4, 2371 .halt_bit = 18, 2372 .clkr = { 2373 .enable_reg = 0x2b00, 2374 .enable_mask = BIT(4), 2375 .hw.init = &(struct clk_init_data){ 2376 .name = "gsbi11_h_clk", 2377 .ops = &clk_branch_ops, 2378 .flags = CLK_IS_ROOT, 2379 }, 2380 }, 2381 }; 2382 2383 static struct clk_branch gsbi12_h_clk = { 2384 .hwcg_reg = 0x2b20, 2385 .hwcg_bit = 6, 2386 .halt_reg = 0x2fd4, 2387 .halt_bit = 14, 2388 .clkr = { 2389 .enable_reg = 0x2b20, 2390 .enable_mask = BIT(4), 2391 .hw.init = &(struct clk_init_data){ 2392 .name = "gsbi12_h_clk", 2393 .ops = &clk_branch_ops, 2394 .flags = CLK_IS_ROOT, 2395 }, 2396 }, 2397 }; 2398 2399 static struct clk_branch tsif_h_clk = { 2400 .hwcg_reg = 0x2700, 2401 .hwcg_bit = 6, 2402 .halt_reg = 0x2fd4, 2403 .halt_bit = 7, 2404 .clkr = { 2405 .enable_reg = 0x2700, 2406 .enable_mask = BIT(4), 2407 .hw.init = &(struct clk_init_data){ 2408 .name = "tsif_h_clk", 2409 .ops = &clk_branch_ops, 2410 .flags = CLK_IS_ROOT, 2411 }, 2412 }, 2413 }; 2414 2415 static struct clk_branch usb_fs1_h_clk = { 2416 .halt_reg = 0x2fcc, 2417 .halt_bit = 17, 2418 .clkr = { 2419 .enable_reg = 0x2960, 2420 .enable_mask = BIT(4), 2421 .hw.init = &(struct clk_init_data){ 2422 .name = "usb_fs1_h_clk", 2423 .ops = &clk_branch_ops, 2424 .flags = CLK_IS_ROOT, 2425 }, 2426 }, 2427 }; 2428 2429 static struct clk_branch usb_fs2_h_clk = { 2430 .halt_reg = 0x2fcc, 2431 .halt_bit = 14, 2432 .clkr = { 2433 .enable_reg = 0x2980, 2434 .enable_mask = BIT(4), 2435 .hw.init = &(struct clk_init_data){ 2436 .name = "usb_fs2_h_clk", 2437 .ops = &clk_branch_ops, 2438 .flags = CLK_IS_ROOT, 2439 }, 2440 }, 2441 }; 2442 2443 static struct clk_branch usb_hs1_h_clk = { 2444 .hwcg_reg = 0x2900, 2445 .hwcg_bit = 6, 2446 .halt_reg = 0x2fc8, 2447 .halt_bit = 1, 2448 .clkr = { 2449 .enable_reg = 0x2900, 2450 .enable_mask = BIT(4), 2451 .hw.init = &(struct clk_init_data){ 2452 .name = "usb_hs1_h_clk", 2453 .ops = &clk_branch_ops, 2454 .flags = CLK_IS_ROOT, 2455 }, 2456 }, 2457 }; 2458 2459 static struct clk_branch usb_hsic_h_clk = { 2460 .halt_reg = 0x2fcc, 2461 .halt_bit = 28, 2462 .clkr = { 2463 .enable_reg = 0x2920, 2464 .enable_mask = BIT(4), 2465 .hw.init = &(struct clk_init_data){ 2466 .name = "usb_hsic_h_clk", 2467 .ops = &clk_branch_ops, 2468 .flags = CLK_IS_ROOT, 2469 }, 2470 }, 2471 }; 2472 2473 static struct clk_branch sdc1_h_clk = { 2474 .hwcg_reg = 0x2820, 2475 .hwcg_bit = 6, 2476 .halt_reg = 0x2fc8, 2477 .halt_bit = 11, 2478 .clkr = { 2479 .enable_reg = 0x2820, 2480 .enable_mask = BIT(4), 2481 .hw.init = &(struct clk_init_data){ 2482 .name = "sdc1_h_clk", 2483 .ops = &clk_branch_ops, 2484 .flags = CLK_IS_ROOT, 2485 }, 2486 }, 2487 }; 2488 2489 static struct clk_branch sdc2_h_clk = { 2490 .hwcg_reg = 0x2840, 2491 .hwcg_bit = 6, 2492 .halt_reg = 0x2fc8, 2493 .halt_bit = 10, 2494 .clkr = { 2495 .enable_reg = 0x2840, 2496 .enable_mask = BIT(4), 2497 .hw.init = &(struct clk_init_data){ 2498 .name = "sdc2_h_clk", 2499 .ops = &clk_branch_ops, 2500 .flags = CLK_IS_ROOT, 2501 }, 2502 }, 2503 }; 2504 2505 static struct clk_branch sdc3_h_clk = { 2506 .hwcg_reg = 0x2860, 2507 .hwcg_bit = 6, 2508 .halt_reg = 0x2fc8, 2509 .halt_bit = 9, 2510 .clkr = { 2511 .enable_reg = 0x2860, 2512 .enable_mask = BIT(4), 2513 .hw.init = &(struct clk_init_data){ 2514 .name = "sdc3_h_clk", 2515 .ops = &clk_branch_ops, 2516 .flags = CLK_IS_ROOT, 2517 }, 2518 }, 2519 }; 2520 2521 static struct clk_branch sdc4_h_clk = { 2522 .hwcg_reg = 0x2880, 2523 .hwcg_bit = 6, 2524 .halt_reg = 0x2fc8, 2525 .halt_bit = 8, 2526 .clkr = { 2527 .enable_reg = 0x2880, 2528 .enable_mask = BIT(4), 2529 .hw.init = &(struct clk_init_data){ 2530 .name = "sdc4_h_clk", 2531 .ops = &clk_branch_ops, 2532 .flags = CLK_IS_ROOT, 2533 }, 2534 }, 2535 }; 2536 2537 static struct clk_branch sdc5_h_clk = { 2538 .hwcg_reg = 0x28a0, 2539 .hwcg_bit = 6, 2540 .halt_reg = 0x2fc8, 2541 .halt_bit = 7, 2542 .clkr = { 2543 .enable_reg = 0x28a0, 2544 .enable_mask = BIT(4), 2545 .hw.init = &(struct clk_init_data){ 2546 .name = "sdc5_h_clk", 2547 .ops = &clk_branch_ops, 2548 .flags = CLK_IS_ROOT, 2549 }, 2550 }, 2551 }; 2552 2553 static struct clk_branch adm0_clk = { 2554 .halt_reg = 0x2fdc, 2555 .halt_check = BRANCH_HALT_VOTED, 2556 .halt_bit = 14, 2557 .clkr = { 2558 .enable_reg = 0x3080, 2559 .enable_mask = BIT(2), 2560 .hw.init = &(struct clk_init_data){ 2561 .name = "adm0_clk", 2562 .ops = &clk_branch_ops, 2563 .flags = CLK_IS_ROOT, 2564 }, 2565 }, 2566 }; 2567 2568 static struct clk_branch adm0_pbus_clk = { 2569 .hwcg_reg = 0x2208, 2570 .hwcg_bit = 6, 2571 .halt_reg = 0x2fdc, 2572 .halt_check = BRANCH_HALT_VOTED, 2573 .halt_bit = 13, 2574 .clkr = { 2575 .enable_reg = 0x3080, 2576 .enable_mask = BIT(3), 2577 .hw.init = &(struct clk_init_data){ 2578 .name = "adm0_pbus_clk", 2579 .ops = &clk_branch_ops, 2580 .flags = CLK_IS_ROOT, 2581 }, 2582 }, 2583 }; 2584 2585 static struct clk_branch pmic_arb0_h_clk = { 2586 .halt_reg = 0x2fd8, 2587 .halt_check = BRANCH_HALT_VOTED, 2588 .halt_bit = 22, 2589 .clkr = { 2590 .enable_reg = 0x3080, 2591 .enable_mask = BIT(8), 2592 .hw.init = &(struct clk_init_data){ 2593 .name = "pmic_arb0_h_clk", 2594 .ops = &clk_branch_ops, 2595 .flags = CLK_IS_ROOT, 2596 }, 2597 }, 2598 }; 2599 2600 static struct clk_branch pmic_arb1_h_clk = { 2601 .halt_reg = 0x2fd8, 2602 .halt_check = BRANCH_HALT_VOTED, 2603 .halt_bit = 21, 2604 .clkr = { 2605 .enable_reg = 0x3080, 2606 .enable_mask = BIT(9), 2607 .hw.init = &(struct clk_init_data){ 2608 .name = "pmic_arb1_h_clk", 2609 .ops = &clk_branch_ops, 2610 .flags = CLK_IS_ROOT, 2611 }, 2612 }, 2613 }; 2614 2615 static struct clk_branch pmic_ssbi2_clk = { 2616 .halt_reg = 0x2fd8, 2617 .halt_check = BRANCH_HALT_VOTED, 2618 .halt_bit = 23, 2619 .clkr = { 2620 .enable_reg = 0x3080, 2621 .enable_mask = BIT(7), 2622 .hw.init = &(struct clk_init_data){ 2623 .name = "pmic_ssbi2_clk", 2624 .ops = &clk_branch_ops, 2625 .flags = CLK_IS_ROOT, 2626 }, 2627 }, 2628 }; 2629 2630 static struct clk_branch rpm_msg_ram_h_clk = { 2631 .hwcg_reg = 0x27e0, 2632 .hwcg_bit = 6, 2633 .halt_reg = 0x2fd8, 2634 .halt_check = BRANCH_HALT_VOTED, 2635 .halt_bit = 12, 2636 .clkr = { 2637 .enable_reg = 0x3080, 2638 .enable_mask = BIT(6), 2639 .hw.init = &(struct clk_init_data){ 2640 .name = "rpm_msg_ram_h_clk", 2641 .ops = &clk_branch_ops, 2642 .flags = CLK_IS_ROOT, 2643 }, 2644 }, 2645 }; 2646 2647 static struct clk_regmap *gcc_msm8960_clks[] = { 2648 [PLL3] = &pll3.clkr, 2649 [PLL8] = &pll8.clkr, 2650 [PLL8_VOTE] = &pll8_vote, 2651 [PLL14] = &pll14.clkr, 2652 [PLL14_VOTE] = &pll14_vote, 2653 [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr, 2654 [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr, 2655 [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr, 2656 [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr, 2657 [GSBI3_UART_SRC] = &gsbi3_uart_src.clkr, 2658 [GSBI3_UART_CLK] = &gsbi3_uart_clk.clkr, 2659 [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr, 2660 [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr, 2661 [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr, 2662 [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr, 2663 [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr, 2664 [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr, 2665 [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr, 2666 [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr, 2667 [GSBI8_UART_SRC] = &gsbi8_uart_src.clkr, 2668 [GSBI8_UART_CLK] = &gsbi8_uart_clk.clkr, 2669 [GSBI9_UART_SRC] = &gsbi9_uart_src.clkr, 2670 [GSBI9_UART_CLK] = &gsbi9_uart_clk.clkr, 2671 [GSBI10_UART_SRC] = &gsbi10_uart_src.clkr, 2672 [GSBI10_UART_CLK] = &gsbi10_uart_clk.clkr, 2673 [GSBI11_UART_SRC] = &gsbi11_uart_src.clkr, 2674 [GSBI11_UART_CLK] = &gsbi11_uart_clk.clkr, 2675 [GSBI12_UART_SRC] = &gsbi12_uart_src.clkr, 2676 [GSBI12_UART_CLK] = &gsbi12_uart_clk.clkr, 2677 [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr, 2678 [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr, 2679 [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr, 2680 [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr, 2681 [GSBI3_QUP_SRC] = &gsbi3_qup_src.clkr, 2682 [GSBI3_QUP_CLK] = &gsbi3_qup_clk.clkr, 2683 [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr, 2684 [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr, 2685 [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr, 2686 [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr, 2687 [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr, 2688 [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr, 2689 [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr, 2690 [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr, 2691 [GSBI8_QUP_SRC] = &gsbi8_qup_src.clkr, 2692 [GSBI8_QUP_CLK] = &gsbi8_qup_clk.clkr, 2693 [GSBI9_QUP_SRC] = &gsbi9_qup_src.clkr, 2694 [GSBI9_QUP_CLK] = &gsbi9_qup_clk.clkr, 2695 [GSBI10_QUP_SRC] = &gsbi10_qup_src.clkr, 2696 [GSBI10_QUP_CLK] = &gsbi10_qup_clk.clkr, 2697 [GSBI11_QUP_SRC] = &gsbi11_qup_src.clkr, 2698 [GSBI11_QUP_CLK] = &gsbi11_qup_clk.clkr, 2699 [GSBI12_QUP_SRC] = &gsbi12_qup_src.clkr, 2700 [GSBI12_QUP_CLK] = &gsbi12_qup_clk.clkr, 2701 [GP0_SRC] = &gp0_src.clkr, 2702 [GP0_CLK] = &gp0_clk.clkr, 2703 [GP1_SRC] = &gp1_src.clkr, 2704 [GP1_CLK] = &gp1_clk.clkr, 2705 [GP2_SRC] = &gp2_src.clkr, 2706 [GP2_CLK] = &gp2_clk.clkr, 2707 [PMEM_A_CLK] = &pmem_clk.clkr, 2708 [PRNG_SRC] = &prng_src.clkr, 2709 [PRNG_CLK] = &prng_clk.clkr, 2710 [SDC1_SRC] = &sdc1_src.clkr, 2711 [SDC1_CLK] = &sdc1_clk.clkr, 2712 [SDC2_SRC] = &sdc2_src.clkr, 2713 [SDC2_CLK] = &sdc2_clk.clkr, 2714 [SDC3_SRC] = &sdc3_src.clkr, 2715 [SDC3_CLK] = &sdc3_clk.clkr, 2716 [SDC4_SRC] = &sdc4_src.clkr, 2717 [SDC4_CLK] = &sdc4_clk.clkr, 2718 [SDC5_SRC] = &sdc5_src.clkr, 2719 [SDC5_CLK] = &sdc5_clk.clkr, 2720 [TSIF_REF_SRC] = &tsif_ref_src.clkr, 2721 [TSIF_REF_CLK] = &tsif_ref_clk.clkr, 2722 [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_src.clkr, 2723 [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr, 2724 [USB_HSIC_XCVR_FS_SRC] = &usb_hsic_xcvr_fs_src.clkr, 2725 [USB_HSIC_XCVR_FS_CLK] = &usb_hsic_xcvr_fs_clk.clkr, 2726 [USB_HSIC_SYSTEM_CLK] = &usb_hsic_system_clk.clkr, 2727 [USB_HSIC_HSIC_CLK] = &usb_hsic_hsic_clk.clkr, 2728 [USB_HSIC_HSIO_CAL_CLK] = &usb_hsic_hsio_cal_clk.clkr, 2729 [USB_FS1_XCVR_FS_SRC] = &usb_fs1_xcvr_fs_src.clkr, 2730 [USB_FS1_XCVR_FS_CLK] = &usb_fs1_xcvr_fs_clk.clkr, 2731 [USB_FS1_SYSTEM_CLK] = &usb_fs1_system_clk.clkr, 2732 [USB_FS2_XCVR_FS_SRC] = &usb_fs2_xcvr_fs_src.clkr, 2733 [USB_FS2_XCVR_FS_CLK] = &usb_fs2_xcvr_fs_clk.clkr, 2734 [USB_FS2_SYSTEM_CLK] = &usb_fs2_system_clk.clkr, 2735 [CE1_CORE_CLK] = &ce1_core_clk.clkr, 2736 [CE1_H_CLK] = &ce1_h_clk.clkr, 2737 [DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr, 2738 [GSBI1_H_CLK] = &gsbi1_h_clk.clkr, 2739 [GSBI2_H_CLK] = &gsbi2_h_clk.clkr, 2740 [GSBI3_H_CLK] = &gsbi3_h_clk.clkr, 2741 [GSBI4_H_CLK] = &gsbi4_h_clk.clkr, 2742 [GSBI5_H_CLK] = &gsbi5_h_clk.clkr, 2743 [GSBI6_H_CLK] = &gsbi6_h_clk.clkr, 2744 [GSBI7_H_CLK] = &gsbi7_h_clk.clkr, 2745 [GSBI8_H_CLK] = &gsbi8_h_clk.clkr, 2746 [GSBI9_H_CLK] = &gsbi9_h_clk.clkr, 2747 [GSBI10_H_CLK] = &gsbi10_h_clk.clkr, 2748 [GSBI11_H_CLK] = &gsbi11_h_clk.clkr, 2749 [GSBI12_H_CLK] = &gsbi12_h_clk.clkr, 2750 [TSIF_H_CLK] = &tsif_h_clk.clkr, 2751 [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr, 2752 [USB_FS2_H_CLK] = &usb_fs2_h_clk.clkr, 2753 [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr, 2754 [USB_HSIC_H_CLK] = &usb_hsic_h_clk.clkr, 2755 [SDC1_H_CLK] = &sdc1_h_clk.clkr, 2756 [SDC2_H_CLK] = &sdc2_h_clk.clkr, 2757 [SDC3_H_CLK] = &sdc3_h_clk.clkr, 2758 [SDC4_H_CLK] = &sdc4_h_clk.clkr, 2759 [SDC5_H_CLK] = &sdc5_h_clk.clkr, 2760 [ADM0_CLK] = &adm0_clk.clkr, 2761 [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr, 2762 [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr, 2763 [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr, 2764 [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr, 2765 [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr, 2766 }; 2767 2768 static const struct qcom_reset_map gcc_msm8960_resets[] = { 2769 [SFAB_MSS_Q6_SW_RESET] = { 0x2040, 7 }, 2770 [SFAB_MSS_Q6_FW_RESET] = { 0x2044, 7 }, 2771 [QDSS_STM_RESET] = { 0x2060, 6 }, 2772 [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 }, 2773 [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 }, 2774 [AFAB_SMPSS_M0_RESET] = { 0x20b8 }, 2775 [AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 }, 2776 [AFAB_EBI1_CH1_RESET] = { 0x20c4, 7}, 2777 [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 }, 2778 [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 }, 2779 [SFAB_ADM0_M2_RESET] = { 0x21e8, 7 }, 2780 [ADM0_C2_RESET] = { 0x220c, 4}, 2781 [ADM0_C1_RESET] = { 0x220c, 3}, 2782 [ADM0_C0_RESET] = { 0x220c, 2}, 2783 [ADM0_PBUS_RESET] = { 0x220c, 1 }, 2784 [ADM0_RESET] = { 0x220c }, 2785 [QDSS_CLKS_SW_RESET] = { 0x2260, 5 }, 2786 [QDSS_POR_RESET] = { 0x2260, 4 }, 2787 [QDSS_TSCTR_RESET] = { 0x2260, 3 }, 2788 [QDSS_HRESET_RESET] = { 0x2260, 2 }, 2789 [QDSS_AXI_RESET] = { 0x2260, 1 }, 2790 [QDSS_DBG_RESET] = { 0x2260 }, 2791 [PCIE_A_RESET] = { 0x22c0, 7 }, 2792 [PCIE_AUX_RESET] = { 0x22c8, 7 }, 2793 [PCIE_H_RESET] = { 0x22d0, 7 }, 2794 [SFAB_PCIE_M_RESET] = { 0x22d4, 1 }, 2795 [SFAB_PCIE_S_RESET] = { 0x22d4 }, 2796 [SFAB_MSS_M_RESET] = { 0x2340, 7 }, 2797 [SFAB_USB3_M_RESET] = { 0x2360, 7 }, 2798 [SFAB_RIVA_M_RESET] = { 0x2380, 7 }, 2799 [SFAB_LPASS_RESET] = { 0x23a0, 7 }, 2800 [SFAB_AFAB_M_RESET] = { 0x23e0, 7 }, 2801 [AFAB_SFAB_M0_RESET] = { 0x2420, 7 }, 2802 [AFAB_SFAB_M1_RESET] = { 0x2424, 7 }, 2803 [SFAB_SATA_S_RESET] = { 0x2480, 7 }, 2804 [SFAB_DFAB_M_RESET] = { 0x2500, 7 }, 2805 [DFAB_SFAB_M_RESET] = { 0x2520, 7 }, 2806 [DFAB_SWAY0_RESET] = { 0x2540, 7 }, 2807 [DFAB_SWAY1_RESET] = { 0x2544, 7 }, 2808 [DFAB_ARB0_RESET] = { 0x2560, 7 }, 2809 [DFAB_ARB1_RESET] = { 0x2564, 7 }, 2810 [PPSS_PROC_RESET] = { 0x2594, 1 }, 2811 [PPSS_RESET] = { 0x2594}, 2812 [DMA_BAM_RESET] = { 0x25c0, 7 }, 2813 [SPS_TIC_H_RESET] = { 0x2600, 7 }, 2814 [SLIMBUS_H_RESET] = { 0x2620, 7 }, 2815 [SFAB_CFPB_M_RESET] = { 0x2680, 7 }, 2816 [SFAB_CFPB_S_RESET] = { 0x26c0, 7 }, 2817 [TSIF_H_RESET] = { 0x2700, 7 }, 2818 [CE1_H_RESET] = { 0x2720, 7 }, 2819 [CE1_CORE_RESET] = { 0x2724, 7 }, 2820 [CE1_SLEEP_RESET] = { 0x2728, 7 }, 2821 [CE2_H_RESET] = { 0x2740, 7 }, 2822 [CE2_CORE_RESET] = { 0x2744, 7 }, 2823 [SFAB_SFPB_M_RESET] = { 0x2780, 7 }, 2824 [SFAB_SFPB_S_RESET] = { 0x27a0, 7 }, 2825 [RPM_PROC_RESET] = { 0x27c0, 7 }, 2826 [PMIC_SSBI2_RESET] = { 0x280c, 12 }, 2827 [SDC1_RESET] = { 0x2830 }, 2828 [SDC2_RESET] = { 0x2850 }, 2829 [SDC3_RESET] = { 0x2870 }, 2830 [SDC4_RESET] = { 0x2890 }, 2831 [SDC5_RESET] = { 0x28b0 }, 2832 [DFAB_A2_RESET] = { 0x28c0, 7 }, 2833 [USB_HS1_RESET] = { 0x2910 }, 2834 [USB_HSIC_RESET] = { 0x2934 }, 2835 [USB_FS1_XCVR_RESET] = { 0x2974, 1 }, 2836 [USB_FS1_RESET] = { 0x2974 }, 2837 [USB_FS2_XCVR_RESET] = { 0x2994, 1 }, 2838 [USB_FS2_RESET] = { 0x2994 }, 2839 [GSBI1_RESET] = { 0x29dc }, 2840 [GSBI2_RESET] = { 0x29fc }, 2841 [GSBI3_RESET] = { 0x2a1c }, 2842 [GSBI4_RESET] = { 0x2a3c }, 2843 [GSBI5_RESET] = { 0x2a5c }, 2844 [GSBI6_RESET] = { 0x2a7c }, 2845 [GSBI7_RESET] = { 0x2a9c }, 2846 [GSBI8_RESET] = { 0x2abc }, 2847 [GSBI9_RESET] = { 0x2adc }, 2848 [GSBI10_RESET] = { 0x2afc }, 2849 [GSBI11_RESET] = { 0x2b1c }, 2850 [GSBI12_RESET] = { 0x2b3c }, 2851 [SPDM_RESET] = { 0x2b6c }, 2852 [TLMM_H_RESET] = { 0x2ba0, 7 }, 2853 [SFAB_MSS_S_RESET] = { 0x2c00, 7 }, 2854 [MSS_SLP_RESET] = { 0x2c60, 7 }, 2855 [MSS_Q6SW_JTAG_RESET] = { 0x2c68, 7 }, 2856 [MSS_Q6FW_JTAG_RESET] = { 0x2c6c, 7 }, 2857 [MSS_RESET] = { 0x2c64 }, 2858 [SATA_H_RESET] = { 0x2c80, 7 }, 2859 [SATA_RXOOB_RESE] = { 0x2c8c, 7 }, 2860 [SATA_PMALIVE_RESET] = { 0x2c90, 7 }, 2861 [SATA_SFAB_M_RESET] = { 0x2c98, 7 }, 2862 [TSSC_RESET] = { 0x2ca0, 7 }, 2863 [PDM_RESET] = { 0x2cc0, 12 }, 2864 [MPM_H_RESET] = { 0x2da0, 7 }, 2865 [MPM_RESET] = { 0x2da4 }, 2866 [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 }, 2867 [PRNG_RESET] = { 0x2e80, 12 }, 2868 [RIVA_RESET] = { 0x35e0 }, 2869 }; 2870 2871 static struct clk_regmap *gcc_apq8064_clks[] = { 2872 [PLL8] = &pll8.clkr, 2873 [PLL8_VOTE] = &pll8_vote, 2874 [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr, 2875 [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr, 2876 [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr, 2877 [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr, 2878 [GSBI7_H_CLK] = &gsbi7_h_clk.clkr, 2879 }; 2880 2881 static const struct regmap_config gcc_msm8960_regmap_config = { 2882 .reg_bits = 32, 2883 .reg_stride = 4, 2884 .val_bits = 32, 2885 .max_register = 0x3660, 2886 .fast_io = true, 2887 }; 2888 2889 static const struct qcom_cc_desc gcc_msm8960_desc = { 2890 .config = &gcc_msm8960_regmap_config, 2891 .clks = gcc_msm8960_clks, 2892 .num_clks = ARRAY_SIZE(gcc_msm8960_clks), 2893 .resets = gcc_msm8960_resets, 2894 .num_resets = ARRAY_SIZE(gcc_msm8960_resets), 2895 }; 2896 2897 static const struct qcom_cc_desc gcc_apq8064_desc = { 2898 .config = &gcc_msm8960_regmap_config, 2899 .clks = gcc_apq8064_clks, 2900 .num_clks = ARRAY_SIZE(gcc_apq8064_clks), 2901 .resets = gcc_msm8960_resets, 2902 .num_resets = ARRAY_SIZE(gcc_msm8960_resets), 2903 }; 2904 2905 static const struct of_device_id gcc_msm8960_match_table[] = { 2906 { .compatible = "qcom,gcc-msm8960", .data = &gcc_msm8960_desc }, 2907 { .compatible = "qcom,gcc-apq8064", .data = &gcc_apq8064_desc }, 2908 { } 2909 }; 2910 MODULE_DEVICE_TABLE(of, gcc_msm8960_match_table); 2911 2912 static int gcc_msm8960_probe(struct platform_device *pdev) 2913 { 2914 struct clk *clk; 2915 struct device *dev = &pdev->dev; 2916 const struct of_device_id *match; 2917 2918 match = of_match_device(gcc_msm8960_match_table, &pdev->dev); 2919 if (!match) 2920 return -EINVAL; 2921 2922 /* Temporary until RPM clocks supported */ 2923 clk = clk_register_fixed_rate(dev, "cxo", NULL, CLK_IS_ROOT, 19200000); 2924 if (IS_ERR(clk)) 2925 return PTR_ERR(clk); 2926 2927 clk = clk_register_fixed_rate(dev, "pxo", NULL, CLK_IS_ROOT, 27000000); 2928 if (IS_ERR(clk)) 2929 return PTR_ERR(clk); 2930 2931 return qcom_cc_probe(pdev, match->data); 2932 } 2933 2934 static int gcc_msm8960_remove(struct platform_device *pdev) 2935 { 2936 qcom_cc_remove(pdev); 2937 return 0; 2938 } 2939 2940 static struct platform_driver gcc_msm8960_driver = { 2941 .probe = gcc_msm8960_probe, 2942 .remove = gcc_msm8960_remove, 2943 .driver = { 2944 .name = "gcc-msm8960", 2945 .owner = THIS_MODULE, 2946 .of_match_table = gcc_msm8960_match_table, 2947 }, 2948 }; 2949 2950 static int __init gcc_msm8960_init(void) 2951 { 2952 return platform_driver_register(&gcc_msm8960_driver); 2953 } 2954 core_initcall(gcc_msm8960_init); 2955 2956 static void __exit gcc_msm8960_exit(void) 2957 { 2958 platform_driver_unregister(&gcc_msm8960_driver); 2959 } 2960 module_exit(gcc_msm8960_exit); 2961 2962 MODULE_DESCRIPTION("QCOM GCC MSM8960 Driver"); 2963 MODULE_LICENSE("GPL v2"); 2964 MODULE_ALIAS("platform:gcc-msm8960"); 2965