1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2023 Otto Pflüger
4 *
5 * Based on gcc-msm8953.c:
6 * Copyright 2021, The Linux Foundation. All rights reserved.
7 * with parts taken from gcc-qcs404.c:
8 * Copyright 2018, The Linux Foundation. All rights reserved.
9 * and gcc-msm8939.c:
10 * Copyright 2020 Linaro Limited
11 * adapted with data from clock-gcc-8952.c in Qualcomm's msm-4.9 release:
12 * Copyright (c) 2014-2020, The Linux Foundation. All rights reserved.
13 */
14
15 #include <linux/bitops.h>
16 #include <linux/clk-provider.h>
17 #include <linux/err.h>
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/of.h>
21 #include <linux/platform_device.h>
22 #include <linux/regmap.h>
23 #include <linux/reset-controller.h>
24
25 #include <dt-bindings/clock/qcom,gcc-msm8917.h>
26
27 #include "clk-alpha-pll.h"
28 #include "clk-branch.h"
29 #include "clk-pll.h"
30 #include "clk-rcg.h"
31 #include "common.h"
32 #include "gdsc.h"
33 #include "reset.h"
34
35 enum {
36 DT_XO,
37 DT_SLEEP_CLK,
38 DT_DSI0PLL,
39 DT_DSI0PLL_BYTE,
40 };
41
42 enum {
43 P_XO,
44 P_SLEEP_CLK,
45 P_GPLL0,
46 P_GPLL3,
47 P_GPLL4,
48 P_GPLL6,
49 P_DSI0PLL,
50 P_DSI0PLL_BYTE,
51 };
52
53 static struct clk_alpha_pll gpll0_sleep_clk_src = {
54 .offset = 0x21000,
55 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
56 .clkr = {
57 .enable_reg = 0x45008,
58 .enable_mask = BIT(23),
59 .enable_is_inverted = true,
60 .hw.init = &(struct clk_init_data){
61 .name = "gpll0_sleep_clk_src",
62 .parent_data = &(const struct clk_parent_data) {
63 .index = DT_XO,
64 },
65 .num_parents = 1,
66 .ops = &clk_branch_simple_ops,
67 },
68 },
69 };
70
71 static struct clk_alpha_pll gpll0_early = {
72 .offset = 0x21000,
73 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
74 .clkr = {
75 .enable_reg = 0x45000,
76 .enable_mask = BIT(0),
77 .hw.init = &(struct clk_init_data) {
78 .name = "gpll0_early",
79 .parent_hws = (const struct clk_hw*[]){
80 &gpll0_sleep_clk_src.clkr.hw,
81 },
82 .num_parents = 1,
83 .ops = &clk_alpha_pll_fixed_ops,
84 },
85 },
86 };
87
88 static struct clk_alpha_pll_postdiv gpll0 = {
89 .offset = 0x21000,
90 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
91 .clkr.hw.init = &(struct clk_init_data){
92 .name = "gpll0",
93 .parent_hws = (const struct clk_hw*[]){
94 &gpll0_early.clkr.hw,
95 },
96 .num_parents = 1,
97 .ops = &clk_alpha_pll_postdiv_ro_ops,
98 },
99 };
100
101 static const struct pll_vco gpll3_p_vco[] = {
102 { 700000000, 1400000000, 0 },
103 };
104
105 static const struct alpha_pll_config gpll3_early_config = {
106 .l = 63,
107 .config_ctl_val = 0x4001055b,
108 .early_output_mask = 0,
109 .post_div_mask = GENMASK(11, 8),
110 .post_div_val = BIT(8),
111 };
112
113 static struct clk_alpha_pll gpll3_early = {
114 .offset = 0x22000,
115 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
116 .vco_table = gpll3_p_vco,
117 .num_vco = ARRAY_SIZE(gpll3_p_vco),
118 .flags = SUPPORTS_DYNAMIC_UPDATE,
119 .clkr = {
120 .hw.init = &(struct clk_init_data){
121 .name = "gpll3_early",
122 .parent_data = &(const struct clk_parent_data) {
123 .index = DT_XO,
124 },
125 .num_parents = 1,
126 .ops = &clk_alpha_pll_ops,
127 },
128 },
129 };
130
131 static struct clk_alpha_pll_postdiv gpll3 = {
132 .offset = 0x22000,
133 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
134 .clkr.hw.init = &(struct clk_init_data){
135 .name = "gpll3",
136 .parent_hws = (const struct clk_hw*[]){
137 &gpll3_early.clkr.hw,
138 },
139 .num_parents = 1,
140 .ops = &clk_alpha_pll_postdiv_ops,
141 .flags = CLK_SET_RATE_PARENT,
142 },
143 };
144
145 static struct clk_alpha_pll gpll4_early = {
146 .offset = 0x24000,
147 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
148 .clkr = {
149 .enable_reg = 0x45000,
150 .enable_mask = BIT(5),
151 .hw.init = &(struct clk_init_data){
152 .name = "gpll4_early",
153 .parent_data = &(const struct clk_parent_data) {
154 .index = DT_XO,
155 },
156 .num_parents = 1,
157 .ops = &clk_alpha_pll_fixed_ops,
158 },
159 },
160 };
161
162 static struct clk_alpha_pll_postdiv gpll4 = {
163 .offset = 0x24000,
164 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
165 .clkr.hw.init = &(struct clk_init_data){
166 .name = "gpll4",
167 .parent_hws = (const struct clk_hw*[]){
168 &gpll4_early.clkr.hw,
169 },
170 .num_parents = 1,
171 .ops = &clk_alpha_pll_postdiv_ro_ops,
172 },
173 };
174
175 static struct clk_pll gpll6_early = {
176 .l_reg = 0x37004,
177 .m_reg = 0x37008,
178 .n_reg = 0x3700c,
179 .config_reg = 0x37014,
180 .mode_reg = 0x37000,
181 .status_reg = 0x3701c,
182 .status_bit = 17,
183 .clkr.hw.init = &(struct clk_init_data){
184 .name = "gpll6_early",
185 .parent_data = &(const struct clk_parent_data) {
186 .index = DT_XO,
187 },
188 .num_parents = 1,
189 .ops = &clk_pll_ops,
190 },
191 };
192
193 static struct clk_regmap gpll6 = {
194 .enable_reg = 0x45000,
195 .enable_mask = BIT(7),
196 .hw.init = &(struct clk_init_data){
197 .name = "gpll6",
198 .parent_hws = (const struct clk_hw*[]){
199 &gpll6_early.clkr.hw,
200 },
201 .num_parents = 1,
202 .ops = &clk_pll_vote_ops,
203 },
204 };
205
206 static const struct parent_map gcc_xo_gpll0_map[] = {
207 { P_XO, 0 },
208 { P_GPLL0, 1 },
209 };
210
211 static const struct parent_map gcc_xo_gpll0_out_aux_map[] = {
212 { P_XO, 0 },
213 { P_GPLL0, 2 },
214 };
215
216 static const struct clk_parent_data gcc_xo_gpll0_data[] = {
217 { .index = DT_XO },
218 { .hw = &gpll0.clkr.hw },
219 };
220
221 static const struct parent_map gcc_xo_gpll0_gpll6_sleep_map[] = {
222 { P_XO, 0 },
223 { P_GPLL0, 1 },
224 { P_GPLL6, 2 },
225 { P_SLEEP_CLK, 6 },
226 };
227
228 static const struct clk_parent_data gcc_xo_gpll0_gpll6_sleep_data[] = {
229 { .index = DT_XO },
230 { .hw = &gpll0.clkr.hw },
231 { .hw = &gpll6.hw },
232 { .index = DT_SLEEP_CLK },
233 };
234
235 static const struct parent_map gcc_xo_gpll0_gpll6_gpll4_map[] = {
236 { P_XO, 0 },
237 { P_GPLL0, 1 },
238 { P_GPLL6, 2 },
239 { P_GPLL4, 3 },
240 };
241
242 static const struct clk_parent_data gcc_xo_gpll0_gpll6_gpll4_data[] = {
243 { .index = DT_XO },
244 { .hw = &gpll0.clkr.hw },
245 { .hw = &gpll6.hw },
246 { .hw = &gpll4.clkr.hw },
247 };
248
249 static const struct freq_tbl ftbl_apss_ahb_clk_src[] = {
250 F(19200000, P_XO, 1, 0, 0),
251 F(50000000, P_GPLL0, 16, 0, 0),
252 F(100000000, P_GPLL0, 8, 0, 0),
253 F(133330000, P_GPLL0, 6, 0, 0),
254 { }
255 };
256
257 static struct clk_rcg2 apss_ahb_clk_src = {
258 .cmd_rcgr = 0x46000,
259 .hid_width = 5,
260 .freq_tbl = ftbl_apss_ahb_clk_src,
261 .parent_map = gcc_xo_gpll0_map,
262 .clkr.hw.init = &(struct clk_init_data) {
263 .name = "apss_ahb_clk_src",
264 .parent_data = gcc_xo_gpll0_data,
265 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
266 .ops = &clk_rcg2_ops,
267 }
268 };
269
270 static const struct freq_tbl ftbl_blsp_i2c_apps_clk_src[] = {
271 F(19200000, P_XO, 1, 0, 0),
272 F(50000000, P_GPLL0, 16, 0, 0),
273 { }
274 };
275
276 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
277 .cmd_rcgr = 0x03000,
278 .hid_width = 5,
279 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
280 .parent_map = gcc_xo_gpll0_map,
281 .clkr.hw.init = &(struct clk_init_data) {
282 .name = "blsp1_qup2_i2c_apps_clk_src",
283 .parent_data = gcc_xo_gpll0_data,
284 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
285 .ops = &clk_rcg2_ops,
286 }
287 };
288
289 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
290 .cmd_rcgr = 0x04000,
291 .hid_width = 5,
292 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
293 .parent_map = gcc_xo_gpll0_map,
294 .clkr.hw.init = &(struct clk_init_data) {
295 .name = "blsp1_qup3_i2c_apps_clk_src",
296 .parent_data = gcc_xo_gpll0_data,
297 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
298 .ops = &clk_rcg2_ops,
299 }
300 };
301
302 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
303 .cmd_rcgr = 0x05000,
304 .hid_width = 5,
305 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
306 .parent_map = gcc_xo_gpll0_map,
307 .clkr.hw.init = &(struct clk_init_data) {
308 .name = "blsp1_qup4_i2c_apps_clk_src",
309 .parent_data = gcc_xo_gpll0_data,
310 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
311 .ops = &clk_rcg2_ops,
312 }
313 };
314
315 static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
316 .cmd_rcgr = 0x0c00c,
317 .hid_width = 5,
318 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
319 .parent_map = gcc_xo_gpll0_map,
320 .clkr.hw.init = &(struct clk_init_data) {
321 .name = "blsp2_qup1_i2c_apps_clk_src",
322 .parent_data = gcc_xo_gpll0_data,
323 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
324 .ops = &clk_rcg2_ops,
325 }
326 };
327
328 static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
329 .cmd_rcgr = 0x0d000,
330 .hid_width = 5,
331 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
332 .parent_map = gcc_xo_gpll0_map,
333 .clkr.hw.init = &(struct clk_init_data) {
334 .name = "blsp2_qup2_i2c_apps_clk_src",
335 .parent_data = gcc_xo_gpll0_data,
336 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
337 .ops = &clk_rcg2_ops,
338 }
339 };
340
341 static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
342 .cmd_rcgr = 0x0f000,
343 .hid_width = 5,
344 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
345 .parent_map = gcc_xo_gpll0_map,
346 .clkr.hw.init = &(struct clk_init_data) {
347 .name = "blsp2_qup3_i2c_apps_clk_src",
348 .parent_data = gcc_xo_gpll0_data,
349 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
350 .ops = &clk_rcg2_ops,
351 }
352 };
353
354 static const struct freq_tbl ftbl_blsp_spi_apps_clk_src[] = {
355 F(960000, P_XO, 10, 1, 2),
356 F(4800000, P_XO, 4, 0, 0),
357 F(9600000, P_XO, 2, 0, 0),
358 F(16000000, P_GPLL0, 10, 1, 5),
359 F(19200000, P_XO, 1, 0, 0),
360 F(25000000, P_GPLL0, 16, 1, 2),
361 F(50000000, P_GPLL0, 16, 0, 0),
362 { }
363 };
364
365 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
366 .cmd_rcgr = 0x03014,
367 .hid_width = 5,
368 .mnd_width = 8,
369 .freq_tbl = ftbl_blsp_spi_apps_clk_src,
370 .parent_map = gcc_xo_gpll0_map,
371 .clkr.hw.init = &(struct clk_init_data) {
372 .name = "blsp1_qup2_spi_apps_clk_src",
373 .parent_data = gcc_xo_gpll0_data,
374 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
375 .ops = &clk_rcg2_ops,
376 }
377 };
378
379 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
380 .cmd_rcgr = 0x04024,
381 .hid_width = 5,
382 .mnd_width = 8,
383 .freq_tbl = ftbl_blsp_spi_apps_clk_src,
384 .parent_map = gcc_xo_gpll0_map,
385 .clkr.hw.init = &(struct clk_init_data) {
386 .name = "blsp1_qup3_spi_apps_clk_src",
387 .parent_data = gcc_xo_gpll0_data,
388 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
389 .ops = &clk_rcg2_ops,
390 }
391 };
392
393 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
394 .cmd_rcgr = 0x05024,
395 .hid_width = 5,
396 .mnd_width = 8,
397 .freq_tbl = ftbl_blsp_spi_apps_clk_src,
398 .parent_map = gcc_xo_gpll0_map,
399 .clkr.hw.init = &(struct clk_init_data) {
400 .name = "blsp1_qup4_spi_apps_clk_src",
401 .parent_data = gcc_xo_gpll0_data,
402 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
403 .ops = &clk_rcg2_ops,
404 }
405 };
406
407 static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
408 .cmd_rcgr = 0x0c024,
409 .hid_width = 5,
410 .mnd_width = 8,
411 .freq_tbl = ftbl_blsp_spi_apps_clk_src,
412 .parent_map = gcc_xo_gpll0_map,
413 .clkr.hw.init = &(struct clk_init_data) {
414 .name = "blsp2_qup1_spi_apps_clk_src",
415 .parent_data = gcc_xo_gpll0_data,
416 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
417 .ops = &clk_rcg2_ops,
418 }
419 };
420
421 static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
422 .cmd_rcgr = 0x0d014,
423 .hid_width = 5,
424 .mnd_width = 8,
425 .freq_tbl = ftbl_blsp_spi_apps_clk_src,
426 .parent_map = gcc_xo_gpll0_map,
427 .clkr.hw.init = &(struct clk_init_data) {
428 .name = "blsp2_qup2_spi_apps_clk_src",
429 .parent_data = gcc_xo_gpll0_data,
430 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
431 .ops = &clk_rcg2_ops,
432 }
433 };
434
435 static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
436 .cmd_rcgr = 0x0f024,
437 .hid_width = 5,
438 .mnd_width = 8,
439 .freq_tbl = ftbl_blsp_spi_apps_clk_src,
440 .parent_map = gcc_xo_gpll0_map,
441 .clkr.hw.init = &(struct clk_init_data) {
442 .name = "blsp2_qup3_spi_apps_clk_src",
443 .parent_data = gcc_xo_gpll0_data,
444 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
445 .ops = &clk_rcg2_ops,
446 }
447 };
448
449 static const struct freq_tbl ftbl_blsp_uart_apps_clk_src[] = {
450 F(3686400, P_GPLL0, 1, 72, 15625),
451 F(7372800, P_GPLL0, 1, 144, 15625),
452 F(14745600, P_GPLL0, 1, 288, 15625),
453 F(16000000, P_GPLL0, 10, 1, 5),
454 F(19200000, P_XO, 1, 0, 0),
455 F(24000000, P_GPLL0, 1, 3, 100),
456 F(25000000, P_GPLL0, 16, 1, 2),
457 F(32000000, P_GPLL0, 1, 1, 25),
458 F(40000000, P_GPLL0, 1, 1, 20),
459 F(46400000, P_GPLL0, 1, 29, 500),
460 F(48000000, P_GPLL0, 1, 3, 50),
461 F(51200000, P_GPLL0, 1, 8, 125),
462 F(56000000, P_GPLL0, 1, 7, 100),
463 F(58982400, P_GPLL0, 1, 1152, 15625),
464 F(60000000, P_GPLL0, 1, 3, 40),
465 F(64000000, P_GPLL0, 1, 2, 25),
466 { }
467 };
468
469 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
470 .cmd_rcgr = 0x02044,
471 .hid_width = 5,
472 .mnd_width = 16,
473 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
474 .parent_map = gcc_xo_gpll0_map,
475 .clkr.hw.init = &(struct clk_init_data) {
476 .name = "blsp1_uart1_apps_clk_src",
477 .parent_data = gcc_xo_gpll0_data,
478 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
479 .ops = &clk_rcg2_ops,
480 }
481 };
482
483 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
484 .cmd_rcgr = 0x03034,
485 .hid_width = 5,
486 .mnd_width = 16,
487 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
488 .parent_map = gcc_xo_gpll0_map,
489 .clkr.hw.init = &(struct clk_init_data) {
490 .name = "blsp1_uart2_apps_clk_src",
491 .parent_data = gcc_xo_gpll0_data,
492 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
493 .ops = &clk_rcg2_ops,
494 }
495 };
496
497 static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
498 .cmd_rcgr = 0x0c044,
499 .hid_width = 5,
500 .mnd_width = 16,
501 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
502 .parent_map = gcc_xo_gpll0_map,
503 .clkr.hw.init = &(struct clk_init_data) {
504 .name = "blsp2_uart1_apps_clk_src",
505 .parent_data = gcc_xo_gpll0_data,
506 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
507 .ops = &clk_rcg2_ops,
508 }
509 };
510
511 static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
512 .cmd_rcgr = 0x0d034,
513 .hid_width = 5,
514 .mnd_width = 16,
515 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
516 .parent_map = gcc_xo_gpll0_map,
517 .clkr.hw.init = &(struct clk_init_data) {
518 .name = "blsp2_uart2_apps_clk_src",
519 .parent_data = gcc_xo_gpll0_data,
520 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
521 .ops = &clk_rcg2_ops,
522 }
523 };
524
525 static const struct parent_map gcc_byte0_map[] = {
526 { P_XO, 0 },
527 { P_DSI0PLL_BYTE, 1 },
528 };
529
530 static const struct clk_parent_data gcc_byte_data[] = {
531 { .index = DT_XO },
532 { .index = DT_DSI0PLL_BYTE },
533 };
534
535 static struct clk_rcg2 byte0_clk_src = {
536 .cmd_rcgr = 0x4d044,
537 .hid_width = 5,
538 .parent_map = gcc_byte0_map,
539 .clkr.hw.init = &(struct clk_init_data) {
540 .name = "byte0_clk_src",
541 .parent_data = gcc_byte_data,
542 .num_parents = ARRAY_SIZE(gcc_byte_data),
543 .ops = &clk_byte2_ops,
544 .flags = CLK_SET_RATE_PARENT,
545 }
546 };
547
548 static const struct freq_tbl ftbl_camss_gp_clk_src[] = {
549 F(100000000, P_GPLL0, 8, 0, 0),
550 F(160000000, P_GPLL0, 5, 0, 0),
551 F(200000000, P_GPLL0, 4, 0, 0),
552 { }
553 };
554
555 static struct clk_rcg2 camss_gp0_clk_src = {
556 .cmd_rcgr = 0x54000,
557 .hid_width = 5,
558 .mnd_width = 8,
559 .freq_tbl = ftbl_camss_gp_clk_src,
560 .parent_map = gcc_xo_gpll0_gpll6_sleep_map,
561 .clkr.hw.init = &(struct clk_init_data) {
562 .name = "camss_gp0_clk_src",
563 .parent_data = gcc_xo_gpll0_gpll6_sleep_data,
564 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_sleep_data),
565 .ops = &clk_rcg2_ops,
566 }
567 };
568
569 static struct clk_rcg2 camss_gp1_clk_src = {
570 .cmd_rcgr = 0x55000,
571 .hid_width = 5,
572 .mnd_width = 8,
573 .freq_tbl = ftbl_camss_gp_clk_src,
574 .parent_map = gcc_xo_gpll0_gpll6_sleep_map,
575 .clkr.hw.init = &(struct clk_init_data) {
576 .name = "camss_gp1_clk_src",
577 .parent_data = gcc_xo_gpll0_gpll6_sleep_data,
578 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_sleep_data),
579 .ops = &clk_rcg2_ops,
580 }
581 };
582
583 static const struct freq_tbl ftbl_camss_top_ahb_clk_src[] = {
584 F(40000000, P_GPLL0, 10, 1, 2),
585 F(61540000, P_GPLL0, 13, 0, 0),
586 F(80000000, P_GPLL0, 10, 0, 0),
587 { }
588 };
589
590 static struct clk_rcg2 camss_top_ahb_clk_src = {
591 .cmd_rcgr = 0x5a000,
592 .hid_width = 5,
593 .freq_tbl = ftbl_camss_top_ahb_clk_src,
594 .parent_map = gcc_xo_gpll0_map,
595 .clkr.hw.init = &(struct clk_init_data) {
596 .name = "camss_top_ahb_clk_src",
597 .parent_data = gcc_xo_gpll0_data,
598 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
599 .ops = &clk_rcg2_ops,
600 }
601 };
602
603 static const struct freq_tbl ftbl_cci_clk_src[] = {
604 F(19200000, P_XO, 1, 0, 0),
605 F(37500000, P_GPLL0, 1, 3, 64),
606 { }
607 };
608
609 static struct clk_rcg2 cci_clk_src = {
610 .cmd_rcgr = 0x51000,
611 .hid_width = 5,
612 .mnd_width = 8,
613 .freq_tbl = ftbl_cci_clk_src,
614 .parent_map = gcc_xo_gpll0_out_aux_map,
615 .clkr.hw.init = &(struct clk_init_data) {
616 .name = "cci_clk_src",
617 .parent_data = gcc_xo_gpll0_data,
618 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
619 .ops = &clk_rcg2_ops,
620 }
621 };
622
623 static const struct parent_map gcc_cpp_map[] = {
624 { P_XO, 0 },
625 { P_GPLL0, 1 },
626 { P_GPLL6, 3 },
627 };
628
629 static const struct clk_parent_data gcc_cpp_data[] = {
630 { .index = DT_XO },
631 { .hw = &gpll0.clkr.hw },
632 { .hw = &gpll6.hw },
633 };
634
635 static const struct freq_tbl ftbl_cpp_clk_src[] = {
636 F(133330000, P_GPLL0, 6, 0, 0),
637 F(160000000, P_GPLL0, 5, 0, 0),
638 F(266670000, P_GPLL0, 3, 0, 0),
639 F(308570000, P_GPLL0, 3.5, 0, 0),
640 F(320000000, P_GPLL0, 2.5, 0, 0),
641 F(360000000, P_GPLL6, 3, 0, 0),
642 { }
643 };
644
645 static struct clk_rcg2 cpp_clk_src = {
646 .cmd_rcgr = 0x58018,
647 .hid_width = 5,
648 .freq_tbl = ftbl_cpp_clk_src,
649 .parent_map = gcc_cpp_map,
650 .clkr.hw.init = &(struct clk_init_data) {
651 .name = "cpp_clk_src",
652 .parent_data = gcc_cpp_data,
653 .num_parents = ARRAY_SIZE(gcc_cpp_data),
654 .ops = &clk_rcg2_ops,
655 }
656 };
657
658 static const struct freq_tbl ftbl_crypto_clk_src[] = {
659 F(50000000, P_GPLL0, 16, 0, 0),
660 F(80000000, P_GPLL0, 10, 0, 0),
661 F(100000000, P_GPLL0, 8, 0, 0),
662 F(160000000, P_GPLL0, 5, 0, 0),
663 { }
664 };
665
666 static struct clk_rcg2 crypto_clk_src = {
667 .cmd_rcgr = 0x16004,
668 .hid_width = 5,
669 .freq_tbl = ftbl_crypto_clk_src,
670 .parent_map = gcc_xo_gpll0_map,
671 .clkr.hw.init = &(struct clk_init_data) {
672 .name = "crypto_clk_src",
673 .parent_data = gcc_xo_gpll0_data,
674 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
675 .ops = &clk_rcg2_ops,
676 }
677 };
678
679 static const struct freq_tbl ftbl_csi_clk_src[] = {
680 F(100000000, P_GPLL0, 8, 0, 0),
681 F(160000000, P_GPLL0, 5, 0, 0),
682 F(200000000, P_GPLL0, 4, 0, 0),
683 { }
684 };
685
686 static struct clk_rcg2 csi0_clk_src = {
687 .cmd_rcgr = 0x4e020,
688 .hid_width = 5,
689 .freq_tbl = ftbl_csi_clk_src,
690 .parent_map = gcc_xo_gpll0_map,
691 .clkr.hw.init = &(struct clk_init_data) {
692 .name = "csi0_clk_src",
693 .parent_data = gcc_xo_gpll0_data,
694 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
695 .ops = &clk_rcg2_ops,
696 }
697 };
698
699 static struct clk_rcg2 csi1_clk_src = {
700 .cmd_rcgr = 0x4f020,
701 .hid_width = 5,
702 .freq_tbl = ftbl_csi_clk_src,
703 .parent_map = gcc_xo_gpll0_map,
704 .clkr.hw.init = &(struct clk_init_data) {
705 .name = "csi1_clk_src",
706 .parent_data = gcc_xo_gpll0_data,
707 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
708 .ops = &clk_rcg2_ops,
709 }
710 };
711
712 static struct clk_rcg2 csi2_clk_src = {
713 .cmd_rcgr = 0x3c020,
714 .hid_width = 5,
715 .freq_tbl = ftbl_csi_clk_src,
716 .parent_map = gcc_xo_gpll0_map,
717 .clkr.hw.init = &(struct clk_init_data) {
718 .name = "csi2_clk_src",
719 .parent_data = gcc_xo_gpll0_data,
720 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
721 .ops = &clk_rcg2_ops,
722 }
723 };
724
725 static const struct freq_tbl ftbl_csi_phytimer_clk_src[] = {
726 F(100000000, P_GPLL0, 8, 0, 0),
727 F(160000000, P_GPLL0, 5, 0, 0),
728 F(200000000, P_GPLL0, 4, 0, 0),
729 F(266670000, P_GPLL0, 3, 0, 0),
730 { }
731 };
732
733 static struct clk_rcg2 csi0phytimer_clk_src = {
734 .cmd_rcgr = 0x4e000,
735 .hid_width = 5,
736 .freq_tbl = ftbl_csi_phytimer_clk_src,
737 .parent_map = gcc_xo_gpll0_map,
738 .clkr.hw.init = &(struct clk_init_data) {
739 .name = "csi0phytimer_clk_src",
740 .parent_data = gcc_xo_gpll0_data,
741 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
742 .ops = &clk_rcg2_ops,
743 }
744 };
745
746 static struct clk_rcg2 csi1phytimer_clk_src = {
747 .cmd_rcgr = 0x4f000,
748 .hid_width = 5,
749 .freq_tbl = ftbl_csi_phytimer_clk_src,
750 .parent_map = gcc_xo_gpll0_map,
751 .clkr.hw.init = &(struct clk_init_data) {
752 .name = "csi1phytimer_clk_src",
753 .parent_data = gcc_xo_gpll0_data,
754 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
755 .ops = &clk_rcg2_ops,
756 }
757 };
758
759 static const struct freq_tbl ftbl_esc0_1_clk_src[] = {
760 F(19200000, P_XO, 1, 0, 0),
761 { }
762 };
763
764 static struct clk_rcg2 esc0_clk_src = {
765 .cmd_rcgr = 0x4d05c,
766 .hid_width = 5,
767 .freq_tbl = ftbl_esc0_1_clk_src,
768 .parent_map = gcc_xo_gpll0_out_aux_map,
769 .clkr.hw.init = &(struct clk_init_data) {
770 .name = "esc0_clk_src",
771 .parent_data = gcc_xo_gpll0_data,
772 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
773 .ops = &clk_rcg2_ops,
774 }
775 };
776
777 static const struct parent_map gcc_gfx3d_map[] = {
778 { P_XO, 0 },
779 { P_GPLL0, 1 },
780 { P_GPLL3, 2 },
781 { P_GPLL6, 3 },
782 };
783
784 static const struct parent_map gcc_gfx3d_map_qm215[] = {
785 { P_XO, 0 },
786 { P_GPLL0, 5 },
787 { P_GPLL3, 2 },
788 { P_GPLL6, 6 },
789 };
790
791 static const struct clk_parent_data gcc_gfx3d_data[] = {
792 { .index = DT_XO },
793 { .hw = &gpll0.clkr.hw },
794 { .hw = &gpll3.clkr.hw },
795 { .hw = &gpll6.hw },
796 };
797
798 static const struct freq_tbl ftbl_gfx3d_clk_src[] = {
799 F(19200000, P_XO, 1, 0, 0),
800 F(50000000, P_GPLL0, 16, 0, 0),
801 F(80000000, P_GPLL0, 10, 0, 0),
802 F(100000000, P_GPLL0, 8, 0, 0),
803 F(160000000, P_GPLL0, 5, 0, 0),
804 F(200000000, P_GPLL0, 4, 0, 0),
805 F(228570000, P_GPLL0, 3.5, 0, 0),
806 F(240000000, P_GPLL6, 4.5, 0, 0),
807 F(266670000, P_GPLL0, 3, 0, 0),
808 F(270000000, P_GPLL6, 4, 0, 0),
809 F(320000000, P_GPLL0, 2.5, 0, 0),
810 F(400000000, P_GPLL0, 2, 0, 0),
811 F(465000000, P_GPLL3, 1, 0, 0),
812 F(484800000, P_GPLL3, 1, 0, 0),
813 F(500000000, P_GPLL3, 1, 0, 0),
814 F(523200000, P_GPLL3, 1, 0, 0),
815 F(550000000, P_GPLL3, 1, 0, 0),
816 F(598000000, P_GPLL3, 1, 0, 0),
817 { }
818 };
819
820 static struct clk_rcg2 gfx3d_clk_src = {
821 .cmd_rcgr = 0x59000,
822 .hid_width = 5,
823 .freq_tbl = ftbl_gfx3d_clk_src,
824 .parent_map = gcc_gfx3d_map,
825 .clkr.hw.init = &(struct clk_init_data) {
826 .name = "gfx3d_clk_src",
827 .parent_data = gcc_gfx3d_data,
828 .num_parents = ARRAY_SIZE(gcc_gfx3d_data),
829 .ops = &clk_rcg2_ops,
830 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
831 }
832 };
833
834 static const struct freq_tbl ftbl_gp_clk_src[] = {
835 F(19200000, P_XO, 1, 0, 0),
836 { }
837 };
838
839 static struct clk_rcg2 gp1_clk_src = {
840 .cmd_rcgr = 0x08004,
841 .hid_width = 5,
842 .mnd_width = 8,
843 .freq_tbl = ftbl_gp_clk_src,
844 .parent_map = gcc_xo_gpll0_gpll6_sleep_map,
845 .clkr.hw.init = &(struct clk_init_data) {
846 .name = "gp1_clk_src",
847 .parent_data = gcc_xo_gpll0_gpll6_sleep_data,
848 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_sleep_data),
849 .ops = &clk_rcg2_ops,
850 }
851 };
852
853 static struct clk_rcg2 gp2_clk_src = {
854 .cmd_rcgr = 0x09004,
855 .hid_width = 5,
856 .mnd_width = 8,
857 .freq_tbl = ftbl_gp_clk_src,
858 .parent_map = gcc_xo_gpll0_gpll6_sleep_map,
859 .clkr.hw.init = &(struct clk_init_data) {
860 .name = "gp2_clk_src",
861 .parent_data = gcc_xo_gpll0_gpll6_sleep_data,
862 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_sleep_data),
863 .ops = &clk_rcg2_ops,
864 }
865 };
866
867 static struct clk_rcg2 gp3_clk_src = {
868 .cmd_rcgr = 0x0a004,
869 .hid_width = 5,
870 .mnd_width = 8,
871 .freq_tbl = ftbl_gp_clk_src,
872 .parent_map = gcc_xo_gpll0_gpll6_sleep_map,
873 .clkr.hw.init = &(struct clk_init_data) {
874 .name = "gp3_clk_src",
875 .parent_data = gcc_xo_gpll0_gpll6_sleep_data,
876 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_sleep_data),
877 .ops = &clk_rcg2_ops,
878 }
879 };
880
881 static const struct freq_tbl ftbl_jpeg0_clk_src[] = {
882 F(133330000, P_GPLL0, 6, 0, 0),
883 F(266670000, P_GPLL0, 3, 0, 0),
884 F(320000000, P_GPLL0, 2.5, 0, 0),
885 { }
886 };
887
888 static struct clk_rcg2 jpeg0_clk_src = {
889 .cmd_rcgr = 0x57000,
890 .hid_width = 5,
891 .freq_tbl = ftbl_jpeg0_clk_src,
892 .parent_map = gcc_xo_gpll0_map,
893 .clkr.hw.init = &(struct clk_init_data) {
894 .name = "jpeg0_clk_src",
895 .parent_data = gcc_xo_gpll0_data,
896 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
897 .ops = &clk_rcg2_ops,
898 }
899 };
900
901 static const struct freq_tbl ftbl_mclk_clk_src[] = {
902 F(19200000, P_XO, 1, 0, 0),
903 F(24000000, P_GPLL6, 1, 1, 45),
904 F(66667000, P_GPLL0, 12, 0, 0),
905 { }
906 };
907
908 static struct clk_rcg2 mclk0_clk_src = {
909 .cmd_rcgr = 0x52000,
910 .hid_width = 5,
911 .mnd_width = 8,
912 .freq_tbl = ftbl_mclk_clk_src,
913 .parent_map = gcc_xo_gpll0_gpll6_sleep_map,
914 .clkr.hw.init = &(struct clk_init_data) {
915 .name = "mclk0_clk_src",
916 .parent_data = gcc_xo_gpll0_gpll6_sleep_data,
917 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_sleep_data),
918 .ops = &clk_rcg2_ops,
919 }
920 };
921
922 static struct clk_rcg2 mclk1_clk_src = {
923 .cmd_rcgr = 0x53000,
924 .hid_width = 5,
925 .mnd_width = 8,
926 .freq_tbl = ftbl_mclk_clk_src,
927 .parent_map = gcc_xo_gpll0_gpll6_sleep_map,
928 .clkr.hw.init = &(struct clk_init_data) {
929 .name = "mclk1_clk_src",
930 .parent_data = gcc_xo_gpll0_gpll6_sleep_data,
931 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_sleep_data),
932 .ops = &clk_rcg2_ops,
933 }
934 };
935
936 static struct clk_rcg2 mclk2_clk_src = {
937 .cmd_rcgr = 0x5c000,
938 .hid_width = 5,
939 .mnd_width = 8,
940 .freq_tbl = ftbl_mclk_clk_src,
941 .parent_map = gcc_xo_gpll0_gpll6_sleep_map,
942 .clkr.hw.init = &(struct clk_init_data) {
943 .name = "mclk2_clk_src",
944 .parent_data = gcc_xo_gpll0_gpll6_sleep_data,
945 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_sleep_data),
946 .ops = &clk_rcg2_ops,
947 }
948 };
949
950 static const struct freq_tbl ftbl_mdp_clk_src[] = {
951 F(50000000, P_GPLL0, 16, 0, 0),
952 F(80000000, P_GPLL0, 10, 0, 0),
953 F(100000000, P_GPLL0, 8, 0, 0),
954 F(145450000, P_GPLL0, 5.5, 0, 0),
955 F(160000000, P_GPLL0, 5, 0, 0),
956 F(177780000, P_GPLL0, 4.5, 0, 0),
957 F(200000000, P_GPLL0, 4, 0, 0),
958 F(266670000, P_GPLL0, 3, 0, 0),
959 F(320000000, P_GPLL0, 2.5, 0, 0),
960 { }
961 };
962
963 static struct clk_rcg2 mdp_clk_src = {
964 .cmd_rcgr = 0x4d014,
965 .hid_width = 5,
966 .freq_tbl = ftbl_mdp_clk_src,
967 .parent_map = gcc_xo_gpll0_map,
968 .clkr.hw.init = &(struct clk_init_data) {
969 .name = "mdp_clk_src",
970 .parent_data = gcc_xo_gpll0_data,
971 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
972 .ops = &clk_rcg2_ops,
973 }
974 };
975
976 static const struct parent_map gcc_pclk_map[] = {
977 { P_XO, 0 },
978 { P_DSI0PLL, 1 },
979 };
980
981 static const struct clk_parent_data gcc_pclk_data[] = {
982 { .index = DT_XO },
983 { .index = DT_DSI0PLL },
984 };
985
986 static struct clk_rcg2 pclk0_clk_src = {
987 .cmd_rcgr = 0x4d000,
988 .hid_width = 5,
989 .mnd_width = 8,
990 .parent_map = gcc_pclk_map,
991 .clkr.hw.init = &(struct clk_init_data) {
992 .name = "pclk0_clk_src",
993 .parent_data = gcc_pclk_data,
994 .num_parents = ARRAY_SIZE(gcc_pclk_data),
995 .ops = &clk_pixel_ops,
996 .flags = CLK_SET_RATE_PARENT,
997 }
998 };
999
1000 static const struct freq_tbl ftbl_pdm2_clk_src[] = {
1001 F(64000000, P_GPLL0, 12.5, 0, 0),
1002 { }
1003 };
1004
1005 static struct clk_rcg2 pdm2_clk_src = {
1006 .cmd_rcgr = 0x44010,
1007 .hid_width = 5,
1008 .freq_tbl = ftbl_pdm2_clk_src,
1009 .parent_map = gcc_xo_gpll0_map,
1010 .clkr.hw.init = &(struct clk_init_data) {
1011 .name = "pdm2_clk_src",
1012 .parent_data = gcc_xo_gpll0_data,
1013 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
1014 .ops = &clk_rcg2_ops,
1015 }
1016 };
1017
1018 static const struct freq_tbl ftbl_sdcc1_ice_core_clk_src[] = {
1019 F(100000000, P_GPLL0, 8, 0, 0),
1020 F(200000000, P_GPLL0, 4, 0, 0),
1021 { }
1022 };
1023
1024 static struct clk_rcg2 sdcc1_ice_core_clk_src = {
1025 .cmd_rcgr = 0x5d000,
1026 .hid_width = 5,
1027 .freq_tbl = ftbl_sdcc1_ice_core_clk_src,
1028 .parent_map = gcc_xo_gpll0_map,
1029 .clkr.hw.init = &(struct clk_init_data) {
1030 .name = "sdcc1_ice_core_clk_src",
1031 .parent_data = gcc_xo_gpll0_data,
1032 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
1033 .ops = &clk_rcg2_ops,
1034 }
1035 };
1036
1037 static const struct parent_map gcc_sdcc1_apps_map[] = {
1038 { P_XO, 0 },
1039 { P_GPLL0, 1 },
1040 { P_GPLL4, 2 },
1041 };
1042
1043 static const struct clk_parent_data gcc_sdcc1_apss_data[] = {
1044 { .index = DT_XO },
1045 { .hw = &gpll0.clkr.hw },
1046 { .hw = &gpll4.clkr.hw },
1047 };
1048
1049 static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
1050 F(144000, P_XO, 16, 3, 25),
1051 F(400000, P_XO, 12, 1, 4),
1052 F(20000000, P_GPLL0, 10, 1, 4),
1053 F(25000000, P_GPLL0, 16, 1, 2),
1054 F(50000000, P_GPLL0, 16, 0, 0),
1055 F(100000000, P_GPLL0, 8, 0, 0),
1056 F(177770000, P_GPLL0, 4.5, 0, 0),
1057 F(192000000, P_GPLL4, 6, 0, 0),
1058 F(200000000, P_GPLL0, 4, 0, 0),
1059 F(384000000, P_GPLL4, 3, 0, 0),
1060 { }
1061 };
1062
1063 static struct clk_rcg2 sdcc1_apps_clk_src = {
1064 .cmd_rcgr = 0x42004,
1065 .hid_width = 5,
1066 .mnd_width = 8,
1067 .freq_tbl = ftbl_sdcc1_apps_clk_src,
1068 .parent_map = gcc_sdcc1_apps_map,
1069 .clkr.hw.init = &(struct clk_init_data) {
1070 .name = "sdcc1_apps_clk_src",
1071 .parent_data = gcc_sdcc1_apss_data,
1072 .num_parents = ARRAY_SIZE(gcc_sdcc1_apss_data),
1073 .ops = &clk_rcg2_floor_ops,
1074 }
1075 };
1076
1077 static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = {
1078 F(144000, P_XO, 16, 3, 25),
1079 F(400000, P_XO, 12, 1, 4),
1080 F(20000000, P_GPLL0, 10, 1, 4),
1081 F(25000000, P_GPLL0, 16, 1, 2),
1082 F(50000000, P_GPLL0, 16, 0, 0),
1083 F(100000000, P_GPLL0, 8, 0, 0),
1084 F(177770000, P_GPLL0, 4.5, 0, 0),
1085 F(200000000, P_GPLL0, 4, 0, 0),
1086 { }
1087 };
1088
1089 static struct clk_rcg2 sdcc2_apps_clk_src = {
1090 .cmd_rcgr = 0x43004,
1091 .hid_width = 5,
1092 .mnd_width = 8,
1093 .freq_tbl = ftbl_sdcc2_apps_clk_src,
1094 .parent_map = gcc_xo_gpll0_map,
1095 .clkr.hw.init = &(struct clk_init_data) {
1096 .name = "sdcc2_apps_clk_src",
1097 .parent_data = gcc_xo_gpll0_data,
1098 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
1099 .ops = &clk_rcg2_floor_ops,
1100 }
1101 };
1102
1103 static const struct freq_tbl ftbl_usb_hs_system_clk_src[] = {
1104 F(80000000, P_GPLL0, 10, 0, 0),
1105 F(100000000, P_GPLL0, 8, 0, 0),
1106 F(133330000, P_GPLL0, 6, 0, 0),
1107 F(177780000, P_GPLL0, 4.5, 0, 0),
1108 { }
1109 };
1110
1111 static struct clk_rcg2 usb_hs_system_clk_src = {
1112 .cmd_rcgr = 0x41010,
1113 .hid_width = 5,
1114 .parent_map = gcc_xo_gpll0_map,
1115 .freq_tbl = ftbl_usb_hs_system_clk_src,
1116 .clkr.hw.init = &(struct clk_init_data){
1117 .name = "usb_hs_system_clk_src",
1118 .parent_data = gcc_xo_gpll0_data,
1119 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
1120 .ops = &clk_rcg2_ops,
1121 },
1122 };
1123
1124 static const struct freq_tbl ftbl_vcodec0_clk_src[] = {
1125 F(133330000, P_GPLL0, 6, 0, 0),
1126 F(180000000, P_GPLL6, 6, 0, 0),
1127 F(228570000, P_GPLL0, 3.5, 0, 0),
1128 F(266670000, P_GPLL0, 3, 0, 0),
1129 F(308570000, P_GPLL6, 3.5, 0, 0),
1130 F(329140000, P_GPLL4, 3.5, 0, 0),
1131 F(360000000, P_GPLL6, 3, 0, 0),
1132 { }
1133 };
1134
1135 static struct clk_rcg2 vcodec0_clk_src = {
1136 .cmd_rcgr = 0x4c000,
1137 .hid_width = 5,
1138 .freq_tbl = ftbl_vcodec0_clk_src,
1139 .parent_map = gcc_xo_gpll0_gpll6_gpll4_map,
1140 .clkr.hw.init = &(struct clk_init_data) {
1141 .name = "vcodec0_clk_src",
1142 .parent_data = gcc_xo_gpll0_gpll6_gpll4_data,
1143 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll4_data),
1144 .ops = &clk_rcg2_ops,
1145 }
1146 };
1147
1148 static const struct freq_tbl ftbl_vfe_clk_src[] = {
1149 F(50000000, P_GPLL0, 16, 0, 0),
1150 F(80000000, P_GPLL0, 10, 0, 0),
1151 F(100000000, P_GPLL0, 8, 0, 0),
1152 F(133330000, P_GPLL0, 6, 0, 0),
1153 F(160000000, P_GPLL0, 5, 0, 0),
1154 F(200000000, P_GPLL0, 4, 0, 0),
1155 F(266670000, P_GPLL0, 3, 0, 0),
1156 F(308570000, P_GPLL6, 3.5, 0, 0),
1157 F(320000000, P_GPLL0, 2.5, 0, 0),
1158 F(329140000, P_GPLL4, 3.5, 0, 0),
1159 F(360000000, P_GPLL6, 3, 0, 0),
1160 { }
1161 };
1162
1163 static struct clk_rcg2 vfe0_clk_src = {
1164 .cmd_rcgr = 0x58000,
1165 .hid_width = 5,
1166 .freq_tbl = ftbl_vfe_clk_src,
1167 .parent_map = gcc_xo_gpll0_gpll6_gpll4_map,
1168 .clkr.hw.init = &(struct clk_init_data) {
1169 .name = "vfe0_clk_src",
1170 .parent_data = gcc_xo_gpll0_gpll6_gpll4_data,
1171 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll4_data),
1172 .ops = &clk_rcg2_ops,
1173 }
1174 };
1175
1176 static struct clk_rcg2 vfe1_clk_src = {
1177 .cmd_rcgr = 0x58054,
1178 .hid_width = 5,
1179 .freq_tbl = ftbl_vfe_clk_src,
1180 .parent_map = gcc_xo_gpll0_gpll6_gpll4_map,
1181 .clkr.hw.init = &(struct clk_init_data) {
1182 .name = "vfe1_clk_src",
1183 .parent_data = gcc_xo_gpll0_gpll6_gpll4_data,
1184 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll4_data),
1185 .ops = &clk_rcg2_ops,
1186 }
1187 };
1188
1189 static const struct freq_tbl ftbl_vsync_clk_src[] = {
1190 F(19200000, P_XO, 1, 0, 0),
1191 { }
1192 };
1193
1194 static struct clk_rcg2 vsync_clk_src = {
1195 .cmd_rcgr = 0x4d02c,
1196 .hid_width = 5,
1197 .freq_tbl = ftbl_vsync_clk_src,
1198 .parent_map = gcc_xo_gpll0_out_aux_map,
1199 .clkr.hw.init = &(struct clk_init_data) {
1200 .name = "vsync_clk_src",
1201 .parent_data = gcc_xo_gpll0_data,
1202 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
1203 .ops = &clk_rcg2_ops,
1204 }
1205 };
1206
1207 static struct clk_branch gcc_apss_tcu_clk = {
1208 .halt_reg = 0x12018,
1209 .halt_check = BRANCH_HALT_VOTED,
1210 .clkr = {
1211 .enable_reg = 0x4500c,
1212 .enable_mask = BIT(1),
1213 .hw.init = &(struct clk_init_data) {
1214 .name = "gcc_apss_tcu_clk",
1215 .ops = &clk_branch2_ops,
1216 }
1217 }
1218 };
1219
1220 static struct clk_branch gcc_bimc_gfx_clk = {
1221 .halt_reg = 0x59034,
1222 .halt_check = BRANCH_HALT,
1223 .clkr = {
1224 .enable_reg = 0x59034,
1225 .enable_mask = BIT(0),
1226 .hw.init = &(struct clk_init_data) {
1227 .name = "gcc_bimc_gfx_clk",
1228 .ops = &clk_branch2_ops,
1229 }
1230 }
1231 };
1232
1233 static struct clk_branch gcc_bimc_gpu_clk = {
1234 .halt_reg = 0x59030,
1235 .halt_check = BRANCH_HALT,
1236 .clkr = {
1237 .enable_reg = 0x59030,
1238 .enable_mask = BIT(0),
1239 .hw.init = &(struct clk_init_data) {
1240 .name = "gcc_bimc_gpu_clk",
1241 .ops = &clk_branch2_ops,
1242 }
1243 }
1244 };
1245
1246 static struct clk_branch gcc_blsp1_ahb_clk = {
1247 .halt_reg = 0x01008,
1248 .halt_check = BRANCH_HALT_VOTED,
1249 .clkr = {
1250 .enable_reg = 0x45004,
1251 .enable_mask = BIT(10),
1252 .hw.init = &(struct clk_init_data) {
1253 .name = "gcc_blsp1_ahb_clk",
1254 .ops = &clk_branch2_ops,
1255 }
1256 }
1257 };
1258
1259 static struct clk_branch gcc_blsp2_ahb_clk = {
1260 .halt_reg = 0x0b008,
1261 .halt_check = BRANCH_HALT_VOTED,
1262 .clkr = {
1263 .enable_reg = 0x45004,
1264 .enable_mask = BIT(20),
1265 .hw.init = &(struct clk_init_data) {
1266 .name = "gcc_blsp2_ahb_clk",
1267 .ops = &clk_branch2_ops,
1268 }
1269 }
1270 };
1271
1272 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1273 .halt_reg = 0x03010,
1274 .halt_check = BRANCH_HALT,
1275 .clkr = {
1276 .enable_reg = 0x03010,
1277 .enable_mask = BIT(0),
1278 .hw.init = &(struct clk_init_data) {
1279 .name = "gcc_blsp1_qup2_i2c_apps_clk",
1280 .parent_hws = (const struct clk_hw*[]){
1281 &blsp1_qup2_i2c_apps_clk_src.clkr.hw,
1282 },
1283 .num_parents = 1,
1284 .ops = &clk_branch2_ops,
1285 .flags = CLK_SET_RATE_PARENT,
1286 }
1287 }
1288 };
1289
1290 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1291 .halt_reg = 0x04020,
1292 .halt_check = BRANCH_HALT,
1293 .clkr = {
1294 .enable_reg = 0x04020,
1295 .enable_mask = BIT(0),
1296 .hw.init = &(struct clk_init_data) {
1297 .name = "gcc_blsp1_qup3_i2c_apps_clk",
1298 .parent_hws = (const struct clk_hw*[]){
1299 &blsp1_qup3_i2c_apps_clk_src.clkr.hw,
1300 },
1301 .num_parents = 1,
1302 .ops = &clk_branch2_ops,
1303 .flags = CLK_SET_RATE_PARENT,
1304 }
1305 }
1306 };
1307
1308 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1309 .halt_reg = 0x05020,
1310 .halt_check = BRANCH_HALT,
1311 .clkr = {
1312 .enable_reg = 0x05020,
1313 .enable_mask = BIT(0),
1314 .hw.init = &(struct clk_init_data) {
1315 .name = "gcc_blsp1_qup4_i2c_apps_clk",
1316 .parent_hws = (const struct clk_hw*[]){
1317 &blsp1_qup4_i2c_apps_clk_src.clkr.hw,
1318 },
1319 .num_parents = 1,
1320 .ops = &clk_branch2_ops,
1321 .flags = CLK_SET_RATE_PARENT,
1322 }
1323 }
1324 };
1325
1326 static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
1327 .halt_reg = 0x0c008,
1328 .halt_check = BRANCH_HALT,
1329 .clkr = {
1330 .enable_reg = 0x0c008,
1331 .enable_mask = BIT(0),
1332 .hw.init = &(struct clk_init_data) {
1333 .name = "gcc_blsp2_qup1_i2c_apps_clk",
1334 .parent_hws = (const struct clk_hw*[]){
1335 &blsp2_qup1_i2c_apps_clk_src.clkr.hw,
1336 },
1337 .num_parents = 1,
1338 .ops = &clk_branch2_ops,
1339 .flags = CLK_SET_RATE_PARENT,
1340 }
1341 }
1342 };
1343
1344 static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
1345 .halt_reg = 0x0d010,
1346 .halt_check = BRANCH_HALT,
1347 .clkr = {
1348 .enable_reg = 0x0d010,
1349 .enable_mask = BIT(0),
1350 .hw.init = &(struct clk_init_data) {
1351 .name = "gcc_blsp2_qup2_i2c_apps_clk",
1352 .parent_hws = (const struct clk_hw*[]){
1353 &blsp2_qup2_i2c_apps_clk_src.clkr.hw,
1354 },
1355 .num_parents = 1,
1356 .ops = &clk_branch2_ops,
1357 .flags = CLK_SET_RATE_PARENT,
1358 }
1359 }
1360 };
1361
1362 static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
1363 .halt_reg = 0x0f020,
1364 .halt_check = BRANCH_HALT,
1365 .clkr = {
1366 .enable_reg = 0x0f020,
1367 .enable_mask = BIT(0),
1368 .hw.init = &(struct clk_init_data) {
1369 .name = "gcc_blsp2_qup3_i2c_apps_clk",
1370 .parent_hws = (const struct clk_hw*[]){
1371 &blsp2_qup3_i2c_apps_clk_src.clkr.hw,
1372 },
1373 .num_parents = 1,
1374 .ops = &clk_branch2_ops,
1375 .flags = CLK_SET_RATE_PARENT,
1376 }
1377 }
1378 };
1379
1380 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1381 .halt_reg = 0x0300c,
1382 .halt_check = BRANCH_HALT,
1383 .clkr = {
1384 .enable_reg = 0x0300c,
1385 .enable_mask = BIT(0),
1386 .hw.init = &(struct clk_init_data) {
1387 .name = "gcc_blsp1_qup2_spi_apps_clk",
1388 .parent_hws = (const struct clk_hw*[]){
1389 &blsp1_qup2_spi_apps_clk_src.clkr.hw,
1390 },
1391 .num_parents = 1,
1392 .ops = &clk_branch2_ops,
1393 .flags = CLK_SET_RATE_PARENT,
1394 }
1395 }
1396 };
1397
1398 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1399 .halt_reg = 0x0401c,
1400 .halt_check = BRANCH_HALT,
1401 .clkr = {
1402 .enable_reg = 0x0401c,
1403 .enable_mask = BIT(0),
1404 .hw.init = &(struct clk_init_data) {
1405 .name = "gcc_blsp1_qup3_spi_apps_clk",
1406 .parent_hws = (const struct clk_hw*[]){
1407 &blsp1_qup3_spi_apps_clk_src.clkr.hw,
1408 },
1409 .num_parents = 1,
1410 .ops = &clk_branch2_ops,
1411 .flags = CLK_SET_RATE_PARENT,
1412 }
1413 }
1414 };
1415
1416 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1417 .halt_reg = 0x0501c,
1418 .halt_check = BRANCH_HALT,
1419 .clkr = {
1420 .enable_reg = 0x0501c,
1421 .enable_mask = BIT(0),
1422 .hw.init = &(struct clk_init_data) {
1423 .name = "gcc_blsp1_qup4_spi_apps_clk",
1424 .parent_hws = (const struct clk_hw*[]){
1425 &blsp1_qup4_spi_apps_clk_src.clkr.hw,
1426 },
1427 .num_parents = 1,
1428 .ops = &clk_branch2_ops,
1429 .flags = CLK_SET_RATE_PARENT,
1430 }
1431 }
1432 };
1433
1434 static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
1435 .halt_reg = 0x0c004,
1436 .halt_check = BRANCH_HALT,
1437 .clkr = {
1438 .enable_reg = 0x0c004,
1439 .enable_mask = BIT(0),
1440 .hw.init = &(struct clk_init_data) {
1441 .name = "gcc_blsp2_qup1_spi_apps_clk",
1442 .parent_hws = (const struct clk_hw*[]){
1443 &blsp2_qup1_spi_apps_clk_src.clkr.hw,
1444 },
1445 .num_parents = 1,
1446 .ops = &clk_branch2_ops,
1447 .flags = CLK_SET_RATE_PARENT,
1448 }
1449 }
1450 };
1451
1452 static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
1453 .halt_reg = 0x0d00c,
1454 .halt_check = BRANCH_HALT,
1455 .clkr = {
1456 .enable_reg = 0x0d00c,
1457 .enable_mask = BIT(0),
1458 .hw.init = &(struct clk_init_data) {
1459 .name = "gcc_blsp2_qup2_spi_apps_clk",
1460 .parent_hws = (const struct clk_hw*[]){
1461 &blsp2_qup2_spi_apps_clk_src.clkr.hw,
1462 },
1463 .num_parents = 1,
1464 .ops = &clk_branch2_ops,
1465 .flags = CLK_SET_RATE_PARENT,
1466 }
1467 }
1468 };
1469
1470 static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
1471 .halt_reg = 0x0f01c,
1472 .halt_check = BRANCH_HALT,
1473 .clkr = {
1474 .enable_reg = 0x0f01c,
1475 .enable_mask = BIT(0),
1476 .hw.init = &(struct clk_init_data) {
1477 .name = "gcc_blsp2_qup3_spi_apps_clk",
1478 .parent_hws = (const struct clk_hw*[]){
1479 &blsp2_qup3_spi_apps_clk_src.clkr.hw,
1480 },
1481 .num_parents = 1,
1482 .ops = &clk_branch2_ops,
1483 .flags = CLK_SET_RATE_PARENT,
1484 }
1485 }
1486 };
1487
1488 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1489 .halt_reg = 0x0203c,
1490 .halt_check = BRANCH_HALT,
1491 .clkr = {
1492 .enable_reg = 0x0203c,
1493 .enable_mask = BIT(0),
1494 .hw.init = &(struct clk_init_data) {
1495 .name = "gcc_blsp1_uart1_apps_clk",
1496 .parent_hws = (const struct clk_hw*[]){
1497 &blsp1_uart1_apps_clk_src.clkr.hw,
1498 },
1499 .num_parents = 1,
1500 .ops = &clk_branch2_ops,
1501 .flags = CLK_SET_RATE_PARENT,
1502 }
1503 }
1504 };
1505
1506 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1507 .halt_reg = 0x0302c,
1508 .halt_check = BRANCH_HALT,
1509 .clkr = {
1510 .enable_reg = 0x0302c,
1511 .enable_mask = BIT(0),
1512 .hw.init = &(struct clk_init_data) {
1513 .name = "gcc_blsp1_uart2_apps_clk",
1514 .parent_hws = (const struct clk_hw*[]){
1515 &blsp1_uart2_apps_clk_src.clkr.hw,
1516 },
1517 .num_parents = 1,
1518 .ops = &clk_branch2_ops,
1519 .flags = CLK_SET_RATE_PARENT,
1520 }
1521 }
1522 };
1523
1524 static struct clk_branch gcc_blsp2_uart1_apps_clk = {
1525 .halt_reg = 0x0c03c,
1526 .halt_check = BRANCH_HALT,
1527 .clkr = {
1528 .enable_reg = 0x0c03c,
1529 .enable_mask = BIT(0),
1530 .hw.init = &(struct clk_init_data) {
1531 .name = "gcc_blsp2_uart1_apps_clk",
1532 .parent_hws = (const struct clk_hw*[]){
1533 &blsp2_uart1_apps_clk_src.clkr.hw,
1534 },
1535 .num_parents = 1,
1536 .ops = &clk_branch2_ops,
1537 .flags = CLK_SET_RATE_PARENT,
1538 }
1539 }
1540 };
1541
1542 static struct clk_branch gcc_blsp2_uart2_apps_clk = {
1543 .halt_reg = 0x0d02c,
1544 .halt_check = BRANCH_HALT,
1545 .clkr = {
1546 .enable_reg = 0x0d02c,
1547 .enable_mask = BIT(0),
1548 .hw.init = &(struct clk_init_data) {
1549 .name = "gcc_blsp2_uart2_apps_clk",
1550 .parent_hws = (const struct clk_hw*[]){
1551 &blsp2_uart2_apps_clk_src.clkr.hw,
1552 },
1553 .num_parents = 1,
1554 .ops = &clk_branch2_ops,
1555 .flags = CLK_SET_RATE_PARENT,
1556 }
1557 }
1558 };
1559
1560 static struct clk_branch gcc_boot_rom_ahb_clk = {
1561 .halt_reg = 0x1300c,
1562 .halt_check = BRANCH_HALT_VOTED,
1563 .clkr = {
1564 .enable_reg = 0x45004,
1565 .enable_mask = BIT(7),
1566 .hw.init = &(struct clk_init_data) {
1567 .name = "gcc_boot_rom_ahb_clk",
1568 .ops = &clk_branch2_ops,
1569 }
1570 }
1571 };
1572
1573 static struct clk_branch gcc_camss_ahb_clk = {
1574 .halt_reg = 0x56004,
1575 .halt_check = BRANCH_HALT,
1576 .clkr = {
1577 .enable_reg = 0x56004,
1578 .enable_mask = BIT(0),
1579 .hw.init = &(struct clk_init_data) {
1580 .name = "gcc_camss_ahb_clk",
1581 .ops = &clk_branch2_ops,
1582 }
1583 }
1584 };
1585
1586 static struct clk_branch gcc_camss_cci_ahb_clk = {
1587 .halt_reg = 0x5101c,
1588 .halt_check = BRANCH_HALT,
1589 .clkr = {
1590 .enable_reg = 0x5101c,
1591 .enable_mask = BIT(0),
1592 .hw.init = &(struct clk_init_data) {
1593 .name = "gcc_camss_cci_ahb_clk",
1594 .parent_hws = (const struct clk_hw*[]){
1595 &camss_top_ahb_clk_src.clkr.hw,
1596 },
1597 .num_parents = 1,
1598 .ops = &clk_branch2_ops,
1599 .flags = CLK_SET_RATE_PARENT,
1600 }
1601 }
1602 };
1603
1604 static struct clk_branch gcc_camss_cci_clk = {
1605 .halt_reg = 0x51018,
1606 .halt_check = BRANCH_HALT,
1607 .clkr = {
1608 .enable_reg = 0x51018,
1609 .enable_mask = BIT(0),
1610 .hw.init = &(struct clk_init_data) {
1611 .name = "gcc_camss_cci_clk",
1612 .parent_hws = (const struct clk_hw*[]){
1613 &cci_clk_src.clkr.hw,
1614 },
1615 .num_parents = 1,
1616 .ops = &clk_branch2_ops,
1617 .flags = CLK_SET_RATE_PARENT,
1618 }
1619 }
1620 };
1621
1622 static struct clk_branch gcc_camss_cpp_ahb_clk = {
1623 .halt_reg = 0x58040,
1624 .halt_check = BRANCH_HALT,
1625 .clkr = {
1626 .enable_reg = 0x58040,
1627 .enable_mask = BIT(0),
1628 .hw.init = &(struct clk_init_data) {
1629 .name = "gcc_camss_cpp_ahb_clk",
1630 .parent_hws = (const struct clk_hw*[]){
1631 &camss_top_ahb_clk_src.clkr.hw,
1632 },
1633 .num_parents = 1,
1634 .ops = &clk_branch2_ops,
1635 .flags = CLK_SET_RATE_PARENT,
1636 }
1637 }
1638 };
1639
1640 static struct clk_branch gcc_camss_cpp_clk = {
1641 .halt_reg = 0x5803c,
1642 .halt_check = BRANCH_HALT,
1643 .clkr = {
1644 .enable_reg = 0x5803c,
1645 .enable_mask = BIT(0),
1646 .hw.init = &(struct clk_init_data) {
1647 .name = "gcc_camss_cpp_clk",
1648 .parent_hws = (const struct clk_hw*[]){
1649 &cpp_clk_src.clkr.hw,
1650 },
1651 .num_parents = 1,
1652 .ops = &clk_branch2_ops,
1653 .flags = CLK_SET_RATE_PARENT,
1654 }
1655 }
1656 };
1657
1658 static struct clk_branch gcc_camss_csi0_ahb_clk = {
1659 .halt_reg = 0x4e040,
1660 .halt_check = BRANCH_HALT,
1661 .clkr = {
1662 .enable_reg = 0x4e040,
1663 .enable_mask = BIT(0),
1664 .hw.init = &(struct clk_init_data) {
1665 .name = "gcc_camss_csi0_ahb_clk",
1666 .parent_hws = (const struct clk_hw*[]){
1667 &camss_top_ahb_clk_src.clkr.hw,
1668 },
1669 .num_parents = 1,
1670 .ops = &clk_branch2_ops,
1671 .flags = CLK_SET_RATE_PARENT,
1672 }
1673 }
1674 };
1675
1676 static struct clk_branch gcc_camss_csi1_ahb_clk = {
1677 .halt_reg = 0x4f040,
1678 .halt_check = BRANCH_HALT,
1679 .clkr = {
1680 .enable_reg = 0x4f040,
1681 .enable_mask = BIT(0),
1682 .hw.init = &(struct clk_init_data) {
1683 .name = "gcc_camss_csi1_ahb_clk",
1684 .parent_hws = (const struct clk_hw*[]){
1685 &camss_top_ahb_clk_src.clkr.hw,
1686 },
1687 .num_parents = 1,
1688 .ops = &clk_branch2_ops,
1689 .flags = CLK_SET_RATE_PARENT,
1690 }
1691 }
1692 };
1693
1694 static struct clk_branch gcc_camss_csi2_ahb_clk = {
1695 .halt_reg = 0x3c040,
1696 .halt_check = BRANCH_HALT,
1697 .clkr = {
1698 .enable_reg = 0x3c040,
1699 .enable_mask = BIT(0),
1700 .hw.init = &(struct clk_init_data) {
1701 .name = "gcc_camss_csi2_ahb_clk",
1702 .parent_hws = (const struct clk_hw*[]){
1703 &camss_top_ahb_clk_src.clkr.hw,
1704 },
1705 .num_parents = 1,
1706 .ops = &clk_branch2_ops,
1707 .flags = CLK_SET_RATE_PARENT,
1708 }
1709 }
1710 };
1711
1712 static struct clk_branch gcc_camss_csi0_clk = {
1713 .halt_reg = 0x4e03c,
1714 .halt_check = BRANCH_HALT,
1715 .clkr = {
1716 .enable_reg = 0x4e03c,
1717 .enable_mask = BIT(0),
1718 .hw.init = &(struct clk_init_data) {
1719 .name = "gcc_camss_csi0_clk",
1720 .parent_hws = (const struct clk_hw*[]){
1721 &csi0_clk_src.clkr.hw,
1722 },
1723 .num_parents = 1,
1724 .ops = &clk_branch2_ops,
1725 .flags = CLK_SET_RATE_PARENT,
1726 }
1727 }
1728 };
1729
1730 static struct clk_branch gcc_camss_csi1_clk = {
1731 .halt_reg = 0x4f03c,
1732 .halt_check = BRANCH_HALT,
1733 .clkr = {
1734 .enable_reg = 0x4f03c,
1735 .enable_mask = BIT(0),
1736 .hw.init = &(struct clk_init_data) {
1737 .name = "gcc_camss_csi1_clk",
1738 .parent_hws = (const struct clk_hw*[]){
1739 &csi1_clk_src.clkr.hw,
1740 },
1741 .num_parents = 1,
1742 .ops = &clk_branch2_ops,
1743 .flags = CLK_SET_RATE_PARENT,
1744 }
1745 }
1746 };
1747
1748 static struct clk_branch gcc_camss_csi2_clk = {
1749 .halt_reg = 0x3c03c,
1750 .halt_check = BRANCH_HALT,
1751 .clkr = {
1752 .enable_reg = 0x3c03c,
1753 .enable_mask = BIT(0),
1754 .hw.init = &(struct clk_init_data) {
1755 .name = "gcc_camss_csi2_clk",
1756 .parent_hws = (const struct clk_hw*[]){
1757 &csi2_clk_src.clkr.hw,
1758 },
1759 .num_parents = 1,
1760 .ops = &clk_branch2_ops,
1761 .flags = CLK_SET_RATE_PARENT,
1762 }
1763 }
1764 };
1765
1766 static struct clk_branch gcc_camss_csi0phy_clk = {
1767 .halt_reg = 0x4e048,
1768 .halt_check = BRANCH_HALT,
1769 .clkr = {
1770 .enable_reg = 0x4e048,
1771 .enable_mask = BIT(0),
1772 .hw.init = &(struct clk_init_data) {
1773 .name = "gcc_camss_csi0phy_clk",
1774 .parent_hws = (const struct clk_hw*[]){
1775 &csi0_clk_src.clkr.hw,
1776 },
1777 .num_parents = 1,
1778 .ops = &clk_branch2_ops,
1779 .flags = CLK_SET_RATE_PARENT,
1780 }
1781 }
1782 };
1783
1784 static struct clk_branch gcc_camss_csi1phy_clk = {
1785 .halt_reg = 0x4f048,
1786 .halt_check = BRANCH_HALT,
1787 .clkr = {
1788 .enable_reg = 0x4f048,
1789 .enable_mask = BIT(0),
1790 .hw.init = &(struct clk_init_data) {
1791 .name = "gcc_camss_csi1phy_clk",
1792 .parent_hws = (const struct clk_hw*[]){
1793 &csi1_clk_src.clkr.hw,
1794 },
1795 .num_parents = 1,
1796 .ops = &clk_branch2_ops,
1797 .flags = CLK_SET_RATE_PARENT,
1798 }
1799 }
1800 };
1801
1802 static struct clk_branch gcc_camss_csi2phy_clk = {
1803 .halt_reg = 0x3c048,
1804 .halt_check = BRANCH_HALT,
1805 .clkr = {
1806 .enable_reg = 0x3c048,
1807 .enable_mask = BIT(0),
1808 .hw.init = &(struct clk_init_data) {
1809 .name = "gcc_camss_csi2phy_clk",
1810 .parent_hws = (const struct clk_hw*[]){
1811 &csi2_clk_src.clkr.hw,
1812 },
1813 .num_parents = 1,
1814 .ops = &clk_branch2_ops,
1815 .flags = CLK_SET_RATE_PARENT,
1816 }
1817 }
1818 };
1819
1820 static struct clk_branch gcc_camss_csi0phytimer_clk = {
1821 .halt_reg = 0x4e01c,
1822 .halt_check = BRANCH_HALT,
1823 .clkr = {
1824 .enable_reg = 0x4e01c,
1825 .enable_mask = BIT(0),
1826 .hw.init = &(struct clk_init_data) {
1827 .name = "gcc_camss_csi0phytimer_clk",
1828 .parent_hws = (const struct clk_hw*[]){
1829 &csi0phytimer_clk_src.clkr.hw,
1830 },
1831 .num_parents = 1,
1832 .ops = &clk_branch2_ops,
1833 .flags = CLK_SET_RATE_PARENT,
1834 }
1835 }
1836 };
1837
1838 static struct clk_branch gcc_camss_csi1phytimer_clk = {
1839 .halt_reg = 0x4f01c,
1840 .halt_check = BRANCH_HALT,
1841 .clkr = {
1842 .enable_reg = 0x4f01c,
1843 .enable_mask = BIT(0),
1844 .hw.init = &(struct clk_init_data) {
1845 .name = "gcc_camss_csi1phytimer_clk",
1846 .parent_hws = (const struct clk_hw*[]){
1847 &csi1phytimer_clk_src.clkr.hw,
1848 },
1849 .num_parents = 1,
1850 .ops = &clk_branch2_ops,
1851 .flags = CLK_SET_RATE_PARENT,
1852 }
1853 }
1854 };
1855
1856 static struct clk_branch gcc_camss_csi0pix_clk = {
1857 .halt_reg = 0x4e058,
1858 .halt_check = BRANCH_HALT,
1859 .clkr = {
1860 .enable_reg = 0x4e058,
1861 .enable_mask = BIT(0),
1862 .hw.init = &(struct clk_init_data) {
1863 .name = "gcc_camss_csi0pix_clk",
1864 .parent_hws = (const struct clk_hw*[]){
1865 &csi0_clk_src.clkr.hw,
1866 },
1867 .num_parents = 1,
1868 .ops = &clk_branch2_ops,
1869 .flags = CLK_SET_RATE_PARENT,
1870 }
1871 }
1872 };
1873
1874 static struct clk_branch gcc_camss_csi1pix_clk = {
1875 .halt_reg = 0x4f058,
1876 .halt_check = BRANCH_HALT,
1877 .clkr = {
1878 .enable_reg = 0x4f058,
1879 .enable_mask = BIT(0),
1880 .hw.init = &(struct clk_init_data) {
1881 .name = "gcc_camss_csi1pix_clk",
1882 .parent_hws = (const struct clk_hw*[]){
1883 &csi1_clk_src.clkr.hw,
1884 },
1885 .num_parents = 1,
1886 .ops = &clk_branch2_ops,
1887 .flags = CLK_SET_RATE_PARENT,
1888 }
1889 }
1890 };
1891
1892 static struct clk_branch gcc_camss_csi2pix_clk = {
1893 .halt_reg = 0x3c058,
1894 .halt_check = BRANCH_HALT,
1895 .clkr = {
1896 .enable_reg = 0x3c058,
1897 .enable_mask = BIT(0),
1898 .hw.init = &(struct clk_init_data) {
1899 .name = "gcc_camss_csi2pix_clk",
1900 .parent_hws = (const struct clk_hw*[]){
1901 &csi2_clk_src.clkr.hw,
1902 },
1903 .num_parents = 1,
1904 .ops = &clk_branch2_ops,
1905 .flags = CLK_SET_RATE_PARENT,
1906 }
1907 }
1908 };
1909
1910 static struct clk_branch gcc_camss_csi0rdi_clk = {
1911 .halt_reg = 0x4e050,
1912 .halt_check = BRANCH_HALT,
1913 .clkr = {
1914 .enable_reg = 0x4e050,
1915 .enable_mask = BIT(0),
1916 .hw.init = &(struct clk_init_data) {
1917 .name = "gcc_camss_csi0rdi_clk",
1918 .parent_hws = (const struct clk_hw*[]){
1919 &csi0_clk_src.clkr.hw,
1920 },
1921 .num_parents = 1,
1922 .ops = &clk_branch2_ops,
1923 .flags = CLK_SET_RATE_PARENT,
1924 }
1925 }
1926 };
1927
1928 static struct clk_branch gcc_camss_csi1rdi_clk = {
1929 .halt_reg = 0x4f050,
1930 .halt_check = BRANCH_HALT,
1931 .clkr = {
1932 .enable_reg = 0x4f050,
1933 .enable_mask = BIT(0),
1934 .hw.init = &(struct clk_init_data) {
1935 .name = "gcc_camss_csi1rdi_clk",
1936 .parent_hws = (const struct clk_hw*[]){
1937 &csi1_clk_src.clkr.hw,
1938 },
1939 .num_parents = 1,
1940 .ops = &clk_branch2_ops,
1941 .flags = CLK_SET_RATE_PARENT,
1942 }
1943 }
1944 };
1945
1946 static struct clk_branch gcc_camss_csi2rdi_clk = {
1947 .halt_reg = 0x3c050,
1948 .halt_check = BRANCH_HALT,
1949 .clkr = {
1950 .enable_reg = 0x3c050,
1951 .enable_mask = BIT(0),
1952 .hw.init = &(struct clk_init_data) {
1953 .name = "gcc_camss_csi2rdi_clk",
1954 .parent_hws = (const struct clk_hw*[]){
1955 &csi2_clk_src.clkr.hw,
1956 },
1957 .num_parents = 1,
1958 .ops = &clk_branch2_ops,
1959 .flags = CLK_SET_RATE_PARENT,
1960 }
1961 }
1962 };
1963
1964 static struct clk_branch gcc_camss_csi_vfe0_clk = {
1965 .halt_reg = 0x58050,
1966 .halt_check = BRANCH_HALT,
1967 .clkr = {
1968 .enable_reg = 0x58050,
1969 .enable_mask = BIT(0),
1970 .hw.init = &(struct clk_init_data) {
1971 .name = "gcc_camss_csi_vfe0_clk",
1972 .parent_hws = (const struct clk_hw*[]){
1973 &vfe0_clk_src.clkr.hw,
1974 },
1975 .num_parents = 1,
1976 .ops = &clk_branch2_ops,
1977 .flags = CLK_SET_RATE_PARENT,
1978 }
1979 }
1980 };
1981
1982 static struct clk_branch gcc_camss_csi_vfe1_clk = {
1983 .halt_reg = 0x58074,
1984 .halt_check = BRANCH_HALT,
1985 .clkr = {
1986 .enable_reg = 0x58074,
1987 .enable_mask = BIT(0),
1988 .hw.init = &(struct clk_init_data) {
1989 .name = "gcc_camss_csi_vfe1_clk",
1990 .parent_hws = (const struct clk_hw*[]){
1991 &vfe1_clk_src.clkr.hw,
1992 },
1993 .num_parents = 1,
1994 .ops = &clk_branch2_ops,
1995 .flags = CLK_SET_RATE_PARENT,
1996 }
1997 }
1998 };
1999
2000 static struct clk_branch gcc_camss_gp0_clk = {
2001 .halt_reg = 0x54018,
2002 .halt_check = BRANCH_HALT,
2003 .clkr = {
2004 .enable_reg = 0x54018,
2005 .enable_mask = BIT(0),
2006 .hw.init = &(struct clk_init_data) {
2007 .name = "gcc_camss_gp0_clk",
2008 .parent_hws = (const struct clk_hw*[]){
2009 &camss_gp0_clk_src.clkr.hw,
2010 },
2011 .num_parents = 1,
2012 .ops = &clk_branch2_ops,
2013 .flags = CLK_SET_RATE_PARENT,
2014 }
2015 }
2016 };
2017
2018 static struct clk_branch gcc_camss_gp1_clk = {
2019 .halt_reg = 0x55018,
2020 .halt_check = BRANCH_HALT,
2021 .clkr = {
2022 .enable_reg = 0x55018,
2023 .enable_mask = BIT(0),
2024 .hw.init = &(struct clk_init_data) {
2025 .name = "gcc_camss_gp1_clk",
2026 .parent_hws = (const struct clk_hw*[]){
2027 &camss_gp1_clk_src.clkr.hw,
2028 },
2029 .num_parents = 1,
2030 .ops = &clk_branch2_ops,
2031 .flags = CLK_SET_RATE_PARENT,
2032 }
2033 }
2034 };
2035
2036 static struct clk_branch gcc_camss_ispif_ahb_clk = {
2037 .halt_reg = 0x50004,
2038 .halt_check = BRANCH_HALT,
2039 .clkr = {
2040 .enable_reg = 0x50004,
2041 .enable_mask = BIT(0),
2042 .hw.init = &(struct clk_init_data) {
2043 .name = "gcc_camss_ispif_ahb_clk",
2044 .parent_hws = (const struct clk_hw*[]){
2045 &camss_top_ahb_clk_src.clkr.hw,
2046 },
2047 .num_parents = 1,
2048 .ops = &clk_branch2_ops,
2049 .flags = CLK_SET_RATE_PARENT,
2050 }
2051 }
2052 };
2053
2054 static struct clk_branch gcc_camss_jpeg0_clk = {
2055 .halt_reg = 0x57020,
2056 .halt_check = BRANCH_HALT,
2057 .clkr = {
2058 .enable_reg = 0x57020,
2059 .enable_mask = BIT(0),
2060 .hw.init = &(struct clk_init_data) {
2061 .name = "gcc_camss_jpeg0_clk",
2062 .parent_hws = (const struct clk_hw*[]){
2063 &jpeg0_clk_src.clkr.hw,
2064 },
2065 .num_parents = 1,
2066 .ops = &clk_branch2_ops,
2067 .flags = CLK_SET_RATE_PARENT,
2068 }
2069 }
2070 };
2071
2072 static struct clk_branch gcc_camss_jpeg_ahb_clk = {
2073 .halt_reg = 0x57024,
2074 .halt_check = BRANCH_HALT,
2075 .clkr = {
2076 .enable_reg = 0x57024,
2077 .enable_mask = BIT(0),
2078 .hw.init = &(struct clk_init_data) {
2079 .name = "gcc_camss_jpeg_ahb_clk",
2080 .parent_hws = (const struct clk_hw*[]){
2081 &camss_top_ahb_clk_src.clkr.hw,
2082 },
2083 .num_parents = 1,
2084 .ops = &clk_branch2_ops,
2085 .flags = CLK_SET_RATE_PARENT,
2086 }
2087 }
2088 };
2089
2090 static struct clk_branch gcc_camss_jpeg_axi_clk = {
2091 .halt_reg = 0x57028,
2092 .halt_check = BRANCH_HALT,
2093 .clkr = {
2094 .enable_reg = 0x57028,
2095 .enable_mask = BIT(0),
2096 .hw.init = &(struct clk_init_data) {
2097 .name = "gcc_camss_jpeg_axi_clk",
2098 .ops = &clk_branch2_ops,
2099 }
2100 }
2101 };
2102
2103 static struct clk_branch gcc_camss_mclk0_clk = {
2104 .halt_reg = 0x52018,
2105 .halt_check = BRANCH_HALT,
2106 .clkr = {
2107 .enable_reg = 0x52018,
2108 .enable_mask = BIT(0),
2109 .hw.init = &(struct clk_init_data) {
2110 .name = "gcc_camss_mclk0_clk",
2111 .parent_hws = (const struct clk_hw*[]){
2112 &mclk0_clk_src.clkr.hw,
2113 },
2114 .num_parents = 1,
2115 .ops = &clk_branch2_ops,
2116 .flags = CLK_SET_RATE_PARENT,
2117 }
2118 }
2119 };
2120
2121 static struct clk_branch gcc_camss_mclk1_clk = {
2122 .halt_reg = 0x53018,
2123 .halt_check = BRANCH_HALT,
2124 .clkr = {
2125 .enable_reg = 0x53018,
2126 .enable_mask = BIT(0),
2127 .hw.init = &(struct clk_init_data) {
2128 .name = "gcc_camss_mclk1_clk",
2129 .parent_hws = (const struct clk_hw*[]){
2130 &mclk1_clk_src.clkr.hw,
2131 },
2132 .num_parents = 1,
2133 .ops = &clk_branch2_ops,
2134 .flags = CLK_SET_RATE_PARENT,
2135 }
2136 }
2137 };
2138
2139 static struct clk_branch gcc_camss_mclk2_clk = {
2140 .halt_reg = 0x5c018,
2141 .halt_check = BRANCH_HALT,
2142 .clkr = {
2143 .enable_reg = 0x5c018,
2144 .enable_mask = BIT(0),
2145 .hw.init = &(struct clk_init_data) {
2146 .name = "gcc_camss_mclk2_clk",
2147 .parent_hws = (const struct clk_hw*[]){
2148 &mclk2_clk_src.clkr.hw,
2149 },
2150 .num_parents = 1,
2151 .ops = &clk_branch2_ops,
2152 .flags = CLK_SET_RATE_PARENT,
2153 }
2154 }
2155 };
2156
2157 static struct clk_branch gcc_camss_micro_ahb_clk = {
2158 .halt_reg = 0x5600c,
2159 .halt_check = BRANCH_HALT,
2160 .clkr = {
2161 .enable_reg = 0x5600c,
2162 .enable_mask = BIT(0),
2163 .hw.init = &(struct clk_init_data) {
2164 .name = "gcc_camss_micro_ahb_clk",
2165 .parent_hws = (const struct clk_hw*[]){
2166 &camss_top_ahb_clk_src.clkr.hw,
2167 },
2168 .num_parents = 1,
2169 .ops = &clk_branch2_ops,
2170 .flags = CLK_SET_RATE_PARENT,
2171 }
2172 }
2173 };
2174
2175 static struct clk_branch gcc_camss_top_ahb_clk = {
2176 .halt_reg = 0x5a014,
2177 .halt_check = BRANCH_HALT,
2178 .clkr = {
2179 .enable_reg = 0x5a014,
2180 .enable_mask = BIT(0),
2181 .hw.init = &(struct clk_init_data) {
2182 .name = "gcc_camss_top_ahb_clk",
2183 .parent_hws = (const struct clk_hw*[]){
2184 &camss_top_ahb_clk_src.clkr.hw,
2185 },
2186 .num_parents = 1,
2187 .ops = &clk_branch2_ops,
2188 .flags = CLK_SET_RATE_PARENT,
2189 }
2190 }
2191 };
2192
2193 static struct clk_branch gcc_camss_vfe0_ahb_clk = {
2194 .halt_reg = 0x58044,
2195 .halt_check = BRANCH_HALT,
2196 .clkr = {
2197 .enable_reg = 0x58044,
2198 .enable_mask = BIT(0),
2199 .hw.init = &(struct clk_init_data) {
2200 .name = "gcc_camss_vfe0_ahb_clk",
2201 .parent_hws = (const struct clk_hw*[]){
2202 &camss_top_ahb_clk_src.clkr.hw,
2203 },
2204 .num_parents = 1,
2205 .ops = &clk_branch2_ops,
2206 .flags = CLK_SET_RATE_PARENT,
2207 }
2208 }
2209 };
2210
2211 static struct clk_branch gcc_camss_vfe0_axi_clk = {
2212 .halt_reg = 0x58048,
2213 .halt_check = BRANCH_HALT,
2214 .clkr = {
2215 .enable_reg = 0x58048,
2216 .enable_mask = BIT(0),
2217 .hw.init = &(struct clk_init_data) {
2218 .name = "gcc_camss_vfe0_axi_clk",
2219 .ops = &clk_branch2_ops,
2220 }
2221 }
2222 };
2223
2224 static struct clk_branch gcc_camss_vfe0_clk = {
2225 .halt_reg = 0x58038,
2226 .halt_check = BRANCH_HALT,
2227 .clkr = {
2228 .enable_reg = 0x58038,
2229 .enable_mask = BIT(0),
2230 .hw.init = &(struct clk_init_data) {
2231 .name = "gcc_camss_vfe0_clk",
2232 .parent_hws = (const struct clk_hw*[]){
2233 &vfe0_clk_src.clkr.hw,
2234 },
2235 .num_parents = 1,
2236 .ops = &clk_branch2_ops,
2237 .flags = CLK_SET_RATE_PARENT,
2238 }
2239 }
2240 };
2241
2242 static struct clk_branch gcc_camss_vfe1_ahb_clk = {
2243 .halt_reg = 0x58060,
2244 .halt_check = BRANCH_HALT,
2245 .clkr = {
2246 .enable_reg = 0x58060,
2247 .enable_mask = BIT(0),
2248 .hw.init = &(struct clk_init_data) {
2249 .name = "gcc_camss_vfe1_ahb_clk",
2250 .parent_hws = (const struct clk_hw*[]){
2251 &camss_top_ahb_clk_src.clkr.hw,
2252 },
2253 .num_parents = 1,
2254 .ops = &clk_branch2_ops,
2255 .flags = CLK_SET_RATE_PARENT,
2256 }
2257 }
2258 };
2259
2260 static struct clk_branch gcc_camss_vfe1_axi_clk = {
2261 .halt_reg = 0x58068,
2262 .halt_check = BRANCH_HALT,
2263 .clkr = {
2264 .enable_reg = 0x58068,
2265 .enable_mask = BIT(0),
2266 .hw.init = &(struct clk_init_data) {
2267 .name = "gcc_camss_vfe1_axi_clk",
2268 .ops = &clk_branch2_ops,
2269 }
2270 }
2271 };
2272
2273 static struct clk_branch gcc_camss_vfe1_clk = {
2274 .halt_reg = 0x5805c,
2275 .halt_check = BRANCH_HALT,
2276 .clkr = {
2277 .enable_reg = 0x5805c,
2278 .enable_mask = BIT(0),
2279 .hw.init = &(struct clk_init_data) {
2280 .name = "gcc_camss_vfe1_clk",
2281 .parent_hws = (const struct clk_hw*[]){
2282 &vfe1_clk_src.clkr.hw,
2283 },
2284 .num_parents = 1,
2285 .ops = &clk_branch2_ops,
2286 .flags = CLK_SET_RATE_PARENT,
2287 }
2288 }
2289 };
2290
2291 static struct clk_branch gcc_cpp_tbu_clk = {
2292 .halt_reg = 0x12040,
2293 .halt_check = BRANCH_HALT_VOTED,
2294 .clkr = {
2295 .enable_reg = 0x4500c,
2296 .enable_mask = BIT(14),
2297 .hw.init = &(struct clk_init_data) {
2298 .name = "gcc_cpp_tbu_clk",
2299 .ops = &clk_branch2_ops,
2300 }
2301 }
2302 };
2303
2304 static struct clk_branch gcc_crypto_ahb_clk = {
2305 .halt_reg = 0x16024,
2306 .halt_check = BRANCH_HALT_VOTED,
2307 .clkr = {
2308 .enable_reg = 0x45004,
2309 .enable_mask = BIT(0),
2310 .hw.init = &(struct clk_init_data) {
2311 .name = "gcc_crypto_ahb_clk",
2312 .ops = &clk_branch2_ops,
2313 }
2314 }
2315 };
2316
2317 static struct clk_branch gcc_crypto_axi_clk = {
2318 .halt_reg = 0x16020,
2319 .halt_check = BRANCH_HALT_VOTED,
2320 .clkr = {
2321 .enable_reg = 0x45004,
2322 .enable_mask = BIT(1),
2323 .hw.init = &(struct clk_init_data) {
2324 .name = "gcc_crypto_axi_clk",
2325 .ops = &clk_branch2_ops,
2326 }
2327 }
2328 };
2329
2330 static struct clk_branch gcc_crypto_clk = {
2331 .halt_reg = 0x1601c,
2332 .halt_check = BRANCH_HALT_VOTED,
2333 .clkr = {
2334 .enable_reg = 0x45004,
2335 .enable_mask = BIT(2),
2336 .hw.init = &(struct clk_init_data) {
2337 .name = "gcc_crypto_clk",
2338 .parent_hws = (const struct clk_hw*[]){
2339 &crypto_clk_src.clkr.hw,
2340 },
2341 .num_parents = 1,
2342 .ops = &clk_branch2_ops,
2343 .flags = CLK_SET_RATE_PARENT,
2344 }
2345 }
2346 };
2347
2348 static struct clk_branch gcc_dcc_clk = {
2349 .halt_reg = 0x77004,
2350 .halt_check = BRANCH_HALT,
2351 .clkr = {
2352 .enable_reg = 0x77004,
2353 .enable_mask = BIT(0),
2354 .hw.init = &(struct clk_init_data) {
2355 .name = "gcc_dcc_clk",
2356 .ops = &clk_branch2_ops,
2357 }
2358 }
2359 };
2360
2361 static struct clk_branch gcc_gfx_tbu_clk = {
2362 .halt_reg = 0x12010,
2363 .halt_check = BRANCH_HALT_VOTED,
2364 .clkr = {
2365 .enable_reg = 0x4500c,
2366 .enable_mask = BIT(3),
2367 .hw.init = &(struct clk_init_data){
2368 .name = "gcc_gfx_tbu_clk",
2369 .ops = &clk_branch2_ops,
2370 },
2371 },
2372 };
2373
2374 static struct clk_branch gcc_gfx_tcu_clk = {
2375 .halt_reg = 0x12020,
2376 .halt_check = BRANCH_HALT_VOTED,
2377 .clkr = {
2378 .enable_reg = 0x4500c,
2379 .enable_mask = BIT(2),
2380 .hw.init = &(struct clk_init_data){
2381 .name = "gcc_gfx_tcu_clk",
2382 .ops = &clk_branch2_ops,
2383 },
2384 },
2385 };
2386
2387 static struct clk_branch gcc_gtcu_ahb_clk = {
2388 .halt_reg = 0x12044,
2389 .halt_check = BRANCH_HALT_VOTED,
2390 .clkr = {
2391 .enable_reg = 0x4500c,
2392 .enable_mask = BIT(13),
2393 .hw.init = &(struct clk_init_data){
2394 .name = "gcc_gtcu_ahb_clk",
2395 .ops = &clk_branch2_ops,
2396 },
2397 },
2398 };
2399
2400 static struct clk_branch gcc_gp1_clk = {
2401 .halt_reg = 0x08000,
2402 .halt_check = BRANCH_HALT,
2403 .clkr = {
2404 .enable_reg = 0x08000,
2405 .enable_mask = BIT(0),
2406 .hw.init = &(struct clk_init_data) {
2407 .name = "gcc_gp1_clk",
2408 .parent_hws = (const struct clk_hw*[]){
2409 &gp1_clk_src.clkr.hw,
2410 },
2411 .num_parents = 1,
2412 .ops = &clk_branch2_ops,
2413 .flags = CLK_SET_RATE_PARENT,
2414 }
2415 }
2416 };
2417
2418 static struct clk_branch gcc_gp2_clk = {
2419 .halt_reg = 0x09000,
2420 .halt_check = BRANCH_HALT,
2421 .clkr = {
2422 .enable_reg = 0x09000,
2423 .enable_mask = BIT(0),
2424 .hw.init = &(struct clk_init_data) {
2425 .name = "gcc_gp2_clk",
2426 .parent_hws = (const struct clk_hw*[]){
2427 &gp2_clk_src.clkr.hw,
2428 },
2429 .num_parents = 1,
2430 .ops = &clk_branch2_ops,
2431 .flags = CLK_SET_RATE_PARENT,
2432 }
2433 }
2434 };
2435
2436 static struct clk_branch gcc_gp3_clk = {
2437 .halt_reg = 0x0a000,
2438 .halt_check = BRANCH_HALT,
2439 .clkr = {
2440 .enable_reg = 0x0a000,
2441 .enable_mask = BIT(0),
2442 .hw.init = &(struct clk_init_data) {
2443 .name = "gcc_gp3_clk",
2444 .parent_hws = (const struct clk_hw*[]){
2445 &gp3_clk_src.clkr.hw,
2446 },
2447 .num_parents = 1,
2448 .ops = &clk_branch2_ops,
2449 .flags = CLK_SET_RATE_PARENT,
2450 }
2451 }
2452 };
2453
2454 static struct clk_branch gcc_jpeg_tbu_clk = {
2455 .halt_reg = 0x12034,
2456 .halt_check = BRANCH_HALT_VOTED,
2457 .clkr = {
2458 .enable_reg = 0x4500c,
2459 .enable_mask = BIT(10),
2460 .hw.init = &(struct clk_init_data) {
2461 .name = "gcc_jpeg_tbu_clk",
2462 .ops = &clk_branch2_ops,
2463 }
2464 }
2465 };
2466
2467 static struct clk_branch gcc_mdp_tbu_clk = {
2468 .halt_reg = 0x1201c,
2469 .halt_check = BRANCH_HALT_VOTED,
2470 .clkr = {
2471 .enable_reg = 0x4500c,
2472 .enable_mask = BIT(4),
2473 .hw.init = &(struct clk_init_data) {
2474 .name = "gcc_mdp_tbu_clk",
2475 .ops = &clk_branch2_ops,
2476 }
2477 }
2478 };
2479
2480 static struct clk_branch gcc_mdss_ahb_clk = {
2481 .halt_reg = 0x4d07c,
2482 .halt_check = BRANCH_HALT,
2483 .clkr = {
2484 .enable_reg = 0x4d07c,
2485 .enable_mask = BIT(0),
2486 .hw.init = &(struct clk_init_data) {
2487 .name = "gcc_mdss_ahb_clk",
2488 .ops = &clk_branch2_ops,
2489 }
2490 }
2491 };
2492
2493 static struct clk_branch gcc_mdss_axi_clk = {
2494 .halt_reg = 0x4d080,
2495 .halt_check = BRANCH_HALT,
2496 .clkr = {
2497 .enable_reg = 0x4d080,
2498 .enable_mask = BIT(0),
2499 .hw.init = &(struct clk_init_data) {
2500 .name = "gcc_mdss_axi_clk",
2501 .ops = &clk_branch2_ops,
2502 }
2503 }
2504 };
2505
2506 static struct clk_branch gcc_mdss_byte0_clk = {
2507 .halt_reg = 0x4d094,
2508 .halt_check = BRANCH_HALT,
2509 .clkr = {
2510 .enable_reg = 0x4d094,
2511 .enable_mask = BIT(0),
2512 .hw.init = &(struct clk_init_data) {
2513 .name = "gcc_mdss_byte0_clk",
2514 .parent_hws = (const struct clk_hw*[]){
2515 &byte0_clk_src.clkr.hw,
2516 },
2517 .num_parents = 1,
2518 .ops = &clk_branch2_ops,
2519 .flags = CLK_SET_RATE_PARENT,
2520 }
2521 }
2522 };
2523
2524 static struct clk_branch gcc_mdss_esc0_clk = {
2525 .halt_reg = 0x4d098,
2526 .halt_check = BRANCH_HALT,
2527 .clkr = {
2528 .enable_reg = 0x4d098,
2529 .enable_mask = BIT(0),
2530 .hw.init = &(struct clk_init_data) {
2531 .name = "gcc_mdss_esc0_clk",
2532 .parent_hws = (const struct clk_hw*[]){
2533 &esc0_clk_src.clkr.hw,
2534 },
2535 .num_parents = 1,
2536 .ops = &clk_branch2_ops,
2537 .flags = CLK_SET_RATE_PARENT,
2538 }
2539 }
2540 };
2541
2542 static struct clk_branch gcc_mdss_mdp_clk = {
2543 .halt_reg = 0x4d088,
2544 .halt_check = BRANCH_HALT,
2545 .clkr = {
2546 .enable_reg = 0x4d088,
2547 .enable_mask = BIT(0),
2548 .hw.init = &(struct clk_init_data) {
2549 .name = "gcc_mdss_mdp_clk",
2550 .parent_hws = (const struct clk_hw*[]){
2551 &mdp_clk_src.clkr.hw,
2552 },
2553 .num_parents = 1,
2554 .ops = &clk_branch2_ops,
2555 .flags = CLK_SET_RATE_PARENT,
2556 }
2557 }
2558 };
2559
2560 static struct clk_branch gcc_mdss_pclk0_clk = {
2561 .halt_reg = 0x4d084,
2562 .halt_check = BRANCH_HALT,
2563 .clkr = {
2564 .enable_reg = 0x4d084,
2565 .enable_mask = BIT(0),
2566 .hw.init = &(struct clk_init_data) {
2567 .name = "gcc_mdss_pclk0_clk",
2568 .parent_hws = (const struct clk_hw*[]){
2569 &pclk0_clk_src.clkr.hw,
2570 },
2571 .num_parents = 1,
2572 .ops = &clk_branch2_ops,
2573 .flags = CLK_SET_RATE_PARENT,
2574 }
2575 }
2576 };
2577
2578 static struct clk_branch gcc_mdss_vsync_clk = {
2579 .halt_reg = 0x4d090,
2580 .halt_check = BRANCH_HALT,
2581 .clkr = {
2582 .enable_reg = 0x4d090,
2583 .enable_mask = BIT(0),
2584 .hw.init = &(struct clk_init_data) {
2585 .name = "gcc_mdss_vsync_clk",
2586 .parent_hws = (const struct clk_hw*[]){
2587 &vsync_clk_src.clkr.hw,
2588 },
2589 .num_parents = 1,
2590 .ops = &clk_branch2_ops,
2591 .flags = CLK_SET_RATE_PARENT,
2592 }
2593 }
2594 };
2595
2596 static struct clk_branch gcc_mss_cfg_ahb_clk = {
2597 .halt_reg = 0x49000,
2598 .halt_check = BRANCH_HALT,
2599 .clkr = {
2600 .enable_reg = 0x49000,
2601 .enable_mask = BIT(0),
2602 .hw.init = &(struct clk_init_data) {
2603 .name = "gcc_mss_cfg_ahb_clk",
2604 .ops = &clk_branch2_ops,
2605 }
2606 }
2607 };
2608
2609 static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
2610 .halt_reg = 0x49004,
2611 .halt_check = BRANCH_HALT,
2612 .clkr = {
2613 .enable_reg = 0x49004,
2614 .enable_mask = BIT(0),
2615 .hw.init = &(struct clk_init_data) {
2616 .name = "gcc_mss_q6_bimc_axi_clk",
2617 .ops = &clk_branch2_ops,
2618 }
2619 }
2620 };
2621
2622 static struct clk_branch gcc_oxili_ahb_clk = {
2623 .halt_reg = 0x59028,
2624 .halt_check = BRANCH_HALT,
2625 .clkr = {
2626 .enable_reg = 0x59028,
2627 .enable_mask = BIT(0),
2628 .hw.init = &(struct clk_init_data) {
2629 .name = "gcc_oxili_ahb_clk",
2630 .ops = &clk_branch2_ops,
2631 }
2632 }
2633 };
2634
2635 static struct clk_branch gcc_oxili_gfx3d_clk = {
2636 .halt_reg = 0x59020,
2637 .halt_check = BRANCH_HALT,
2638 .clkr = {
2639 .enable_reg = 0x59020,
2640 .enable_mask = BIT(0),
2641 .hw.init = &(struct clk_init_data) {
2642 .name = "gcc_oxili_gfx3d_clk",
2643 .parent_hws = (const struct clk_hw*[]){
2644 &gfx3d_clk_src.clkr.hw,
2645 },
2646 .num_parents = 1,
2647 .ops = &clk_branch2_ops,
2648 .flags = CLK_SET_RATE_PARENT,
2649 }
2650 }
2651 };
2652
2653 static struct clk_branch gcc_pdm2_clk = {
2654 .halt_reg = 0x4400c,
2655 .halt_check = BRANCH_HALT,
2656 .clkr = {
2657 .enable_reg = 0x4400c,
2658 .enable_mask = BIT(0),
2659 .hw.init = &(struct clk_init_data) {
2660 .name = "gcc_pdm2_clk",
2661 .parent_hws = (const struct clk_hw*[]){
2662 &pdm2_clk_src.clkr.hw,
2663 },
2664 .num_parents = 1,
2665 .ops = &clk_branch2_ops,
2666 .flags = CLK_SET_RATE_PARENT,
2667 }
2668 }
2669 };
2670
2671 static struct clk_branch gcc_pdm_ahb_clk = {
2672 .halt_reg = 0x44004,
2673 .halt_check = BRANCH_HALT,
2674 .clkr = {
2675 .enable_reg = 0x44004,
2676 .enable_mask = BIT(0),
2677 .hw.init = &(struct clk_init_data) {
2678 .name = "gcc_pdm_ahb_clk",
2679 .ops = &clk_branch2_ops,
2680 }
2681 }
2682 };
2683
2684 static struct clk_branch gcc_prng_ahb_clk = {
2685 .halt_reg = 0x13004,
2686 .halt_check = BRANCH_HALT_VOTED,
2687 .clkr = {
2688 .enable_reg = 0x45004,
2689 .enable_mask = BIT(8),
2690 .hw.init = &(struct clk_init_data) {
2691 .name = "gcc_prng_ahb_clk",
2692 .ops = &clk_branch2_ops,
2693 }
2694 }
2695 };
2696
2697 static struct clk_branch gcc_qdss_dap_clk = {
2698 .halt_reg = 0x29084,
2699 .halt_check = BRANCH_HALT_VOTED,
2700 .clkr = {
2701 .enable_reg = 0x45004,
2702 .enable_mask = BIT(11),
2703 .hw.init = &(struct clk_init_data) {
2704 .name = "gcc_qdss_dap_clk",
2705 .ops = &clk_branch2_ops,
2706 }
2707 }
2708 };
2709
2710 static struct clk_branch gcc_sdcc1_ice_core_clk = {
2711 .halt_reg = 0x5d014,
2712 .halt_check = BRANCH_HALT,
2713 .clkr = {
2714 .enable_reg = 0x5d014,
2715 .enable_mask = BIT(0),
2716 .hw.init = &(struct clk_init_data) {
2717 .name = "gcc_sdcc1_ice_core_clk",
2718 .parent_hws = (const struct clk_hw*[]){
2719 &sdcc1_ice_core_clk_src.clkr.hw,
2720 },
2721 .num_parents = 1,
2722 .ops = &clk_branch2_ops,
2723 .flags = CLK_SET_RATE_PARENT,
2724 }
2725 }
2726 };
2727
2728 static struct clk_branch gcc_sdcc1_ahb_clk = {
2729 .halt_reg = 0x4201c,
2730 .halt_check = BRANCH_HALT,
2731 .clkr = {
2732 .enable_reg = 0x4201c,
2733 .enable_mask = BIT(0),
2734 .hw.init = &(struct clk_init_data) {
2735 .name = "gcc_sdcc1_ahb_clk",
2736 .ops = &clk_branch2_ops,
2737 }
2738 }
2739 };
2740
2741 static struct clk_branch gcc_sdcc2_ahb_clk = {
2742 .halt_reg = 0x4301c,
2743 .halt_check = BRANCH_HALT,
2744 .clkr = {
2745 .enable_reg = 0x4301c,
2746 .enable_mask = BIT(0),
2747 .hw.init = &(struct clk_init_data) {
2748 .name = "gcc_sdcc2_ahb_clk",
2749 .ops = &clk_branch2_ops,
2750 }
2751 }
2752 };
2753
2754 static struct clk_branch gcc_sdcc1_apps_clk = {
2755 .halt_reg = 0x42018,
2756 .halt_check = BRANCH_HALT,
2757 .clkr = {
2758 .enable_reg = 0x42018,
2759 .enable_mask = BIT(0),
2760 .hw.init = &(struct clk_init_data) {
2761 .name = "gcc_sdcc1_apps_clk",
2762 .parent_hws = (const struct clk_hw*[]){
2763 &sdcc1_apps_clk_src.clkr.hw,
2764 },
2765 .num_parents = 1,
2766 .ops = &clk_branch2_ops,
2767 .flags = CLK_SET_RATE_PARENT,
2768 }
2769 }
2770 };
2771
2772 static struct clk_branch gcc_sdcc2_apps_clk = {
2773 .halt_reg = 0x43018,
2774 .halt_check = BRANCH_HALT,
2775 .clkr = {
2776 .enable_reg = 0x43018,
2777 .enable_mask = BIT(0),
2778 .hw.init = &(struct clk_init_data) {
2779 .name = "gcc_sdcc2_apps_clk",
2780 .parent_hws = (const struct clk_hw*[]){
2781 &sdcc2_apps_clk_src.clkr.hw,
2782 },
2783 .num_parents = 1,
2784 .ops = &clk_branch2_ops,
2785 .flags = CLK_SET_RATE_PARENT,
2786 }
2787 }
2788 };
2789
2790 static struct clk_branch gcc_smmu_cfg_clk = {
2791 .halt_reg = 0x12038,
2792 .halt_check = BRANCH_HALT_VOTED,
2793 .clkr = {
2794 .enable_reg = 0x4500c,
2795 .enable_mask = BIT(12),
2796 .hw.init = &(struct clk_init_data) {
2797 .name = "gcc_smmu_cfg_clk",
2798 .ops = &clk_branch2_ops,
2799 }
2800 }
2801 };
2802
2803 static struct clk_branch gcc_usb2a_phy_sleep_clk = {
2804 .halt_reg = 0x4102c,
2805 .clkr = {
2806 .enable_reg = 0x4102c,
2807 .enable_mask = BIT(0),
2808 .hw.init = &(struct clk_init_data){
2809 .name = "gcc_usb2a_phy_sleep_clk",
2810 .ops = &clk_branch2_ops,
2811 },
2812 },
2813 };
2814
2815 static struct clk_branch gcc_usb_hs_ahb_clk = {
2816 .halt_reg = 0x41008,
2817 .clkr = {
2818 .enable_reg = 0x41008,
2819 .enable_mask = BIT(0),
2820 .hw.init = &(struct clk_init_data){
2821 .name = "gcc_usb_hs_ahb_clk",
2822 .ops = &clk_branch2_ops,
2823 },
2824 },
2825 };
2826
2827 static struct clk_branch gcc_usb_hs_phy_cfg_ahb_clk = {
2828 .halt_reg = 0x41030,
2829 .clkr = {
2830 .enable_reg = 0x41030,
2831 .enable_mask = BIT(0),
2832 .hw.init = &(struct clk_init_data){
2833 .name = "gcc_usb_hs_phy_cfg_ahb_clk",
2834 .ops = &clk_branch2_ops,
2835 },
2836 },
2837 };
2838
2839 static struct clk_branch gcc_usb_hs_system_clk = {
2840 .halt_reg = 0x41004,
2841 .clkr = {
2842 .enable_reg = 0x41004,
2843 .enable_mask = BIT(0),
2844 .hw.init = &(struct clk_init_data){
2845 .name = "gcc_usb_hs_system_clk",
2846 .parent_hws = (const struct clk_hw*[]){
2847 &usb_hs_system_clk_src.clkr.hw,
2848 },
2849 .num_parents = 1,
2850 .flags = CLK_SET_RATE_PARENT,
2851 .ops = &clk_branch2_ops,
2852 },
2853 },
2854 };
2855
2856 static struct clk_branch gcc_venus0_ahb_clk = {
2857 .halt_reg = 0x4c020,
2858 .halt_check = BRANCH_HALT,
2859 .clkr = {
2860 .enable_reg = 0x4c020,
2861 .enable_mask = BIT(0),
2862 .hw.init = &(struct clk_init_data) {
2863 .name = "gcc_venus0_ahb_clk",
2864 .ops = &clk_branch2_ops,
2865 }
2866 }
2867 };
2868
2869 static struct clk_branch gcc_venus0_axi_clk = {
2870 .halt_reg = 0x4c024,
2871 .halt_check = BRANCH_HALT,
2872 .clkr = {
2873 .enable_reg = 0x4c024,
2874 .enable_mask = BIT(0),
2875 .hw.init = &(struct clk_init_data) {
2876 .name = "gcc_venus0_axi_clk",
2877 .ops = &clk_branch2_ops,
2878 }
2879 }
2880 };
2881
2882 static struct clk_branch gcc_venus0_core0_vcodec0_clk = {
2883 .halt_reg = 0x4c02c,
2884 .halt_check = BRANCH_HALT,
2885 .clkr = {
2886 .enable_reg = 0x4c02c,
2887 .enable_mask = BIT(0),
2888 .hw.init = &(struct clk_init_data) {
2889 .name = "gcc_venus0_core0_vcodec0_clk",
2890 .parent_hws = (const struct clk_hw*[]){
2891 &vcodec0_clk_src.clkr.hw,
2892 },
2893 .num_parents = 1,
2894 .ops = &clk_branch2_ops,
2895 .flags = CLK_SET_RATE_PARENT,
2896 }
2897 }
2898 };
2899
2900 static struct clk_branch gcc_venus0_vcodec0_clk = {
2901 .halt_reg = 0x4c01c,
2902 .halt_check = BRANCH_HALT,
2903 .clkr = {
2904 .enable_reg = 0x4c01c,
2905 .enable_mask = BIT(0),
2906 .hw.init = &(struct clk_init_data) {
2907 .name = "gcc_venus0_vcodec0_clk",
2908 .parent_hws = (const struct clk_hw*[]){
2909 &vcodec0_clk_src.clkr.hw,
2910 },
2911 .num_parents = 1,
2912 .ops = &clk_branch2_ops,
2913 .flags = CLK_SET_RATE_PARENT,
2914 }
2915 }
2916 };
2917
2918 static struct clk_branch gcc_venus_tbu_clk = {
2919 .halt_reg = 0x12014,
2920 .halt_check = BRANCH_HALT_VOTED,
2921 .clkr = {
2922 .enable_reg = 0x4500c,
2923 .enable_mask = BIT(5),
2924 .hw.init = &(struct clk_init_data) {
2925 .name = "gcc_venus_tbu_clk",
2926 .ops = &clk_branch2_ops,
2927 }
2928 }
2929 };
2930
2931 static struct clk_branch gcc_vfe1_tbu_clk = {
2932 .halt_reg = 0x12090,
2933 .halt_check = BRANCH_HALT_VOTED,
2934 .clkr = {
2935 .enable_reg = 0x4500c,
2936 .enable_mask = BIT(17),
2937 .hw.init = &(struct clk_init_data) {
2938 .name = "gcc_vfe1_tbu_clk",
2939 .ops = &clk_branch2_ops,
2940 }
2941 }
2942 };
2943
2944 static struct clk_branch gcc_vfe_tbu_clk = {
2945 .halt_reg = 0x1203c,
2946 .halt_check = BRANCH_HALT_VOTED,
2947 .clkr = {
2948 .enable_reg = 0x4500c,
2949 .enable_mask = BIT(9),
2950 .hw.init = &(struct clk_init_data) {
2951 .name = "gcc_vfe_tbu_clk",
2952 .ops = &clk_branch2_ops,
2953 }
2954 }
2955 };
2956
2957 static struct gdsc venus_gdsc = {
2958 .gdscr = 0x4c018,
2959 .cxcs = (unsigned int []){ 0x4c024, 0x4c01c },
2960 .cxc_count = 2,
2961 .pd = {
2962 .name = "venus_gdsc",
2963 },
2964 .pwrsts = PWRSTS_OFF_ON,
2965 };
2966
2967 static struct gdsc venus_core0_gdsc = {
2968 .gdscr = 0x4c028,
2969 .cxcs = (unsigned int []){ 0x4c02c },
2970 .cxc_count = 1,
2971 .pd = {
2972 .name = "venus_core0",
2973 },
2974 .flags = HW_CTRL,
2975 .pwrsts = PWRSTS_OFF_ON,
2976 };
2977
2978 static struct gdsc mdss_gdsc = {
2979 .gdscr = 0x4d078,
2980 .cxcs = (unsigned int []){ 0x4d080, 0x4d088 },
2981 .cxc_count = 2,
2982 .pd = {
2983 .name = "mdss_gdsc",
2984 },
2985 .pwrsts = PWRSTS_OFF_ON,
2986 };
2987
2988 static struct gdsc jpeg_gdsc = {
2989 .gdscr = 0x5701c,
2990 .cxcs = (unsigned int []){ 0x57020, 0x57028 },
2991 .cxc_count = 2,
2992 .pd = {
2993 .name = "jpeg_gdsc",
2994 },
2995 .pwrsts = PWRSTS_OFF_ON,
2996 };
2997
2998 static struct gdsc vfe0_gdsc = {
2999 .gdscr = 0x58034,
3000 .cxcs = (unsigned int []){ 0x58038, 0x58048, 0x5600c, 0x58050 },
3001 .cxc_count = 4,
3002 .pd = {
3003 .name = "vfe0_gdsc",
3004 },
3005 .pwrsts = PWRSTS_OFF_ON,
3006 };
3007
3008 static struct gdsc vfe1_gdsc = {
3009 .gdscr = 0x5806c,
3010 .cxcs = (unsigned int []){ 0x5805c, 0x58068, 0x5600c, 0x58074 },
3011 .cxc_count = 4,
3012 .pd = {
3013 .name = "vfe1_gdsc",
3014 },
3015 .pwrsts = PWRSTS_OFF_ON,
3016 };
3017
3018 static struct gdsc oxili_gx_gdsc = {
3019 .gdscr = 0x5901c,
3020 .clamp_io_ctrl = 0x5b00c,
3021 .cxcs = (unsigned int []){ 0x59000, 0x59020 },
3022 .cxc_count = 2,
3023 .pd = {
3024 .name = "oxili_gx_gdsc",
3025 },
3026 .pwrsts = PWRSTS_OFF_ON,
3027 .flags = CLAMP_IO,
3028 };
3029
3030 static struct gdsc cpp_gdsc = {
3031 .gdscr = 0x58078,
3032 .cxcs = (unsigned int []){ 0x5803c, 0x58064 },
3033 .cxc_count = 2,
3034 .pd = {
3035 .name = "cpp_gdsc",
3036 },
3037 .flags = ALWAYS_ON,
3038 .pwrsts = PWRSTS_OFF_ON,
3039 };
3040
3041 static struct clk_regmap *gcc_msm8917_clocks[] = {
3042 [GPLL0] = &gpll0.clkr,
3043 [GPLL0_EARLY] = &gpll0_early.clkr,
3044 [GPLL0_SLEEP_CLK_SRC] = &gpll0_sleep_clk_src.clkr,
3045 [GPLL3] = &gpll3.clkr,
3046 [GPLL3_EARLY] = &gpll3_early.clkr,
3047 [GPLL4] = &gpll4.clkr,
3048 [GPLL4_EARLY] = &gpll4_early.clkr,
3049 [GPLL6] = &gpll6,
3050 [GPLL6_EARLY] = &gpll6_early.clkr,
3051 [APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
3052 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
3053 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
3054 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
3055 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
3056 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
3057 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
3058 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
3059 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
3060 [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
3061 [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
3062 [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
3063 [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
3064 [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
3065 [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
3066 [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
3067 [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
3068 [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
3069 [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
3070 [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
3071 [CAMSS_TOP_AHB_CLK_SRC] = &camss_top_ahb_clk_src.clkr,
3072 [CCI_CLK_SRC] = &cci_clk_src.clkr,
3073 [CPP_CLK_SRC] = &cpp_clk_src.clkr,
3074 [CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
3075 [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
3076 [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
3077 [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
3078 [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
3079 [CSI2_CLK_SRC] = &csi2_clk_src.clkr,
3080 [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
3081 [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
3082 [GP1_CLK_SRC] = &gp1_clk_src.clkr,
3083 [GP2_CLK_SRC] = &gp2_clk_src.clkr,
3084 [GP3_CLK_SRC] = &gp3_clk_src.clkr,
3085 [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
3086 [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
3087 [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
3088 [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
3089 [MDP_CLK_SRC] = &mdp_clk_src.clkr,
3090 [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
3091 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
3092 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
3093 [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
3094 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
3095 [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
3096 [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
3097 [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
3098 [VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
3099 [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
3100 [GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr,
3101 [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
3102 [GCC_BIMC_GPU_CLK] = &gcc_bimc_gpu_clk.clkr,
3103 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
3104 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
3105 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
3106 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
3107 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
3108 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
3109 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
3110 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
3111 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
3112 [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
3113 [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
3114 [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
3115 [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
3116 [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
3117 [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
3118 [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
3119 [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
3120 [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
3121 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3122 [GCC_CAMSS_AHB_CLK] = &gcc_camss_ahb_clk.clkr,
3123 [GCC_CAMSS_CCI_AHB_CLK] = &gcc_camss_cci_ahb_clk.clkr,
3124 [GCC_CAMSS_CCI_CLK] = &gcc_camss_cci_clk.clkr,
3125 [GCC_CAMSS_CPP_AHB_CLK] = &gcc_camss_cpp_ahb_clk.clkr,
3126 [GCC_CAMSS_CPP_CLK] = &gcc_camss_cpp_clk.clkr,
3127 [GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr,
3128 [GCC_CAMSS_CSI0PHY_CLK] = &gcc_camss_csi0phy_clk.clkr,
3129 [GCC_CAMSS_CSI0PIX_CLK] = &gcc_camss_csi0pix_clk.clkr,
3130 [GCC_CAMSS_CSI0RDI_CLK] = &gcc_camss_csi0rdi_clk.clkr,
3131 [GCC_CAMSS_CSI0_AHB_CLK] = &gcc_camss_csi0_ahb_clk.clkr,
3132 [GCC_CAMSS_CSI0_CLK] = &gcc_camss_csi0_clk.clkr,
3133 [GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr,
3134 [GCC_CAMSS_CSI1PHY_CLK] = &gcc_camss_csi1phy_clk.clkr,
3135 [GCC_CAMSS_CSI1PIX_CLK] = &gcc_camss_csi1pix_clk.clkr,
3136 [GCC_CAMSS_CSI1RDI_CLK] = &gcc_camss_csi1rdi_clk.clkr,
3137 [GCC_CAMSS_CSI1_AHB_CLK] = &gcc_camss_csi1_ahb_clk.clkr,
3138 [GCC_CAMSS_CSI1_CLK] = &gcc_camss_csi1_clk.clkr,
3139 [GCC_CAMSS_CSI2PHY_CLK] = &gcc_camss_csi2phy_clk.clkr,
3140 [GCC_CAMSS_CSI2PIX_CLK] = &gcc_camss_csi2pix_clk.clkr,
3141 [GCC_CAMSS_CSI2RDI_CLK] = &gcc_camss_csi2rdi_clk.clkr,
3142 [GCC_CAMSS_CSI2_AHB_CLK] = &gcc_camss_csi2_ahb_clk.clkr,
3143 [GCC_CAMSS_CSI2_CLK] = &gcc_camss_csi2_clk.clkr,
3144 [GCC_CAMSS_CSI_VFE0_CLK] = &gcc_camss_csi_vfe0_clk.clkr,
3145 [GCC_CAMSS_CSI_VFE1_CLK] = &gcc_camss_csi_vfe1_clk.clkr,
3146 [GCC_CAMSS_GP0_CLK] = &gcc_camss_gp0_clk.clkr,
3147 [GCC_CAMSS_GP1_CLK] = &gcc_camss_gp1_clk.clkr,
3148 [GCC_CAMSS_ISPIF_AHB_CLK] = &gcc_camss_ispif_ahb_clk.clkr,
3149 [GCC_CAMSS_JPEG0_CLK] = &gcc_camss_jpeg0_clk.clkr,
3150 [GCC_CAMSS_JPEG_AHB_CLK] = &gcc_camss_jpeg_ahb_clk.clkr,
3151 [GCC_CAMSS_JPEG_AXI_CLK] = &gcc_camss_jpeg_axi_clk.clkr,
3152 [GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr,
3153 [GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr,
3154 [GCC_CAMSS_MCLK2_CLK] = &gcc_camss_mclk2_clk.clkr,
3155 [GCC_CAMSS_MICRO_AHB_CLK] = &gcc_camss_micro_ahb_clk.clkr,
3156 [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr,
3157 [GCC_CAMSS_VFE0_AHB_CLK] = &gcc_camss_vfe0_ahb_clk.clkr,
3158 [GCC_CAMSS_VFE0_AXI_CLK] = &gcc_camss_vfe0_axi_clk.clkr,
3159 [GCC_CAMSS_VFE0_CLK] = &gcc_camss_vfe0_clk.clkr,
3160 [GCC_CAMSS_VFE1_AHB_CLK] = &gcc_camss_vfe1_ahb_clk.clkr,
3161 [GCC_CAMSS_VFE1_AXI_CLK] = &gcc_camss_vfe1_axi_clk.clkr,
3162 [GCC_CAMSS_VFE1_CLK] = &gcc_camss_vfe1_clk.clkr,
3163 [GCC_CPP_TBU_CLK] = &gcc_cpp_tbu_clk.clkr,
3164 [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
3165 [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
3166 [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
3167 [GCC_DCC_CLK] = &gcc_dcc_clk.clkr,
3168 [GCC_GFX_TBU_CLK] = &gcc_gfx_tbu_clk.clkr,
3169 [GCC_GFX_TCU_CLK] = &gcc_gfx_tcu_clk.clkr,
3170 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3171 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3172 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3173 [GCC_GTCU_AHB_CLK] = &gcc_gtcu_ahb_clk.clkr,
3174 [GCC_JPEG_TBU_CLK] = &gcc_jpeg_tbu_clk.clkr,
3175 [GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr,
3176 [GCC_MDSS_AHB_CLK] = &gcc_mdss_ahb_clk.clkr,
3177 [GCC_MDSS_AXI_CLK] = &gcc_mdss_axi_clk.clkr,
3178 [GCC_MDSS_BYTE0_CLK] = &gcc_mdss_byte0_clk.clkr,
3179 [GCC_MDSS_ESC0_CLK] = &gcc_mdss_esc0_clk.clkr,
3180 [GCC_MDSS_MDP_CLK] = &gcc_mdss_mdp_clk.clkr,
3181 [GCC_MDSS_PCLK0_CLK] = &gcc_mdss_pclk0_clk.clkr,
3182 [GCC_MDSS_VSYNC_CLK] = &gcc_mdss_vsync_clk.clkr,
3183 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
3184 [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
3185 [GCC_OXILI_AHB_CLK] = &gcc_oxili_ahb_clk.clkr,
3186 [GCC_OXILI_GFX3D_CLK] = &gcc_oxili_gfx3d_clk.clkr,
3187 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3188 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3189 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3190 [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
3191 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
3192 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
3193 [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
3194 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3195 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3196 [GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr,
3197 [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
3198 [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
3199 [GCC_USB_HS_PHY_CFG_AHB_CLK] = &gcc_usb_hs_phy_cfg_ahb_clk.clkr,
3200 [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
3201 [GCC_VENUS0_AHB_CLK] = &gcc_venus0_ahb_clk.clkr,
3202 [GCC_VENUS0_AXI_CLK] = &gcc_venus0_axi_clk.clkr,
3203 [GCC_VENUS0_CORE0_VCODEC0_CLK] = &gcc_venus0_core0_vcodec0_clk.clkr,
3204 [GCC_VENUS0_VCODEC0_CLK] = &gcc_venus0_vcodec0_clk.clkr,
3205 [GCC_VENUS_TBU_CLK] = &gcc_venus_tbu_clk.clkr,
3206 [GCC_VFE1_TBU_CLK] = &gcc_vfe1_tbu_clk.clkr,
3207 [GCC_VFE_TBU_CLK] = &gcc_vfe_tbu_clk.clkr,
3208 };
3209
3210 static const struct qcom_reset_map gcc_msm8917_resets[] = {
3211 [GCC_CAMSS_MICRO_BCR] = { 0x56008 },
3212 [GCC_MSS_BCR] = { 0x71000 },
3213 [GCC_QUSB2_PHY_BCR] = { 0x4103c },
3214 [GCC_USB_HS_BCR] = { 0x41000 },
3215 [GCC_USB2_HS_PHY_ONLY_BCR] = { 0x41034 },
3216 };
3217
3218 static const struct regmap_config gcc_msm8917_regmap_config = {
3219 .reg_bits = 32,
3220 .reg_stride = 4,
3221 .val_bits = 32,
3222 .max_register = 0x80000,
3223 .fast_io = true,
3224 };
3225
3226 static struct gdsc *gcc_msm8917_gdscs[] = {
3227 [CPP_GDSC] = &cpp_gdsc,
3228 [JPEG_GDSC] = &jpeg_gdsc,
3229 [MDSS_GDSC] = &mdss_gdsc,
3230 [OXILI_GX_GDSC] = &oxili_gx_gdsc,
3231 [VENUS_CORE0_GDSC] = &venus_core0_gdsc,
3232 [VENUS_GDSC] = &venus_gdsc,
3233 [VFE0_GDSC] = &vfe0_gdsc,
3234 [VFE1_GDSC] = &vfe1_gdsc,
3235 };
3236
3237 static const struct qcom_cc_desc gcc_msm8917_desc = {
3238 .config = &gcc_msm8917_regmap_config,
3239 .clks = gcc_msm8917_clocks,
3240 .num_clks = ARRAY_SIZE(gcc_msm8917_clocks),
3241 .resets = gcc_msm8917_resets,
3242 .num_resets = ARRAY_SIZE(gcc_msm8917_resets),
3243 .gdscs = gcc_msm8917_gdscs,
3244 .num_gdscs = ARRAY_SIZE(gcc_msm8917_gdscs),
3245 };
3246
3247 static const struct qcom_cc_desc gcc_qm215_desc = {
3248 .config = &gcc_msm8917_regmap_config,
3249 .clks = gcc_msm8917_clocks,
3250 .num_clks = ARRAY_SIZE(gcc_msm8917_clocks),
3251 .resets = gcc_msm8917_resets,
3252 .num_resets = ARRAY_SIZE(gcc_msm8917_resets),
3253 .gdscs = gcc_msm8917_gdscs,
3254 .num_gdscs = ARRAY_SIZE(gcc_msm8917_gdscs),
3255 };
3256
gcc_msm8917_probe(struct platform_device * pdev)3257 static int gcc_msm8917_probe(struct platform_device *pdev)
3258 {
3259 struct regmap *regmap;
3260 const struct qcom_cc_desc *gcc_desc;
3261
3262 gcc_desc = of_device_get_match_data(&pdev->dev);
3263
3264 if (gcc_desc == &gcc_qm215_desc)
3265 gfx3d_clk_src.parent_map = gcc_gfx3d_map_qm215;
3266
3267 regmap = qcom_cc_map(pdev, gcc_desc);
3268 if (IS_ERR(regmap))
3269 return PTR_ERR(regmap);
3270
3271 clk_alpha_pll_configure(&gpll3_early, regmap, &gpll3_early_config);
3272
3273 return qcom_cc_really_probe(pdev, gcc_desc, regmap);
3274 }
3275
3276 static const struct of_device_id gcc_msm8917_match_table[] = {
3277 { .compatible = "qcom,gcc-msm8917", .data = &gcc_msm8917_desc },
3278 { .compatible = "qcom,gcc-qm215", .data = &gcc_qm215_desc },
3279 {},
3280 };
3281
3282 static struct platform_driver gcc_msm8917_driver = {
3283 .probe = gcc_msm8917_probe,
3284 .driver = {
3285 .name = "gcc-msm8917",
3286 .of_match_table = gcc_msm8917_match_table,
3287 },
3288 };
3289
gcc_msm8917_init(void)3290 static int __init gcc_msm8917_init(void)
3291 {
3292 return platform_driver_register(&gcc_msm8917_driver);
3293 }
3294 core_initcall(gcc_msm8917_init);
3295
gcc_msm8917_exit(void)3296 static void __exit gcc_msm8917_exit(void)
3297 {
3298 platform_driver_unregister(&gcc_msm8917_driver);
3299 }
3300 module_exit(gcc_msm8917_exit);
3301
3302 MODULE_DESCRIPTION("Qualcomm GCC MSM8917 Driver");
3303 MODULE_LICENSE("GPL");
3304