1 /* 2 * Copyright 2015 Linaro Limited 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include <linux/kernel.h> 15 #include <linux/bitops.h> 16 #include <linux/err.h> 17 #include <linux/platform_device.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/of_device.h> 21 #include <linux/clk-provider.h> 22 #include <linux/regmap.h> 23 #include <linux/reset-controller.h> 24 25 #include <dt-bindings/clock/qcom,gcc-msm8916.h> 26 #include <dt-bindings/reset/qcom,gcc-msm8916.h> 27 28 #include "common.h" 29 #include "clk-regmap.h" 30 #include "clk-pll.h" 31 #include "clk-rcg.h" 32 #include "clk-branch.h" 33 #include "reset.h" 34 #include "gdsc.h" 35 36 enum { 37 P_XO, 38 P_GPLL0, 39 P_GPLL0_AUX, 40 P_BIMC, 41 P_GPLL1, 42 P_GPLL1_AUX, 43 P_GPLL2, 44 P_GPLL2_AUX, 45 P_SLEEP_CLK, 46 P_DSI0_PHYPLL_BYTE, 47 P_DSI0_PHYPLL_DSI, 48 P_EXT_PRI_I2S, 49 P_EXT_SEC_I2S, 50 P_EXT_MCLK, 51 }; 52 53 static const struct parent_map gcc_xo_gpll0_map[] = { 54 { P_XO, 0 }, 55 { P_GPLL0, 1 }, 56 }; 57 58 static const char * const gcc_xo_gpll0[] = { 59 "xo", 60 "gpll0_vote", 61 }; 62 63 static const struct parent_map gcc_xo_gpll0_bimc_map[] = { 64 { P_XO, 0 }, 65 { P_GPLL0, 1 }, 66 { P_BIMC, 2 }, 67 }; 68 69 static const char * const gcc_xo_gpll0_bimc[] = { 70 "xo", 71 "gpll0_vote", 72 "bimc_pll_vote", 73 }; 74 75 static const struct parent_map gcc_xo_gpll0a_gpll1_gpll2a_map[] = { 76 { P_XO, 0 }, 77 { P_GPLL0_AUX, 3 }, 78 { P_GPLL1, 1 }, 79 { P_GPLL2_AUX, 2 }, 80 }; 81 82 static const char * const gcc_xo_gpll0a_gpll1_gpll2a[] = { 83 "xo", 84 "gpll0_vote", 85 "gpll1_vote", 86 "gpll2_vote", 87 }; 88 89 static const struct parent_map gcc_xo_gpll0_gpll2_map[] = { 90 { P_XO, 0 }, 91 { P_GPLL0, 1 }, 92 { P_GPLL2, 2 }, 93 }; 94 95 static const char * const gcc_xo_gpll0_gpll2[] = { 96 "xo", 97 "gpll0_vote", 98 "gpll2_vote", 99 }; 100 101 static const struct parent_map gcc_xo_gpll0a_map[] = { 102 { P_XO, 0 }, 103 { P_GPLL0_AUX, 2 }, 104 }; 105 106 static const char * const gcc_xo_gpll0a[] = { 107 "xo", 108 "gpll0_vote", 109 }; 110 111 static const struct parent_map gcc_xo_gpll0_gpll1a_sleep_map[] = { 112 { P_XO, 0 }, 113 { P_GPLL0, 1 }, 114 { P_GPLL1_AUX, 2 }, 115 { P_SLEEP_CLK, 6 }, 116 }; 117 118 static const char * const gcc_xo_gpll0_gpll1a_sleep[] = { 119 "xo", 120 "gpll0_vote", 121 "gpll1_vote", 122 "sleep_clk", 123 }; 124 125 static const struct parent_map gcc_xo_gpll0_gpll1a_map[] = { 126 { P_XO, 0 }, 127 { P_GPLL0, 1 }, 128 { P_GPLL1_AUX, 2 }, 129 }; 130 131 static const char * const gcc_xo_gpll0_gpll1a[] = { 132 "xo", 133 "gpll0_vote", 134 "gpll1_vote", 135 }; 136 137 static const struct parent_map gcc_xo_dsibyte_map[] = { 138 { P_XO, 0, }, 139 { P_DSI0_PHYPLL_BYTE, 2 }, 140 }; 141 142 static const char * const gcc_xo_dsibyte[] = { 143 "xo", 144 "dsi0pllbyte", 145 }; 146 147 static const struct parent_map gcc_xo_gpll0a_dsibyte_map[] = { 148 { P_XO, 0 }, 149 { P_GPLL0_AUX, 2 }, 150 { P_DSI0_PHYPLL_BYTE, 1 }, 151 }; 152 153 static const char * const gcc_xo_gpll0a_dsibyte[] = { 154 "xo", 155 "gpll0_vote", 156 "dsi0pllbyte", 157 }; 158 159 static const struct parent_map gcc_xo_gpll0_dsiphy_map[] = { 160 { P_XO, 0 }, 161 { P_GPLL0, 1 }, 162 { P_DSI0_PHYPLL_DSI, 2 }, 163 }; 164 165 static const char * const gcc_xo_gpll0_dsiphy[] = { 166 "xo", 167 "gpll0_vote", 168 "dsi0pll", 169 }; 170 171 static const struct parent_map gcc_xo_gpll0a_dsiphy_map[] = { 172 { P_XO, 0 }, 173 { P_GPLL0_AUX, 2 }, 174 { P_DSI0_PHYPLL_DSI, 1 }, 175 }; 176 177 static const char * const gcc_xo_gpll0a_dsiphy[] = { 178 "xo", 179 "gpll0_vote", 180 "dsi0pll", 181 }; 182 183 static const struct parent_map gcc_xo_gpll0a_gpll1_gpll2_map[] = { 184 { P_XO, 0 }, 185 { P_GPLL0_AUX, 1 }, 186 { P_GPLL1, 3 }, 187 { P_GPLL2, 2 }, 188 }; 189 190 static const char * const gcc_xo_gpll0a_gpll1_gpll2[] = { 191 "xo", 192 "gpll0_vote", 193 "gpll1_vote", 194 "gpll2_vote", 195 }; 196 197 static const struct parent_map gcc_xo_gpll0_gpll1_sleep_map[] = { 198 { P_XO, 0 }, 199 { P_GPLL0, 1 }, 200 { P_GPLL1, 2 }, 201 { P_SLEEP_CLK, 6 } 202 }; 203 204 static const char * const gcc_xo_gpll0_gpll1_sleep[] = { 205 "xo", 206 "gpll0_vote", 207 "gpll1_vote", 208 "sleep_clk", 209 }; 210 211 static const struct parent_map gcc_xo_gpll1_epi2s_emclk_sleep_map[] = { 212 { P_XO, 0 }, 213 { P_GPLL1, 1 }, 214 { P_EXT_PRI_I2S, 2 }, 215 { P_EXT_MCLK, 3 }, 216 { P_SLEEP_CLK, 6 } 217 }; 218 219 static const char * const gcc_xo_gpll1_epi2s_emclk_sleep[] = { 220 "xo", 221 "gpll1_vote", 222 "ext_pri_i2s", 223 "ext_mclk", 224 "sleep_clk", 225 }; 226 227 static const struct parent_map gcc_xo_gpll1_esi2s_emclk_sleep_map[] = { 228 { P_XO, 0 }, 229 { P_GPLL1, 1 }, 230 { P_EXT_SEC_I2S, 2 }, 231 { P_EXT_MCLK, 3 }, 232 { P_SLEEP_CLK, 6 } 233 }; 234 235 static const char * const gcc_xo_gpll1_esi2s_emclk_sleep[] = { 236 "xo", 237 "gpll1_vote", 238 "ext_sec_i2s", 239 "ext_mclk", 240 "sleep_clk", 241 }; 242 243 static const struct parent_map gcc_xo_sleep_map[] = { 244 { P_XO, 0 }, 245 { P_SLEEP_CLK, 6 } 246 }; 247 248 static const char * const gcc_xo_sleep[] = { 249 "xo", 250 "sleep_clk", 251 }; 252 253 static const struct parent_map gcc_xo_gpll1_emclk_sleep_map[] = { 254 { P_XO, 0 }, 255 { P_GPLL1, 1 }, 256 { P_EXT_MCLK, 2 }, 257 { P_SLEEP_CLK, 6 } 258 }; 259 260 static const char * const gcc_xo_gpll1_emclk_sleep[] = { 261 "xo", 262 "gpll1_vote", 263 "ext_mclk", 264 "sleep_clk", 265 }; 266 267 static struct clk_pll gpll0 = { 268 .l_reg = 0x21004, 269 .m_reg = 0x21008, 270 .n_reg = 0x2100c, 271 .config_reg = 0x21014, 272 .mode_reg = 0x21000, 273 .status_reg = 0x2101c, 274 .status_bit = 17, 275 .clkr.hw.init = &(struct clk_init_data){ 276 .name = "gpll0", 277 .parent_names = (const char *[]){ "xo" }, 278 .num_parents = 1, 279 .ops = &clk_pll_ops, 280 }, 281 }; 282 283 static struct clk_regmap gpll0_vote = { 284 .enable_reg = 0x45000, 285 .enable_mask = BIT(0), 286 .hw.init = &(struct clk_init_data){ 287 .name = "gpll0_vote", 288 .parent_names = (const char *[]){ "gpll0" }, 289 .num_parents = 1, 290 .ops = &clk_pll_vote_ops, 291 }, 292 }; 293 294 static struct clk_pll gpll1 = { 295 .l_reg = 0x20004, 296 .m_reg = 0x20008, 297 .n_reg = 0x2000c, 298 .config_reg = 0x20014, 299 .mode_reg = 0x20000, 300 .status_reg = 0x2001c, 301 .status_bit = 17, 302 .clkr.hw.init = &(struct clk_init_data){ 303 .name = "gpll1", 304 .parent_names = (const char *[]){ "xo" }, 305 .num_parents = 1, 306 .ops = &clk_pll_ops, 307 }, 308 }; 309 310 static struct clk_regmap gpll1_vote = { 311 .enable_reg = 0x45000, 312 .enable_mask = BIT(1), 313 .hw.init = &(struct clk_init_data){ 314 .name = "gpll1_vote", 315 .parent_names = (const char *[]){ "gpll1" }, 316 .num_parents = 1, 317 .ops = &clk_pll_vote_ops, 318 }, 319 }; 320 321 static struct clk_pll gpll2 = { 322 .l_reg = 0x4a004, 323 .m_reg = 0x4a008, 324 .n_reg = 0x4a00c, 325 .config_reg = 0x4a014, 326 .mode_reg = 0x4a000, 327 .status_reg = 0x4a01c, 328 .status_bit = 17, 329 .clkr.hw.init = &(struct clk_init_data){ 330 .name = "gpll2", 331 .parent_names = (const char *[]){ "xo" }, 332 .num_parents = 1, 333 .ops = &clk_pll_ops, 334 }, 335 }; 336 337 static struct clk_regmap gpll2_vote = { 338 .enable_reg = 0x45000, 339 .enable_mask = BIT(2), 340 .hw.init = &(struct clk_init_data){ 341 .name = "gpll2_vote", 342 .parent_names = (const char *[]){ "gpll2" }, 343 .num_parents = 1, 344 .ops = &clk_pll_vote_ops, 345 }, 346 }; 347 348 static struct clk_pll bimc_pll = { 349 .l_reg = 0x23004, 350 .m_reg = 0x23008, 351 .n_reg = 0x2300c, 352 .config_reg = 0x23014, 353 .mode_reg = 0x23000, 354 .status_reg = 0x2301c, 355 .status_bit = 17, 356 .clkr.hw.init = &(struct clk_init_data){ 357 .name = "bimc_pll", 358 .parent_names = (const char *[]){ "xo" }, 359 .num_parents = 1, 360 .ops = &clk_pll_ops, 361 }, 362 }; 363 364 static struct clk_regmap bimc_pll_vote = { 365 .enable_reg = 0x45000, 366 .enable_mask = BIT(3), 367 .hw.init = &(struct clk_init_data){ 368 .name = "bimc_pll_vote", 369 .parent_names = (const char *[]){ "bimc_pll" }, 370 .num_parents = 1, 371 .ops = &clk_pll_vote_ops, 372 }, 373 }; 374 375 static struct clk_rcg2 pcnoc_bfdcd_clk_src = { 376 .cmd_rcgr = 0x27000, 377 .hid_width = 5, 378 .parent_map = gcc_xo_gpll0_bimc_map, 379 .clkr.hw.init = &(struct clk_init_data){ 380 .name = "pcnoc_bfdcd_clk_src", 381 .parent_names = gcc_xo_gpll0_bimc, 382 .num_parents = 3, 383 .ops = &clk_rcg2_ops, 384 }, 385 }; 386 387 static struct clk_rcg2 system_noc_bfdcd_clk_src = { 388 .cmd_rcgr = 0x26004, 389 .hid_width = 5, 390 .parent_map = gcc_xo_gpll0_bimc_map, 391 .clkr.hw.init = &(struct clk_init_data){ 392 .name = "system_noc_bfdcd_clk_src", 393 .parent_names = gcc_xo_gpll0_bimc, 394 .num_parents = 3, 395 .ops = &clk_rcg2_ops, 396 }, 397 }; 398 399 static const struct freq_tbl ftbl_gcc_camss_ahb_clk[] = { 400 F(40000000, P_GPLL0, 10, 1, 2), 401 F(80000000, P_GPLL0, 10, 0, 0), 402 { } 403 }; 404 405 static struct clk_rcg2 camss_ahb_clk_src = { 406 .cmd_rcgr = 0x5a000, 407 .mnd_width = 8, 408 .hid_width = 5, 409 .parent_map = gcc_xo_gpll0_map, 410 .freq_tbl = ftbl_gcc_camss_ahb_clk, 411 .clkr.hw.init = &(struct clk_init_data){ 412 .name = "camss_ahb_clk_src", 413 .parent_names = gcc_xo_gpll0, 414 .num_parents = 2, 415 .ops = &clk_rcg2_ops, 416 }, 417 }; 418 419 static const struct freq_tbl ftbl_apss_ahb_clk[] = { 420 F(19200000, P_XO, 1, 0, 0), 421 F(50000000, P_GPLL0, 16, 0, 0), 422 F(100000000, P_GPLL0, 8, 0, 0), 423 F(133330000, P_GPLL0, 6, 0, 0), 424 { } 425 }; 426 427 static struct clk_rcg2 apss_ahb_clk_src = { 428 .cmd_rcgr = 0x46000, 429 .hid_width = 5, 430 .parent_map = gcc_xo_gpll0_map, 431 .freq_tbl = ftbl_apss_ahb_clk, 432 .clkr.hw.init = &(struct clk_init_data){ 433 .name = "apss_ahb_clk_src", 434 .parent_names = gcc_xo_gpll0, 435 .num_parents = 2, 436 .ops = &clk_rcg2_ops, 437 }, 438 }; 439 440 static const struct freq_tbl ftbl_gcc_camss_csi0_1_clk[] = { 441 F(100000000, P_GPLL0, 8, 0, 0), 442 F(200000000, P_GPLL0, 4, 0, 0), 443 { } 444 }; 445 446 static struct clk_rcg2 csi0_clk_src = { 447 .cmd_rcgr = 0x4e020, 448 .hid_width = 5, 449 .parent_map = gcc_xo_gpll0_map, 450 .freq_tbl = ftbl_gcc_camss_csi0_1_clk, 451 .clkr.hw.init = &(struct clk_init_data){ 452 .name = "csi0_clk_src", 453 .parent_names = gcc_xo_gpll0, 454 .num_parents = 2, 455 .ops = &clk_rcg2_ops, 456 }, 457 }; 458 459 static struct clk_rcg2 csi1_clk_src = { 460 .cmd_rcgr = 0x4f020, 461 .hid_width = 5, 462 .parent_map = gcc_xo_gpll0_map, 463 .freq_tbl = ftbl_gcc_camss_csi0_1_clk, 464 .clkr.hw.init = &(struct clk_init_data){ 465 .name = "csi1_clk_src", 466 .parent_names = gcc_xo_gpll0, 467 .num_parents = 2, 468 .ops = &clk_rcg2_ops, 469 }, 470 }; 471 472 static const struct freq_tbl ftbl_gcc_oxili_gfx3d_clk[] = { 473 F(19200000, P_XO, 1, 0, 0), 474 F(50000000, P_GPLL0_AUX, 16, 0, 0), 475 F(80000000, P_GPLL0_AUX, 10, 0, 0), 476 F(100000000, P_GPLL0_AUX, 8, 0, 0), 477 F(160000000, P_GPLL0_AUX, 5, 0, 0), 478 F(177780000, P_GPLL0_AUX, 4.5, 0, 0), 479 F(200000000, P_GPLL0_AUX, 4, 0, 0), 480 F(266670000, P_GPLL0_AUX, 3, 0, 0), 481 F(294912000, P_GPLL1, 3, 0, 0), 482 F(310000000, P_GPLL2, 3, 0, 0), 483 F(400000000, P_GPLL0_AUX, 2, 0, 0), 484 { } 485 }; 486 487 static struct clk_rcg2 gfx3d_clk_src = { 488 .cmd_rcgr = 0x59000, 489 .hid_width = 5, 490 .parent_map = gcc_xo_gpll0a_gpll1_gpll2a_map, 491 .freq_tbl = ftbl_gcc_oxili_gfx3d_clk, 492 .clkr.hw.init = &(struct clk_init_data){ 493 .name = "gfx3d_clk_src", 494 .parent_names = gcc_xo_gpll0a_gpll1_gpll2a, 495 .num_parents = 4, 496 .ops = &clk_rcg2_ops, 497 }, 498 }; 499 500 static const struct freq_tbl ftbl_gcc_camss_vfe0_clk[] = { 501 F(50000000, P_GPLL0, 16, 0, 0), 502 F(80000000, P_GPLL0, 10, 0, 0), 503 F(100000000, P_GPLL0, 8, 0, 0), 504 F(160000000, P_GPLL0, 5, 0, 0), 505 F(177780000, P_GPLL0, 4.5, 0, 0), 506 F(200000000, P_GPLL0, 4, 0, 0), 507 F(266670000, P_GPLL0, 3, 0, 0), 508 F(320000000, P_GPLL0, 2.5, 0, 0), 509 F(400000000, P_GPLL0, 2, 0, 0), 510 F(465000000, P_GPLL2, 2, 0, 0), 511 { } 512 }; 513 514 static struct clk_rcg2 vfe0_clk_src = { 515 .cmd_rcgr = 0x58000, 516 .hid_width = 5, 517 .parent_map = gcc_xo_gpll0_gpll2_map, 518 .freq_tbl = ftbl_gcc_camss_vfe0_clk, 519 .clkr.hw.init = &(struct clk_init_data){ 520 .name = "vfe0_clk_src", 521 .parent_names = gcc_xo_gpll0_gpll2, 522 .num_parents = 3, 523 .ops = &clk_rcg2_ops, 524 }, 525 }; 526 527 static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_i2c_apps_clk[] = { 528 F(19200000, P_XO, 1, 0, 0), 529 F(50000000, P_GPLL0, 16, 0, 0), 530 { } 531 }; 532 533 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { 534 .cmd_rcgr = 0x0200c, 535 .hid_width = 5, 536 .parent_map = gcc_xo_gpll0_map, 537 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, 538 .clkr.hw.init = &(struct clk_init_data){ 539 .name = "blsp1_qup1_i2c_apps_clk_src", 540 .parent_names = gcc_xo_gpll0, 541 .num_parents = 2, 542 .ops = &clk_rcg2_ops, 543 }, 544 }; 545 546 static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_spi_apps_clk[] = { 547 F(960000, P_XO, 10, 1, 2), 548 F(4800000, P_XO, 4, 0, 0), 549 F(9600000, P_XO, 2, 0, 0), 550 F(16000000, P_GPLL0, 10, 1, 5), 551 F(19200000, P_XO, 1, 0, 0), 552 F(25000000, P_GPLL0, 16, 1, 2), 553 F(50000000, P_GPLL0, 16, 0, 0), 554 { } 555 }; 556 557 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { 558 .cmd_rcgr = 0x02024, 559 .mnd_width = 8, 560 .hid_width = 5, 561 .parent_map = gcc_xo_gpll0_map, 562 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, 563 .clkr.hw.init = &(struct clk_init_data){ 564 .name = "blsp1_qup1_spi_apps_clk_src", 565 .parent_names = gcc_xo_gpll0, 566 .num_parents = 2, 567 .ops = &clk_rcg2_ops, 568 }, 569 }; 570 571 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { 572 .cmd_rcgr = 0x03000, 573 .hid_width = 5, 574 .parent_map = gcc_xo_gpll0_map, 575 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, 576 .clkr.hw.init = &(struct clk_init_data){ 577 .name = "blsp1_qup2_i2c_apps_clk_src", 578 .parent_names = gcc_xo_gpll0, 579 .num_parents = 2, 580 .ops = &clk_rcg2_ops, 581 }, 582 }; 583 584 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { 585 .cmd_rcgr = 0x03014, 586 .mnd_width = 8, 587 .hid_width = 5, 588 .parent_map = gcc_xo_gpll0_map, 589 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, 590 .clkr.hw.init = &(struct clk_init_data){ 591 .name = "blsp1_qup2_spi_apps_clk_src", 592 .parent_names = gcc_xo_gpll0, 593 .num_parents = 2, 594 .ops = &clk_rcg2_ops, 595 }, 596 }; 597 598 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { 599 .cmd_rcgr = 0x04000, 600 .hid_width = 5, 601 .parent_map = gcc_xo_gpll0_map, 602 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, 603 .clkr.hw.init = &(struct clk_init_data){ 604 .name = "blsp1_qup3_i2c_apps_clk_src", 605 .parent_names = gcc_xo_gpll0, 606 .num_parents = 2, 607 .ops = &clk_rcg2_ops, 608 }, 609 }; 610 611 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { 612 .cmd_rcgr = 0x04024, 613 .mnd_width = 8, 614 .hid_width = 5, 615 .parent_map = gcc_xo_gpll0_map, 616 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, 617 .clkr.hw.init = &(struct clk_init_data){ 618 .name = "blsp1_qup3_spi_apps_clk_src", 619 .parent_names = gcc_xo_gpll0, 620 .num_parents = 2, 621 .ops = &clk_rcg2_ops, 622 }, 623 }; 624 625 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { 626 .cmd_rcgr = 0x05000, 627 .hid_width = 5, 628 .parent_map = gcc_xo_gpll0_map, 629 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, 630 .clkr.hw.init = &(struct clk_init_data){ 631 .name = "blsp1_qup4_i2c_apps_clk_src", 632 .parent_names = gcc_xo_gpll0, 633 .num_parents = 2, 634 .ops = &clk_rcg2_ops, 635 }, 636 }; 637 638 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { 639 .cmd_rcgr = 0x05024, 640 .mnd_width = 8, 641 .hid_width = 5, 642 .parent_map = gcc_xo_gpll0_map, 643 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, 644 .clkr.hw.init = &(struct clk_init_data){ 645 .name = "blsp1_qup4_spi_apps_clk_src", 646 .parent_names = gcc_xo_gpll0, 647 .num_parents = 2, 648 .ops = &clk_rcg2_ops, 649 }, 650 }; 651 652 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = { 653 .cmd_rcgr = 0x06000, 654 .hid_width = 5, 655 .parent_map = gcc_xo_gpll0_map, 656 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, 657 .clkr.hw.init = &(struct clk_init_data){ 658 .name = "blsp1_qup5_i2c_apps_clk_src", 659 .parent_names = gcc_xo_gpll0, 660 .num_parents = 2, 661 .ops = &clk_rcg2_ops, 662 }, 663 }; 664 665 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = { 666 .cmd_rcgr = 0x06024, 667 .mnd_width = 8, 668 .hid_width = 5, 669 .parent_map = gcc_xo_gpll0_map, 670 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, 671 .clkr.hw.init = &(struct clk_init_data){ 672 .name = "blsp1_qup5_spi_apps_clk_src", 673 .parent_names = gcc_xo_gpll0, 674 .num_parents = 2, 675 .ops = &clk_rcg2_ops, 676 }, 677 }; 678 679 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = { 680 .cmd_rcgr = 0x07000, 681 .hid_width = 5, 682 .parent_map = gcc_xo_gpll0_map, 683 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, 684 .clkr.hw.init = &(struct clk_init_data){ 685 .name = "blsp1_qup6_i2c_apps_clk_src", 686 .parent_names = gcc_xo_gpll0, 687 .num_parents = 2, 688 .ops = &clk_rcg2_ops, 689 }, 690 }; 691 692 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = { 693 .cmd_rcgr = 0x07024, 694 .mnd_width = 8, 695 .hid_width = 5, 696 .parent_map = gcc_xo_gpll0_map, 697 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, 698 .clkr.hw.init = &(struct clk_init_data){ 699 .name = "blsp1_qup6_spi_apps_clk_src", 700 .parent_names = gcc_xo_gpll0, 701 .num_parents = 2, 702 .ops = &clk_rcg2_ops, 703 }, 704 }; 705 706 static const struct freq_tbl ftbl_gcc_blsp1_uart1_6_apps_clk[] = { 707 F(3686400, P_GPLL0, 1, 72, 15625), 708 F(7372800, P_GPLL0, 1, 144, 15625), 709 F(14745600, P_GPLL0, 1, 288, 15625), 710 F(16000000, P_GPLL0, 10, 1, 5), 711 F(19200000, P_XO, 1, 0, 0), 712 F(24000000, P_GPLL0, 1, 3, 100), 713 F(25000000, P_GPLL0, 16, 1, 2), 714 F(32000000, P_GPLL0, 1, 1, 25), 715 F(40000000, P_GPLL0, 1, 1, 20), 716 F(46400000, P_GPLL0, 1, 29, 500), 717 F(48000000, P_GPLL0, 1, 3, 50), 718 F(51200000, P_GPLL0, 1, 8, 125), 719 F(56000000, P_GPLL0, 1, 7, 100), 720 F(58982400, P_GPLL0, 1, 1152, 15625), 721 F(60000000, P_GPLL0, 1, 3, 40), 722 { } 723 }; 724 725 static struct clk_rcg2 blsp1_uart1_apps_clk_src = { 726 .cmd_rcgr = 0x02044, 727 .mnd_width = 16, 728 .hid_width = 5, 729 .parent_map = gcc_xo_gpll0_map, 730 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk, 731 .clkr.hw.init = &(struct clk_init_data){ 732 .name = "blsp1_uart1_apps_clk_src", 733 .parent_names = gcc_xo_gpll0, 734 .num_parents = 2, 735 .ops = &clk_rcg2_ops, 736 }, 737 }; 738 739 static struct clk_rcg2 blsp1_uart2_apps_clk_src = { 740 .cmd_rcgr = 0x03034, 741 .mnd_width = 16, 742 .hid_width = 5, 743 .parent_map = gcc_xo_gpll0_map, 744 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk, 745 .clkr.hw.init = &(struct clk_init_data){ 746 .name = "blsp1_uart2_apps_clk_src", 747 .parent_names = gcc_xo_gpll0, 748 .num_parents = 2, 749 .ops = &clk_rcg2_ops, 750 }, 751 }; 752 753 static const struct freq_tbl ftbl_gcc_camss_cci_clk[] = { 754 F(19200000, P_XO, 1, 0, 0), 755 { } 756 }; 757 758 static struct clk_rcg2 cci_clk_src = { 759 .cmd_rcgr = 0x51000, 760 .mnd_width = 8, 761 .hid_width = 5, 762 .parent_map = gcc_xo_gpll0a_map, 763 .freq_tbl = ftbl_gcc_camss_cci_clk, 764 .clkr.hw.init = &(struct clk_init_data){ 765 .name = "cci_clk_src", 766 .parent_names = gcc_xo_gpll0a, 767 .num_parents = 2, 768 .ops = &clk_rcg2_ops, 769 }, 770 }; 771 772 static const struct freq_tbl ftbl_gcc_camss_gp0_1_clk[] = { 773 F(100000000, P_GPLL0, 8, 0, 0), 774 F(200000000, P_GPLL0, 4, 0, 0), 775 { } 776 }; 777 778 static struct clk_rcg2 camss_gp0_clk_src = { 779 .cmd_rcgr = 0x54000, 780 .mnd_width = 8, 781 .hid_width = 5, 782 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map, 783 .freq_tbl = ftbl_gcc_camss_gp0_1_clk, 784 .clkr.hw.init = &(struct clk_init_data){ 785 .name = "camss_gp0_clk_src", 786 .parent_names = gcc_xo_gpll0_gpll1a_sleep, 787 .num_parents = 4, 788 .ops = &clk_rcg2_ops, 789 }, 790 }; 791 792 static struct clk_rcg2 camss_gp1_clk_src = { 793 .cmd_rcgr = 0x55000, 794 .mnd_width = 8, 795 .hid_width = 5, 796 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map, 797 .freq_tbl = ftbl_gcc_camss_gp0_1_clk, 798 .clkr.hw.init = &(struct clk_init_data){ 799 .name = "camss_gp1_clk_src", 800 .parent_names = gcc_xo_gpll0_gpll1a_sleep, 801 .num_parents = 4, 802 .ops = &clk_rcg2_ops, 803 }, 804 }; 805 806 static const struct freq_tbl ftbl_gcc_camss_jpeg0_clk[] = { 807 F(133330000, P_GPLL0, 6, 0, 0), 808 F(266670000, P_GPLL0, 3, 0, 0), 809 F(320000000, P_GPLL0, 2.5, 0, 0), 810 { } 811 }; 812 813 static struct clk_rcg2 jpeg0_clk_src = { 814 .cmd_rcgr = 0x57000, 815 .hid_width = 5, 816 .parent_map = gcc_xo_gpll0_map, 817 .freq_tbl = ftbl_gcc_camss_jpeg0_clk, 818 .clkr.hw.init = &(struct clk_init_data){ 819 .name = "jpeg0_clk_src", 820 .parent_names = gcc_xo_gpll0, 821 .num_parents = 2, 822 .ops = &clk_rcg2_ops, 823 }, 824 }; 825 826 static const struct freq_tbl ftbl_gcc_camss_mclk0_1_clk[] = { 827 F(9600000, P_XO, 2, 0, 0), 828 F(23880000, P_GPLL0, 1, 2, 67), 829 F(66670000, P_GPLL0, 12, 0, 0), 830 { } 831 }; 832 833 static struct clk_rcg2 mclk0_clk_src = { 834 .cmd_rcgr = 0x52000, 835 .mnd_width = 8, 836 .hid_width = 5, 837 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map, 838 .freq_tbl = ftbl_gcc_camss_mclk0_1_clk, 839 .clkr.hw.init = &(struct clk_init_data){ 840 .name = "mclk0_clk_src", 841 .parent_names = gcc_xo_gpll0_gpll1a_sleep, 842 .num_parents = 4, 843 .ops = &clk_rcg2_ops, 844 }, 845 }; 846 847 static struct clk_rcg2 mclk1_clk_src = { 848 .cmd_rcgr = 0x53000, 849 .mnd_width = 8, 850 .hid_width = 5, 851 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map, 852 .freq_tbl = ftbl_gcc_camss_mclk0_1_clk, 853 .clkr.hw.init = &(struct clk_init_data){ 854 .name = "mclk1_clk_src", 855 .parent_names = gcc_xo_gpll0_gpll1a_sleep, 856 .num_parents = 4, 857 .ops = &clk_rcg2_ops, 858 }, 859 }; 860 861 static const struct freq_tbl ftbl_gcc_camss_csi0_1phytimer_clk[] = { 862 F(100000000, P_GPLL0, 8, 0, 0), 863 F(200000000, P_GPLL0, 4, 0, 0), 864 { } 865 }; 866 867 static struct clk_rcg2 csi0phytimer_clk_src = { 868 .cmd_rcgr = 0x4e000, 869 .hid_width = 5, 870 .parent_map = gcc_xo_gpll0_gpll1a_map, 871 .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk, 872 .clkr.hw.init = &(struct clk_init_data){ 873 .name = "csi0phytimer_clk_src", 874 .parent_names = gcc_xo_gpll0_gpll1a, 875 .num_parents = 3, 876 .ops = &clk_rcg2_ops, 877 }, 878 }; 879 880 static struct clk_rcg2 csi1phytimer_clk_src = { 881 .cmd_rcgr = 0x4f000, 882 .hid_width = 5, 883 .parent_map = gcc_xo_gpll0_gpll1a_map, 884 .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk, 885 .clkr.hw.init = &(struct clk_init_data){ 886 .name = "csi1phytimer_clk_src", 887 .parent_names = gcc_xo_gpll0_gpll1a, 888 .num_parents = 3, 889 .ops = &clk_rcg2_ops, 890 }, 891 }; 892 893 static const struct freq_tbl ftbl_gcc_camss_cpp_clk[] = { 894 F(160000000, P_GPLL0, 5, 0, 0), 895 F(320000000, P_GPLL0, 2.5, 0, 0), 896 F(465000000, P_GPLL2, 2, 0, 0), 897 { } 898 }; 899 900 static struct clk_rcg2 cpp_clk_src = { 901 .cmd_rcgr = 0x58018, 902 .hid_width = 5, 903 .parent_map = gcc_xo_gpll0_gpll2_map, 904 .freq_tbl = ftbl_gcc_camss_cpp_clk, 905 .clkr.hw.init = &(struct clk_init_data){ 906 .name = "cpp_clk_src", 907 .parent_names = gcc_xo_gpll0_gpll2, 908 .num_parents = 3, 909 .ops = &clk_rcg2_ops, 910 }, 911 }; 912 913 static const struct freq_tbl ftbl_gcc_crypto_clk[] = { 914 F(50000000, P_GPLL0, 16, 0, 0), 915 F(80000000, P_GPLL0, 10, 0, 0), 916 F(100000000, P_GPLL0, 8, 0, 0), 917 F(160000000, P_GPLL0, 5, 0, 0), 918 { } 919 }; 920 921 static struct clk_rcg2 crypto_clk_src = { 922 .cmd_rcgr = 0x16004, 923 .hid_width = 5, 924 .parent_map = gcc_xo_gpll0_map, 925 .freq_tbl = ftbl_gcc_crypto_clk, 926 .clkr.hw.init = &(struct clk_init_data){ 927 .name = "crypto_clk_src", 928 .parent_names = gcc_xo_gpll0, 929 .num_parents = 2, 930 .ops = &clk_rcg2_ops, 931 }, 932 }; 933 934 static const struct freq_tbl ftbl_gcc_gp1_3_clk[] = { 935 F(19200000, P_XO, 1, 0, 0), 936 { } 937 }; 938 939 static struct clk_rcg2 gp1_clk_src = { 940 .cmd_rcgr = 0x08004, 941 .mnd_width = 8, 942 .hid_width = 5, 943 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map, 944 .freq_tbl = ftbl_gcc_gp1_3_clk, 945 .clkr.hw.init = &(struct clk_init_data){ 946 .name = "gp1_clk_src", 947 .parent_names = gcc_xo_gpll0_gpll1a_sleep, 948 .num_parents = 3, 949 .ops = &clk_rcg2_ops, 950 }, 951 }; 952 953 static struct clk_rcg2 gp2_clk_src = { 954 .cmd_rcgr = 0x09004, 955 .mnd_width = 8, 956 .hid_width = 5, 957 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map, 958 .freq_tbl = ftbl_gcc_gp1_3_clk, 959 .clkr.hw.init = &(struct clk_init_data){ 960 .name = "gp2_clk_src", 961 .parent_names = gcc_xo_gpll0_gpll1a_sleep, 962 .num_parents = 3, 963 .ops = &clk_rcg2_ops, 964 }, 965 }; 966 967 static struct clk_rcg2 gp3_clk_src = { 968 .cmd_rcgr = 0x0a004, 969 .mnd_width = 8, 970 .hid_width = 5, 971 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map, 972 .freq_tbl = ftbl_gcc_gp1_3_clk, 973 .clkr.hw.init = &(struct clk_init_data){ 974 .name = "gp3_clk_src", 975 .parent_names = gcc_xo_gpll0_gpll1a_sleep, 976 .num_parents = 3, 977 .ops = &clk_rcg2_ops, 978 }, 979 }; 980 981 static struct clk_rcg2 byte0_clk_src = { 982 .cmd_rcgr = 0x4d044, 983 .hid_width = 5, 984 .parent_map = gcc_xo_gpll0a_dsibyte_map, 985 .clkr.hw.init = &(struct clk_init_data){ 986 .name = "byte0_clk_src", 987 .parent_names = gcc_xo_gpll0a_dsibyte, 988 .num_parents = 3, 989 .ops = &clk_byte2_ops, 990 .flags = CLK_SET_RATE_PARENT, 991 }, 992 }; 993 994 static const struct freq_tbl ftbl_gcc_mdss_esc0_clk[] = { 995 F(19200000, P_XO, 1, 0, 0), 996 { } 997 }; 998 999 static struct clk_rcg2 esc0_clk_src = { 1000 .cmd_rcgr = 0x4d05c, 1001 .hid_width = 5, 1002 .parent_map = gcc_xo_dsibyte_map, 1003 .freq_tbl = ftbl_gcc_mdss_esc0_clk, 1004 .clkr.hw.init = &(struct clk_init_data){ 1005 .name = "esc0_clk_src", 1006 .parent_names = gcc_xo_dsibyte, 1007 .num_parents = 2, 1008 .ops = &clk_rcg2_ops, 1009 }, 1010 }; 1011 1012 static const struct freq_tbl ftbl_gcc_mdss_mdp_clk[] = { 1013 F(50000000, P_GPLL0, 16, 0, 0), 1014 F(80000000, P_GPLL0, 10, 0, 0), 1015 F(100000000, P_GPLL0, 8, 0, 0), 1016 F(160000000, P_GPLL0, 5, 0, 0), 1017 F(177780000, P_GPLL0, 4.5, 0, 0), 1018 F(200000000, P_GPLL0, 4, 0, 0), 1019 F(266670000, P_GPLL0, 3, 0, 0), 1020 F(320000000, P_GPLL0, 2.5, 0, 0), 1021 { } 1022 }; 1023 1024 static struct clk_rcg2 mdp_clk_src = { 1025 .cmd_rcgr = 0x4d014, 1026 .hid_width = 5, 1027 .parent_map = gcc_xo_gpll0_dsiphy_map, 1028 .freq_tbl = ftbl_gcc_mdss_mdp_clk, 1029 .clkr.hw.init = &(struct clk_init_data){ 1030 .name = "mdp_clk_src", 1031 .parent_names = gcc_xo_gpll0_dsiphy, 1032 .num_parents = 3, 1033 .ops = &clk_rcg2_ops, 1034 }, 1035 }; 1036 1037 static struct clk_rcg2 pclk0_clk_src = { 1038 .cmd_rcgr = 0x4d000, 1039 .mnd_width = 8, 1040 .hid_width = 5, 1041 .parent_map = gcc_xo_gpll0a_dsiphy_map, 1042 .clkr.hw.init = &(struct clk_init_data){ 1043 .name = "pclk0_clk_src", 1044 .parent_names = gcc_xo_gpll0a_dsiphy, 1045 .num_parents = 3, 1046 .ops = &clk_pixel_ops, 1047 .flags = CLK_SET_RATE_PARENT, 1048 }, 1049 }; 1050 1051 static const struct freq_tbl ftbl_gcc_mdss_vsync_clk[] = { 1052 F(19200000, P_XO, 1, 0, 0), 1053 { } 1054 }; 1055 1056 static struct clk_rcg2 vsync_clk_src = { 1057 .cmd_rcgr = 0x4d02c, 1058 .hid_width = 5, 1059 .parent_map = gcc_xo_gpll0a_map, 1060 .freq_tbl = ftbl_gcc_mdss_vsync_clk, 1061 .clkr.hw.init = &(struct clk_init_data){ 1062 .name = "vsync_clk_src", 1063 .parent_names = gcc_xo_gpll0a, 1064 .num_parents = 2, 1065 .ops = &clk_rcg2_ops, 1066 }, 1067 }; 1068 1069 static const struct freq_tbl ftbl_gcc_pdm2_clk[] = { 1070 F(64000000, P_GPLL0, 12.5, 0, 0), 1071 { } 1072 }; 1073 1074 static struct clk_rcg2 pdm2_clk_src = { 1075 .cmd_rcgr = 0x44010, 1076 .hid_width = 5, 1077 .parent_map = gcc_xo_gpll0_map, 1078 .freq_tbl = ftbl_gcc_pdm2_clk, 1079 .clkr.hw.init = &(struct clk_init_data){ 1080 .name = "pdm2_clk_src", 1081 .parent_names = gcc_xo_gpll0, 1082 .num_parents = 2, 1083 .ops = &clk_rcg2_ops, 1084 }, 1085 }; 1086 1087 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk[] = { 1088 F(144000, P_XO, 16, 3, 25), 1089 F(400000, P_XO, 12, 1, 4), 1090 F(20000000, P_GPLL0, 10, 1, 4), 1091 F(25000000, P_GPLL0, 16, 1, 2), 1092 F(50000000, P_GPLL0, 16, 0, 0), 1093 F(100000000, P_GPLL0, 8, 0, 0), 1094 F(177770000, P_GPLL0, 4.5, 0, 0), 1095 { } 1096 }; 1097 1098 static struct clk_rcg2 sdcc1_apps_clk_src = { 1099 .cmd_rcgr = 0x42004, 1100 .mnd_width = 8, 1101 .hid_width = 5, 1102 .parent_map = gcc_xo_gpll0_map, 1103 .freq_tbl = ftbl_gcc_sdcc1_apps_clk, 1104 .clkr.hw.init = &(struct clk_init_data){ 1105 .name = "sdcc1_apps_clk_src", 1106 .parent_names = gcc_xo_gpll0, 1107 .num_parents = 2, 1108 .ops = &clk_rcg2_floor_ops, 1109 }, 1110 }; 1111 1112 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk[] = { 1113 F(144000, P_XO, 16, 3, 25), 1114 F(400000, P_XO, 12, 1, 4), 1115 F(20000000, P_GPLL0, 10, 1, 4), 1116 F(25000000, P_GPLL0, 16, 1, 2), 1117 F(50000000, P_GPLL0, 16, 0, 0), 1118 F(100000000, P_GPLL0, 8, 0, 0), 1119 F(200000000, P_GPLL0, 4, 0, 0), 1120 { } 1121 }; 1122 1123 static struct clk_rcg2 sdcc2_apps_clk_src = { 1124 .cmd_rcgr = 0x43004, 1125 .mnd_width = 8, 1126 .hid_width = 5, 1127 .parent_map = gcc_xo_gpll0_map, 1128 .freq_tbl = ftbl_gcc_sdcc2_apps_clk, 1129 .clkr.hw.init = &(struct clk_init_data){ 1130 .name = "sdcc2_apps_clk_src", 1131 .parent_names = gcc_xo_gpll0, 1132 .num_parents = 2, 1133 .ops = &clk_rcg2_floor_ops, 1134 }, 1135 }; 1136 1137 static const struct freq_tbl ftbl_gcc_apss_tcu_clk[] = { 1138 F(155000000, P_GPLL2, 6, 0, 0), 1139 F(310000000, P_GPLL2, 3, 0, 0), 1140 F(400000000, P_GPLL0, 2, 0, 0), 1141 { } 1142 }; 1143 1144 static struct clk_rcg2 apss_tcu_clk_src = { 1145 .cmd_rcgr = 0x1207c, 1146 .hid_width = 5, 1147 .parent_map = gcc_xo_gpll0a_gpll1_gpll2_map, 1148 .freq_tbl = ftbl_gcc_apss_tcu_clk, 1149 .clkr.hw.init = &(struct clk_init_data){ 1150 .name = "apss_tcu_clk_src", 1151 .parent_names = gcc_xo_gpll0a_gpll1_gpll2, 1152 .num_parents = 4, 1153 .ops = &clk_rcg2_ops, 1154 }, 1155 }; 1156 1157 static const struct freq_tbl ftbl_gcc_bimc_gpu_clk[] = { 1158 F(19200000, P_XO, 1, 0, 0), 1159 F(100000000, P_GPLL0, 8, 0, 0), 1160 F(200000000, P_GPLL0, 4, 0, 0), 1161 F(266500000, P_BIMC, 4, 0, 0), 1162 F(400000000, P_GPLL0, 2, 0, 0), 1163 F(533000000, P_BIMC, 2, 0, 0), 1164 { } 1165 }; 1166 1167 static struct clk_rcg2 bimc_gpu_clk_src = { 1168 .cmd_rcgr = 0x31028, 1169 .hid_width = 5, 1170 .parent_map = gcc_xo_gpll0_bimc_map, 1171 .freq_tbl = ftbl_gcc_bimc_gpu_clk, 1172 .clkr.hw.init = &(struct clk_init_data){ 1173 .name = "bimc_gpu_clk_src", 1174 .parent_names = gcc_xo_gpll0_bimc, 1175 .num_parents = 3, 1176 .flags = CLK_GET_RATE_NOCACHE, 1177 .ops = &clk_rcg2_ops, 1178 }, 1179 }; 1180 1181 static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = { 1182 F(80000000, P_GPLL0, 10, 0, 0), 1183 { } 1184 }; 1185 1186 static struct clk_rcg2 usb_hs_system_clk_src = { 1187 .cmd_rcgr = 0x41010, 1188 .hid_width = 5, 1189 .parent_map = gcc_xo_gpll0_map, 1190 .freq_tbl = ftbl_gcc_usb_hs_system_clk, 1191 .clkr.hw.init = &(struct clk_init_data){ 1192 .name = "usb_hs_system_clk_src", 1193 .parent_names = gcc_xo_gpll0, 1194 .num_parents = 2, 1195 .ops = &clk_rcg2_ops, 1196 }, 1197 }; 1198 1199 static const struct freq_tbl ftbl_gcc_ultaudio_ahb_clk[] = { 1200 F(3200000, P_XO, 6, 0, 0), 1201 F(6400000, P_XO, 3, 0, 0), 1202 F(9600000, P_XO, 2, 0, 0), 1203 F(19200000, P_XO, 1, 0, 0), 1204 F(40000000, P_GPLL0, 10, 1, 2), 1205 F(66670000, P_GPLL0, 12, 0, 0), 1206 F(80000000, P_GPLL0, 10, 0, 0), 1207 F(100000000, P_GPLL0, 8, 0, 0), 1208 { } 1209 }; 1210 1211 static struct clk_rcg2 ultaudio_ahbfabric_clk_src = { 1212 .cmd_rcgr = 0x1c010, 1213 .hid_width = 5, 1214 .mnd_width = 8, 1215 .parent_map = gcc_xo_gpll0_gpll1_sleep_map, 1216 .freq_tbl = ftbl_gcc_ultaudio_ahb_clk, 1217 .clkr.hw.init = &(struct clk_init_data){ 1218 .name = "ultaudio_ahbfabric_clk_src", 1219 .parent_names = gcc_xo_gpll0_gpll1_sleep, 1220 .num_parents = 4, 1221 .ops = &clk_rcg2_ops, 1222 }, 1223 }; 1224 1225 static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_clk = { 1226 .halt_reg = 0x1c028, 1227 .clkr = { 1228 .enable_reg = 0x1c028, 1229 .enable_mask = BIT(0), 1230 .hw.init = &(struct clk_init_data){ 1231 .name = "gcc_ultaudio_ahbfabric_ixfabric_clk", 1232 .parent_names = (const char *[]){ 1233 "ultaudio_ahbfabric_clk_src", 1234 }, 1235 .num_parents = 1, 1236 .flags = CLK_SET_RATE_PARENT, 1237 .ops = &clk_branch2_ops, 1238 }, 1239 }, 1240 }; 1241 1242 static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_lpm_clk = { 1243 .halt_reg = 0x1c024, 1244 .clkr = { 1245 .enable_reg = 0x1c024, 1246 .enable_mask = BIT(0), 1247 .hw.init = &(struct clk_init_data){ 1248 .name = "gcc_ultaudio_ahbfabric_ixfabric_lpm_clk", 1249 .parent_names = (const char *[]){ 1250 "ultaudio_ahbfabric_clk_src", 1251 }, 1252 .num_parents = 1, 1253 .flags = CLK_SET_RATE_PARENT, 1254 .ops = &clk_branch2_ops, 1255 }, 1256 }, 1257 }; 1258 1259 static const struct freq_tbl ftbl_gcc_ultaudio_lpaif_i2s_clk[] = { 1260 F(128000, P_XO, 10, 1, 15), 1261 F(256000, P_XO, 5, 1, 15), 1262 F(384000, P_XO, 5, 1, 10), 1263 F(512000, P_XO, 5, 2, 15), 1264 F(576000, P_XO, 5, 3, 20), 1265 F(705600, P_GPLL1, 16, 1, 80), 1266 F(768000, P_XO, 5, 1, 5), 1267 F(800000, P_XO, 5, 5, 24), 1268 F(1024000, P_XO, 5, 4, 15), 1269 F(1152000, P_XO, 1, 3, 50), 1270 F(1411200, P_GPLL1, 16, 1, 40), 1271 F(1536000, P_XO, 1, 2, 25), 1272 F(1600000, P_XO, 12, 0, 0), 1273 F(1728000, P_XO, 5, 9, 20), 1274 F(2048000, P_XO, 5, 8, 15), 1275 F(2304000, P_XO, 5, 3, 5), 1276 F(2400000, P_XO, 8, 0, 0), 1277 F(2822400, P_GPLL1, 16, 1, 20), 1278 F(3072000, P_XO, 5, 4, 5), 1279 F(4096000, P_GPLL1, 9, 2, 49), 1280 F(4800000, P_XO, 4, 0, 0), 1281 F(5644800, P_GPLL1, 16, 1, 10), 1282 F(6144000, P_GPLL1, 7, 1, 21), 1283 F(8192000, P_GPLL1, 9, 4, 49), 1284 F(9600000, P_XO, 2, 0, 0), 1285 F(11289600, P_GPLL1, 16, 1, 5), 1286 F(12288000, P_GPLL1, 7, 2, 21), 1287 { } 1288 }; 1289 1290 static struct clk_rcg2 ultaudio_lpaif_pri_i2s_clk_src = { 1291 .cmd_rcgr = 0x1c054, 1292 .hid_width = 5, 1293 .mnd_width = 8, 1294 .parent_map = gcc_xo_gpll1_epi2s_emclk_sleep_map, 1295 .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk, 1296 .clkr.hw.init = &(struct clk_init_data){ 1297 .name = "ultaudio_lpaif_pri_i2s_clk_src", 1298 .parent_names = gcc_xo_gpll1_epi2s_emclk_sleep, 1299 .num_parents = 5, 1300 .ops = &clk_rcg2_ops, 1301 }, 1302 }; 1303 1304 static struct clk_branch gcc_ultaudio_lpaif_pri_i2s_clk = { 1305 .halt_reg = 0x1c068, 1306 .clkr = { 1307 .enable_reg = 0x1c068, 1308 .enable_mask = BIT(0), 1309 .hw.init = &(struct clk_init_data){ 1310 .name = "gcc_ultaudio_lpaif_pri_i2s_clk", 1311 .parent_names = (const char *[]){ 1312 "ultaudio_lpaif_pri_i2s_clk_src", 1313 }, 1314 .num_parents = 1, 1315 .flags = CLK_SET_RATE_PARENT, 1316 .ops = &clk_branch2_ops, 1317 }, 1318 }, 1319 }; 1320 1321 static struct clk_rcg2 ultaudio_lpaif_sec_i2s_clk_src = { 1322 .cmd_rcgr = 0x1c06c, 1323 .hid_width = 5, 1324 .mnd_width = 8, 1325 .parent_map = gcc_xo_gpll1_esi2s_emclk_sleep_map, 1326 .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk, 1327 .clkr.hw.init = &(struct clk_init_data){ 1328 .name = "ultaudio_lpaif_sec_i2s_clk_src", 1329 .parent_names = gcc_xo_gpll1_esi2s_emclk_sleep, 1330 .num_parents = 5, 1331 .ops = &clk_rcg2_ops, 1332 }, 1333 }; 1334 1335 static struct clk_branch gcc_ultaudio_lpaif_sec_i2s_clk = { 1336 .halt_reg = 0x1c080, 1337 .clkr = { 1338 .enable_reg = 0x1c080, 1339 .enable_mask = BIT(0), 1340 .hw.init = &(struct clk_init_data){ 1341 .name = "gcc_ultaudio_lpaif_sec_i2s_clk", 1342 .parent_names = (const char *[]){ 1343 "ultaudio_lpaif_sec_i2s_clk_src", 1344 }, 1345 .num_parents = 1, 1346 .flags = CLK_SET_RATE_PARENT, 1347 .ops = &clk_branch2_ops, 1348 }, 1349 }, 1350 }; 1351 1352 static struct clk_rcg2 ultaudio_lpaif_aux_i2s_clk_src = { 1353 .cmd_rcgr = 0x1c084, 1354 .hid_width = 5, 1355 .mnd_width = 8, 1356 .parent_map = gcc_xo_gpll1_emclk_sleep_map, 1357 .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk, 1358 .clkr.hw.init = &(struct clk_init_data){ 1359 .name = "ultaudio_lpaif_aux_i2s_clk_src", 1360 .parent_names = gcc_xo_gpll1_esi2s_emclk_sleep, 1361 .num_parents = 5, 1362 .ops = &clk_rcg2_ops, 1363 }, 1364 }; 1365 1366 static struct clk_branch gcc_ultaudio_lpaif_aux_i2s_clk = { 1367 .halt_reg = 0x1c098, 1368 .clkr = { 1369 .enable_reg = 0x1c098, 1370 .enable_mask = BIT(0), 1371 .hw.init = &(struct clk_init_data){ 1372 .name = "gcc_ultaudio_lpaif_aux_i2s_clk", 1373 .parent_names = (const char *[]){ 1374 "ultaudio_lpaif_aux_i2s_clk_src", 1375 }, 1376 .num_parents = 1, 1377 .flags = CLK_SET_RATE_PARENT, 1378 .ops = &clk_branch2_ops, 1379 }, 1380 }, 1381 }; 1382 1383 static const struct freq_tbl ftbl_gcc_ultaudio_xo_clk[] = { 1384 F(19200000, P_XO, 1, 0, 0), 1385 { } 1386 }; 1387 1388 static struct clk_rcg2 ultaudio_xo_clk_src = { 1389 .cmd_rcgr = 0x1c034, 1390 .hid_width = 5, 1391 .parent_map = gcc_xo_sleep_map, 1392 .freq_tbl = ftbl_gcc_ultaudio_xo_clk, 1393 .clkr.hw.init = &(struct clk_init_data){ 1394 .name = "ultaudio_xo_clk_src", 1395 .parent_names = gcc_xo_sleep, 1396 .num_parents = 2, 1397 .ops = &clk_rcg2_ops, 1398 }, 1399 }; 1400 1401 static struct clk_branch gcc_ultaudio_avsync_xo_clk = { 1402 .halt_reg = 0x1c04c, 1403 .clkr = { 1404 .enable_reg = 0x1c04c, 1405 .enable_mask = BIT(0), 1406 .hw.init = &(struct clk_init_data){ 1407 .name = "gcc_ultaudio_avsync_xo_clk", 1408 .parent_names = (const char *[]){ 1409 "ultaudio_xo_clk_src", 1410 }, 1411 .num_parents = 1, 1412 .flags = CLK_SET_RATE_PARENT, 1413 .ops = &clk_branch2_ops, 1414 }, 1415 }, 1416 }; 1417 1418 static struct clk_branch gcc_ultaudio_stc_xo_clk = { 1419 .halt_reg = 0x1c050, 1420 .clkr = { 1421 .enable_reg = 0x1c050, 1422 .enable_mask = BIT(0), 1423 .hw.init = &(struct clk_init_data){ 1424 .name = "gcc_ultaudio_stc_xo_clk", 1425 .parent_names = (const char *[]){ 1426 "ultaudio_xo_clk_src", 1427 }, 1428 .num_parents = 1, 1429 .flags = CLK_SET_RATE_PARENT, 1430 .ops = &clk_branch2_ops, 1431 }, 1432 }, 1433 }; 1434 1435 static const struct freq_tbl ftbl_codec_clk[] = { 1436 F(9600000, P_XO, 2, 0, 0), 1437 F(12288000, P_XO, 1, 16, 25), 1438 F(19200000, P_XO, 1, 0, 0), 1439 F(11289600, P_EXT_MCLK, 1, 0, 0), 1440 { } 1441 }; 1442 1443 static struct clk_rcg2 codec_digcodec_clk_src = { 1444 .cmd_rcgr = 0x1c09c, 1445 .mnd_width = 8, 1446 .hid_width = 5, 1447 .parent_map = gcc_xo_gpll1_emclk_sleep_map, 1448 .freq_tbl = ftbl_codec_clk, 1449 .clkr.hw.init = &(struct clk_init_data){ 1450 .name = "codec_digcodec_clk_src", 1451 .parent_names = gcc_xo_gpll1_emclk_sleep, 1452 .num_parents = 4, 1453 .ops = &clk_rcg2_ops, 1454 }, 1455 }; 1456 1457 static struct clk_branch gcc_codec_digcodec_clk = { 1458 .halt_reg = 0x1c0b0, 1459 .clkr = { 1460 .enable_reg = 0x1c0b0, 1461 .enable_mask = BIT(0), 1462 .hw.init = &(struct clk_init_data){ 1463 .name = "gcc_ultaudio_codec_digcodec_clk", 1464 .parent_names = (const char *[]){ 1465 "codec_digcodec_clk_src", 1466 }, 1467 .num_parents = 1, 1468 .flags = CLK_SET_RATE_PARENT, 1469 .ops = &clk_branch2_ops, 1470 }, 1471 }, 1472 }; 1473 1474 static struct clk_branch gcc_ultaudio_pcnoc_mport_clk = { 1475 .halt_reg = 0x1c000, 1476 .clkr = { 1477 .enable_reg = 0x1c000, 1478 .enable_mask = BIT(0), 1479 .hw.init = &(struct clk_init_data){ 1480 .name = "gcc_ultaudio_pcnoc_mport_clk", 1481 .parent_names = (const char *[]){ 1482 "pcnoc_bfdcd_clk_src", 1483 }, 1484 .num_parents = 1, 1485 .ops = &clk_branch2_ops, 1486 }, 1487 }, 1488 }; 1489 1490 static struct clk_branch gcc_ultaudio_pcnoc_sway_clk = { 1491 .halt_reg = 0x1c004, 1492 .clkr = { 1493 .enable_reg = 0x1c004, 1494 .enable_mask = BIT(0), 1495 .hw.init = &(struct clk_init_data){ 1496 .name = "gcc_ultaudio_pcnoc_sway_clk", 1497 .parent_names = (const char *[]){ 1498 "pcnoc_bfdcd_clk_src", 1499 }, 1500 .num_parents = 1, 1501 .ops = &clk_branch2_ops, 1502 }, 1503 }, 1504 }; 1505 1506 static const struct freq_tbl ftbl_gcc_venus0_vcodec0_clk[] = { 1507 F(100000000, P_GPLL0, 8, 0, 0), 1508 F(160000000, P_GPLL0, 5, 0, 0), 1509 F(228570000, P_GPLL0, 3.5, 0, 0), 1510 { } 1511 }; 1512 1513 static struct clk_rcg2 vcodec0_clk_src = { 1514 .cmd_rcgr = 0x4C000, 1515 .mnd_width = 8, 1516 .hid_width = 5, 1517 .parent_map = gcc_xo_gpll0_map, 1518 .freq_tbl = ftbl_gcc_venus0_vcodec0_clk, 1519 .clkr.hw.init = &(struct clk_init_data){ 1520 .name = "vcodec0_clk_src", 1521 .parent_names = gcc_xo_gpll0, 1522 .num_parents = 2, 1523 .ops = &clk_rcg2_ops, 1524 }, 1525 }; 1526 1527 static struct clk_branch gcc_blsp1_ahb_clk = { 1528 .halt_reg = 0x01008, 1529 .halt_check = BRANCH_HALT_VOTED, 1530 .clkr = { 1531 .enable_reg = 0x45004, 1532 .enable_mask = BIT(10), 1533 .hw.init = &(struct clk_init_data){ 1534 .name = "gcc_blsp1_ahb_clk", 1535 .parent_names = (const char *[]){ 1536 "pcnoc_bfdcd_clk_src", 1537 }, 1538 .num_parents = 1, 1539 .ops = &clk_branch2_ops, 1540 }, 1541 }, 1542 }; 1543 1544 static struct clk_branch gcc_blsp1_sleep_clk = { 1545 .halt_reg = 0x01004, 1546 .clkr = { 1547 .enable_reg = 0x01004, 1548 .enable_mask = BIT(0), 1549 .hw.init = &(struct clk_init_data){ 1550 .name = "gcc_blsp1_sleep_clk", 1551 .parent_names = (const char *[]){ 1552 "sleep_clk_src", 1553 }, 1554 .num_parents = 1, 1555 .flags = CLK_SET_RATE_PARENT, 1556 .ops = &clk_branch2_ops, 1557 }, 1558 }, 1559 }; 1560 1561 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { 1562 .halt_reg = 0x02008, 1563 .clkr = { 1564 .enable_reg = 0x02008, 1565 .enable_mask = BIT(0), 1566 .hw.init = &(struct clk_init_data){ 1567 .name = "gcc_blsp1_qup1_i2c_apps_clk", 1568 .parent_names = (const char *[]){ 1569 "blsp1_qup1_i2c_apps_clk_src", 1570 }, 1571 .num_parents = 1, 1572 .flags = CLK_SET_RATE_PARENT, 1573 .ops = &clk_branch2_ops, 1574 }, 1575 }, 1576 }; 1577 1578 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { 1579 .halt_reg = 0x02004, 1580 .clkr = { 1581 .enable_reg = 0x02004, 1582 .enable_mask = BIT(0), 1583 .hw.init = &(struct clk_init_data){ 1584 .name = "gcc_blsp1_qup1_spi_apps_clk", 1585 .parent_names = (const char *[]){ 1586 "blsp1_qup1_spi_apps_clk_src", 1587 }, 1588 .num_parents = 1, 1589 .flags = CLK_SET_RATE_PARENT, 1590 .ops = &clk_branch2_ops, 1591 }, 1592 }, 1593 }; 1594 1595 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { 1596 .halt_reg = 0x03010, 1597 .clkr = { 1598 .enable_reg = 0x03010, 1599 .enable_mask = BIT(0), 1600 .hw.init = &(struct clk_init_data){ 1601 .name = "gcc_blsp1_qup2_i2c_apps_clk", 1602 .parent_names = (const char *[]){ 1603 "blsp1_qup2_i2c_apps_clk_src", 1604 }, 1605 .num_parents = 1, 1606 .flags = CLK_SET_RATE_PARENT, 1607 .ops = &clk_branch2_ops, 1608 }, 1609 }, 1610 }; 1611 1612 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { 1613 .halt_reg = 0x0300c, 1614 .clkr = { 1615 .enable_reg = 0x0300c, 1616 .enable_mask = BIT(0), 1617 .hw.init = &(struct clk_init_data){ 1618 .name = "gcc_blsp1_qup2_spi_apps_clk", 1619 .parent_names = (const char *[]){ 1620 "blsp1_qup2_spi_apps_clk_src", 1621 }, 1622 .num_parents = 1, 1623 .flags = CLK_SET_RATE_PARENT, 1624 .ops = &clk_branch2_ops, 1625 }, 1626 }, 1627 }; 1628 1629 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = { 1630 .halt_reg = 0x04020, 1631 .clkr = { 1632 .enable_reg = 0x04020, 1633 .enable_mask = BIT(0), 1634 .hw.init = &(struct clk_init_data){ 1635 .name = "gcc_blsp1_qup3_i2c_apps_clk", 1636 .parent_names = (const char *[]){ 1637 "blsp1_qup3_i2c_apps_clk_src", 1638 }, 1639 .num_parents = 1, 1640 .flags = CLK_SET_RATE_PARENT, 1641 .ops = &clk_branch2_ops, 1642 }, 1643 }, 1644 }; 1645 1646 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = { 1647 .halt_reg = 0x0401c, 1648 .clkr = { 1649 .enable_reg = 0x0401c, 1650 .enable_mask = BIT(0), 1651 .hw.init = &(struct clk_init_data){ 1652 .name = "gcc_blsp1_qup3_spi_apps_clk", 1653 .parent_names = (const char *[]){ 1654 "blsp1_qup3_spi_apps_clk_src", 1655 }, 1656 .num_parents = 1, 1657 .flags = CLK_SET_RATE_PARENT, 1658 .ops = &clk_branch2_ops, 1659 }, 1660 }, 1661 }; 1662 1663 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = { 1664 .halt_reg = 0x05020, 1665 .clkr = { 1666 .enable_reg = 0x05020, 1667 .enable_mask = BIT(0), 1668 .hw.init = &(struct clk_init_data){ 1669 .name = "gcc_blsp1_qup4_i2c_apps_clk", 1670 .parent_names = (const char *[]){ 1671 "blsp1_qup4_i2c_apps_clk_src", 1672 }, 1673 .num_parents = 1, 1674 .flags = CLK_SET_RATE_PARENT, 1675 .ops = &clk_branch2_ops, 1676 }, 1677 }, 1678 }; 1679 1680 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = { 1681 .halt_reg = 0x0501c, 1682 .clkr = { 1683 .enable_reg = 0x0501c, 1684 .enable_mask = BIT(0), 1685 .hw.init = &(struct clk_init_data){ 1686 .name = "gcc_blsp1_qup4_spi_apps_clk", 1687 .parent_names = (const char *[]){ 1688 "blsp1_qup4_spi_apps_clk_src", 1689 }, 1690 .num_parents = 1, 1691 .flags = CLK_SET_RATE_PARENT, 1692 .ops = &clk_branch2_ops, 1693 }, 1694 }, 1695 }; 1696 1697 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = { 1698 .halt_reg = 0x06020, 1699 .clkr = { 1700 .enable_reg = 0x06020, 1701 .enable_mask = BIT(0), 1702 .hw.init = &(struct clk_init_data){ 1703 .name = "gcc_blsp1_qup5_i2c_apps_clk", 1704 .parent_names = (const char *[]){ 1705 "blsp1_qup5_i2c_apps_clk_src", 1706 }, 1707 .num_parents = 1, 1708 .flags = CLK_SET_RATE_PARENT, 1709 .ops = &clk_branch2_ops, 1710 }, 1711 }, 1712 }; 1713 1714 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = { 1715 .halt_reg = 0x0601c, 1716 .clkr = { 1717 .enable_reg = 0x0601c, 1718 .enable_mask = BIT(0), 1719 .hw.init = &(struct clk_init_data){ 1720 .name = "gcc_blsp1_qup5_spi_apps_clk", 1721 .parent_names = (const char *[]){ 1722 "blsp1_qup5_spi_apps_clk_src", 1723 }, 1724 .num_parents = 1, 1725 .flags = CLK_SET_RATE_PARENT, 1726 .ops = &clk_branch2_ops, 1727 }, 1728 }, 1729 }; 1730 1731 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = { 1732 .halt_reg = 0x07020, 1733 .clkr = { 1734 .enable_reg = 0x07020, 1735 .enable_mask = BIT(0), 1736 .hw.init = &(struct clk_init_data){ 1737 .name = "gcc_blsp1_qup6_i2c_apps_clk", 1738 .parent_names = (const char *[]){ 1739 "blsp1_qup6_i2c_apps_clk_src", 1740 }, 1741 .num_parents = 1, 1742 .flags = CLK_SET_RATE_PARENT, 1743 .ops = &clk_branch2_ops, 1744 }, 1745 }, 1746 }; 1747 1748 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = { 1749 .halt_reg = 0x0701c, 1750 .clkr = { 1751 .enable_reg = 0x0701c, 1752 .enable_mask = BIT(0), 1753 .hw.init = &(struct clk_init_data){ 1754 .name = "gcc_blsp1_qup6_spi_apps_clk", 1755 .parent_names = (const char *[]){ 1756 "blsp1_qup6_spi_apps_clk_src", 1757 }, 1758 .num_parents = 1, 1759 .flags = CLK_SET_RATE_PARENT, 1760 .ops = &clk_branch2_ops, 1761 }, 1762 }, 1763 }; 1764 1765 static struct clk_branch gcc_blsp1_uart1_apps_clk = { 1766 .halt_reg = 0x0203c, 1767 .clkr = { 1768 .enable_reg = 0x0203c, 1769 .enable_mask = BIT(0), 1770 .hw.init = &(struct clk_init_data){ 1771 .name = "gcc_blsp1_uart1_apps_clk", 1772 .parent_names = (const char *[]){ 1773 "blsp1_uart1_apps_clk_src", 1774 }, 1775 .num_parents = 1, 1776 .flags = CLK_SET_RATE_PARENT, 1777 .ops = &clk_branch2_ops, 1778 }, 1779 }, 1780 }; 1781 1782 static struct clk_branch gcc_blsp1_uart2_apps_clk = { 1783 .halt_reg = 0x0302c, 1784 .clkr = { 1785 .enable_reg = 0x0302c, 1786 .enable_mask = BIT(0), 1787 .hw.init = &(struct clk_init_data){ 1788 .name = "gcc_blsp1_uart2_apps_clk", 1789 .parent_names = (const char *[]){ 1790 "blsp1_uart2_apps_clk_src", 1791 }, 1792 .num_parents = 1, 1793 .flags = CLK_SET_RATE_PARENT, 1794 .ops = &clk_branch2_ops, 1795 }, 1796 }, 1797 }; 1798 1799 static struct clk_branch gcc_boot_rom_ahb_clk = { 1800 .halt_reg = 0x1300c, 1801 .halt_check = BRANCH_HALT_VOTED, 1802 .clkr = { 1803 .enable_reg = 0x45004, 1804 .enable_mask = BIT(7), 1805 .hw.init = &(struct clk_init_data){ 1806 .name = "gcc_boot_rom_ahb_clk", 1807 .parent_names = (const char *[]){ 1808 "pcnoc_bfdcd_clk_src", 1809 }, 1810 .num_parents = 1, 1811 .ops = &clk_branch2_ops, 1812 }, 1813 }, 1814 }; 1815 1816 static struct clk_branch gcc_camss_cci_ahb_clk = { 1817 .halt_reg = 0x5101c, 1818 .clkr = { 1819 .enable_reg = 0x5101c, 1820 .enable_mask = BIT(0), 1821 .hw.init = &(struct clk_init_data){ 1822 .name = "gcc_camss_cci_ahb_clk", 1823 .parent_names = (const char *[]){ 1824 "camss_ahb_clk_src", 1825 }, 1826 .num_parents = 1, 1827 .flags = CLK_SET_RATE_PARENT, 1828 .ops = &clk_branch2_ops, 1829 }, 1830 }, 1831 }; 1832 1833 static struct clk_branch gcc_camss_cci_clk = { 1834 .halt_reg = 0x51018, 1835 .clkr = { 1836 .enable_reg = 0x51018, 1837 .enable_mask = BIT(0), 1838 .hw.init = &(struct clk_init_data){ 1839 .name = "gcc_camss_cci_clk", 1840 .parent_names = (const char *[]){ 1841 "cci_clk_src", 1842 }, 1843 .num_parents = 1, 1844 .flags = CLK_SET_RATE_PARENT, 1845 .ops = &clk_branch2_ops, 1846 }, 1847 }, 1848 }; 1849 1850 static struct clk_branch gcc_camss_csi0_ahb_clk = { 1851 .halt_reg = 0x4e040, 1852 .clkr = { 1853 .enable_reg = 0x4e040, 1854 .enable_mask = BIT(0), 1855 .hw.init = &(struct clk_init_data){ 1856 .name = "gcc_camss_csi0_ahb_clk", 1857 .parent_names = (const char *[]){ 1858 "camss_ahb_clk_src", 1859 }, 1860 .num_parents = 1, 1861 .flags = CLK_SET_RATE_PARENT, 1862 .ops = &clk_branch2_ops, 1863 }, 1864 }, 1865 }; 1866 1867 static struct clk_branch gcc_camss_csi0_clk = { 1868 .halt_reg = 0x4e03c, 1869 .clkr = { 1870 .enable_reg = 0x4e03c, 1871 .enable_mask = BIT(0), 1872 .hw.init = &(struct clk_init_data){ 1873 .name = "gcc_camss_csi0_clk", 1874 .parent_names = (const char *[]){ 1875 "csi0_clk_src", 1876 }, 1877 .num_parents = 1, 1878 .flags = CLK_SET_RATE_PARENT, 1879 .ops = &clk_branch2_ops, 1880 }, 1881 }, 1882 }; 1883 1884 static struct clk_branch gcc_camss_csi0phy_clk = { 1885 .halt_reg = 0x4e048, 1886 .clkr = { 1887 .enable_reg = 0x4e048, 1888 .enable_mask = BIT(0), 1889 .hw.init = &(struct clk_init_data){ 1890 .name = "gcc_camss_csi0phy_clk", 1891 .parent_names = (const char *[]){ 1892 "csi0_clk_src", 1893 }, 1894 .num_parents = 1, 1895 .flags = CLK_SET_RATE_PARENT, 1896 .ops = &clk_branch2_ops, 1897 }, 1898 }, 1899 }; 1900 1901 static struct clk_branch gcc_camss_csi0pix_clk = { 1902 .halt_reg = 0x4e058, 1903 .clkr = { 1904 .enable_reg = 0x4e058, 1905 .enable_mask = BIT(0), 1906 .hw.init = &(struct clk_init_data){ 1907 .name = "gcc_camss_csi0pix_clk", 1908 .parent_names = (const char *[]){ 1909 "csi0_clk_src", 1910 }, 1911 .num_parents = 1, 1912 .flags = CLK_SET_RATE_PARENT, 1913 .ops = &clk_branch2_ops, 1914 }, 1915 }, 1916 }; 1917 1918 static struct clk_branch gcc_camss_csi0rdi_clk = { 1919 .halt_reg = 0x4e050, 1920 .clkr = { 1921 .enable_reg = 0x4e050, 1922 .enable_mask = BIT(0), 1923 .hw.init = &(struct clk_init_data){ 1924 .name = "gcc_camss_csi0rdi_clk", 1925 .parent_names = (const char *[]){ 1926 "csi0_clk_src", 1927 }, 1928 .num_parents = 1, 1929 .flags = CLK_SET_RATE_PARENT, 1930 .ops = &clk_branch2_ops, 1931 }, 1932 }, 1933 }; 1934 1935 static struct clk_branch gcc_camss_csi1_ahb_clk = { 1936 .halt_reg = 0x4f040, 1937 .clkr = { 1938 .enable_reg = 0x4f040, 1939 .enable_mask = BIT(0), 1940 .hw.init = &(struct clk_init_data){ 1941 .name = "gcc_camss_csi1_ahb_clk", 1942 .parent_names = (const char *[]){ 1943 "camss_ahb_clk_src", 1944 }, 1945 .num_parents = 1, 1946 .flags = CLK_SET_RATE_PARENT, 1947 .ops = &clk_branch2_ops, 1948 }, 1949 }, 1950 }; 1951 1952 static struct clk_branch gcc_camss_csi1_clk = { 1953 .halt_reg = 0x4f03c, 1954 .clkr = { 1955 .enable_reg = 0x4f03c, 1956 .enable_mask = BIT(0), 1957 .hw.init = &(struct clk_init_data){ 1958 .name = "gcc_camss_csi1_clk", 1959 .parent_names = (const char *[]){ 1960 "csi1_clk_src", 1961 }, 1962 .num_parents = 1, 1963 .flags = CLK_SET_RATE_PARENT, 1964 .ops = &clk_branch2_ops, 1965 }, 1966 }, 1967 }; 1968 1969 static struct clk_branch gcc_camss_csi1phy_clk = { 1970 .halt_reg = 0x4f048, 1971 .clkr = { 1972 .enable_reg = 0x4f048, 1973 .enable_mask = BIT(0), 1974 .hw.init = &(struct clk_init_data){ 1975 .name = "gcc_camss_csi1phy_clk", 1976 .parent_names = (const char *[]){ 1977 "csi1_clk_src", 1978 }, 1979 .num_parents = 1, 1980 .flags = CLK_SET_RATE_PARENT, 1981 .ops = &clk_branch2_ops, 1982 }, 1983 }, 1984 }; 1985 1986 static struct clk_branch gcc_camss_csi1pix_clk = { 1987 .halt_reg = 0x4f058, 1988 .clkr = { 1989 .enable_reg = 0x4f058, 1990 .enable_mask = BIT(0), 1991 .hw.init = &(struct clk_init_data){ 1992 .name = "gcc_camss_csi1pix_clk", 1993 .parent_names = (const char *[]){ 1994 "csi1_clk_src", 1995 }, 1996 .num_parents = 1, 1997 .flags = CLK_SET_RATE_PARENT, 1998 .ops = &clk_branch2_ops, 1999 }, 2000 }, 2001 }; 2002 2003 static struct clk_branch gcc_camss_csi1rdi_clk = { 2004 .halt_reg = 0x4f050, 2005 .clkr = { 2006 .enable_reg = 0x4f050, 2007 .enable_mask = BIT(0), 2008 .hw.init = &(struct clk_init_data){ 2009 .name = "gcc_camss_csi1rdi_clk", 2010 .parent_names = (const char *[]){ 2011 "csi1_clk_src", 2012 }, 2013 .num_parents = 1, 2014 .flags = CLK_SET_RATE_PARENT, 2015 .ops = &clk_branch2_ops, 2016 }, 2017 }, 2018 }; 2019 2020 static struct clk_branch gcc_camss_csi_vfe0_clk = { 2021 .halt_reg = 0x58050, 2022 .clkr = { 2023 .enable_reg = 0x58050, 2024 .enable_mask = BIT(0), 2025 .hw.init = &(struct clk_init_data){ 2026 .name = "gcc_camss_csi_vfe0_clk", 2027 .parent_names = (const char *[]){ 2028 "vfe0_clk_src", 2029 }, 2030 .num_parents = 1, 2031 .flags = CLK_SET_RATE_PARENT, 2032 .ops = &clk_branch2_ops, 2033 }, 2034 }, 2035 }; 2036 2037 static struct clk_branch gcc_camss_gp0_clk = { 2038 .halt_reg = 0x54018, 2039 .clkr = { 2040 .enable_reg = 0x54018, 2041 .enable_mask = BIT(0), 2042 .hw.init = &(struct clk_init_data){ 2043 .name = "gcc_camss_gp0_clk", 2044 .parent_names = (const char *[]){ 2045 "camss_gp0_clk_src", 2046 }, 2047 .num_parents = 1, 2048 .flags = CLK_SET_RATE_PARENT, 2049 .ops = &clk_branch2_ops, 2050 }, 2051 }, 2052 }; 2053 2054 static struct clk_branch gcc_camss_gp1_clk = { 2055 .halt_reg = 0x55018, 2056 .clkr = { 2057 .enable_reg = 0x55018, 2058 .enable_mask = BIT(0), 2059 .hw.init = &(struct clk_init_data){ 2060 .name = "gcc_camss_gp1_clk", 2061 .parent_names = (const char *[]){ 2062 "camss_gp1_clk_src", 2063 }, 2064 .num_parents = 1, 2065 .flags = CLK_SET_RATE_PARENT, 2066 .ops = &clk_branch2_ops, 2067 }, 2068 }, 2069 }; 2070 2071 static struct clk_branch gcc_camss_ispif_ahb_clk = { 2072 .halt_reg = 0x50004, 2073 .clkr = { 2074 .enable_reg = 0x50004, 2075 .enable_mask = BIT(0), 2076 .hw.init = &(struct clk_init_data){ 2077 .name = "gcc_camss_ispif_ahb_clk", 2078 .parent_names = (const char *[]){ 2079 "camss_ahb_clk_src", 2080 }, 2081 .num_parents = 1, 2082 .flags = CLK_SET_RATE_PARENT, 2083 .ops = &clk_branch2_ops, 2084 }, 2085 }, 2086 }; 2087 2088 static struct clk_branch gcc_camss_jpeg0_clk = { 2089 .halt_reg = 0x57020, 2090 .clkr = { 2091 .enable_reg = 0x57020, 2092 .enable_mask = BIT(0), 2093 .hw.init = &(struct clk_init_data){ 2094 .name = "gcc_camss_jpeg0_clk", 2095 .parent_names = (const char *[]){ 2096 "jpeg0_clk_src", 2097 }, 2098 .num_parents = 1, 2099 .flags = CLK_SET_RATE_PARENT, 2100 .ops = &clk_branch2_ops, 2101 }, 2102 }, 2103 }; 2104 2105 static struct clk_branch gcc_camss_jpeg_ahb_clk = { 2106 .halt_reg = 0x57024, 2107 .clkr = { 2108 .enable_reg = 0x57024, 2109 .enable_mask = BIT(0), 2110 .hw.init = &(struct clk_init_data){ 2111 .name = "gcc_camss_jpeg_ahb_clk", 2112 .parent_names = (const char *[]){ 2113 "camss_ahb_clk_src", 2114 }, 2115 .num_parents = 1, 2116 .flags = CLK_SET_RATE_PARENT, 2117 .ops = &clk_branch2_ops, 2118 }, 2119 }, 2120 }; 2121 2122 static struct clk_branch gcc_camss_jpeg_axi_clk = { 2123 .halt_reg = 0x57028, 2124 .clkr = { 2125 .enable_reg = 0x57028, 2126 .enable_mask = BIT(0), 2127 .hw.init = &(struct clk_init_data){ 2128 .name = "gcc_camss_jpeg_axi_clk", 2129 .parent_names = (const char *[]){ 2130 "system_noc_bfdcd_clk_src", 2131 }, 2132 .num_parents = 1, 2133 .flags = CLK_SET_RATE_PARENT, 2134 .ops = &clk_branch2_ops, 2135 }, 2136 }, 2137 }; 2138 2139 static struct clk_branch gcc_camss_mclk0_clk = { 2140 .halt_reg = 0x52018, 2141 .clkr = { 2142 .enable_reg = 0x52018, 2143 .enable_mask = BIT(0), 2144 .hw.init = &(struct clk_init_data){ 2145 .name = "gcc_camss_mclk0_clk", 2146 .parent_names = (const char *[]){ 2147 "mclk0_clk_src", 2148 }, 2149 .num_parents = 1, 2150 .flags = CLK_SET_RATE_PARENT, 2151 .ops = &clk_branch2_ops, 2152 }, 2153 }, 2154 }; 2155 2156 static struct clk_branch gcc_camss_mclk1_clk = { 2157 .halt_reg = 0x53018, 2158 .clkr = { 2159 .enable_reg = 0x53018, 2160 .enable_mask = BIT(0), 2161 .hw.init = &(struct clk_init_data){ 2162 .name = "gcc_camss_mclk1_clk", 2163 .parent_names = (const char *[]){ 2164 "mclk1_clk_src", 2165 }, 2166 .num_parents = 1, 2167 .flags = CLK_SET_RATE_PARENT, 2168 .ops = &clk_branch2_ops, 2169 }, 2170 }, 2171 }; 2172 2173 static struct clk_branch gcc_camss_micro_ahb_clk = { 2174 .halt_reg = 0x5600c, 2175 .clkr = { 2176 .enable_reg = 0x5600c, 2177 .enable_mask = BIT(0), 2178 .hw.init = &(struct clk_init_data){ 2179 .name = "gcc_camss_micro_ahb_clk", 2180 .parent_names = (const char *[]){ 2181 "camss_ahb_clk_src", 2182 }, 2183 .num_parents = 1, 2184 .flags = CLK_SET_RATE_PARENT, 2185 .ops = &clk_branch2_ops, 2186 }, 2187 }, 2188 }; 2189 2190 static struct clk_branch gcc_camss_csi0phytimer_clk = { 2191 .halt_reg = 0x4e01c, 2192 .clkr = { 2193 .enable_reg = 0x4e01c, 2194 .enable_mask = BIT(0), 2195 .hw.init = &(struct clk_init_data){ 2196 .name = "gcc_camss_csi0phytimer_clk", 2197 .parent_names = (const char *[]){ 2198 "csi0phytimer_clk_src", 2199 }, 2200 .num_parents = 1, 2201 .flags = CLK_SET_RATE_PARENT, 2202 .ops = &clk_branch2_ops, 2203 }, 2204 }, 2205 }; 2206 2207 static struct clk_branch gcc_camss_csi1phytimer_clk = { 2208 .halt_reg = 0x4f01c, 2209 .clkr = { 2210 .enable_reg = 0x4f01c, 2211 .enable_mask = BIT(0), 2212 .hw.init = &(struct clk_init_data){ 2213 .name = "gcc_camss_csi1phytimer_clk", 2214 .parent_names = (const char *[]){ 2215 "csi1phytimer_clk_src", 2216 }, 2217 .num_parents = 1, 2218 .flags = CLK_SET_RATE_PARENT, 2219 .ops = &clk_branch2_ops, 2220 }, 2221 }, 2222 }; 2223 2224 static struct clk_branch gcc_camss_ahb_clk = { 2225 .halt_reg = 0x5a014, 2226 .clkr = { 2227 .enable_reg = 0x5a014, 2228 .enable_mask = BIT(0), 2229 .hw.init = &(struct clk_init_data){ 2230 .name = "gcc_camss_ahb_clk", 2231 .parent_names = (const char *[]){ 2232 "camss_ahb_clk_src", 2233 }, 2234 .num_parents = 1, 2235 .flags = CLK_SET_RATE_PARENT, 2236 .ops = &clk_branch2_ops, 2237 }, 2238 }, 2239 }; 2240 2241 static struct clk_branch gcc_camss_top_ahb_clk = { 2242 .halt_reg = 0x56004, 2243 .clkr = { 2244 .enable_reg = 0x56004, 2245 .enable_mask = BIT(0), 2246 .hw.init = &(struct clk_init_data){ 2247 .name = "gcc_camss_top_ahb_clk", 2248 .parent_names = (const char *[]){ 2249 "pcnoc_bfdcd_clk_src", 2250 }, 2251 .num_parents = 1, 2252 .flags = CLK_SET_RATE_PARENT, 2253 .ops = &clk_branch2_ops, 2254 }, 2255 }, 2256 }; 2257 2258 static struct clk_branch gcc_camss_cpp_ahb_clk = { 2259 .halt_reg = 0x58040, 2260 .clkr = { 2261 .enable_reg = 0x58040, 2262 .enable_mask = BIT(0), 2263 .hw.init = &(struct clk_init_data){ 2264 .name = "gcc_camss_cpp_ahb_clk", 2265 .parent_names = (const char *[]){ 2266 "camss_ahb_clk_src", 2267 }, 2268 .num_parents = 1, 2269 .flags = CLK_SET_RATE_PARENT, 2270 .ops = &clk_branch2_ops, 2271 }, 2272 }, 2273 }; 2274 2275 static struct clk_branch gcc_camss_cpp_clk = { 2276 .halt_reg = 0x5803c, 2277 .clkr = { 2278 .enable_reg = 0x5803c, 2279 .enable_mask = BIT(0), 2280 .hw.init = &(struct clk_init_data){ 2281 .name = "gcc_camss_cpp_clk", 2282 .parent_names = (const char *[]){ 2283 "cpp_clk_src", 2284 }, 2285 .num_parents = 1, 2286 .flags = CLK_SET_RATE_PARENT, 2287 .ops = &clk_branch2_ops, 2288 }, 2289 }, 2290 }; 2291 2292 static struct clk_branch gcc_camss_vfe0_clk = { 2293 .halt_reg = 0x58038, 2294 .clkr = { 2295 .enable_reg = 0x58038, 2296 .enable_mask = BIT(0), 2297 .hw.init = &(struct clk_init_data){ 2298 .name = "gcc_camss_vfe0_clk", 2299 .parent_names = (const char *[]){ 2300 "vfe0_clk_src", 2301 }, 2302 .num_parents = 1, 2303 .flags = CLK_SET_RATE_PARENT, 2304 .ops = &clk_branch2_ops, 2305 }, 2306 }, 2307 }; 2308 2309 static struct clk_branch gcc_camss_vfe_ahb_clk = { 2310 .halt_reg = 0x58044, 2311 .clkr = { 2312 .enable_reg = 0x58044, 2313 .enable_mask = BIT(0), 2314 .hw.init = &(struct clk_init_data){ 2315 .name = "gcc_camss_vfe_ahb_clk", 2316 .parent_names = (const char *[]){ 2317 "camss_ahb_clk_src", 2318 }, 2319 .num_parents = 1, 2320 .flags = CLK_SET_RATE_PARENT, 2321 .ops = &clk_branch2_ops, 2322 }, 2323 }, 2324 }; 2325 2326 static struct clk_branch gcc_camss_vfe_axi_clk = { 2327 .halt_reg = 0x58048, 2328 .clkr = { 2329 .enable_reg = 0x58048, 2330 .enable_mask = BIT(0), 2331 .hw.init = &(struct clk_init_data){ 2332 .name = "gcc_camss_vfe_axi_clk", 2333 .parent_names = (const char *[]){ 2334 "system_noc_bfdcd_clk_src", 2335 }, 2336 .num_parents = 1, 2337 .flags = CLK_SET_RATE_PARENT, 2338 .ops = &clk_branch2_ops, 2339 }, 2340 }, 2341 }; 2342 2343 static struct clk_branch gcc_crypto_ahb_clk = { 2344 .halt_reg = 0x16024, 2345 .halt_check = BRANCH_HALT_VOTED, 2346 .clkr = { 2347 .enable_reg = 0x45004, 2348 .enable_mask = BIT(0), 2349 .hw.init = &(struct clk_init_data){ 2350 .name = "gcc_crypto_ahb_clk", 2351 .parent_names = (const char *[]){ 2352 "pcnoc_bfdcd_clk_src", 2353 }, 2354 .num_parents = 1, 2355 .flags = CLK_SET_RATE_PARENT, 2356 .ops = &clk_branch2_ops, 2357 }, 2358 }, 2359 }; 2360 2361 static struct clk_branch gcc_crypto_axi_clk = { 2362 .halt_reg = 0x16020, 2363 .halt_check = BRANCH_HALT_VOTED, 2364 .clkr = { 2365 .enable_reg = 0x45004, 2366 .enable_mask = BIT(1), 2367 .hw.init = &(struct clk_init_data){ 2368 .name = "gcc_crypto_axi_clk", 2369 .parent_names = (const char *[]){ 2370 "pcnoc_bfdcd_clk_src", 2371 }, 2372 .num_parents = 1, 2373 .flags = CLK_SET_RATE_PARENT, 2374 .ops = &clk_branch2_ops, 2375 }, 2376 }, 2377 }; 2378 2379 static struct clk_branch gcc_crypto_clk = { 2380 .halt_reg = 0x1601c, 2381 .halt_check = BRANCH_HALT_VOTED, 2382 .clkr = { 2383 .enable_reg = 0x45004, 2384 .enable_mask = BIT(2), 2385 .hw.init = &(struct clk_init_data){ 2386 .name = "gcc_crypto_clk", 2387 .parent_names = (const char *[]){ 2388 "crypto_clk_src", 2389 }, 2390 .num_parents = 1, 2391 .flags = CLK_SET_RATE_PARENT, 2392 .ops = &clk_branch2_ops, 2393 }, 2394 }, 2395 }; 2396 2397 static struct clk_branch gcc_oxili_gmem_clk = { 2398 .halt_reg = 0x59024, 2399 .clkr = { 2400 .enable_reg = 0x59024, 2401 .enable_mask = BIT(0), 2402 .hw.init = &(struct clk_init_data){ 2403 .name = "gcc_oxili_gmem_clk", 2404 .parent_names = (const char *[]){ 2405 "gfx3d_clk_src", 2406 }, 2407 .num_parents = 1, 2408 .flags = CLK_SET_RATE_PARENT, 2409 .ops = &clk_branch2_ops, 2410 }, 2411 }, 2412 }; 2413 2414 static struct clk_branch gcc_gp1_clk = { 2415 .halt_reg = 0x08000, 2416 .clkr = { 2417 .enable_reg = 0x08000, 2418 .enable_mask = BIT(0), 2419 .hw.init = &(struct clk_init_data){ 2420 .name = "gcc_gp1_clk", 2421 .parent_names = (const char *[]){ 2422 "gp1_clk_src", 2423 }, 2424 .num_parents = 1, 2425 .flags = CLK_SET_RATE_PARENT, 2426 .ops = &clk_branch2_ops, 2427 }, 2428 }, 2429 }; 2430 2431 static struct clk_branch gcc_gp2_clk = { 2432 .halt_reg = 0x09000, 2433 .clkr = { 2434 .enable_reg = 0x09000, 2435 .enable_mask = BIT(0), 2436 .hw.init = &(struct clk_init_data){ 2437 .name = "gcc_gp2_clk", 2438 .parent_names = (const char *[]){ 2439 "gp2_clk_src", 2440 }, 2441 .num_parents = 1, 2442 .flags = CLK_SET_RATE_PARENT, 2443 .ops = &clk_branch2_ops, 2444 }, 2445 }, 2446 }; 2447 2448 static struct clk_branch gcc_gp3_clk = { 2449 .halt_reg = 0x0a000, 2450 .clkr = { 2451 .enable_reg = 0x0a000, 2452 .enable_mask = BIT(0), 2453 .hw.init = &(struct clk_init_data){ 2454 .name = "gcc_gp3_clk", 2455 .parent_names = (const char *[]){ 2456 "gp3_clk_src", 2457 }, 2458 .num_parents = 1, 2459 .flags = CLK_SET_RATE_PARENT, 2460 .ops = &clk_branch2_ops, 2461 }, 2462 }, 2463 }; 2464 2465 static struct clk_branch gcc_mdss_ahb_clk = { 2466 .halt_reg = 0x4d07c, 2467 .clkr = { 2468 .enable_reg = 0x4d07c, 2469 .enable_mask = BIT(0), 2470 .hw.init = &(struct clk_init_data){ 2471 .name = "gcc_mdss_ahb_clk", 2472 .parent_names = (const char *[]){ 2473 "pcnoc_bfdcd_clk_src", 2474 }, 2475 .num_parents = 1, 2476 .flags = CLK_SET_RATE_PARENT, 2477 .ops = &clk_branch2_ops, 2478 }, 2479 }, 2480 }; 2481 2482 static struct clk_branch gcc_mdss_axi_clk = { 2483 .halt_reg = 0x4d080, 2484 .clkr = { 2485 .enable_reg = 0x4d080, 2486 .enable_mask = BIT(0), 2487 .hw.init = &(struct clk_init_data){ 2488 .name = "gcc_mdss_axi_clk", 2489 .parent_names = (const char *[]){ 2490 "system_noc_bfdcd_clk_src", 2491 }, 2492 .num_parents = 1, 2493 .flags = CLK_SET_RATE_PARENT, 2494 .ops = &clk_branch2_ops, 2495 }, 2496 }, 2497 }; 2498 2499 static struct clk_branch gcc_mdss_byte0_clk = { 2500 .halt_reg = 0x4d094, 2501 .clkr = { 2502 .enable_reg = 0x4d094, 2503 .enable_mask = BIT(0), 2504 .hw.init = &(struct clk_init_data){ 2505 .name = "gcc_mdss_byte0_clk", 2506 .parent_names = (const char *[]){ 2507 "byte0_clk_src", 2508 }, 2509 .num_parents = 1, 2510 .flags = CLK_SET_RATE_PARENT, 2511 .ops = &clk_branch2_ops, 2512 }, 2513 }, 2514 }; 2515 2516 static struct clk_branch gcc_mdss_esc0_clk = { 2517 .halt_reg = 0x4d098, 2518 .clkr = { 2519 .enable_reg = 0x4d098, 2520 .enable_mask = BIT(0), 2521 .hw.init = &(struct clk_init_data){ 2522 .name = "gcc_mdss_esc0_clk", 2523 .parent_names = (const char *[]){ 2524 "esc0_clk_src", 2525 }, 2526 .num_parents = 1, 2527 .flags = CLK_SET_RATE_PARENT, 2528 .ops = &clk_branch2_ops, 2529 }, 2530 }, 2531 }; 2532 2533 static struct clk_branch gcc_mdss_mdp_clk = { 2534 .halt_reg = 0x4D088, 2535 .clkr = { 2536 .enable_reg = 0x4D088, 2537 .enable_mask = BIT(0), 2538 .hw.init = &(struct clk_init_data){ 2539 .name = "gcc_mdss_mdp_clk", 2540 .parent_names = (const char *[]){ 2541 "mdp_clk_src", 2542 }, 2543 .num_parents = 1, 2544 .flags = CLK_SET_RATE_PARENT, 2545 .ops = &clk_branch2_ops, 2546 }, 2547 }, 2548 }; 2549 2550 static struct clk_branch gcc_mdss_pclk0_clk = { 2551 .halt_reg = 0x4d084, 2552 .clkr = { 2553 .enable_reg = 0x4d084, 2554 .enable_mask = BIT(0), 2555 .hw.init = &(struct clk_init_data){ 2556 .name = "gcc_mdss_pclk0_clk", 2557 .parent_names = (const char *[]){ 2558 "pclk0_clk_src", 2559 }, 2560 .num_parents = 1, 2561 .flags = CLK_SET_RATE_PARENT, 2562 .ops = &clk_branch2_ops, 2563 }, 2564 }, 2565 }; 2566 2567 static struct clk_branch gcc_mdss_vsync_clk = { 2568 .halt_reg = 0x4d090, 2569 .clkr = { 2570 .enable_reg = 0x4d090, 2571 .enable_mask = BIT(0), 2572 .hw.init = &(struct clk_init_data){ 2573 .name = "gcc_mdss_vsync_clk", 2574 .parent_names = (const char *[]){ 2575 "vsync_clk_src", 2576 }, 2577 .num_parents = 1, 2578 .flags = CLK_SET_RATE_PARENT, 2579 .ops = &clk_branch2_ops, 2580 }, 2581 }, 2582 }; 2583 2584 static struct clk_branch gcc_mss_cfg_ahb_clk = { 2585 .halt_reg = 0x49000, 2586 .clkr = { 2587 .enable_reg = 0x49000, 2588 .enable_mask = BIT(0), 2589 .hw.init = &(struct clk_init_data){ 2590 .name = "gcc_mss_cfg_ahb_clk", 2591 .parent_names = (const char *[]){ 2592 "pcnoc_bfdcd_clk_src", 2593 }, 2594 .num_parents = 1, 2595 .flags = CLK_SET_RATE_PARENT, 2596 .ops = &clk_branch2_ops, 2597 }, 2598 }, 2599 }; 2600 2601 static struct clk_branch gcc_mss_q6_bimc_axi_clk = { 2602 .halt_reg = 0x49004, 2603 .clkr = { 2604 .enable_reg = 0x49004, 2605 .enable_mask = BIT(0), 2606 .hw.init = &(struct clk_init_data){ 2607 .name = "gcc_mss_q6_bimc_axi_clk", 2608 .parent_names = (const char *[]){ 2609 "bimc_ddr_clk_src", 2610 }, 2611 .num_parents = 1, 2612 .flags = CLK_SET_RATE_PARENT, 2613 .ops = &clk_branch2_ops, 2614 }, 2615 }, 2616 }; 2617 2618 static struct clk_branch gcc_oxili_ahb_clk = { 2619 .halt_reg = 0x59028, 2620 .clkr = { 2621 .enable_reg = 0x59028, 2622 .enable_mask = BIT(0), 2623 .hw.init = &(struct clk_init_data){ 2624 .name = "gcc_oxili_ahb_clk", 2625 .parent_names = (const char *[]){ 2626 "pcnoc_bfdcd_clk_src", 2627 }, 2628 .num_parents = 1, 2629 .flags = CLK_SET_RATE_PARENT, 2630 .ops = &clk_branch2_ops, 2631 }, 2632 }, 2633 }; 2634 2635 static struct clk_branch gcc_oxili_gfx3d_clk = { 2636 .halt_reg = 0x59020, 2637 .clkr = { 2638 .enable_reg = 0x59020, 2639 .enable_mask = BIT(0), 2640 .hw.init = &(struct clk_init_data){ 2641 .name = "gcc_oxili_gfx3d_clk", 2642 .parent_names = (const char *[]){ 2643 "gfx3d_clk_src", 2644 }, 2645 .num_parents = 1, 2646 .flags = CLK_SET_RATE_PARENT, 2647 .ops = &clk_branch2_ops, 2648 }, 2649 }, 2650 }; 2651 2652 static struct clk_branch gcc_pdm2_clk = { 2653 .halt_reg = 0x4400c, 2654 .clkr = { 2655 .enable_reg = 0x4400c, 2656 .enable_mask = BIT(0), 2657 .hw.init = &(struct clk_init_data){ 2658 .name = "gcc_pdm2_clk", 2659 .parent_names = (const char *[]){ 2660 "pdm2_clk_src", 2661 }, 2662 .num_parents = 1, 2663 .flags = CLK_SET_RATE_PARENT, 2664 .ops = &clk_branch2_ops, 2665 }, 2666 }, 2667 }; 2668 2669 static struct clk_branch gcc_pdm_ahb_clk = { 2670 .halt_reg = 0x44004, 2671 .clkr = { 2672 .enable_reg = 0x44004, 2673 .enable_mask = BIT(0), 2674 .hw.init = &(struct clk_init_data){ 2675 .name = "gcc_pdm_ahb_clk", 2676 .parent_names = (const char *[]){ 2677 "pcnoc_bfdcd_clk_src", 2678 }, 2679 .num_parents = 1, 2680 .flags = CLK_SET_RATE_PARENT, 2681 .ops = &clk_branch2_ops, 2682 }, 2683 }, 2684 }; 2685 2686 static struct clk_branch gcc_prng_ahb_clk = { 2687 .halt_reg = 0x13004, 2688 .halt_check = BRANCH_HALT_VOTED, 2689 .clkr = { 2690 .enable_reg = 0x45004, 2691 .enable_mask = BIT(8), 2692 .hw.init = &(struct clk_init_data){ 2693 .name = "gcc_prng_ahb_clk", 2694 .parent_names = (const char *[]){ 2695 "pcnoc_bfdcd_clk_src", 2696 }, 2697 .num_parents = 1, 2698 .ops = &clk_branch2_ops, 2699 }, 2700 }, 2701 }; 2702 2703 static struct clk_branch gcc_sdcc1_ahb_clk = { 2704 .halt_reg = 0x4201c, 2705 .clkr = { 2706 .enable_reg = 0x4201c, 2707 .enable_mask = BIT(0), 2708 .hw.init = &(struct clk_init_data){ 2709 .name = "gcc_sdcc1_ahb_clk", 2710 .parent_names = (const char *[]){ 2711 "pcnoc_bfdcd_clk_src", 2712 }, 2713 .num_parents = 1, 2714 .flags = CLK_SET_RATE_PARENT, 2715 .ops = &clk_branch2_ops, 2716 }, 2717 }, 2718 }; 2719 2720 static struct clk_branch gcc_sdcc1_apps_clk = { 2721 .halt_reg = 0x42018, 2722 .clkr = { 2723 .enable_reg = 0x42018, 2724 .enable_mask = BIT(0), 2725 .hw.init = &(struct clk_init_data){ 2726 .name = "gcc_sdcc1_apps_clk", 2727 .parent_names = (const char *[]){ 2728 "sdcc1_apps_clk_src", 2729 }, 2730 .num_parents = 1, 2731 .flags = CLK_SET_RATE_PARENT, 2732 .ops = &clk_branch2_ops, 2733 }, 2734 }, 2735 }; 2736 2737 static struct clk_branch gcc_sdcc2_ahb_clk = { 2738 .halt_reg = 0x4301c, 2739 .clkr = { 2740 .enable_reg = 0x4301c, 2741 .enable_mask = BIT(0), 2742 .hw.init = &(struct clk_init_data){ 2743 .name = "gcc_sdcc2_ahb_clk", 2744 .parent_names = (const char *[]){ 2745 "pcnoc_bfdcd_clk_src", 2746 }, 2747 .num_parents = 1, 2748 .flags = CLK_SET_RATE_PARENT, 2749 .ops = &clk_branch2_ops, 2750 }, 2751 }, 2752 }; 2753 2754 static struct clk_branch gcc_sdcc2_apps_clk = { 2755 .halt_reg = 0x43018, 2756 .clkr = { 2757 .enable_reg = 0x43018, 2758 .enable_mask = BIT(0), 2759 .hw.init = &(struct clk_init_data){ 2760 .name = "gcc_sdcc2_apps_clk", 2761 .parent_names = (const char *[]){ 2762 "sdcc2_apps_clk_src", 2763 }, 2764 .num_parents = 1, 2765 .flags = CLK_SET_RATE_PARENT, 2766 .ops = &clk_branch2_ops, 2767 }, 2768 }, 2769 }; 2770 2771 static struct clk_rcg2 bimc_ddr_clk_src = { 2772 .cmd_rcgr = 0x32004, 2773 .hid_width = 5, 2774 .parent_map = gcc_xo_gpll0_bimc_map, 2775 .clkr.hw.init = &(struct clk_init_data){ 2776 .name = "bimc_ddr_clk_src", 2777 .parent_names = gcc_xo_gpll0_bimc, 2778 .num_parents = 3, 2779 .ops = &clk_rcg2_ops, 2780 .flags = CLK_GET_RATE_NOCACHE, 2781 }, 2782 }; 2783 2784 static struct clk_branch gcc_apss_tcu_clk = { 2785 .halt_reg = 0x12018, 2786 .clkr = { 2787 .enable_reg = 0x4500c, 2788 .enable_mask = BIT(1), 2789 .hw.init = &(struct clk_init_data){ 2790 .name = "gcc_apss_tcu_clk", 2791 .parent_names = (const char *[]){ 2792 "bimc_ddr_clk_src", 2793 }, 2794 .num_parents = 1, 2795 .ops = &clk_branch2_ops, 2796 }, 2797 }, 2798 }; 2799 2800 static struct clk_branch gcc_gfx_tcu_clk = { 2801 .halt_reg = 0x12020, 2802 .clkr = { 2803 .enable_reg = 0x4500c, 2804 .enable_mask = BIT(2), 2805 .hw.init = &(struct clk_init_data){ 2806 .name = "gcc_gfx_tcu_clk", 2807 .parent_names = (const char *[]){ 2808 "bimc_ddr_clk_src", 2809 }, 2810 .num_parents = 1, 2811 .ops = &clk_branch2_ops, 2812 }, 2813 }, 2814 }; 2815 2816 static struct clk_branch gcc_gtcu_ahb_clk = { 2817 .halt_reg = 0x12044, 2818 .clkr = { 2819 .enable_reg = 0x4500c, 2820 .enable_mask = BIT(13), 2821 .hw.init = &(struct clk_init_data){ 2822 .name = "gcc_gtcu_ahb_clk", 2823 .parent_names = (const char *[]){ 2824 "pcnoc_bfdcd_clk_src", 2825 }, 2826 .num_parents = 1, 2827 .flags = CLK_SET_RATE_PARENT, 2828 .ops = &clk_branch2_ops, 2829 }, 2830 }, 2831 }; 2832 2833 static struct clk_branch gcc_bimc_gfx_clk = { 2834 .halt_reg = 0x31024, 2835 .clkr = { 2836 .enable_reg = 0x31024, 2837 .enable_mask = BIT(0), 2838 .hw.init = &(struct clk_init_data){ 2839 .name = "gcc_bimc_gfx_clk", 2840 .parent_names = (const char *[]){ 2841 "bimc_gpu_clk_src", 2842 }, 2843 .num_parents = 1, 2844 .flags = CLK_SET_RATE_PARENT, 2845 .ops = &clk_branch2_ops, 2846 }, 2847 }, 2848 }; 2849 2850 static struct clk_branch gcc_bimc_gpu_clk = { 2851 .halt_reg = 0x31040, 2852 .clkr = { 2853 .enable_reg = 0x31040, 2854 .enable_mask = BIT(0), 2855 .hw.init = &(struct clk_init_data){ 2856 .name = "gcc_bimc_gpu_clk", 2857 .parent_names = (const char *[]){ 2858 "bimc_gpu_clk_src", 2859 }, 2860 .num_parents = 1, 2861 .flags = CLK_SET_RATE_PARENT, 2862 .ops = &clk_branch2_ops, 2863 }, 2864 }, 2865 }; 2866 2867 static struct clk_branch gcc_jpeg_tbu_clk = { 2868 .halt_reg = 0x12034, 2869 .clkr = { 2870 .enable_reg = 0x4500c, 2871 .enable_mask = BIT(10), 2872 .hw.init = &(struct clk_init_data){ 2873 .name = "gcc_jpeg_tbu_clk", 2874 .parent_names = (const char *[]){ 2875 "system_noc_bfdcd_clk_src", 2876 }, 2877 .num_parents = 1, 2878 .flags = CLK_SET_RATE_PARENT, 2879 .ops = &clk_branch2_ops, 2880 }, 2881 }, 2882 }; 2883 2884 static struct clk_branch gcc_mdp_tbu_clk = { 2885 .halt_reg = 0x1201c, 2886 .clkr = { 2887 .enable_reg = 0x4500c, 2888 .enable_mask = BIT(4), 2889 .hw.init = &(struct clk_init_data){ 2890 .name = "gcc_mdp_tbu_clk", 2891 .parent_names = (const char *[]){ 2892 "system_noc_bfdcd_clk_src", 2893 }, 2894 .num_parents = 1, 2895 .flags = CLK_SET_RATE_PARENT, 2896 .ops = &clk_branch2_ops, 2897 }, 2898 }, 2899 }; 2900 2901 static struct clk_branch gcc_smmu_cfg_clk = { 2902 .halt_reg = 0x12038, 2903 .clkr = { 2904 .enable_reg = 0x4500c, 2905 .enable_mask = BIT(12), 2906 .hw.init = &(struct clk_init_data){ 2907 .name = "gcc_smmu_cfg_clk", 2908 .parent_names = (const char *[]){ 2909 "pcnoc_bfdcd_clk_src", 2910 }, 2911 .num_parents = 1, 2912 .flags = CLK_SET_RATE_PARENT, 2913 .ops = &clk_branch2_ops, 2914 }, 2915 }, 2916 }; 2917 2918 static struct clk_branch gcc_venus_tbu_clk = { 2919 .halt_reg = 0x12014, 2920 .clkr = { 2921 .enable_reg = 0x4500c, 2922 .enable_mask = BIT(5), 2923 .hw.init = &(struct clk_init_data){ 2924 .name = "gcc_venus_tbu_clk", 2925 .parent_names = (const char *[]){ 2926 "system_noc_bfdcd_clk_src", 2927 }, 2928 .num_parents = 1, 2929 .flags = CLK_SET_RATE_PARENT, 2930 .ops = &clk_branch2_ops, 2931 }, 2932 }, 2933 }; 2934 2935 static struct clk_branch gcc_vfe_tbu_clk = { 2936 .halt_reg = 0x1203c, 2937 .clkr = { 2938 .enable_reg = 0x4500c, 2939 .enable_mask = BIT(9), 2940 .hw.init = &(struct clk_init_data){ 2941 .name = "gcc_vfe_tbu_clk", 2942 .parent_names = (const char *[]){ 2943 "system_noc_bfdcd_clk_src", 2944 }, 2945 .num_parents = 1, 2946 .flags = CLK_SET_RATE_PARENT, 2947 .ops = &clk_branch2_ops, 2948 }, 2949 }, 2950 }; 2951 2952 static struct clk_branch gcc_usb2a_phy_sleep_clk = { 2953 .halt_reg = 0x4102c, 2954 .clkr = { 2955 .enable_reg = 0x4102c, 2956 .enable_mask = BIT(0), 2957 .hw.init = &(struct clk_init_data){ 2958 .name = "gcc_usb2a_phy_sleep_clk", 2959 .parent_names = (const char *[]){ 2960 "sleep_clk_src", 2961 }, 2962 .num_parents = 1, 2963 .flags = CLK_SET_RATE_PARENT, 2964 .ops = &clk_branch2_ops, 2965 }, 2966 }, 2967 }; 2968 2969 static struct clk_branch gcc_usb_hs_ahb_clk = { 2970 .halt_reg = 0x41008, 2971 .clkr = { 2972 .enable_reg = 0x41008, 2973 .enable_mask = BIT(0), 2974 .hw.init = &(struct clk_init_data){ 2975 .name = "gcc_usb_hs_ahb_clk", 2976 .parent_names = (const char *[]){ 2977 "pcnoc_bfdcd_clk_src", 2978 }, 2979 .num_parents = 1, 2980 .flags = CLK_SET_RATE_PARENT, 2981 .ops = &clk_branch2_ops, 2982 }, 2983 }, 2984 }; 2985 2986 static struct clk_branch gcc_usb_hs_system_clk = { 2987 .halt_reg = 0x41004, 2988 .clkr = { 2989 .enable_reg = 0x41004, 2990 .enable_mask = BIT(0), 2991 .hw.init = &(struct clk_init_data){ 2992 .name = "gcc_usb_hs_system_clk", 2993 .parent_names = (const char *[]){ 2994 "usb_hs_system_clk_src", 2995 }, 2996 .num_parents = 1, 2997 .flags = CLK_SET_RATE_PARENT, 2998 .ops = &clk_branch2_ops, 2999 }, 3000 }, 3001 }; 3002 3003 static struct clk_branch gcc_venus0_ahb_clk = { 3004 .halt_reg = 0x4c020, 3005 .clkr = { 3006 .enable_reg = 0x4c020, 3007 .enable_mask = BIT(0), 3008 .hw.init = &(struct clk_init_data){ 3009 .name = "gcc_venus0_ahb_clk", 3010 .parent_names = (const char *[]){ 3011 "pcnoc_bfdcd_clk_src", 3012 }, 3013 .num_parents = 1, 3014 .flags = CLK_SET_RATE_PARENT, 3015 .ops = &clk_branch2_ops, 3016 }, 3017 }, 3018 }; 3019 3020 static struct clk_branch gcc_venus0_axi_clk = { 3021 .halt_reg = 0x4c024, 3022 .clkr = { 3023 .enable_reg = 0x4c024, 3024 .enable_mask = BIT(0), 3025 .hw.init = &(struct clk_init_data){ 3026 .name = "gcc_venus0_axi_clk", 3027 .parent_names = (const char *[]){ 3028 "system_noc_bfdcd_clk_src", 3029 }, 3030 .num_parents = 1, 3031 .flags = CLK_SET_RATE_PARENT, 3032 .ops = &clk_branch2_ops, 3033 }, 3034 }, 3035 }; 3036 3037 static struct clk_branch gcc_venus0_vcodec0_clk = { 3038 .halt_reg = 0x4c01c, 3039 .clkr = { 3040 .enable_reg = 0x4c01c, 3041 .enable_mask = BIT(0), 3042 .hw.init = &(struct clk_init_data){ 3043 .name = "gcc_venus0_vcodec0_clk", 3044 .parent_names = (const char *[]){ 3045 "vcodec0_clk_src", 3046 }, 3047 .num_parents = 1, 3048 .flags = CLK_SET_RATE_PARENT, 3049 .ops = &clk_branch2_ops, 3050 }, 3051 }, 3052 }; 3053 3054 static struct gdsc venus_gdsc = { 3055 .gdscr = 0x4c018, 3056 .pd = { 3057 .name = "venus", 3058 }, 3059 .pwrsts = PWRSTS_OFF_ON, 3060 }; 3061 3062 static struct gdsc mdss_gdsc = { 3063 .gdscr = 0x4d078, 3064 .pd = { 3065 .name = "mdss", 3066 }, 3067 .pwrsts = PWRSTS_OFF_ON, 3068 }; 3069 3070 static struct gdsc jpeg_gdsc = { 3071 .gdscr = 0x5701c, 3072 .pd = { 3073 .name = "jpeg", 3074 }, 3075 .pwrsts = PWRSTS_OFF_ON, 3076 }; 3077 3078 static struct gdsc vfe_gdsc = { 3079 .gdscr = 0x58034, 3080 .pd = { 3081 .name = "vfe", 3082 }, 3083 .pwrsts = PWRSTS_OFF_ON, 3084 }; 3085 3086 static struct gdsc oxili_gdsc = { 3087 .gdscr = 0x5901c, 3088 .pd = { 3089 .name = "oxili", 3090 }, 3091 .pwrsts = PWRSTS_OFF_ON, 3092 }; 3093 3094 static struct clk_regmap *gcc_msm8916_clocks[] = { 3095 [GPLL0] = &gpll0.clkr, 3096 [GPLL0_VOTE] = &gpll0_vote, 3097 [BIMC_PLL] = &bimc_pll.clkr, 3098 [BIMC_PLL_VOTE] = &bimc_pll_vote, 3099 [GPLL1] = &gpll1.clkr, 3100 [GPLL1_VOTE] = &gpll1_vote, 3101 [GPLL2] = &gpll2.clkr, 3102 [GPLL2_VOTE] = &gpll2_vote, 3103 [PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr, 3104 [SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr, 3105 [CAMSS_AHB_CLK_SRC] = &camss_ahb_clk_src.clkr, 3106 [APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr, 3107 [CSI0_CLK_SRC] = &csi0_clk_src.clkr, 3108 [CSI1_CLK_SRC] = &csi1_clk_src.clkr, 3109 [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr, 3110 [VFE0_CLK_SRC] = &vfe0_clk_src.clkr, 3111 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr, 3112 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr, 3113 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr, 3114 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr, 3115 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr, 3116 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr, 3117 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr, 3118 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr, 3119 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr, 3120 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr, 3121 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr, 3122 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr, 3123 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr, 3124 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr, 3125 [CCI_CLK_SRC] = &cci_clk_src.clkr, 3126 [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr, 3127 [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr, 3128 [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr, 3129 [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr, 3130 [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr, 3131 [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr, 3132 [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr, 3133 [CPP_CLK_SRC] = &cpp_clk_src.clkr, 3134 [CRYPTO_CLK_SRC] = &crypto_clk_src.clkr, 3135 [GP1_CLK_SRC] = &gp1_clk_src.clkr, 3136 [GP2_CLK_SRC] = &gp2_clk_src.clkr, 3137 [GP3_CLK_SRC] = &gp3_clk_src.clkr, 3138 [BYTE0_CLK_SRC] = &byte0_clk_src.clkr, 3139 [ESC0_CLK_SRC] = &esc0_clk_src.clkr, 3140 [MDP_CLK_SRC] = &mdp_clk_src.clkr, 3141 [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr, 3142 [VSYNC_CLK_SRC] = &vsync_clk_src.clkr, 3143 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr, 3144 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr, 3145 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr, 3146 [APSS_TCU_CLK_SRC] = &apss_tcu_clk_src.clkr, 3147 [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr, 3148 [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr, 3149 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr, 3150 [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr, 3151 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr, 3152 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr, 3153 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr, 3154 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr, 3155 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr, 3156 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr, 3157 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr, 3158 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr, 3159 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr, 3160 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr, 3161 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr, 3162 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr, 3163 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, 3164 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr, 3165 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 3166 [GCC_CAMSS_CCI_AHB_CLK] = &gcc_camss_cci_ahb_clk.clkr, 3167 [GCC_CAMSS_CCI_CLK] = &gcc_camss_cci_clk.clkr, 3168 [GCC_CAMSS_CSI0_AHB_CLK] = &gcc_camss_csi0_ahb_clk.clkr, 3169 [GCC_CAMSS_CSI0_CLK] = &gcc_camss_csi0_clk.clkr, 3170 [GCC_CAMSS_CSI0PHY_CLK] = &gcc_camss_csi0phy_clk.clkr, 3171 [GCC_CAMSS_CSI0PIX_CLK] = &gcc_camss_csi0pix_clk.clkr, 3172 [GCC_CAMSS_CSI0RDI_CLK] = &gcc_camss_csi0rdi_clk.clkr, 3173 [GCC_CAMSS_CSI1_AHB_CLK] = &gcc_camss_csi1_ahb_clk.clkr, 3174 [GCC_CAMSS_CSI1_CLK] = &gcc_camss_csi1_clk.clkr, 3175 [GCC_CAMSS_CSI1PHY_CLK] = &gcc_camss_csi1phy_clk.clkr, 3176 [GCC_CAMSS_CSI1PIX_CLK] = &gcc_camss_csi1pix_clk.clkr, 3177 [GCC_CAMSS_CSI1RDI_CLK] = &gcc_camss_csi1rdi_clk.clkr, 3178 [GCC_CAMSS_CSI_VFE0_CLK] = &gcc_camss_csi_vfe0_clk.clkr, 3179 [GCC_CAMSS_GP0_CLK] = &gcc_camss_gp0_clk.clkr, 3180 [GCC_CAMSS_GP1_CLK] = &gcc_camss_gp1_clk.clkr, 3181 [GCC_CAMSS_ISPIF_AHB_CLK] = &gcc_camss_ispif_ahb_clk.clkr, 3182 [GCC_CAMSS_JPEG0_CLK] = &gcc_camss_jpeg0_clk.clkr, 3183 [GCC_CAMSS_JPEG_AHB_CLK] = &gcc_camss_jpeg_ahb_clk.clkr, 3184 [GCC_CAMSS_JPEG_AXI_CLK] = &gcc_camss_jpeg_axi_clk.clkr, 3185 [GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr, 3186 [GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr, 3187 [GCC_CAMSS_MICRO_AHB_CLK] = &gcc_camss_micro_ahb_clk.clkr, 3188 [GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr, 3189 [GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr, 3190 [GCC_CAMSS_AHB_CLK] = &gcc_camss_ahb_clk.clkr, 3191 [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr, 3192 [GCC_CAMSS_CPP_AHB_CLK] = &gcc_camss_cpp_ahb_clk.clkr, 3193 [GCC_CAMSS_CPP_CLK] = &gcc_camss_cpp_clk.clkr, 3194 [GCC_CAMSS_VFE0_CLK] = &gcc_camss_vfe0_clk.clkr, 3195 [GCC_CAMSS_VFE_AHB_CLK] = &gcc_camss_vfe_ahb_clk.clkr, 3196 [GCC_CAMSS_VFE_AXI_CLK] = &gcc_camss_vfe_axi_clk.clkr, 3197 [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr, 3198 [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr, 3199 [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr, 3200 [GCC_OXILI_GMEM_CLK] = &gcc_oxili_gmem_clk.clkr, 3201 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 3202 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 3203 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 3204 [GCC_MDSS_AHB_CLK] = &gcc_mdss_ahb_clk.clkr, 3205 [GCC_MDSS_AXI_CLK] = &gcc_mdss_axi_clk.clkr, 3206 [GCC_MDSS_BYTE0_CLK] = &gcc_mdss_byte0_clk.clkr, 3207 [GCC_MDSS_ESC0_CLK] = &gcc_mdss_esc0_clk.clkr, 3208 [GCC_MDSS_MDP_CLK] = &gcc_mdss_mdp_clk.clkr, 3209 [GCC_MDSS_PCLK0_CLK] = &gcc_mdss_pclk0_clk.clkr, 3210 [GCC_MDSS_VSYNC_CLK] = &gcc_mdss_vsync_clk.clkr, 3211 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr, 3212 [GCC_OXILI_AHB_CLK] = &gcc_oxili_ahb_clk.clkr, 3213 [GCC_OXILI_GFX3D_CLK] = &gcc_oxili_gfx3d_clk.clkr, 3214 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 3215 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 3216 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, 3217 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, 3218 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, 3219 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 3220 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 3221 [GCC_GTCU_AHB_CLK] = &gcc_gtcu_ahb_clk.clkr, 3222 [GCC_JPEG_TBU_CLK] = &gcc_jpeg_tbu_clk.clkr, 3223 [GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr, 3224 [GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr, 3225 [GCC_VENUS_TBU_CLK] = &gcc_venus_tbu_clk.clkr, 3226 [GCC_VFE_TBU_CLK] = &gcc_vfe_tbu_clk.clkr, 3227 [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr, 3228 [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr, 3229 [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr, 3230 [GCC_VENUS0_AHB_CLK] = &gcc_venus0_ahb_clk.clkr, 3231 [GCC_VENUS0_AXI_CLK] = &gcc_venus0_axi_clk.clkr, 3232 [GCC_VENUS0_VCODEC0_CLK] = &gcc_venus0_vcodec0_clk.clkr, 3233 [BIMC_DDR_CLK_SRC] = &bimc_ddr_clk_src.clkr, 3234 [GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr, 3235 [GCC_GFX_TCU_CLK] = &gcc_gfx_tcu_clk.clkr, 3236 [BIMC_GPU_CLK_SRC] = &bimc_gpu_clk_src.clkr, 3237 [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr, 3238 [GCC_BIMC_GPU_CLK] = &gcc_bimc_gpu_clk.clkr, 3239 [ULTAUDIO_AHBFABRIC_CLK_SRC] = &ultaudio_ahbfabric_clk_src.clkr, 3240 [ULTAUDIO_LPAIF_PRI_I2S_CLK_SRC] = &ultaudio_lpaif_pri_i2s_clk_src.clkr, 3241 [ULTAUDIO_LPAIF_SEC_I2S_CLK_SRC] = &ultaudio_lpaif_sec_i2s_clk_src.clkr, 3242 [ULTAUDIO_LPAIF_AUX_I2S_CLK_SRC] = &ultaudio_lpaif_aux_i2s_clk_src.clkr, 3243 [ULTAUDIO_XO_CLK_SRC] = &ultaudio_xo_clk_src.clkr, 3244 [CODEC_DIGCODEC_CLK_SRC] = &codec_digcodec_clk_src.clkr, 3245 [GCC_ULTAUDIO_PCNOC_MPORT_CLK] = &gcc_ultaudio_pcnoc_mport_clk.clkr, 3246 [GCC_ULTAUDIO_PCNOC_SWAY_CLK] = &gcc_ultaudio_pcnoc_sway_clk.clkr, 3247 [GCC_ULTAUDIO_AVSYNC_XO_CLK] = &gcc_ultaudio_avsync_xo_clk.clkr, 3248 [GCC_ULTAUDIO_STC_XO_CLK] = &gcc_ultaudio_stc_xo_clk.clkr, 3249 [GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK] = &gcc_ultaudio_ahbfabric_ixfabric_clk.clkr, 3250 [GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CLK] = &gcc_ultaudio_ahbfabric_ixfabric_lpm_clk.clkr, 3251 [GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK] = &gcc_ultaudio_lpaif_pri_i2s_clk.clkr, 3252 [GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK] = &gcc_ultaudio_lpaif_sec_i2s_clk.clkr, 3253 [GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK] = &gcc_ultaudio_lpaif_aux_i2s_clk.clkr, 3254 [GCC_CODEC_DIGCODEC_CLK] = &gcc_codec_digcodec_clk.clkr, 3255 [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr, 3256 }; 3257 3258 static struct gdsc *gcc_msm8916_gdscs[] = { 3259 [VENUS_GDSC] = &venus_gdsc, 3260 [MDSS_GDSC] = &mdss_gdsc, 3261 [JPEG_GDSC] = &jpeg_gdsc, 3262 [VFE_GDSC] = &vfe_gdsc, 3263 [OXILI_GDSC] = &oxili_gdsc, 3264 }; 3265 3266 static const struct qcom_reset_map gcc_msm8916_resets[] = { 3267 [GCC_BLSP1_BCR] = { 0x01000 }, 3268 [GCC_BLSP1_QUP1_BCR] = { 0x02000 }, 3269 [GCC_BLSP1_UART1_BCR] = { 0x02038 }, 3270 [GCC_BLSP1_QUP2_BCR] = { 0x03008 }, 3271 [GCC_BLSP1_UART2_BCR] = { 0x03028 }, 3272 [GCC_BLSP1_QUP3_BCR] = { 0x04018 }, 3273 [GCC_BLSP1_QUP4_BCR] = { 0x05018 }, 3274 [GCC_BLSP1_QUP5_BCR] = { 0x06018 }, 3275 [GCC_BLSP1_QUP6_BCR] = { 0x07018 }, 3276 [GCC_IMEM_BCR] = { 0x0e000 }, 3277 [GCC_SMMU_BCR] = { 0x12000 }, 3278 [GCC_APSS_TCU_BCR] = { 0x12050 }, 3279 [GCC_SMMU_XPU_BCR] = { 0x12054 }, 3280 [GCC_PCNOC_TBU_BCR] = { 0x12058 }, 3281 [GCC_PRNG_BCR] = { 0x13000 }, 3282 [GCC_BOOT_ROM_BCR] = { 0x13008 }, 3283 [GCC_CRYPTO_BCR] = { 0x16000 }, 3284 [GCC_SEC_CTRL_BCR] = { 0x1a000 }, 3285 [GCC_AUDIO_CORE_BCR] = { 0x1c008 }, 3286 [GCC_ULT_AUDIO_BCR] = { 0x1c0b4 }, 3287 [GCC_DEHR_BCR] = { 0x1f000 }, 3288 [GCC_SYSTEM_NOC_BCR] = { 0x26000 }, 3289 [GCC_PCNOC_BCR] = { 0x27018 }, 3290 [GCC_TCSR_BCR] = { 0x28000 }, 3291 [GCC_QDSS_BCR] = { 0x29000 }, 3292 [GCC_DCD_BCR] = { 0x2a000 }, 3293 [GCC_MSG_RAM_BCR] = { 0x2b000 }, 3294 [GCC_MPM_BCR] = { 0x2c000 }, 3295 [GCC_SPMI_BCR] = { 0x2e000 }, 3296 [GCC_SPDM_BCR] = { 0x2f000 }, 3297 [GCC_MM_SPDM_BCR] = { 0x2f024 }, 3298 [GCC_BIMC_BCR] = { 0x31000 }, 3299 [GCC_RBCPR_BCR] = { 0x33000 }, 3300 [GCC_TLMM_BCR] = { 0x34000 }, 3301 [GCC_USB_HS_BCR] = { 0x41000 }, 3302 [GCC_USB2A_PHY_BCR] = { 0x41028 }, 3303 [GCC_SDCC1_BCR] = { 0x42000 }, 3304 [GCC_SDCC2_BCR] = { 0x43000 }, 3305 [GCC_PDM_BCR] = { 0x44000 }, 3306 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000 }, 3307 [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000 }, 3308 [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008 }, 3309 [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010 }, 3310 [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018 }, 3311 [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020 }, 3312 [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028 }, 3313 [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030 }, 3314 [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038 }, 3315 [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040 }, 3316 [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048 }, 3317 [GCC_MMSS_BCR] = { 0x4b000 }, 3318 [GCC_VENUS0_BCR] = { 0x4c014 }, 3319 [GCC_MDSS_BCR] = { 0x4d074 }, 3320 [GCC_CAMSS_PHY0_BCR] = { 0x4e018 }, 3321 [GCC_CAMSS_CSI0_BCR] = { 0x4e038 }, 3322 [GCC_CAMSS_CSI0PHY_BCR] = { 0x4e044 }, 3323 [GCC_CAMSS_CSI0RDI_BCR] = { 0x4e04c }, 3324 [GCC_CAMSS_CSI0PIX_BCR] = { 0x4e054 }, 3325 [GCC_CAMSS_PHY1_BCR] = { 0x4f018 }, 3326 [GCC_CAMSS_CSI1_BCR] = { 0x4f038 }, 3327 [GCC_CAMSS_CSI1PHY_BCR] = { 0x4f044 }, 3328 [GCC_CAMSS_CSI1RDI_BCR] = { 0x4f04c }, 3329 [GCC_CAMSS_CSI1PIX_BCR] = { 0x4f054 }, 3330 [GCC_CAMSS_ISPIF_BCR] = { 0x50000 }, 3331 [GCC_CAMSS_CCI_BCR] = { 0x51014 }, 3332 [GCC_CAMSS_MCLK0_BCR] = { 0x52014 }, 3333 [GCC_CAMSS_MCLK1_BCR] = { 0x53014 }, 3334 [GCC_CAMSS_GP0_BCR] = { 0x54014 }, 3335 [GCC_CAMSS_GP1_BCR] = { 0x55014 }, 3336 [GCC_CAMSS_TOP_BCR] = { 0x56000 }, 3337 [GCC_CAMSS_MICRO_BCR] = { 0x56008 }, 3338 [GCC_CAMSS_JPEG_BCR] = { 0x57018 }, 3339 [GCC_CAMSS_VFE_BCR] = { 0x58030 }, 3340 [GCC_CAMSS_CSI_VFE0_BCR] = { 0x5804c }, 3341 [GCC_OXILI_BCR] = { 0x59018 }, 3342 [GCC_GMEM_BCR] = { 0x5902c }, 3343 [GCC_CAMSS_AHB_BCR] = { 0x5a018 }, 3344 [GCC_MDP_TBU_BCR] = { 0x62000 }, 3345 [GCC_GFX_TBU_BCR] = { 0x63000 }, 3346 [GCC_GFX_TCU_BCR] = { 0x64000 }, 3347 [GCC_MSS_TBU_AXI_BCR] = { 0x65000 }, 3348 [GCC_MSS_TBU_GSS_AXI_BCR] = { 0x66000 }, 3349 [GCC_MSS_TBU_Q6_AXI_BCR] = { 0x67000 }, 3350 [GCC_GTCU_AHB_BCR] = { 0x68000 }, 3351 [GCC_SMMU_CFG_BCR] = { 0x69000 }, 3352 [GCC_VFE_TBU_BCR] = { 0x6a000 }, 3353 [GCC_VENUS_TBU_BCR] = { 0x6b000 }, 3354 [GCC_JPEG_TBU_BCR] = { 0x6c000 }, 3355 [GCC_PRONTO_TBU_BCR] = { 0x6d000 }, 3356 [GCC_SMMU_CATS_BCR] = { 0x7c000 }, 3357 }; 3358 3359 static const struct regmap_config gcc_msm8916_regmap_config = { 3360 .reg_bits = 32, 3361 .reg_stride = 4, 3362 .val_bits = 32, 3363 .max_register = 0x80000, 3364 .fast_io = true, 3365 }; 3366 3367 static const struct qcom_cc_desc gcc_msm8916_desc = { 3368 .config = &gcc_msm8916_regmap_config, 3369 .clks = gcc_msm8916_clocks, 3370 .num_clks = ARRAY_SIZE(gcc_msm8916_clocks), 3371 .resets = gcc_msm8916_resets, 3372 .num_resets = ARRAY_SIZE(gcc_msm8916_resets), 3373 .gdscs = gcc_msm8916_gdscs, 3374 .num_gdscs = ARRAY_SIZE(gcc_msm8916_gdscs), 3375 }; 3376 3377 static const struct of_device_id gcc_msm8916_match_table[] = { 3378 { .compatible = "qcom,gcc-msm8916" }, 3379 { } 3380 }; 3381 MODULE_DEVICE_TABLE(of, gcc_msm8916_match_table); 3382 3383 static int gcc_msm8916_probe(struct platform_device *pdev) 3384 { 3385 int ret; 3386 struct device *dev = &pdev->dev; 3387 3388 ret = qcom_cc_register_board_clk(dev, "xo_board", "xo", 19200000); 3389 if (ret) 3390 return ret; 3391 3392 ret = qcom_cc_register_sleep_clk(dev); 3393 if (ret) 3394 return ret; 3395 3396 return qcom_cc_probe(pdev, &gcc_msm8916_desc); 3397 } 3398 3399 static struct platform_driver gcc_msm8916_driver = { 3400 .probe = gcc_msm8916_probe, 3401 .driver = { 3402 .name = "gcc-msm8916", 3403 .of_match_table = gcc_msm8916_match_table, 3404 }, 3405 }; 3406 3407 static int __init gcc_msm8916_init(void) 3408 { 3409 return platform_driver_register(&gcc_msm8916_driver); 3410 } 3411 core_initcall(gcc_msm8916_init); 3412 3413 static void __exit gcc_msm8916_exit(void) 3414 { 3415 platform_driver_unregister(&gcc_msm8916_driver); 3416 } 3417 module_exit(gcc_msm8916_exit); 3418 3419 MODULE_DESCRIPTION("Qualcomm GCC MSM8916 Driver"); 3420 MODULE_LICENSE("GPL v2"); 3421 MODULE_ALIAS("platform:gcc-msm8916"); 3422