1 /* 2 * Copyright 2015 Linaro Limited 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include <linux/kernel.h> 15 #include <linux/bitops.h> 16 #include <linux/err.h> 17 #include <linux/platform_device.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/of_device.h> 21 #include <linux/clk-provider.h> 22 #include <linux/regmap.h> 23 #include <linux/reset-controller.h> 24 25 #include <dt-bindings/clock/qcom,gcc-msm8916.h> 26 #include <dt-bindings/reset/qcom,gcc-msm8916.h> 27 28 #include "common.h" 29 #include "clk-regmap.h" 30 #include "clk-pll.h" 31 #include "clk-rcg.h" 32 #include "clk-branch.h" 33 #include "reset.h" 34 #include "gdsc.h" 35 36 enum { 37 P_XO, 38 P_GPLL0, 39 P_GPLL0_AUX, 40 P_BIMC, 41 P_GPLL1, 42 P_GPLL1_AUX, 43 P_GPLL2, 44 P_GPLL2_AUX, 45 P_SLEEP_CLK, 46 P_DSI0_PHYPLL_BYTE, 47 P_DSI0_PHYPLL_DSI, 48 P_EXT_PRI_I2S, 49 P_EXT_SEC_I2S, 50 P_EXT_MCLK, 51 }; 52 53 static const struct parent_map gcc_xo_gpll0_map[] = { 54 { P_XO, 0 }, 55 { P_GPLL0, 1 }, 56 }; 57 58 static const char * const gcc_xo_gpll0[] = { 59 "xo", 60 "gpll0_vote", 61 }; 62 63 static const struct parent_map gcc_xo_gpll0_bimc_map[] = { 64 { P_XO, 0 }, 65 { P_GPLL0, 1 }, 66 { P_BIMC, 2 }, 67 }; 68 69 static const char * const gcc_xo_gpll0_bimc[] = { 70 "xo", 71 "gpll0_vote", 72 "bimc_pll_vote", 73 }; 74 75 static const struct parent_map gcc_xo_gpll0a_gpll1_gpll2a_map[] = { 76 { P_XO, 0 }, 77 { P_GPLL0_AUX, 3 }, 78 { P_GPLL1, 1 }, 79 { P_GPLL2_AUX, 2 }, 80 }; 81 82 static const char * const gcc_xo_gpll0a_gpll1_gpll2a[] = { 83 "xo", 84 "gpll0_vote", 85 "gpll1_vote", 86 "gpll2_vote", 87 }; 88 89 static const struct parent_map gcc_xo_gpll0_gpll2_map[] = { 90 { P_XO, 0 }, 91 { P_GPLL0, 1 }, 92 { P_GPLL2, 2 }, 93 }; 94 95 static const char * const gcc_xo_gpll0_gpll2[] = { 96 "xo", 97 "gpll0_vote", 98 "gpll2_vote", 99 }; 100 101 static const struct parent_map gcc_xo_gpll0a_map[] = { 102 { P_XO, 0 }, 103 { P_GPLL0_AUX, 2 }, 104 }; 105 106 static const char * const gcc_xo_gpll0a[] = { 107 "xo", 108 "gpll0_vote", 109 }; 110 111 static const struct parent_map gcc_xo_gpll0_gpll1a_sleep_map[] = { 112 { P_XO, 0 }, 113 { P_GPLL0, 1 }, 114 { P_GPLL1_AUX, 2 }, 115 { P_SLEEP_CLK, 6 }, 116 }; 117 118 static const char * const gcc_xo_gpll0_gpll1a_sleep[] = { 119 "xo", 120 "gpll0_vote", 121 "gpll1_vote", 122 "sleep_clk", 123 }; 124 125 static const struct parent_map gcc_xo_gpll0_gpll1a_map[] = { 126 { P_XO, 0 }, 127 { P_GPLL0, 1 }, 128 { P_GPLL1_AUX, 2 }, 129 }; 130 131 static const char * const gcc_xo_gpll0_gpll1a[] = { 132 "xo", 133 "gpll0_vote", 134 "gpll1_vote", 135 }; 136 137 static const struct parent_map gcc_xo_dsibyte_map[] = { 138 { P_XO, 0, }, 139 { P_DSI0_PHYPLL_BYTE, 2 }, 140 }; 141 142 static const char * const gcc_xo_dsibyte[] = { 143 "xo", 144 "dsi0pllbyte", 145 }; 146 147 static const struct parent_map gcc_xo_gpll0a_dsibyte_map[] = { 148 { P_XO, 0 }, 149 { P_GPLL0_AUX, 2 }, 150 { P_DSI0_PHYPLL_BYTE, 1 }, 151 }; 152 153 static const char * const gcc_xo_gpll0a_dsibyte[] = { 154 "xo", 155 "gpll0_vote", 156 "dsi0pllbyte", 157 }; 158 159 static const struct parent_map gcc_xo_gpll0_dsiphy_map[] = { 160 { P_XO, 0 }, 161 { P_GPLL0, 1 }, 162 { P_DSI0_PHYPLL_DSI, 2 }, 163 }; 164 165 static const char * const gcc_xo_gpll0_dsiphy[] = { 166 "xo", 167 "gpll0_vote", 168 "dsi0pll", 169 }; 170 171 static const struct parent_map gcc_xo_gpll0a_dsiphy_map[] = { 172 { P_XO, 0 }, 173 { P_GPLL0_AUX, 2 }, 174 { P_DSI0_PHYPLL_DSI, 1 }, 175 }; 176 177 static const char * const gcc_xo_gpll0a_dsiphy[] = { 178 "xo", 179 "gpll0_vote", 180 "dsi0pll", 181 }; 182 183 static const struct parent_map gcc_xo_gpll0a_gpll1_gpll2_map[] = { 184 { P_XO, 0 }, 185 { P_GPLL0_AUX, 1 }, 186 { P_GPLL1, 3 }, 187 { P_GPLL2, 2 }, 188 }; 189 190 static const char * const gcc_xo_gpll0a_gpll1_gpll2[] = { 191 "xo", 192 "gpll0_vote", 193 "gpll1_vote", 194 "gpll2_vote", 195 }; 196 197 static const struct parent_map gcc_xo_gpll0_gpll1_sleep_map[] = { 198 { P_XO, 0 }, 199 { P_GPLL0, 1 }, 200 { P_GPLL1, 2 }, 201 { P_SLEEP_CLK, 6 } 202 }; 203 204 static const char * const gcc_xo_gpll0_gpll1_sleep[] = { 205 "xo", 206 "gpll0_vote", 207 "gpll1_vote", 208 "sleep_clk", 209 }; 210 211 static const struct parent_map gcc_xo_gpll1_epi2s_emclk_sleep_map[] = { 212 { P_XO, 0 }, 213 { P_GPLL1, 1 }, 214 { P_EXT_PRI_I2S, 2 }, 215 { P_EXT_MCLK, 3 }, 216 { P_SLEEP_CLK, 6 } 217 }; 218 219 static const char * const gcc_xo_gpll1_epi2s_emclk_sleep[] = { 220 "xo", 221 "gpll1_vote", 222 "ext_pri_i2s", 223 "ext_mclk", 224 "sleep_clk", 225 }; 226 227 static const struct parent_map gcc_xo_gpll1_esi2s_emclk_sleep_map[] = { 228 { P_XO, 0 }, 229 { P_GPLL1, 1 }, 230 { P_EXT_SEC_I2S, 2 }, 231 { P_EXT_MCLK, 3 }, 232 { P_SLEEP_CLK, 6 } 233 }; 234 235 static const char * const gcc_xo_gpll1_esi2s_emclk_sleep[] = { 236 "xo", 237 "gpll1_vote", 238 "ext_sec_i2s", 239 "ext_mclk", 240 "sleep_clk", 241 }; 242 243 static const struct parent_map gcc_xo_sleep_map[] = { 244 { P_XO, 0 }, 245 { P_SLEEP_CLK, 6 } 246 }; 247 248 static const char * const gcc_xo_sleep[] = { 249 "xo", 250 "sleep_clk", 251 }; 252 253 static const struct parent_map gcc_xo_gpll1_emclk_sleep_map[] = { 254 { P_XO, 0 }, 255 { P_GPLL1, 1 }, 256 { P_EXT_MCLK, 2 }, 257 { P_SLEEP_CLK, 6 } 258 }; 259 260 static const char * const gcc_xo_gpll1_emclk_sleep[] = { 261 "xo", 262 "gpll1_vote", 263 "ext_mclk", 264 "sleep_clk", 265 }; 266 267 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } 268 269 static struct clk_pll gpll0 = { 270 .l_reg = 0x21004, 271 .m_reg = 0x21008, 272 .n_reg = 0x2100c, 273 .config_reg = 0x21014, 274 .mode_reg = 0x21000, 275 .status_reg = 0x2101c, 276 .status_bit = 17, 277 .clkr.hw.init = &(struct clk_init_data){ 278 .name = "gpll0", 279 .parent_names = (const char *[]){ "xo" }, 280 .num_parents = 1, 281 .ops = &clk_pll_ops, 282 }, 283 }; 284 285 static struct clk_regmap gpll0_vote = { 286 .enable_reg = 0x45000, 287 .enable_mask = BIT(0), 288 .hw.init = &(struct clk_init_data){ 289 .name = "gpll0_vote", 290 .parent_names = (const char *[]){ "gpll0" }, 291 .num_parents = 1, 292 .ops = &clk_pll_vote_ops, 293 }, 294 }; 295 296 static struct clk_pll gpll1 = { 297 .l_reg = 0x20004, 298 .m_reg = 0x20008, 299 .n_reg = 0x2000c, 300 .config_reg = 0x20014, 301 .mode_reg = 0x20000, 302 .status_reg = 0x2001c, 303 .status_bit = 17, 304 .clkr.hw.init = &(struct clk_init_data){ 305 .name = "gpll1", 306 .parent_names = (const char *[]){ "xo" }, 307 .num_parents = 1, 308 .ops = &clk_pll_ops, 309 }, 310 }; 311 312 static struct clk_regmap gpll1_vote = { 313 .enable_reg = 0x45000, 314 .enable_mask = BIT(1), 315 .hw.init = &(struct clk_init_data){ 316 .name = "gpll1_vote", 317 .parent_names = (const char *[]){ "gpll1" }, 318 .num_parents = 1, 319 .ops = &clk_pll_vote_ops, 320 }, 321 }; 322 323 static struct clk_pll gpll2 = { 324 .l_reg = 0x4a004, 325 .m_reg = 0x4a008, 326 .n_reg = 0x4a00c, 327 .config_reg = 0x4a014, 328 .mode_reg = 0x4a000, 329 .status_reg = 0x4a01c, 330 .status_bit = 17, 331 .clkr.hw.init = &(struct clk_init_data){ 332 .name = "gpll2", 333 .parent_names = (const char *[]){ "xo" }, 334 .num_parents = 1, 335 .ops = &clk_pll_ops, 336 }, 337 }; 338 339 static struct clk_regmap gpll2_vote = { 340 .enable_reg = 0x45000, 341 .enable_mask = BIT(2), 342 .hw.init = &(struct clk_init_data){ 343 .name = "gpll2_vote", 344 .parent_names = (const char *[]){ "gpll2" }, 345 .num_parents = 1, 346 .ops = &clk_pll_vote_ops, 347 }, 348 }; 349 350 static struct clk_pll bimc_pll = { 351 .l_reg = 0x23004, 352 .m_reg = 0x23008, 353 .n_reg = 0x2300c, 354 .config_reg = 0x23014, 355 .mode_reg = 0x23000, 356 .status_reg = 0x2301c, 357 .status_bit = 17, 358 .clkr.hw.init = &(struct clk_init_data){ 359 .name = "bimc_pll", 360 .parent_names = (const char *[]){ "xo" }, 361 .num_parents = 1, 362 .ops = &clk_pll_ops, 363 }, 364 }; 365 366 static struct clk_regmap bimc_pll_vote = { 367 .enable_reg = 0x45000, 368 .enable_mask = BIT(3), 369 .hw.init = &(struct clk_init_data){ 370 .name = "bimc_pll_vote", 371 .parent_names = (const char *[]){ "bimc_pll" }, 372 .num_parents = 1, 373 .ops = &clk_pll_vote_ops, 374 }, 375 }; 376 377 static struct clk_rcg2 pcnoc_bfdcd_clk_src = { 378 .cmd_rcgr = 0x27000, 379 .hid_width = 5, 380 .parent_map = gcc_xo_gpll0_bimc_map, 381 .clkr.hw.init = &(struct clk_init_data){ 382 .name = "pcnoc_bfdcd_clk_src", 383 .parent_names = gcc_xo_gpll0_bimc, 384 .num_parents = 3, 385 .ops = &clk_rcg2_ops, 386 }, 387 }; 388 389 static struct clk_rcg2 system_noc_bfdcd_clk_src = { 390 .cmd_rcgr = 0x26004, 391 .hid_width = 5, 392 .parent_map = gcc_xo_gpll0_bimc_map, 393 .clkr.hw.init = &(struct clk_init_data){ 394 .name = "system_noc_bfdcd_clk_src", 395 .parent_names = gcc_xo_gpll0_bimc, 396 .num_parents = 3, 397 .ops = &clk_rcg2_ops, 398 }, 399 }; 400 401 static const struct freq_tbl ftbl_gcc_camss_ahb_clk[] = { 402 F(40000000, P_GPLL0, 10, 1, 2), 403 F(80000000, P_GPLL0, 10, 0, 0), 404 { } 405 }; 406 407 static struct clk_rcg2 camss_ahb_clk_src = { 408 .cmd_rcgr = 0x5a000, 409 .mnd_width = 8, 410 .hid_width = 5, 411 .parent_map = gcc_xo_gpll0_map, 412 .freq_tbl = ftbl_gcc_camss_ahb_clk, 413 .clkr.hw.init = &(struct clk_init_data){ 414 .name = "camss_ahb_clk_src", 415 .parent_names = gcc_xo_gpll0, 416 .num_parents = 2, 417 .ops = &clk_rcg2_ops, 418 }, 419 }; 420 421 static const struct freq_tbl ftbl_apss_ahb_clk[] = { 422 F(19200000, P_XO, 1, 0, 0), 423 F(50000000, P_GPLL0, 16, 0, 0), 424 F(100000000, P_GPLL0, 8, 0, 0), 425 F(133330000, P_GPLL0, 6, 0, 0), 426 { } 427 }; 428 429 static struct clk_rcg2 apss_ahb_clk_src = { 430 .cmd_rcgr = 0x46000, 431 .hid_width = 5, 432 .parent_map = gcc_xo_gpll0_map, 433 .freq_tbl = ftbl_apss_ahb_clk, 434 .clkr.hw.init = &(struct clk_init_data){ 435 .name = "apss_ahb_clk_src", 436 .parent_names = gcc_xo_gpll0, 437 .num_parents = 2, 438 .ops = &clk_rcg2_ops, 439 }, 440 }; 441 442 static const struct freq_tbl ftbl_gcc_camss_csi0_1_clk[] = { 443 F(100000000, P_GPLL0, 8, 0, 0), 444 F(200000000, P_GPLL0, 4, 0, 0), 445 { } 446 }; 447 448 static struct clk_rcg2 csi0_clk_src = { 449 .cmd_rcgr = 0x4e020, 450 .hid_width = 5, 451 .parent_map = gcc_xo_gpll0_map, 452 .freq_tbl = ftbl_gcc_camss_csi0_1_clk, 453 .clkr.hw.init = &(struct clk_init_data){ 454 .name = "csi0_clk_src", 455 .parent_names = gcc_xo_gpll0, 456 .num_parents = 2, 457 .ops = &clk_rcg2_ops, 458 }, 459 }; 460 461 static struct clk_rcg2 csi1_clk_src = { 462 .cmd_rcgr = 0x4f020, 463 .hid_width = 5, 464 .parent_map = gcc_xo_gpll0_map, 465 .freq_tbl = ftbl_gcc_camss_csi0_1_clk, 466 .clkr.hw.init = &(struct clk_init_data){ 467 .name = "csi1_clk_src", 468 .parent_names = gcc_xo_gpll0, 469 .num_parents = 2, 470 .ops = &clk_rcg2_ops, 471 }, 472 }; 473 474 static const struct freq_tbl ftbl_gcc_oxili_gfx3d_clk[] = { 475 F(19200000, P_XO, 1, 0, 0), 476 F(50000000, P_GPLL0_AUX, 16, 0, 0), 477 F(80000000, P_GPLL0_AUX, 10, 0, 0), 478 F(100000000, P_GPLL0_AUX, 8, 0, 0), 479 F(160000000, P_GPLL0_AUX, 5, 0, 0), 480 F(177780000, P_GPLL0_AUX, 4.5, 0, 0), 481 F(200000000, P_GPLL0_AUX, 4, 0, 0), 482 F(266670000, P_GPLL0_AUX, 3, 0, 0), 483 F(294912000, P_GPLL1, 3, 0, 0), 484 F(310000000, P_GPLL2, 3, 0, 0), 485 F(400000000, P_GPLL0_AUX, 2, 0, 0), 486 { } 487 }; 488 489 static struct clk_rcg2 gfx3d_clk_src = { 490 .cmd_rcgr = 0x59000, 491 .hid_width = 5, 492 .parent_map = gcc_xo_gpll0a_gpll1_gpll2a_map, 493 .freq_tbl = ftbl_gcc_oxili_gfx3d_clk, 494 .clkr.hw.init = &(struct clk_init_data){ 495 .name = "gfx3d_clk_src", 496 .parent_names = gcc_xo_gpll0a_gpll1_gpll2a, 497 .num_parents = 4, 498 .ops = &clk_rcg2_ops, 499 }, 500 }; 501 502 static const struct freq_tbl ftbl_gcc_camss_vfe0_clk[] = { 503 F(50000000, P_GPLL0, 16, 0, 0), 504 F(80000000, P_GPLL0, 10, 0, 0), 505 F(100000000, P_GPLL0, 8, 0, 0), 506 F(160000000, P_GPLL0, 5, 0, 0), 507 F(177780000, P_GPLL0, 4.5, 0, 0), 508 F(200000000, P_GPLL0, 4, 0, 0), 509 F(266670000, P_GPLL0, 3, 0, 0), 510 F(320000000, P_GPLL0, 2.5, 0, 0), 511 F(400000000, P_GPLL0, 2, 0, 0), 512 F(465000000, P_GPLL2, 2, 0, 0), 513 { } 514 }; 515 516 static struct clk_rcg2 vfe0_clk_src = { 517 .cmd_rcgr = 0x58000, 518 .hid_width = 5, 519 .parent_map = gcc_xo_gpll0_gpll2_map, 520 .freq_tbl = ftbl_gcc_camss_vfe0_clk, 521 .clkr.hw.init = &(struct clk_init_data){ 522 .name = "vfe0_clk_src", 523 .parent_names = gcc_xo_gpll0_gpll2, 524 .num_parents = 3, 525 .ops = &clk_rcg2_ops, 526 }, 527 }; 528 529 static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_i2c_apps_clk[] = { 530 F(19200000, P_XO, 1, 0, 0), 531 F(50000000, P_GPLL0, 16, 0, 0), 532 { } 533 }; 534 535 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { 536 .cmd_rcgr = 0x0200c, 537 .hid_width = 5, 538 .parent_map = gcc_xo_gpll0_map, 539 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, 540 .clkr.hw.init = &(struct clk_init_data){ 541 .name = "blsp1_qup1_i2c_apps_clk_src", 542 .parent_names = gcc_xo_gpll0, 543 .num_parents = 2, 544 .ops = &clk_rcg2_ops, 545 }, 546 }; 547 548 static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_spi_apps_clk[] = { 549 F(960000, P_XO, 10, 1, 2), 550 F(4800000, P_XO, 4, 0, 0), 551 F(9600000, P_XO, 2, 0, 0), 552 F(16000000, P_GPLL0, 10, 1, 5), 553 F(19200000, P_XO, 1, 0, 0), 554 F(25000000, P_GPLL0, 16, 1, 2), 555 F(50000000, P_GPLL0, 16, 0, 0), 556 { } 557 }; 558 559 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { 560 .cmd_rcgr = 0x02024, 561 .mnd_width = 8, 562 .hid_width = 5, 563 .parent_map = gcc_xo_gpll0_map, 564 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, 565 .clkr.hw.init = &(struct clk_init_data){ 566 .name = "blsp1_qup1_spi_apps_clk_src", 567 .parent_names = gcc_xo_gpll0, 568 .num_parents = 2, 569 .ops = &clk_rcg2_ops, 570 }, 571 }; 572 573 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { 574 .cmd_rcgr = 0x03000, 575 .hid_width = 5, 576 .parent_map = gcc_xo_gpll0_map, 577 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, 578 .clkr.hw.init = &(struct clk_init_data){ 579 .name = "blsp1_qup2_i2c_apps_clk_src", 580 .parent_names = gcc_xo_gpll0, 581 .num_parents = 2, 582 .ops = &clk_rcg2_ops, 583 }, 584 }; 585 586 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { 587 .cmd_rcgr = 0x03014, 588 .mnd_width = 8, 589 .hid_width = 5, 590 .parent_map = gcc_xo_gpll0_map, 591 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, 592 .clkr.hw.init = &(struct clk_init_data){ 593 .name = "blsp1_qup2_spi_apps_clk_src", 594 .parent_names = gcc_xo_gpll0, 595 .num_parents = 2, 596 .ops = &clk_rcg2_ops, 597 }, 598 }; 599 600 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { 601 .cmd_rcgr = 0x04000, 602 .hid_width = 5, 603 .parent_map = gcc_xo_gpll0_map, 604 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, 605 .clkr.hw.init = &(struct clk_init_data){ 606 .name = "blsp1_qup3_i2c_apps_clk_src", 607 .parent_names = gcc_xo_gpll0, 608 .num_parents = 2, 609 .ops = &clk_rcg2_ops, 610 }, 611 }; 612 613 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { 614 .cmd_rcgr = 0x04024, 615 .mnd_width = 8, 616 .hid_width = 5, 617 .parent_map = gcc_xo_gpll0_map, 618 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, 619 .clkr.hw.init = &(struct clk_init_data){ 620 .name = "blsp1_qup3_spi_apps_clk_src", 621 .parent_names = gcc_xo_gpll0, 622 .num_parents = 2, 623 .ops = &clk_rcg2_ops, 624 }, 625 }; 626 627 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { 628 .cmd_rcgr = 0x05000, 629 .hid_width = 5, 630 .parent_map = gcc_xo_gpll0_map, 631 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, 632 .clkr.hw.init = &(struct clk_init_data){ 633 .name = "blsp1_qup4_i2c_apps_clk_src", 634 .parent_names = gcc_xo_gpll0, 635 .num_parents = 2, 636 .ops = &clk_rcg2_ops, 637 }, 638 }; 639 640 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { 641 .cmd_rcgr = 0x05024, 642 .mnd_width = 8, 643 .hid_width = 5, 644 .parent_map = gcc_xo_gpll0_map, 645 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, 646 .clkr.hw.init = &(struct clk_init_data){ 647 .name = "blsp1_qup4_spi_apps_clk_src", 648 .parent_names = gcc_xo_gpll0, 649 .num_parents = 2, 650 .ops = &clk_rcg2_ops, 651 }, 652 }; 653 654 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = { 655 .cmd_rcgr = 0x06000, 656 .hid_width = 5, 657 .parent_map = gcc_xo_gpll0_map, 658 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, 659 .clkr.hw.init = &(struct clk_init_data){ 660 .name = "blsp1_qup5_i2c_apps_clk_src", 661 .parent_names = gcc_xo_gpll0, 662 .num_parents = 2, 663 .ops = &clk_rcg2_ops, 664 }, 665 }; 666 667 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = { 668 .cmd_rcgr = 0x06024, 669 .mnd_width = 8, 670 .hid_width = 5, 671 .parent_map = gcc_xo_gpll0_map, 672 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, 673 .clkr.hw.init = &(struct clk_init_data){ 674 .name = "blsp1_qup5_spi_apps_clk_src", 675 .parent_names = gcc_xo_gpll0, 676 .num_parents = 2, 677 .ops = &clk_rcg2_ops, 678 }, 679 }; 680 681 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = { 682 .cmd_rcgr = 0x07000, 683 .hid_width = 5, 684 .parent_map = gcc_xo_gpll0_map, 685 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, 686 .clkr.hw.init = &(struct clk_init_data){ 687 .name = "blsp1_qup6_i2c_apps_clk_src", 688 .parent_names = gcc_xo_gpll0, 689 .num_parents = 2, 690 .ops = &clk_rcg2_ops, 691 }, 692 }; 693 694 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = { 695 .cmd_rcgr = 0x07024, 696 .mnd_width = 8, 697 .hid_width = 5, 698 .parent_map = gcc_xo_gpll0_map, 699 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, 700 .clkr.hw.init = &(struct clk_init_data){ 701 .name = "blsp1_qup6_spi_apps_clk_src", 702 .parent_names = gcc_xo_gpll0, 703 .num_parents = 2, 704 .ops = &clk_rcg2_ops, 705 }, 706 }; 707 708 static const struct freq_tbl ftbl_gcc_blsp1_uart1_6_apps_clk[] = { 709 F(3686400, P_GPLL0, 1, 72, 15625), 710 F(7372800, P_GPLL0, 1, 144, 15625), 711 F(14745600, P_GPLL0, 1, 288, 15625), 712 F(16000000, P_GPLL0, 10, 1, 5), 713 F(19200000, P_XO, 1, 0, 0), 714 F(24000000, P_GPLL0, 1, 3, 100), 715 F(25000000, P_GPLL0, 16, 1, 2), 716 F(32000000, P_GPLL0, 1, 1, 25), 717 F(40000000, P_GPLL0, 1, 1, 20), 718 F(46400000, P_GPLL0, 1, 29, 500), 719 F(48000000, P_GPLL0, 1, 3, 50), 720 F(51200000, P_GPLL0, 1, 8, 125), 721 F(56000000, P_GPLL0, 1, 7, 100), 722 F(58982400, P_GPLL0, 1, 1152, 15625), 723 F(60000000, P_GPLL0, 1, 3, 40), 724 { } 725 }; 726 727 static struct clk_rcg2 blsp1_uart1_apps_clk_src = { 728 .cmd_rcgr = 0x02044, 729 .mnd_width = 16, 730 .hid_width = 5, 731 .parent_map = gcc_xo_gpll0_map, 732 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk, 733 .clkr.hw.init = &(struct clk_init_data){ 734 .name = "blsp1_uart1_apps_clk_src", 735 .parent_names = gcc_xo_gpll0, 736 .num_parents = 2, 737 .ops = &clk_rcg2_ops, 738 }, 739 }; 740 741 static struct clk_rcg2 blsp1_uart2_apps_clk_src = { 742 .cmd_rcgr = 0x03034, 743 .mnd_width = 16, 744 .hid_width = 5, 745 .parent_map = gcc_xo_gpll0_map, 746 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk, 747 .clkr.hw.init = &(struct clk_init_data){ 748 .name = "blsp1_uart2_apps_clk_src", 749 .parent_names = gcc_xo_gpll0, 750 .num_parents = 2, 751 .ops = &clk_rcg2_ops, 752 }, 753 }; 754 755 static const struct freq_tbl ftbl_gcc_camss_cci_clk[] = { 756 F(19200000, P_XO, 1, 0, 0), 757 { } 758 }; 759 760 static struct clk_rcg2 cci_clk_src = { 761 .cmd_rcgr = 0x51000, 762 .mnd_width = 8, 763 .hid_width = 5, 764 .parent_map = gcc_xo_gpll0a_map, 765 .freq_tbl = ftbl_gcc_camss_cci_clk, 766 .clkr.hw.init = &(struct clk_init_data){ 767 .name = "cci_clk_src", 768 .parent_names = gcc_xo_gpll0a, 769 .num_parents = 2, 770 .ops = &clk_rcg2_ops, 771 }, 772 }; 773 774 static const struct freq_tbl ftbl_gcc_camss_gp0_1_clk[] = { 775 F(100000000, P_GPLL0, 8, 0, 0), 776 F(200000000, P_GPLL0, 4, 0, 0), 777 { } 778 }; 779 780 static struct clk_rcg2 camss_gp0_clk_src = { 781 .cmd_rcgr = 0x54000, 782 .mnd_width = 8, 783 .hid_width = 5, 784 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map, 785 .freq_tbl = ftbl_gcc_camss_gp0_1_clk, 786 .clkr.hw.init = &(struct clk_init_data){ 787 .name = "camss_gp0_clk_src", 788 .parent_names = gcc_xo_gpll0_gpll1a_sleep, 789 .num_parents = 4, 790 .ops = &clk_rcg2_ops, 791 }, 792 }; 793 794 static struct clk_rcg2 camss_gp1_clk_src = { 795 .cmd_rcgr = 0x55000, 796 .mnd_width = 8, 797 .hid_width = 5, 798 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map, 799 .freq_tbl = ftbl_gcc_camss_gp0_1_clk, 800 .clkr.hw.init = &(struct clk_init_data){ 801 .name = "camss_gp1_clk_src", 802 .parent_names = gcc_xo_gpll0_gpll1a_sleep, 803 .num_parents = 4, 804 .ops = &clk_rcg2_ops, 805 }, 806 }; 807 808 static const struct freq_tbl ftbl_gcc_camss_jpeg0_clk[] = { 809 F(133330000, P_GPLL0, 6, 0, 0), 810 F(266670000, P_GPLL0, 3, 0, 0), 811 F(320000000, P_GPLL0, 2.5, 0, 0), 812 { } 813 }; 814 815 static struct clk_rcg2 jpeg0_clk_src = { 816 .cmd_rcgr = 0x57000, 817 .hid_width = 5, 818 .parent_map = gcc_xo_gpll0_map, 819 .freq_tbl = ftbl_gcc_camss_jpeg0_clk, 820 .clkr.hw.init = &(struct clk_init_data){ 821 .name = "jpeg0_clk_src", 822 .parent_names = gcc_xo_gpll0, 823 .num_parents = 2, 824 .ops = &clk_rcg2_ops, 825 }, 826 }; 827 828 static const struct freq_tbl ftbl_gcc_camss_mclk0_1_clk[] = { 829 F(9600000, P_XO, 2, 0, 0), 830 F(23880000, P_GPLL0, 1, 2, 67), 831 F(66670000, P_GPLL0, 12, 0, 0), 832 { } 833 }; 834 835 static struct clk_rcg2 mclk0_clk_src = { 836 .cmd_rcgr = 0x52000, 837 .mnd_width = 8, 838 .hid_width = 5, 839 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map, 840 .freq_tbl = ftbl_gcc_camss_mclk0_1_clk, 841 .clkr.hw.init = &(struct clk_init_data){ 842 .name = "mclk0_clk_src", 843 .parent_names = gcc_xo_gpll0_gpll1a_sleep, 844 .num_parents = 4, 845 .ops = &clk_rcg2_ops, 846 }, 847 }; 848 849 static struct clk_rcg2 mclk1_clk_src = { 850 .cmd_rcgr = 0x53000, 851 .mnd_width = 8, 852 .hid_width = 5, 853 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map, 854 .freq_tbl = ftbl_gcc_camss_mclk0_1_clk, 855 .clkr.hw.init = &(struct clk_init_data){ 856 .name = "mclk1_clk_src", 857 .parent_names = gcc_xo_gpll0_gpll1a_sleep, 858 .num_parents = 4, 859 .ops = &clk_rcg2_ops, 860 }, 861 }; 862 863 static const struct freq_tbl ftbl_gcc_camss_csi0_1phytimer_clk[] = { 864 F(100000000, P_GPLL0, 8, 0, 0), 865 F(200000000, P_GPLL0, 4, 0, 0), 866 { } 867 }; 868 869 static struct clk_rcg2 csi0phytimer_clk_src = { 870 .cmd_rcgr = 0x4e000, 871 .hid_width = 5, 872 .parent_map = gcc_xo_gpll0_gpll1a_map, 873 .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk, 874 .clkr.hw.init = &(struct clk_init_data){ 875 .name = "csi0phytimer_clk_src", 876 .parent_names = gcc_xo_gpll0_gpll1a, 877 .num_parents = 3, 878 .ops = &clk_rcg2_ops, 879 }, 880 }; 881 882 static struct clk_rcg2 csi1phytimer_clk_src = { 883 .cmd_rcgr = 0x4f000, 884 .hid_width = 5, 885 .parent_map = gcc_xo_gpll0_gpll1a_map, 886 .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk, 887 .clkr.hw.init = &(struct clk_init_data){ 888 .name = "csi1phytimer_clk_src", 889 .parent_names = gcc_xo_gpll0_gpll1a, 890 .num_parents = 3, 891 .ops = &clk_rcg2_ops, 892 }, 893 }; 894 895 static const struct freq_tbl ftbl_gcc_camss_cpp_clk[] = { 896 F(160000000, P_GPLL0, 5, 0, 0), 897 F(320000000, P_GPLL0, 2.5, 0, 0), 898 F(465000000, P_GPLL2, 2, 0, 0), 899 { } 900 }; 901 902 static struct clk_rcg2 cpp_clk_src = { 903 .cmd_rcgr = 0x58018, 904 .hid_width = 5, 905 .parent_map = gcc_xo_gpll0_gpll2_map, 906 .freq_tbl = ftbl_gcc_camss_cpp_clk, 907 .clkr.hw.init = &(struct clk_init_data){ 908 .name = "cpp_clk_src", 909 .parent_names = gcc_xo_gpll0_gpll2, 910 .num_parents = 3, 911 .ops = &clk_rcg2_ops, 912 }, 913 }; 914 915 static const struct freq_tbl ftbl_gcc_crypto_clk[] = { 916 F(50000000, P_GPLL0, 16, 0, 0), 917 F(80000000, P_GPLL0, 10, 0, 0), 918 F(100000000, P_GPLL0, 8, 0, 0), 919 F(160000000, P_GPLL0, 5, 0, 0), 920 { } 921 }; 922 923 static struct clk_rcg2 crypto_clk_src = { 924 .cmd_rcgr = 0x16004, 925 .hid_width = 5, 926 .parent_map = gcc_xo_gpll0_map, 927 .freq_tbl = ftbl_gcc_crypto_clk, 928 .clkr.hw.init = &(struct clk_init_data){ 929 .name = "crypto_clk_src", 930 .parent_names = gcc_xo_gpll0, 931 .num_parents = 2, 932 .ops = &clk_rcg2_ops, 933 }, 934 }; 935 936 static const struct freq_tbl ftbl_gcc_gp1_3_clk[] = { 937 F(19200000, P_XO, 1, 0, 0), 938 { } 939 }; 940 941 static struct clk_rcg2 gp1_clk_src = { 942 .cmd_rcgr = 0x08004, 943 .mnd_width = 8, 944 .hid_width = 5, 945 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map, 946 .freq_tbl = ftbl_gcc_gp1_3_clk, 947 .clkr.hw.init = &(struct clk_init_data){ 948 .name = "gp1_clk_src", 949 .parent_names = gcc_xo_gpll0_gpll1a_sleep, 950 .num_parents = 3, 951 .ops = &clk_rcg2_ops, 952 }, 953 }; 954 955 static struct clk_rcg2 gp2_clk_src = { 956 .cmd_rcgr = 0x09004, 957 .mnd_width = 8, 958 .hid_width = 5, 959 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map, 960 .freq_tbl = ftbl_gcc_gp1_3_clk, 961 .clkr.hw.init = &(struct clk_init_data){ 962 .name = "gp2_clk_src", 963 .parent_names = gcc_xo_gpll0_gpll1a_sleep, 964 .num_parents = 3, 965 .ops = &clk_rcg2_ops, 966 }, 967 }; 968 969 static struct clk_rcg2 gp3_clk_src = { 970 .cmd_rcgr = 0x0a004, 971 .mnd_width = 8, 972 .hid_width = 5, 973 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map, 974 .freq_tbl = ftbl_gcc_gp1_3_clk, 975 .clkr.hw.init = &(struct clk_init_data){ 976 .name = "gp3_clk_src", 977 .parent_names = gcc_xo_gpll0_gpll1a_sleep, 978 .num_parents = 3, 979 .ops = &clk_rcg2_ops, 980 }, 981 }; 982 983 static struct clk_rcg2 byte0_clk_src = { 984 .cmd_rcgr = 0x4d044, 985 .hid_width = 5, 986 .parent_map = gcc_xo_gpll0a_dsibyte_map, 987 .clkr.hw.init = &(struct clk_init_data){ 988 .name = "byte0_clk_src", 989 .parent_names = gcc_xo_gpll0a_dsibyte, 990 .num_parents = 3, 991 .ops = &clk_byte2_ops, 992 .flags = CLK_SET_RATE_PARENT, 993 }, 994 }; 995 996 static const struct freq_tbl ftbl_gcc_mdss_esc0_clk[] = { 997 F(19200000, P_XO, 1, 0, 0), 998 { } 999 }; 1000 1001 static struct clk_rcg2 esc0_clk_src = { 1002 .cmd_rcgr = 0x4d05c, 1003 .hid_width = 5, 1004 .parent_map = gcc_xo_dsibyte_map, 1005 .freq_tbl = ftbl_gcc_mdss_esc0_clk, 1006 .clkr.hw.init = &(struct clk_init_data){ 1007 .name = "esc0_clk_src", 1008 .parent_names = gcc_xo_dsibyte, 1009 .num_parents = 2, 1010 .ops = &clk_rcg2_ops, 1011 }, 1012 }; 1013 1014 static const struct freq_tbl ftbl_gcc_mdss_mdp_clk[] = { 1015 F(50000000, P_GPLL0, 16, 0, 0), 1016 F(80000000, P_GPLL0, 10, 0, 0), 1017 F(100000000, P_GPLL0, 8, 0, 0), 1018 F(160000000, P_GPLL0, 5, 0, 0), 1019 F(177780000, P_GPLL0, 4.5, 0, 0), 1020 F(200000000, P_GPLL0, 4, 0, 0), 1021 F(266670000, P_GPLL0, 3, 0, 0), 1022 F(320000000, P_GPLL0, 2.5, 0, 0), 1023 { } 1024 }; 1025 1026 static struct clk_rcg2 mdp_clk_src = { 1027 .cmd_rcgr = 0x4d014, 1028 .hid_width = 5, 1029 .parent_map = gcc_xo_gpll0_dsiphy_map, 1030 .freq_tbl = ftbl_gcc_mdss_mdp_clk, 1031 .clkr.hw.init = &(struct clk_init_data){ 1032 .name = "mdp_clk_src", 1033 .parent_names = gcc_xo_gpll0_dsiphy, 1034 .num_parents = 3, 1035 .ops = &clk_rcg2_ops, 1036 }, 1037 }; 1038 1039 static struct clk_rcg2 pclk0_clk_src = { 1040 .cmd_rcgr = 0x4d000, 1041 .mnd_width = 8, 1042 .hid_width = 5, 1043 .parent_map = gcc_xo_gpll0a_dsiphy_map, 1044 .clkr.hw.init = &(struct clk_init_data){ 1045 .name = "pclk0_clk_src", 1046 .parent_names = gcc_xo_gpll0a_dsiphy, 1047 .num_parents = 3, 1048 .ops = &clk_pixel_ops, 1049 .flags = CLK_SET_RATE_PARENT, 1050 }, 1051 }; 1052 1053 static const struct freq_tbl ftbl_gcc_mdss_vsync_clk[] = { 1054 F(19200000, P_XO, 1, 0, 0), 1055 { } 1056 }; 1057 1058 static struct clk_rcg2 vsync_clk_src = { 1059 .cmd_rcgr = 0x4d02c, 1060 .hid_width = 5, 1061 .parent_map = gcc_xo_gpll0a_map, 1062 .freq_tbl = ftbl_gcc_mdss_vsync_clk, 1063 .clkr.hw.init = &(struct clk_init_data){ 1064 .name = "vsync_clk_src", 1065 .parent_names = gcc_xo_gpll0a, 1066 .num_parents = 2, 1067 .ops = &clk_rcg2_ops, 1068 }, 1069 }; 1070 1071 static const struct freq_tbl ftbl_gcc_pdm2_clk[] = { 1072 F(64000000, P_GPLL0, 12.5, 0, 0), 1073 { } 1074 }; 1075 1076 static struct clk_rcg2 pdm2_clk_src = { 1077 .cmd_rcgr = 0x44010, 1078 .hid_width = 5, 1079 .parent_map = gcc_xo_gpll0_map, 1080 .freq_tbl = ftbl_gcc_pdm2_clk, 1081 .clkr.hw.init = &(struct clk_init_data){ 1082 .name = "pdm2_clk_src", 1083 .parent_names = gcc_xo_gpll0, 1084 .num_parents = 2, 1085 .ops = &clk_rcg2_ops, 1086 }, 1087 }; 1088 1089 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk[] = { 1090 F(144000, P_XO, 16, 3, 25), 1091 F(400000, P_XO, 12, 1, 4), 1092 F(20000000, P_GPLL0, 10, 1, 4), 1093 F(25000000, P_GPLL0, 16, 1, 2), 1094 F(50000000, P_GPLL0, 16, 0, 0), 1095 F(100000000, P_GPLL0, 8, 0, 0), 1096 F(177770000, P_GPLL0, 4.5, 0, 0), 1097 { } 1098 }; 1099 1100 static struct clk_rcg2 sdcc1_apps_clk_src = { 1101 .cmd_rcgr = 0x42004, 1102 .mnd_width = 8, 1103 .hid_width = 5, 1104 .parent_map = gcc_xo_gpll0_map, 1105 .freq_tbl = ftbl_gcc_sdcc1_apps_clk, 1106 .clkr.hw.init = &(struct clk_init_data){ 1107 .name = "sdcc1_apps_clk_src", 1108 .parent_names = gcc_xo_gpll0, 1109 .num_parents = 2, 1110 .ops = &clk_rcg2_floor_ops, 1111 }, 1112 }; 1113 1114 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk[] = { 1115 F(144000, P_XO, 16, 3, 25), 1116 F(400000, P_XO, 12, 1, 4), 1117 F(20000000, P_GPLL0, 10, 1, 4), 1118 F(25000000, P_GPLL0, 16, 1, 2), 1119 F(50000000, P_GPLL0, 16, 0, 0), 1120 F(100000000, P_GPLL0, 8, 0, 0), 1121 F(200000000, P_GPLL0, 4, 0, 0), 1122 { } 1123 }; 1124 1125 static struct clk_rcg2 sdcc2_apps_clk_src = { 1126 .cmd_rcgr = 0x43004, 1127 .mnd_width = 8, 1128 .hid_width = 5, 1129 .parent_map = gcc_xo_gpll0_map, 1130 .freq_tbl = ftbl_gcc_sdcc2_apps_clk, 1131 .clkr.hw.init = &(struct clk_init_data){ 1132 .name = "sdcc2_apps_clk_src", 1133 .parent_names = gcc_xo_gpll0, 1134 .num_parents = 2, 1135 .ops = &clk_rcg2_floor_ops, 1136 }, 1137 }; 1138 1139 static const struct freq_tbl ftbl_gcc_apss_tcu_clk[] = { 1140 F(155000000, P_GPLL2, 6, 0, 0), 1141 F(310000000, P_GPLL2, 3, 0, 0), 1142 F(400000000, P_GPLL0, 2, 0, 0), 1143 { } 1144 }; 1145 1146 static struct clk_rcg2 apss_tcu_clk_src = { 1147 .cmd_rcgr = 0x1207c, 1148 .hid_width = 5, 1149 .parent_map = gcc_xo_gpll0a_gpll1_gpll2_map, 1150 .freq_tbl = ftbl_gcc_apss_tcu_clk, 1151 .clkr.hw.init = &(struct clk_init_data){ 1152 .name = "apss_tcu_clk_src", 1153 .parent_names = gcc_xo_gpll0a_gpll1_gpll2, 1154 .num_parents = 4, 1155 .ops = &clk_rcg2_ops, 1156 }, 1157 }; 1158 1159 static const struct freq_tbl ftbl_gcc_bimc_gpu_clk[] = { 1160 F(19200000, P_XO, 1, 0, 0), 1161 F(100000000, P_GPLL0, 8, 0, 0), 1162 F(200000000, P_GPLL0, 4, 0, 0), 1163 F(266500000, P_BIMC, 4, 0, 0), 1164 F(400000000, P_GPLL0, 2, 0, 0), 1165 F(533000000, P_BIMC, 2, 0, 0), 1166 { } 1167 }; 1168 1169 static struct clk_rcg2 bimc_gpu_clk_src = { 1170 .cmd_rcgr = 0x31028, 1171 .hid_width = 5, 1172 .parent_map = gcc_xo_gpll0_bimc_map, 1173 .freq_tbl = ftbl_gcc_bimc_gpu_clk, 1174 .clkr.hw.init = &(struct clk_init_data){ 1175 .name = "bimc_gpu_clk_src", 1176 .parent_names = gcc_xo_gpll0_bimc, 1177 .num_parents = 3, 1178 .flags = CLK_GET_RATE_NOCACHE, 1179 .ops = &clk_rcg2_ops, 1180 }, 1181 }; 1182 1183 static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = { 1184 F(80000000, P_GPLL0, 10, 0, 0), 1185 { } 1186 }; 1187 1188 static struct clk_rcg2 usb_hs_system_clk_src = { 1189 .cmd_rcgr = 0x41010, 1190 .hid_width = 5, 1191 .parent_map = gcc_xo_gpll0_map, 1192 .freq_tbl = ftbl_gcc_usb_hs_system_clk, 1193 .clkr.hw.init = &(struct clk_init_data){ 1194 .name = "usb_hs_system_clk_src", 1195 .parent_names = gcc_xo_gpll0, 1196 .num_parents = 2, 1197 .ops = &clk_rcg2_ops, 1198 }, 1199 }; 1200 1201 static const struct freq_tbl ftbl_gcc_ultaudio_ahb_clk[] = { 1202 F(3200000, P_XO, 6, 0, 0), 1203 F(6400000, P_XO, 3, 0, 0), 1204 F(9600000, P_XO, 2, 0, 0), 1205 F(19200000, P_XO, 1, 0, 0), 1206 F(40000000, P_GPLL0, 10, 1, 2), 1207 F(66670000, P_GPLL0, 12, 0, 0), 1208 F(80000000, P_GPLL0, 10, 0, 0), 1209 F(100000000, P_GPLL0, 8, 0, 0), 1210 { } 1211 }; 1212 1213 static struct clk_rcg2 ultaudio_ahbfabric_clk_src = { 1214 .cmd_rcgr = 0x1c010, 1215 .hid_width = 5, 1216 .mnd_width = 8, 1217 .parent_map = gcc_xo_gpll0_gpll1_sleep_map, 1218 .freq_tbl = ftbl_gcc_ultaudio_ahb_clk, 1219 .clkr.hw.init = &(struct clk_init_data){ 1220 .name = "ultaudio_ahbfabric_clk_src", 1221 .parent_names = gcc_xo_gpll0_gpll1_sleep, 1222 .num_parents = 4, 1223 .ops = &clk_rcg2_ops, 1224 }, 1225 }; 1226 1227 static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_clk = { 1228 .halt_reg = 0x1c028, 1229 .clkr = { 1230 .enable_reg = 0x1c028, 1231 .enable_mask = BIT(0), 1232 .hw.init = &(struct clk_init_data){ 1233 .name = "gcc_ultaudio_ahbfabric_ixfabric_clk", 1234 .parent_names = (const char *[]){ 1235 "ultaudio_ahbfabric_clk_src", 1236 }, 1237 .num_parents = 1, 1238 .flags = CLK_SET_RATE_PARENT, 1239 .ops = &clk_branch2_ops, 1240 }, 1241 }, 1242 }; 1243 1244 static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_lpm_clk = { 1245 .halt_reg = 0x1c024, 1246 .clkr = { 1247 .enable_reg = 0x1c024, 1248 .enable_mask = BIT(0), 1249 .hw.init = &(struct clk_init_data){ 1250 .name = "gcc_ultaudio_ahbfabric_ixfabric_lpm_clk", 1251 .parent_names = (const char *[]){ 1252 "ultaudio_ahbfabric_clk_src", 1253 }, 1254 .num_parents = 1, 1255 .flags = CLK_SET_RATE_PARENT, 1256 .ops = &clk_branch2_ops, 1257 }, 1258 }, 1259 }; 1260 1261 static const struct freq_tbl ftbl_gcc_ultaudio_lpaif_i2s_clk[] = { 1262 F(256000, P_XO, 5, 1, 15), 1263 F(512000, P_XO, 5, 2, 15), 1264 F(705600, P_GPLL1, 16, 1, 80), 1265 F(768000, P_XO, 5, 1, 5), 1266 F(800000, P_XO, 5, 5, 24), 1267 F(1024000, P_GPLL1, 14, 1, 63), 1268 F(1152000, P_XO, 1, 3, 50), 1269 F(1411200, P_GPLL1, 16, 1, 40), 1270 F(1536000, P_XO, 1, 2, 25), 1271 F(1600000, P_XO, 12, 0, 0), 1272 F(2048000, P_GPLL1, 9, 1, 49), 1273 F(2400000, P_XO, 8, 0, 0), 1274 F(2822400, P_GPLL1, 16, 1, 20), 1275 F(3072000, P_GPLL1, 14, 1, 21), 1276 F(4096000, P_GPLL1, 9, 2, 49), 1277 F(4800000, P_XO, 4, 0, 0), 1278 F(5644800, P_GPLL1, 16, 1, 10), 1279 F(6144000, P_GPLL1, 7, 1, 21), 1280 F(8192000, P_GPLL1, 9, 4, 49), 1281 F(9600000, P_XO, 2, 0, 0), 1282 F(11289600, P_GPLL1, 16, 1, 5), 1283 F(12288000, P_GPLL1, 7, 2, 21), 1284 { } 1285 }; 1286 1287 static struct clk_rcg2 ultaudio_lpaif_pri_i2s_clk_src = { 1288 .cmd_rcgr = 0x1c054, 1289 .hid_width = 5, 1290 .mnd_width = 8, 1291 .parent_map = gcc_xo_gpll1_epi2s_emclk_sleep_map, 1292 .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk, 1293 .clkr.hw.init = &(struct clk_init_data){ 1294 .name = "ultaudio_lpaif_pri_i2s_clk_src", 1295 .parent_names = gcc_xo_gpll1_epi2s_emclk_sleep, 1296 .num_parents = 5, 1297 .ops = &clk_rcg2_ops, 1298 }, 1299 }; 1300 1301 static struct clk_branch gcc_ultaudio_lpaif_pri_i2s_clk = { 1302 .halt_reg = 0x1c068, 1303 .clkr = { 1304 .enable_reg = 0x1c068, 1305 .enable_mask = BIT(0), 1306 .hw.init = &(struct clk_init_data){ 1307 .name = "gcc_ultaudio_lpaif_pri_i2s_clk", 1308 .parent_names = (const char *[]){ 1309 "ultaudio_lpaif_pri_i2s_clk_src", 1310 }, 1311 .num_parents = 1, 1312 .flags = CLK_SET_RATE_PARENT, 1313 .ops = &clk_branch2_ops, 1314 }, 1315 }, 1316 }; 1317 1318 static struct clk_rcg2 ultaudio_lpaif_sec_i2s_clk_src = { 1319 .cmd_rcgr = 0x1c06c, 1320 .hid_width = 5, 1321 .mnd_width = 8, 1322 .parent_map = gcc_xo_gpll1_esi2s_emclk_sleep_map, 1323 .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk, 1324 .clkr.hw.init = &(struct clk_init_data){ 1325 .name = "ultaudio_lpaif_sec_i2s_clk_src", 1326 .parent_names = gcc_xo_gpll1_esi2s_emclk_sleep, 1327 .num_parents = 5, 1328 .ops = &clk_rcg2_ops, 1329 }, 1330 }; 1331 1332 static struct clk_branch gcc_ultaudio_lpaif_sec_i2s_clk = { 1333 .halt_reg = 0x1c080, 1334 .clkr = { 1335 .enable_reg = 0x1c080, 1336 .enable_mask = BIT(0), 1337 .hw.init = &(struct clk_init_data){ 1338 .name = "gcc_ultaudio_lpaif_sec_i2s_clk", 1339 .parent_names = (const char *[]){ 1340 "ultaudio_lpaif_sec_i2s_clk_src", 1341 }, 1342 .num_parents = 1, 1343 .flags = CLK_SET_RATE_PARENT, 1344 .ops = &clk_branch2_ops, 1345 }, 1346 }, 1347 }; 1348 1349 static struct clk_rcg2 ultaudio_lpaif_aux_i2s_clk_src = { 1350 .cmd_rcgr = 0x1c084, 1351 .hid_width = 5, 1352 .mnd_width = 8, 1353 .parent_map = gcc_xo_gpll1_emclk_sleep_map, 1354 .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk, 1355 .clkr.hw.init = &(struct clk_init_data){ 1356 .name = "ultaudio_lpaif_aux_i2s_clk_src", 1357 .parent_names = gcc_xo_gpll1_esi2s_emclk_sleep, 1358 .num_parents = 5, 1359 .ops = &clk_rcg2_ops, 1360 }, 1361 }; 1362 1363 static struct clk_branch gcc_ultaudio_lpaif_aux_i2s_clk = { 1364 .halt_reg = 0x1c098, 1365 .clkr = { 1366 .enable_reg = 0x1c098, 1367 .enable_mask = BIT(0), 1368 .hw.init = &(struct clk_init_data){ 1369 .name = "gcc_ultaudio_lpaif_aux_i2s_clk", 1370 .parent_names = (const char *[]){ 1371 "ultaudio_lpaif_aux_i2s_clk_src", 1372 }, 1373 .num_parents = 1, 1374 .flags = CLK_SET_RATE_PARENT, 1375 .ops = &clk_branch2_ops, 1376 }, 1377 }, 1378 }; 1379 1380 static const struct freq_tbl ftbl_gcc_ultaudio_xo_clk[] = { 1381 F(19200000, P_XO, 1, 0, 0), 1382 { } 1383 }; 1384 1385 static struct clk_rcg2 ultaudio_xo_clk_src = { 1386 .cmd_rcgr = 0x1c034, 1387 .hid_width = 5, 1388 .parent_map = gcc_xo_sleep_map, 1389 .freq_tbl = ftbl_gcc_ultaudio_xo_clk, 1390 .clkr.hw.init = &(struct clk_init_data){ 1391 .name = "ultaudio_xo_clk_src", 1392 .parent_names = gcc_xo_sleep, 1393 .num_parents = 2, 1394 .ops = &clk_rcg2_ops, 1395 }, 1396 }; 1397 1398 static struct clk_branch gcc_ultaudio_avsync_xo_clk = { 1399 .halt_reg = 0x1c04c, 1400 .clkr = { 1401 .enable_reg = 0x1c04c, 1402 .enable_mask = BIT(0), 1403 .hw.init = &(struct clk_init_data){ 1404 .name = "gcc_ultaudio_avsync_xo_clk", 1405 .parent_names = (const char *[]){ 1406 "ultaudio_xo_clk_src", 1407 }, 1408 .num_parents = 1, 1409 .flags = CLK_SET_RATE_PARENT, 1410 .ops = &clk_branch2_ops, 1411 }, 1412 }, 1413 }; 1414 1415 static struct clk_branch gcc_ultaudio_stc_xo_clk = { 1416 .halt_reg = 0x1c050, 1417 .clkr = { 1418 .enable_reg = 0x1c050, 1419 .enable_mask = BIT(0), 1420 .hw.init = &(struct clk_init_data){ 1421 .name = "gcc_ultaudio_stc_xo_clk", 1422 .parent_names = (const char *[]){ 1423 "ultaudio_xo_clk_src", 1424 }, 1425 .num_parents = 1, 1426 .flags = CLK_SET_RATE_PARENT, 1427 .ops = &clk_branch2_ops, 1428 }, 1429 }, 1430 }; 1431 1432 static const struct freq_tbl ftbl_codec_clk[] = { 1433 F(9600000, P_XO, 2, 0, 0), 1434 F(19200000, P_XO, 1, 0, 0), 1435 F(11289600, P_EXT_MCLK, 1, 0, 0), 1436 { } 1437 }; 1438 1439 static struct clk_rcg2 codec_digcodec_clk_src = { 1440 .cmd_rcgr = 0x1c09c, 1441 .hid_width = 5, 1442 .parent_map = gcc_xo_gpll1_emclk_sleep_map, 1443 .freq_tbl = ftbl_codec_clk, 1444 .clkr.hw.init = &(struct clk_init_data){ 1445 .name = "codec_digcodec_clk_src", 1446 .parent_names = gcc_xo_gpll1_emclk_sleep, 1447 .num_parents = 4, 1448 .ops = &clk_rcg2_ops, 1449 }, 1450 }; 1451 1452 static struct clk_branch gcc_codec_digcodec_clk = { 1453 .halt_reg = 0x1c0b0, 1454 .clkr = { 1455 .enable_reg = 0x1c0b0, 1456 .enable_mask = BIT(0), 1457 .hw.init = &(struct clk_init_data){ 1458 .name = "gcc_ultaudio_codec_digcodec_clk", 1459 .parent_names = (const char *[]){ 1460 "codec_digcodec_clk_src", 1461 }, 1462 .num_parents = 1, 1463 .flags = CLK_SET_RATE_PARENT, 1464 .ops = &clk_branch2_ops, 1465 }, 1466 }, 1467 }; 1468 1469 static struct clk_branch gcc_ultaudio_pcnoc_mport_clk = { 1470 .halt_reg = 0x1c000, 1471 .clkr = { 1472 .enable_reg = 0x1c000, 1473 .enable_mask = BIT(0), 1474 .hw.init = &(struct clk_init_data){ 1475 .name = "gcc_ultaudio_pcnoc_mport_clk", 1476 .parent_names = (const char *[]){ 1477 "pcnoc_bfdcd_clk_src", 1478 }, 1479 .num_parents = 1, 1480 .ops = &clk_branch2_ops, 1481 }, 1482 }, 1483 }; 1484 1485 static struct clk_branch gcc_ultaudio_pcnoc_sway_clk = { 1486 .halt_reg = 0x1c004, 1487 .clkr = { 1488 .enable_reg = 0x1c004, 1489 .enable_mask = BIT(0), 1490 .hw.init = &(struct clk_init_data){ 1491 .name = "gcc_ultaudio_pcnoc_sway_clk", 1492 .parent_names = (const char *[]){ 1493 "pcnoc_bfdcd_clk_src", 1494 }, 1495 .num_parents = 1, 1496 .ops = &clk_branch2_ops, 1497 }, 1498 }, 1499 }; 1500 1501 static const struct freq_tbl ftbl_gcc_venus0_vcodec0_clk[] = { 1502 F(100000000, P_GPLL0, 8, 0, 0), 1503 F(160000000, P_GPLL0, 5, 0, 0), 1504 F(228570000, P_GPLL0, 3.5, 0, 0), 1505 { } 1506 }; 1507 1508 static struct clk_rcg2 vcodec0_clk_src = { 1509 .cmd_rcgr = 0x4C000, 1510 .mnd_width = 8, 1511 .hid_width = 5, 1512 .parent_map = gcc_xo_gpll0_map, 1513 .freq_tbl = ftbl_gcc_venus0_vcodec0_clk, 1514 .clkr.hw.init = &(struct clk_init_data){ 1515 .name = "vcodec0_clk_src", 1516 .parent_names = gcc_xo_gpll0, 1517 .num_parents = 2, 1518 .ops = &clk_rcg2_ops, 1519 }, 1520 }; 1521 1522 static struct clk_branch gcc_blsp1_ahb_clk = { 1523 .halt_reg = 0x01008, 1524 .halt_check = BRANCH_HALT_VOTED, 1525 .clkr = { 1526 .enable_reg = 0x45004, 1527 .enable_mask = BIT(10), 1528 .hw.init = &(struct clk_init_data){ 1529 .name = "gcc_blsp1_ahb_clk", 1530 .parent_names = (const char *[]){ 1531 "pcnoc_bfdcd_clk_src", 1532 }, 1533 .num_parents = 1, 1534 .ops = &clk_branch2_ops, 1535 }, 1536 }, 1537 }; 1538 1539 static struct clk_branch gcc_blsp1_sleep_clk = { 1540 .halt_reg = 0x01004, 1541 .clkr = { 1542 .enable_reg = 0x01004, 1543 .enable_mask = BIT(0), 1544 .hw.init = &(struct clk_init_data){ 1545 .name = "gcc_blsp1_sleep_clk", 1546 .parent_names = (const char *[]){ 1547 "sleep_clk_src", 1548 }, 1549 .num_parents = 1, 1550 .flags = CLK_SET_RATE_PARENT, 1551 .ops = &clk_branch2_ops, 1552 }, 1553 }, 1554 }; 1555 1556 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { 1557 .halt_reg = 0x02008, 1558 .clkr = { 1559 .enable_reg = 0x02008, 1560 .enable_mask = BIT(0), 1561 .hw.init = &(struct clk_init_data){ 1562 .name = "gcc_blsp1_qup1_i2c_apps_clk", 1563 .parent_names = (const char *[]){ 1564 "blsp1_qup1_i2c_apps_clk_src", 1565 }, 1566 .num_parents = 1, 1567 .flags = CLK_SET_RATE_PARENT, 1568 .ops = &clk_branch2_ops, 1569 }, 1570 }, 1571 }; 1572 1573 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { 1574 .halt_reg = 0x02004, 1575 .clkr = { 1576 .enable_reg = 0x02004, 1577 .enable_mask = BIT(0), 1578 .hw.init = &(struct clk_init_data){ 1579 .name = "gcc_blsp1_qup1_spi_apps_clk", 1580 .parent_names = (const char *[]){ 1581 "blsp1_qup1_spi_apps_clk_src", 1582 }, 1583 .num_parents = 1, 1584 .flags = CLK_SET_RATE_PARENT, 1585 .ops = &clk_branch2_ops, 1586 }, 1587 }, 1588 }; 1589 1590 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { 1591 .halt_reg = 0x03010, 1592 .clkr = { 1593 .enable_reg = 0x03010, 1594 .enable_mask = BIT(0), 1595 .hw.init = &(struct clk_init_data){ 1596 .name = "gcc_blsp1_qup2_i2c_apps_clk", 1597 .parent_names = (const char *[]){ 1598 "blsp1_qup2_i2c_apps_clk_src", 1599 }, 1600 .num_parents = 1, 1601 .flags = CLK_SET_RATE_PARENT, 1602 .ops = &clk_branch2_ops, 1603 }, 1604 }, 1605 }; 1606 1607 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { 1608 .halt_reg = 0x0300c, 1609 .clkr = { 1610 .enable_reg = 0x0300c, 1611 .enable_mask = BIT(0), 1612 .hw.init = &(struct clk_init_data){ 1613 .name = "gcc_blsp1_qup2_spi_apps_clk", 1614 .parent_names = (const char *[]){ 1615 "blsp1_qup2_spi_apps_clk_src", 1616 }, 1617 .num_parents = 1, 1618 .flags = CLK_SET_RATE_PARENT, 1619 .ops = &clk_branch2_ops, 1620 }, 1621 }, 1622 }; 1623 1624 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = { 1625 .halt_reg = 0x04020, 1626 .clkr = { 1627 .enable_reg = 0x04020, 1628 .enable_mask = BIT(0), 1629 .hw.init = &(struct clk_init_data){ 1630 .name = "gcc_blsp1_qup3_i2c_apps_clk", 1631 .parent_names = (const char *[]){ 1632 "blsp1_qup3_i2c_apps_clk_src", 1633 }, 1634 .num_parents = 1, 1635 .flags = CLK_SET_RATE_PARENT, 1636 .ops = &clk_branch2_ops, 1637 }, 1638 }, 1639 }; 1640 1641 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = { 1642 .halt_reg = 0x0401c, 1643 .clkr = { 1644 .enable_reg = 0x0401c, 1645 .enable_mask = BIT(0), 1646 .hw.init = &(struct clk_init_data){ 1647 .name = "gcc_blsp1_qup3_spi_apps_clk", 1648 .parent_names = (const char *[]){ 1649 "blsp1_qup3_spi_apps_clk_src", 1650 }, 1651 .num_parents = 1, 1652 .flags = CLK_SET_RATE_PARENT, 1653 .ops = &clk_branch2_ops, 1654 }, 1655 }, 1656 }; 1657 1658 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = { 1659 .halt_reg = 0x05020, 1660 .clkr = { 1661 .enable_reg = 0x05020, 1662 .enable_mask = BIT(0), 1663 .hw.init = &(struct clk_init_data){ 1664 .name = "gcc_blsp1_qup4_i2c_apps_clk", 1665 .parent_names = (const char *[]){ 1666 "blsp1_qup4_i2c_apps_clk_src", 1667 }, 1668 .num_parents = 1, 1669 .flags = CLK_SET_RATE_PARENT, 1670 .ops = &clk_branch2_ops, 1671 }, 1672 }, 1673 }; 1674 1675 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = { 1676 .halt_reg = 0x0501c, 1677 .clkr = { 1678 .enable_reg = 0x0501c, 1679 .enable_mask = BIT(0), 1680 .hw.init = &(struct clk_init_data){ 1681 .name = "gcc_blsp1_qup4_spi_apps_clk", 1682 .parent_names = (const char *[]){ 1683 "blsp1_qup4_spi_apps_clk_src", 1684 }, 1685 .num_parents = 1, 1686 .flags = CLK_SET_RATE_PARENT, 1687 .ops = &clk_branch2_ops, 1688 }, 1689 }, 1690 }; 1691 1692 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = { 1693 .halt_reg = 0x06020, 1694 .clkr = { 1695 .enable_reg = 0x06020, 1696 .enable_mask = BIT(0), 1697 .hw.init = &(struct clk_init_data){ 1698 .name = "gcc_blsp1_qup5_i2c_apps_clk", 1699 .parent_names = (const char *[]){ 1700 "blsp1_qup5_i2c_apps_clk_src", 1701 }, 1702 .num_parents = 1, 1703 .flags = CLK_SET_RATE_PARENT, 1704 .ops = &clk_branch2_ops, 1705 }, 1706 }, 1707 }; 1708 1709 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = { 1710 .halt_reg = 0x0601c, 1711 .clkr = { 1712 .enable_reg = 0x0601c, 1713 .enable_mask = BIT(0), 1714 .hw.init = &(struct clk_init_data){ 1715 .name = "gcc_blsp1_qup5_spi_apps_clk", 1716 .parent_names = (const char *[]){ 1717 "blsp1_qup5_spi_apps_clk_src", 1718 }, 1719 .num_parents = 1, 1720 .flags = CLK_SET_RATE_PARENT, 1721 .ops = &clk_branch2_ops, 1722 }, 1723 }, 1724 }; 1725 1726 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = { 1727 .halt_reg = 0x07020, 1728 .clkr = { 1729 .enable_reg = 0x07020, 1730 .enable_mask = BIT(0), 1731 .hw.init = &(struct clk_init_data){ 1732 .name = "gcc_blsp1_qup6_i2c_apps_clk", 1733 .parent_names = (const char *[]){ 1734 "blsp1_qup6_i2c_apps_clk_src", 1735 }, 1736 .num_parents = 1, 1737 .flags = CLK_SET_RATE_PARENT, 1738 .ops = &clk_branch2_ops, 1739 }, 1740 }, 1741 }; 1742 1743 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = { 1744 .halt_reg = 0x0701c, 1745 .clkr = { 1746 .enable_reg = 0x0701c, 1747 .enable_mask = BIT(0), 1748 .hw.init = &(struct clk_init_data){ 1749 .name = "gcc_blsp1_qup6_spi_apps_clk", 1750 .parent_names = (const char *[]){ 1751 "blsp1_qup6_spi_apps_clk_src", 1752 }, 1753 .num_parents = 1, 1754 .flags = CLK_SET_RATE_PARENT, 1755 .ops = &clk_branch2_ops, 1756 }, 1757 }, 1758 }; 1759 1760 static struct clk_branch gcc_blsp1_uart1_apps_clk = { 1761 .halt_reg = 0x0203c, 1762 .clkr = { 1763 .enable_reg = 0x0203c, 1764 .enable_mask = BIT(0), 1765 .hw.init = &(struct clk_init_data){ 1766 .name = "gcc_blsp1_uart1_apps_clk", 1767 .parent_names = (const char *[]){ 1768 "blsp1_uart1_apps_clk_src", 1769 }, 1770 .num_parents = 1, 1771 .flags = CLK_SET_RATE_PARENT, 1772 .ops = &clk_branch2_ops, 1773 }, 1774 }, 1775 }; 1776 1777 static struct clk_branch gcc_blsp1_uart2_apps_clk = { 1778 .halt_reg = 0x0302c, 1779 .clkr = { 1780 .enable_reg = 0x0302c, 1781 .enable_mask = BIT(0), 1782 .hw.init = &(struct clk_init_data){ 1783 .name = "gcc_blsp1_uart2_apps_clk", 1784 .parent_names = (const char *[]){ 1785 "blsp1_uart2_apps_clk_src", 1786 }, 1787 .num_parents = 1, 1788 .flags = CLK_SET_RATE_PARENT, 1789 .ops = &clk_branch2_ops, 1790 }, 1791 }, 1792 }; 1793 1794 static struct clk_branch gcc_boot_rom_ahb_clk = { 1795 .halt_reg = 0x1300c, 1796 .halt_check = BRANCH_HALT_VOTED, 1797 .clkr = { 1798 .enable_reg = 0x45004, 1799 .enable_mask = BIT(7), 1800 .hw.init = &(struct clk_init_data){ 1801 .name = "gcc_boot_rom_ahb_clk", 1802 .parent_names = (const char *[]){ 1803 "pcnoc_bfdcd_clk_src", 1804 }, 1805 .num_parents = 1, 1806 .ops = &clk_branch2_ops, 1807 }, 1808 }, 1809 }; 1810 1811 static struct clk_branch gcc_camss_cci_ahb_clk = { 1812 .halt_reg = 0x5101c, 1813 .clkr = { 1814 .enable_reg = 0x5101c, 1815 .enable_mask = BIT(0), 1816 .hw.init = &(struct clk_init_data){ 1817 .name = "gcc_camss_cci_ahb_clk", 1818 .parent_names = (const char *[]){ 1819 "camss_ahb_clk_src", 1820 }, 1821 .num_parents = 1, 1822 .flags = CLK_SET_RATE_PARENT, 1823 .ops = &clk_branch2_ops, 1824 }, 1825 }, 1826 }; 1827 1828 static struct clk_branch gcc_camss_cci_clk = { 1829 .halt_reg = 0x51018, 1830 .clkr = { 1831 .enable_reg = 0x51018, 1832 .enable_mask = BIT(0), 1833 .hw.init = &(struct clk_init_data){ 1834 .name = "gcc_camss_cci_clk", 1835 .parent_names = (const char *[]){ 1836 "cci_clk_src", 1837 }, 1838 .num_parents = 1, 1839 .flags = CLK_SET_RATE_PARENT, 1840 .ops = &clk_branch2_ops, 1841 }, 1842 }, 1843 }; 1844 1845 static struct clk_branch gcc_camss_csi0_ahb_clk = { 1846 .halt_reg = 0x4e040, 1847 .clkr = { 1848 .enable_reg = 0x4e040, 1849 .enable_mask = BIT(0), 1850 .hw.init = &(struct clk_init_data){ 1851 .name = "gcc_camss_csi0_ahb_clk", 1852 .parent_names = (const char *[]){ 1853 "camss_ahb_clk_src", 1854 }, 1855 .num_parents = 1, 1856 .flags = CLK_SET_RATE_PARENT, 1857 .ops = &clk_branch2_ops, 1858 }, 1859 }, 1860 }; 1861 1862 static struct clk_branch gcc_camss_csi0_clk = { 1863 .halt_reg = 0x4e03c, 1864 .clkr = { 1865 .enable_reg = 0x4e03c, 1866 .enable_mask = BIT(0), 1867 .hw.init = &(struct clk_init_data){ 1868 .name = "gcc_camss_csi0_clk", 1869 .parent_names = (const char *[]){ 1870 "csi0_clk_src", 1871 }, 1872 .num_parents = 1, 1873 .flags = CLK_SET_RATE_PARENT, 1874 .ops = &clk_branch2_ops, 1875 }, 1876 }, 1877 }; 1878 1879 static struct clk_branch gcc_camss_csi0phy_clk = { 1880 .halt_reg = 0x4e048, 1881 .clkr = { 1882 .enable_reg = 0x4e048, 1883 .enable_mask = BIT(0), 1884 .hw.init = &(struct clk_init_data){ 1885 .name = "gcc_camss_csi0phy_clk", 1886 .parent_names = (const char *[]){ 1887 "csi0_clk_src", 1888 }, 1889 .num_parents = 1, 1890 .flags = CLK_SET_RATE_PARENT, 1891 .ops = &clk_branch2_ops, 1892 }, 1893 }, 1894 }; 1895 1896 static struct clk_branch gcc_camss_csi0pix_clk = { 1897 .halt_reg = 0x4e058, 1898 .clkr = { 1899 .enable_reg = 0x4e058, 1900 .enable_mask = BIT(0), 1901 .hw.init = &(struct clk_init_data){ 1902 .name = "gcc_camss_csi0pix_clk", 1903 .parent_names = (const char *[]){ 1904 "csi0_clk_src", 1905 }, 1906 .num_parents = 1, 1907 .flags = CLK_SET_RATE_PARENT, 1908 .ops = &clk_branch2_ops, 1909 }, 1910 }, 1911 }; 1912 1913 static struct clk_branch gcc_camss_csi0rdi_clk = { 1914 .halt_reg = 0x4e050, 1915 .clkr = { 1916 .enable_reg = 0x4e050, 1917 .enable_mask = BIT(0), 1918 .hw.init = &(struct clk_init_data){ 1919 .name = "gcc_camss_csi0rdi_clk", 1920 .parent_names = (const char *[]){ 1921 "csi0_clk_src", 1922 }, 1923 .num_parents = 1, 1924 .flags = CLK_SET_RATE_PARENT, 1925 .ops = &clk_branch2_ops, 1926 }, 1927 }, 1928 }; 1929 1930 static struct clk_branch gcc_camss_csi1_ahb_clk = { 1931 .halt_reg = 0x4f040, 1932 .clkr = { 1933 .enable_reg = 0x4f040, 1934 .enable_mask = BIT(0), 1935 .hw.init = &(struct clk_init_data){ 1936 .name = "gcc_camss_csi1_ahb_clk", 1937 .parent_names = (const char *[]){ 1938 "camss_ahb_clk_src", 1939 }, 1940 .num_parents = 1, 1941 .flags = CLK_SET_RATE_PARENT, 1942 .ops = &clk_branch2_ops, 1943 }, 1944 }, 1945 }; 1946 1947 static struct clk_branch gcc_camss_csi1_clk = { 1948 .halt_reg = 0x4f03c, 1949 .clkr = { 1950 .enable_reg = 0x4f03c, 1951 .enable_mask = BIT(0), 1952 .hw.init = &(struct clk_init_data){ 1953 .name = "gcc_camss_csi1_clk", 1954 .parent_names = (const char *[]){ 1955 "csi1_clk_src", 1956 }, 1957 .num_parents = 1, 1958 .flags = CLK_SET_RATE_PARENT, 1959 .ops = &clk_branch2_ops, 1960 }, 1961 }, 1962 }; 1963 1964 static struct clk_branch gcc_camss_csi1phy_clk = { 1965 .halt_reg = 0x4f048, 1966 .clkr = { 1967 .enable_reg = 0x4f048, 1968 .enable_mask = BIT(0), 1969 .hw.init = &(struct clk_init_data){ 1970 .name = "gcc_camss_csi1phy_clk", 1971 .parent_names = (const char *[]){ 1972 "csi1_clk_src", 1973 }, 1974 .num_parents = 1, 1975 .flags = CLK_SET_RATE_PARENT, 1976 .ops = &clk_branch2_ops, 1977 }, 1978 }, 1979 }; 1980 1981 static struct clk_branch gcc_camss_csi1pix_clk = { 1982 .halt_reg = 0x4f058, 1983 .clkr = { 1984 .enable_reg = 0x4f058, 1985 .enable_mask = BIT(0), 1986 .hw.init = &(struct clk_init_data){ 1987 .name = "gcc_camss_csi1pix_clk", 1988 .parent_names = (const char *[]){ 1989 "csi1_clk_src", 1990 }, 1991 .num_parents = 1, 1992 .flags = CLK_SET_RATE_PARENT, 1993 .ops = &clk_branch2_ops, 1994 }, 1995 }, 1996 }; 1997 1998 static struct clk_branch gcc_camss_csi1rdi_clk = { 1999 .halt_reg = 0x4f050, 2000 .clkr = { 2001 .enable_reg = 0x4f050, 2002 .enable_mask = BIT(0), 2003 .hw.init = &(struct clk_init_data){ 2004 .name = "gcc_camss_csi1rdi_clk", 2005 .parent_names = (const char *[]){ 2006 "csi1_clk_src", 2007 }, 2008 .num_parents = 1, 2009 .flags = CLK_SET_RATE_PARENT, 2010 .ops = &clk_branch2_ops, 2011 }, 2012 }, 2013 }; 2014 2015 static struct clk_branch gcc_camss_csi_vfe0_clk = { 2016 .halt_reg = 0x58050, 2017 .clkr = { 2018 .enable_reg = 0x58050, 2019 .enable_mask = BIT(0), 2020 .hw.init = &(struct clk_init_data){ 2021 .name = "gcc_camss_csi_vfe0_clk", 2022 .parent_names = (const char *[]){ 2023 "vfe0_clk_src", 2024 }, 2025 .num_parents = 1, 2026 .flags = CLK_SET_RATE_PARENT, 2027 .ops = &clk_branch2_ops, 2028 }, 2029 }, 2030 }; 2031 2032 static struct clk_branch gcc_camss_gp0_clk = { 2033 .halt_reg = 0x54018, 2034 .clkr = { 2035 .enable_reg = 0x54018, 2036 .enable_mask = BIT(0), 2037 .hw.init = &(struct clk_init_data){ 2038 .name = "gcc_camss_gp0_clk", 2039 .parent_names = (const char *[]){ 2040 "camss_gp0_clk_src", 2041 }, 2042 .num_parents = 1, 2043 .flags = CLK_SET_RATE_PARENT, 2044 .ops = &clk_branch2_ops, 2045 }, 2046 }, 2047 }; 2048 2049 static struct clk_branch gcc_camss_gp1_clk = { 2050 .halt_reg = 0x55018, 2051 .clkr = { 2052 .enable_reg = 0x55018, 2053 .enable_mask = BIT(0), 2054 .hw.init = &(struct clk_init_data){ 2055 .name = "gcc_camss_gp1_clk", 2056 .parent_names = (const char *[]){ 2057 "camss_gp1_clk_src", 2058 }, 2059 .num_parents = 1, 2060 .flags = CLK_SET_RATE_PARENT, 2061 .ops = &clk_branch2_ops, 2062 }, 2063 }, 2064 }; 2065 2066 static struct clk_branch gcc_camss_ispif_ahb_clk = { 2067 .halt_reg = 0x50004, 2068 .clkr = { 2069 .enable_reg = 0x50004, 2070 .enable_mask = BIT(0), 2071 .hw.init = &(struct clk_init_data){ 2072 .name = "gcc_camss_ispif_ahb_clk", 2073 .parent_names = (const char *[]){ 2074 "camss_ahb_clk_src", 2075 }, 2076 .num_parents = 1, 2077 .flags = CLK_SET_RATE_PARENT, 2078 .ops = &clk_branch2_ops, 2079 }, 2080 }, 2081 }; 2082 2083 static struct clk_branch gcc_camss_jpeg0_clk = { 2084 .halt_reg = 0x57020, 2085 .clkr = { 2086 .enable_reg = 0x57020, 2087 .enable_mask = BIT(0), 2088 .hw.init = &(struct clk_init_data){ 2089 .name = "gcc_camss_jpeg0_clk", 2090 .parent_names = (const char *[]){ 2091 "jpeg0_clk_src", 2092 }, 2093 .num_parents = 1, 2094 .flags = CLK_SET_RATE_PARENT, 2095 .ops = &clk_branch2_ops, 2096 }, 2097 }, 2098 }; 2099 2100 static struct clk_branch gcc_camss_jpeg_ahb_clk = { 2101 .halt_reg = 0x57024, 2102 .clkr = { 2103 .enable_reg = 0x57024, 2104 .enable_mask = BIT(0), 2105 .hw.init = &(struct clk_init_data){ 2106 .name = "gcc_camss_jpeg_ahb_clk", 2107 .parent_names = (const char *[]){ 2108 "camss_ahb_clk_src", 2109 }, 2110 .num_parents = 1, 2111 .flags = CLK_SET_RATE_PARENT, 2112 .ops = &clk_branch2_ops, 2113 }, 2114 }, 2115 }; 2116 2117 static struct clk_branch gcc_camss_jpeg_axi_clk = { 2118 .halt_reg = 0x57028, 2119 .clkr = { 2120 .enable_reg = 0x57028, 2121 .enable_mask = BIT(0), 2122 .hw.init = &(struct clk_init_data){ 2123 .name = "gcc_camss_jpeg_axi_clk", 2124 .parent_names = (const char *[]){ 2125 "system_noc_bfdcd_clk_src", 2126 }, 2127 .num_parents = 1, 2128 .flags = CLK_SET_RATE_PARENT, 2129 .ops = &clk_branch2_ops, 2130 }, 2131 }, 2132 }; 2133 2134 static struct clk_branch gcc_camss_mclk0_clk = { 2135 .halt_reg = 0x52018, 2136 .clkr = { 2137 .enable_reg = 0x52018, 2138 .enable_mask = BIT(0), 2139 .hw.init = &(struct clk_init_data){ 2140 .name = "gcc_camss_mclk0_clk", 2141 .parent_names = (const char *[]){ 2142 "mclk0_clk_src", 2143 }, 2144 .num_parents = 1, 2145 .flags = CLK_SET_RATE_PARENT, 2146 .ops = &clk_branch2_ops, 2147 }, 2148 }, 2149 }; 2150 2151 static struct clk_branch gcc_camss_mclk1_clk = { 2152 .halt_reg = 0x53018, 2153 .clkr = { 2154 .enable_reg = 0x53018, 2155 .enable_mask = BIT(0), 2156 .hw.init = &(struct clk_init_data){ 2157 .name = "gcc_camss_mclk1_clk", 2158 .parent_names = (const char *[]){ 2159 "mclk1_clk_src", 2160 }, 2161 .num_parents = 1, 2162 .flags = CLK_SET_RATE_PARENT, 2163 .ops = &clk_branch2_ops, 2164 }, 2165 }, 2166 }; 2167 2168 static struct clk_branch gcc_camss_micro_ahb_clk = { 2169 .halt_reg = 0x5600c, 2170 .clkr = { 2171 .enable_reg = 0x5600c, 2172 .enable_mask = BIT(0), 2173 .hw.init = &(struct clk_init_data){ 2174 .name = "gcc_camss_micro_ahb_clk", 2175 .parent_names = (const char *[]){ 2176 "camss_ahb_clk_src", 2177 }, 2178 .num_parents = 1, 2179 .flags = CLK_SET_RATE_PARENT, 2180 .ops = &clk_branch2_ops, 2181 }, 2182 }, 2183 }; 2184 2185 static struct clk_branch gcc_camss_csi0phytimer_clk = { 2186 .halt_reg = 0x4e01c, 2187 .clkr = { 2188 .enable_reg = 0x4e01c, 2189 .enable_mask = BIT(0), 2190 .hw.init = &(struct clk_init_data){ 2191 .name = "gcc_camss_csi0phytimer_clk", 2192 .parent_names = (const char *[]){ 2193 "csi0phytimer_clk_src", 2194 }, 2195 .num_parents = 1, 2196 .flags = CLK_SET_RATE_PARENT, 2197 .ops = &clk_branch2_ops, 2198 }, 2199 }, 2200 }; 2201 2202 static struct clk_branch gcc_camss_csi1phytimer_clk = { 2203 .halt_reg = 0x4f01c, 2204 .clkr = { 2205 .enable_reg = 0x4f01c, 2206 .enable_mask = BIT(0), 2207 .hw.init = &(struct clk_init_data){ 2208 .name = "gcc_camss_csi1phytimer_clk", 2209 .parent_names = (const char *[]){ 2210 "csi1phytimer_clk_src", 2211 }, 2212 .num_parents = 1, 2213 .flags = CLK_SET_RATE_PARENT, 2214 .ops = &clk_branch2_ops, 2215 }, 2216 }, 2217 }; 2218 2219 static struct clk_branch gcc_camss_ahb_clk = { 2220 .halt_reg = 0x5a014, 2221 .clkr = { 2222 .enable_reg = 0x5a014, 2223 .enable_mask = BIT(0), 2224 .hw.init = &(struct clk_init_data){ 2225 .name = "gcc_camss_ahb_clk", 2226 .parent_names = (const char *[]){ 2227 "camss_ahb_clk_src", 2228 }, 2229 .num_parents = 1, 2230 .flags = CLK_SET_RATE_PARENT, 2231 .ops = &clk_branch2_ops, 2232 }, 2233 }, 2234 }; 2235 2236 static struct clk_branch gcc_camss_top_ahb_clk = { 2237 .halt_reg = 0x56004, 2238 .clkr = { 2239 .enable_reg = 0x56004, 2240 .enable_mask = BIT(0), 2241 .hw.init = &(struct clk_init_data){ 2242 .name = "gcc_camss_top_ahb_clk", 2243 .parent_names = (const char *[]){ 2244 "pcnoc_bfdcd_clk_src", 2245 }, 2246 .num_parents = 1, 2247 .flags = CLK_SET_RATE_PARENT, 2248 .ops = &clk_branch2_ops, 2249 }, 2250 }, 2251 }; 2252 2253 static struct clk_branch gcc_camss_cpp_ahb_clk = { 2254 .halt_reg = 0x58040, 2255 .clkr = { 2256 .enable_reg = 0x58040, 2257 .enable_mask = BIT(0), 2258 .hw.init = &(struct clk_init_data){ 2259 .name = "gcc_camss_cpp_ahb_clk", 2260 .parent_names = (const char *[]){ 2261 "camss_ahb_clk_src", 2262 }, 2263 .num_parents = 1, 2264 .flags = CLK_SET_RATE_PARENT, 2265 .ops = &clk_branch2_ops, 2266 }, 2267 }, 2268 }; 2269 2270 static struct clk_branch gcc_camss_cpp_clk = { 2271 .halt_reg = 0x5803c, 2272 .clkr = { 2273 .enable_reg = 0x5803c, 2274 .enable_mask = BIT(0), 2275 .hw.init = &(struct clk_init_data){ 2276 .name = "gcc_camss_cpp_clk", 2277 .parent_names = (const char *[]){ 2278 "cpp_clk_src", 2279 }, 2280 .num_parents = 1, 2281 .flags = CLK_SET_RATE_PARENT, 2282 .ops = &clk_branch2_ops, 2283 }, 2284 }, 2285 }; 2286 2287 static struct clk_branch gcc_camss_vfe0_clk = { 2288 .halt_reg = 0x58038, 2289 .clkr = { 2290 .enable_reg = 0x58038, 2291 .enable_mask = BIT(0), 2292 .hw.init = &(struct clk_init_data){ 2293 .name = "gcc_camss_vfe0_clk", 2294 .parent_names = (const char *[]){ 2295 "vfe0_clk_src", 2296 }, 2297 .num_parents = 1, 2298 .flags = CLK_SET_RATE_PARENT, 2299 .ops = &clk_branch2_ops, 2300 }, 2301 }, 2302 }; 2303 2304 static struct clk_branch gcc_camss_vfe_ahb_clk = { 2305 .halt_reg = 0x58044, 2306 .clkr = { 2307 .enable_reg = 0x58044, 2308 .enable_mask = BIT(0), 2309 .hw.init = &(struct clk_init_data){ 2310 .name = "gcc_camss_vfe_ahb_clk", 2311 .parent_names = (const char *[]){ 2312 "camss_ahb_clk_src", 2313 }, 2314 .num_parents = 1, 2315 .flags = CLK_SET_RATE_PARENT, 2316 .ops = &clk_branch2_ops, 2317 }, 2318 }, 2319 }; 2320 2321 static struct clk_branch gcc_camss_vfe_axi_clk = { 2322 .halt_reg = 0x58048, 2323 .clkr = { 2324 .enable_reg = 0x58048, 2325 .enable_mask = BIT(0), 2326 .hw.init = &(struct clk_init_data){ 2327 .name = "gcc_camss_vfe_axi_clk", 2328 .parent_names = (const char *[]){ 2329 "system_noc_bfdcd_clk_src", 2330 }, 2331 .num_parents = 1, 2332 .flags = CLK_SET_RATE_PARENT, 2333 .ops = &clk_branch2_ops, 2334 }, 2335 }, 2336 }; 2337 2338 static struct clk_branch gcc_crypto_ahb_clk = { 2339 .halt_reg = 0x16024, 2340 .halt_check = BRANCH_HALT_VOTED, 2341 .clkr = { 2342 .enable_reg = 0x45004, 2343 .enable_mask = BIT(0), 2344 .hw.init = &(struct clk_init_data){ 2345 .name = "gcc_crypto_ahb_clk", 2346 .parent_names = (const char *[]){ 2347 "pcnoc_bfdcd_clk_src", 2348 }, 2349 .num_parents = 1, 2350 .flags = CLK_SET_RATE_PARENT, 2351 .ops = &clk_branch2_ops, 2352 }, 2353 }, 2354 }; 2355 2356 static struct clk_branch gcc_crypto_axi_clk = { 2357 .halt_reg = 0x16020, 2358 .halt_check = BRANCH_HALT_VOTED, 2359 .clkr = { 2360 .enable_reg = 0x45004, 2361 .enable_mask = BIT(1), 2362 .hw.init = &(struct clk_init_data){ 2363 .name = "gcc_crypto_axi_clk", 2364 .parent_names = (const char *[]){ 2365 "pcnoc_bfdcd_clk_src", 2366 }, 2367 .num_parents = 1, 2368 .flags = CLK_SET_RATE_PARENT, 2369 .ops = &clk_branch2_ops, 2370 }, 2371 }, 2372 }; 2373 2374 static struct clk_branch gcc_crypto_clk = { 2375 .halt_reg = 0x1601c, 2376 .halt_check = BRANCH_HALT_VOTED, 2377 .clkr = { 2378 .enable_reg = 0x45004, 2379 .enable_mask = BIT(2), 2380 .hw.init = &(struct clk_init_data){ 2381 .name = "gcc_crypto_clk", 2382 .parent_names = (const char *[]){ 2383 "crypto_clk_src", 2384 }, 2385 .num_parents = 1, 2386 .flags = CLK_SET_RATE_PARENT, 2387 .ops = &clk_branch2_ops, 2388 }, 2389 }, 2390 }; 2391 2392 static struct clk_branch gcc_oxili_gmem_clk = { 2393 .halt_reg = 0x59024, 2394 .clkr = { 2395 .enable_reg = 0x59024, 2396 .enable_mask = BIT(0), 2397 .hw.init = &(struct clk_init_data){ 2398 .name = "gcc_oxili_gmem_clk", 2399 .parent_names = (const char *[]){ 2400 "gfx3d_clk_src", 2401 }, 2402 .num_parents = 1, 2403 .flags = CLK_SET_RATE_PARENT, 2404 .ops = &clk_branch2_ops, 2405 }, 2406 }, 2407 }; 2408 2409 static struct clk_branch gcc_gp1_clk = { 2410 .halt_reg = 0x08000, 2411 .clkr = { 2412 .enable_reg = 0x08000, 2413 .enable_mask = BIT(0), 2414 .hw.init = &(struct clk_init_data){ 2415 .name = "gcc_gp1_clk", 2416 .parent_names = (const char *[]){ 2417 "gp1_clk_src", 2418 }, 2419 .num_parents = 1, 2420 .flags = CLK_SET_RATE_PARENT, 2421 .ops = &clk_branch2_ops, 2422 }, 2423 }, 2424 }; 2425 2426 static struct clk_branch gcc_gp2_clk = { 2427 .halt_reg = 0x09000, 2428 .clkr = { 2429 .enable_reg = 0x09000, 2430 .enable_mask = BIT(0), 2431 .hw.init = &(struct clk_init_data){ 2432 .name = "gcc_gp2_clk", 2433 .parent_names = (const char *[]){ 2434 "gp2_clk_src", 2435 }, 2436 .num_parents = 1, 2437 .flags = CLK_SET_RATE_PARENT, 2438 .ops = &clk_branch2_ops, 2439 }, 2440 }, 2441 }; 2442 2443 static struct clk_branch gcc_gp3_clk = { 2444 .halt_reg = 0x0a000, 2445 .clkr = { 2446 .enable_reg = 0x0a000, 2447 .enable_mask = BIT(0), 2448 .hw.init = &(struct clk_init_data){ 2449 .name = "gcc_gp3_clk", 2450 .parent_names = (const char *[]){ 2451 "gp3_clk_src", 2452 }, 2453 .num_parents = 1, 2454 .flags = CLK_SET_RATE_PARENT, 2455 .ops = &clk_branch2_ops, 2456 }, 2457 }, 2458 }; 2459 2460 static struct clk_branch gcc_mdss_ahb_clk = { 2461 .halt_reg = 0x4d07c, 2462 .clkr = { 2463 .enable_reg = 0x4d07c, 2464 .enable_mask = BIT(0), 2465 .hw.init = &(struct clk_init_data){ 2466 .name = "gcc_mdss_ahb_clk", 2467 .parent_names = (const char *[]){ 2468 "pcnoc_bfdcd_clk_src", 2469 }, 2470 .num_parents = 1, 2471 .flags = CLK_SET_RATE_PARENT, 2472 .ops = &clk_branch2_ops, 2473 }, 2474 }, 2475 }; 2476 2477 static struct clk_branch gcc_mdss_axi_clk = { 2478 .halt_reg = 0x4d080, 2479 .clkr = { 2480 .enable_reg = 0x4d080, 2481 .enable_mask = BIT(0), 2482 .hw.init = &(struct clk_init_data){ 2483 .name = "gcc_mdss_axi_clk", 2484 .parent_names = (const char *[]){ 2485 "system_noc_bfdcd_clk_src", 2486 }, 2487 .num_parents = 1, 2488 .flags = CLK_SET_RATE_PARENT, 2489 .ops = &clk_branch2_ops, 2490 }, 2491 }, 2492 }; 2493 2494 static struct clk_branch gcc_mdss_byte0_clk = { 2495 .halt_reg = 0x4d094, 2496 .clkr = { 2497 .enable_reg = 0x4d094, 2498 .enable_mask = BIT(0), 2499 .hw.init = &(struct clk_init_data){ 2500 .name = "gcc_mdss_byte0_clk", 2501 .parent_names = (const char *[]){ 2502 "byte0_clk_src", 2503 }, 2504 .num_parents = 1, 2505 .flags = CLK_SET_RATE_PARENT, 2506 .ops = &clk_branch2_ops, 2507 }, 2508 }, 2509 }; 2510 2511 static struct clk_branch gcc_mdss_esc0_clk = { 2512 .halt_reg = 0x4d098, 2513 .clkr = { 2514 .enable_reg = 0x4d098, 2515 .enable_mask = BIT(0), 2516 .hw.init = &(struct clk_init_data){ 2517 .name = "gcc_mdss_esc0_clk", 2518 .parent_names = (const char *[]){ 2519 "esc0_clk_src", 2520 }, 2521 .num_parents = 1, 2522 .flags = CLK_SET_RATE_PARENT, 2523 .ops = &clk_branch2_ops, 2524 }, 2525 }, 2526 }; 2527 2528 static struct clk_branch gcc_mdss_mdp_clk = { 2529 .halt_reg = 0x4D088, 2530 .clkr = { 2531 .enable_reg = 0x4D088, 2532 .enable_mask = BIT(0), 2533 .hw.init = &(struct clk_init_data){ 2534 .name = "gcc_mdss_mdp_clk", 2535 .parent_names = (const char *[]){ 2536 "mdp_clk_src", 2537 }, 2538 .num_parents = 1, 2539 .flags = CLK_SET_RATE_PARENT, 2540 .ops = &clk_branch2_ops, 2541 }, 2542 }, 2543 }; 2544 2545 static struct clk_branch gcc_mdss_pclk0_clk = { 2546 .halt_reg = 0x4d084, 2547 .clkr = { 2548 .enable_reg = 0x4d084, 2549 .enable_mask = BIT(0), 2550 .hw.init = &(struct clk_init_data){ 2551 .name = "gcc_mdss_pclk0_clk", 2552 .parent_names = (const char *[]){ 2553 "pclk0_clk_src", 2554 }, 2555 .num_parents = 1, 2556 .flags = CLK_SET_RATE_PARENT, 2557 .ops = &clk_branch2_ops, 2558 }, 2559 }, 2560 }; 2561 2562 static struct clk_branch gcc_mdss_vsync_clk = { 2563 .halt_reg = 0x4d090, 2564 .clkr = { 2565 .enable_reg = 0x4d090, 2566 .enable_mask = BIT(0), 2567 .hw.init = &(struct clk_init_data){ 2568 .name = "gcc_mdss_vsync_clk", 2569 .parent_names = (const char *[]){ 2570 "vsync_clk_src", 2571 }, 2572 .num_parents = 1, 2573 .flags = CLK_SET_RATE_PARENT, 2574 .ops = &clk_branch2_ops, 2575 }, 2576 }, 2577 }; 2578 2579 static struct clk_branch gcc_mss_cfg_ahb_clk = { 2580 .halt_reg = 0x49000, 2581 .clkr = { 2582 .enable_reg = 0x49000, 2583 .enable_mask = BIT(0), 2584 .hw.init = &(struct clk_init_data){ 2585 .name = "gcc_mss_cfg_ahb_clk", 2586 .parent_names = (const char *[]){ 2587 "pcnoc_bfdcd_clk_src", 2588 }, 2589 .num_parents = 1, 2590 .flags = CLK_SET_RATE_PARENT, 2591 .ops = &clk_branch2_ops, 2592 }, 2593 }, 2594 }; 2595 2596 static struct clk_branch gcc_mss_q6_bimc_axi_clk = { 2597 .halt_reg = 0x49004, 2598 .clkr = { 2599 .enable_reg = 0x49004, 2600 .enable_mask = BIT(0), 2601 .hw.init = &(struct clk_init_data){ 2602 .name = "gcc_mss_q6_bimc_axi_clk", 2603 .parent_names = (const char *[]){ 2604 "bimc_ddr_clk_src", 2605 }, 2606 .num_parents = 1, 2607 .flags = CLK_SET_RATE_PARENT, 2608 .ops = &clk_branch2_ops, 2609 }, 2610 }, 2611 }; 2612 2613 static struct clk_branch gcc_oxili_ahb_clk = { 2614 .halt_reg = 0x59028, 2615 .clkr = { 2616 .enable_reg = 0x59028, 2617 .enable_mask = BIT(0), 2618 .hw.init = &(struct clk_init_data){ 2619 .name = "gcc_oxili_ahb_clk", 2620 .parent_names = (const char *[]){ 2621 "pcnoc_bfdcd_clk_src", 2622 }, 2623 .num_parents = 1, 2624 .flags = CLK_SET_RATE_PARENT, 2625 .ops = &clk_branch2_ops, 2626 }, 2627 }, 2628 }; 2629 2630 static struct clk_branch gcc_oxili_gfx3d_clk = { 2631 .halt_reg = 0x59020, 2632 .clkr = { 2633 .enable_reg = 0x59020, 2634 .enable_mask = BIT(0), 2635 .hw.init = &(struct clk_init_data){ 2636 .name = "gcc_oxili_gfx3d_clk", 2637 .parent_names = (const char *[]){ 2638 "gfx3d_clk_src", 2639 }, 2640 .num_parents = 1, 2641 .flags = CLK_SET_RATE_PARENT, 2642 .ops = &clk_branch2_ops, 2643 }, 2644 }, 2645 }; 2646 2647 static struct clk_branch gcc_pdm2_clk = { 2648 .halt_reg = 0x4400c, 2649 .clkr = { 2650 .enable_reg = 0x4400c, 2651 .enable_mask = BIT(0), 2652 .hw.init = &(struct clk_init_data){ 2653 .name = "gcc_pdm2_clk", 2654 .parent_names = (const char *[]){ 2655 "pdm2_clk_src", 2656 }, 2657 .num_parents = 1, 2658 .flags = CLK_SET_RATE_PARENT, 2659 .ops = &clk_branch2_ops, 2660 }, 2661 }, 2662 }; 2663 2664 static struct clk_branch gcc_pdm_ahb_clk = { 2665 .halt_reg = 0x44004, 2666 .clkr = { 2667 .enable_reg = 0x44004, 2668 .enable_mask = BIT(0), 2669 .hw.init = &(struct clk_init_data){ 2670 .name = "gcc_pdm_ahb_clk", 2671 .parent_names = (const char *[]){ 2672 "pcnoc_bfdcd_clk_src", 2673 }, 2674 .num_parents = 1, 2675 .flags = CLK_SET_RATE_PARENT, 2676 .ops = &clk_branch2_ops, 2677 }, 2678 }, 2679 }; 2680 2681 static struct clk_branch gcc_prng_ahb_clk = { 2682 .halt_reg = 0x13004, 2683 .halt_check = BRANCH_HALT_VOTED, 2684 .clkr = { 2685 .enable_reg = 0x45004, 2686 .enable_mask = BIT(8), 2687 .hw.init = &(struct clk_init_data){ 2688 .name = "gcc_prng_ahb_clk", 2689 .parent_names = (const char *[]){ 2690 "pcnoc_bfdcd_clk_src", 2691 }, 2692 .num_parents = 1, 2693 .ops = &clk_branch2_ops, 2694 }, 2695 }, 2696 }; 2697 2698 static struct clk_branch gcc_sdcc1_ahb_clk = { 2699 .halt_reg = 0x4201c, 2700 .clkr = { 2701 .enable_reg = 0x4201c, 2702 .enable_mask = BIT(0), 2703 .hw.init = &(struct clk_init_data){ 2704 .name = "gcc_sdcc1_ahb_clk", 2705 .parent_names = (const char *[]){ 2706 "pcnoc_bfdcd_clk_src", 2707 }, 2708 .num_parents = 1, 2709 .flags = CLK_SET_RATE_PARENT, 2710 .ops = &clk_branch2_ops, 2711 }, 2712 }, 2713 }; 2714 2715 static struct clk_branch gcc_sdcc1_apps_clk = { 2716 .halt_reg = 0x42018, 2717 .clkr = { 2718 .enable_reg = 0x42018, 2719 .enable_mask = BIT(0), 2720 .hw.init = &(struct clk_init_data){ 2721 .name = "gcc_sdcc1_apps_clk", 2722 .parent_names = (const char *[]){ 2723 "sdcc1_apps_clk_src", 2724 }, 2725 .num_parents = 1, 2726 .flags = CLK_SET_RATE_PARENT, 2727 .ops = &clk_branch2_ops, 2728 }, 2729 }, 2730 }; 2731 2732 static struct clk_branch gcc_sdcc2_ahb_clk = { 2733 .halt_reg = 0x4301c, 2734 .clkr = { 2735 .enable_reg = 0x4301c, 2736 .enable_mask = BIT(0), 2737 .hw.init = &(struct clk_init_data){ 2738 .name = "gcc_sdcc2_ahb_clk", 2739 .parent_names = (const char *[]){ 2740 "pcnoc_bfdcd_clk_src", 2741 }, 2742 .num_parents = 1, 2743 .flags = CLK_SET_RATE_PARENT, 2744 .ops = &clk_branch2_ops, 2745 }, 2746 }, 2747 }; 2748 2749 static struct clk_branch gcc_sdcc2_apps_clk = { 2750 .halt_reg = 0x43018, 2751 .clkr = { 2752 .enable_reg = 0x43018, 2753 .enable_mask = BIT(0), 2754 .hw.init = &(struct clk_init_data){ 2755 .name = "gcc_sdcc2_apps_clk", 2756 .parent_names = (const char *[]){ 2757 "sdcc2_apps_clk_src", 2758 }, 2759 .num_parents = 1, 2760 .flags = CLK_SET_RATE_PARENT, 2761 .ops = &clk_branch2_ops, 2762 }, 2763 }, 2764 }; 2765 2766 static struct clk_rcg2 bimc_ddr_clk_src = { 2767 .cmd_rcgr = 0x32004, 2768 .hid_width = 5, 2769 .parent_map = gcc_xo_gpll0_bimc_map, 2770 .clkr.hw.init = &(struct clk_init_data){ 2771 .name = "bimc_ddr_clk_src", 2772 .parent_names = gcc_xo_gpll0_bimc, 2773 .num_parents = 3, 2774 .ops = &clk_rcg2_ops, 2775 .flags = CLK_GET_RATE_NOCACHE, 2776 }, 2777 }; 2778 2779 static struct clk_branch gcc_apss_tcu_clk = { 2780 .halt_reg = 0x12018, 2781 .clkr = { 2782 .enable_reg = 0x4500c, 2783 .enable_mask = BIT(1), 2784 .hw.init = &(struct clk_init_data){ 2785 .name = "gcc_apss_tcu_clk", 2786 .parent_names = (const char *[]){ 2787 "bimc_ddr_clk_src", 2788 }, 2789 .num_parents = 1, 2790 .ops = &clk_branch2_ops, 2791 }, 2792 }, 2793 }; 2794 2795 static struct clk_branch gcc_gfx_tcu_clk = { 2796 .halt_reg = 0x12020, 2797 .clkr = { 2798 .enable_reg = 0x4500c, 2799 .enable_mask = BIT(2), 2800 .hw.init = &(struct clk_init_data){ 2801 .name = "gcc_gfx_tcu_clk", 2802 .parent_names = (const char *[]){ 2803 "bimc_ddr_clk_src", 2804 }, 2805 .num_parents = 1, 2806 .ops = &clk_branch2_ops, 2807 }, 2808 }, 2809 }; 2810 2811 static struct clk_branch gcc_gtcu_ahb_clk = { 2812 .halt_reg = 0x12044, 2813 .clkr = { 2814 .enable_reg = 0x4500c, 2815 .enable_mask = BIT(13), 2816 .hw.init = &(struct clk_init_data){ 2817 .name = "gcc_gtcu_ahb_clk", 2818 .parent_names = (const char *[]){ 2819 "pcnoc_bfdcd_clk_src", 2820 }, 2821 .num_parents = 1, 2822 .flags = CLK_SET_RATE_PARENT, 2823 .ops = &clk_branch2_ops, 2824 }, 2825 }, 2826 }; 2827 2828 static struct clk_branch gcc_bimc_gfx_clk = { 2829 .halt_reg = 0x31024, 2830 .clkr = { 2831 .enable_reg = 0x31024, 2832 .enable_mask = BIT(0), 2833 .hw.init = &(struct clk_init_data){ 2834 .name = "gcc_bimc_gfx_clk", 2835 .parent_names = (const char *[]){ 2836 "bimc_gpu_clk_src", 2837 }, 2838 .num_parents = 1, 2839 .flags = CLK_SET_RATE_PARENT, 2840 .ops = &clk_branch2_ops, 2841 }, 2842 }, 2843 }; 2844 2845 static struct clk_branch gcc_bimc_gpu_clk = { 2846 .halt_reg = 0x31040, 2847 .clkr = { 2848 .enable_reg = 0x31040, 2849 .enable_mask = BIT(0), 2850 .hw.init = &(struct clk_init_data){ 2851 .name = "gcc_bimc_gpu_clk", 2852 .parent_names = (const char *[]){ 2853 "bimc_gpu_clk_src", 2854 }, 2855 .num_parents = 1, 2856 .flags = CLK_SET_RATE_PARENT, 2857 .ops = &clk_branch2_ops, 2858 }, 2859 }, 2860 }; 2861 2862 static struct clk_branch gcc_jpeg_tbu_clk = { 2863 .halt_reg = 0x12034, 2864 .clkr = { 2865 .enable_reg = 0x4500c, 2866 .enable_mask = BIT(10), 2867 .hw.init = &(struct clk_init_data){ 2868 .name = "gcc_jpeg_tbu_clk", 2869 .parent_names = (const char *[]){ 2870 "system_noc_bfdcd_clk_src", 2871 }, 2872 .num_parents = 1, 2873 .flags = CLK_SET_RATE_PARENT, 2874 .ops = &clk_branch2_ops, 2875 }, 2876 }, 2877 }; 2878 2879 static struct clk_branch gcc_mdp_tbu_clk = { 2880 .halt_reg = 0x1201c, 2881 .clkr = { 2882 .enable_reg = 0x4500c, 2883 .enable_mask = BIT(4), 2884 .hw.init = &(struct clk_init_data){ 2885 .name = "gcc_mdp_tbu_clk", 2886 .parent_names = (const char *[]){ 2887 "system_noc_bfdcd_clk_src", 2888 }, 2889 .num_parents = 1, 2890 .flags = CLK_SET_RATE_PARENT, 2891 .ops = &clk_branch2_ops, 2892 }, 2893 }, 2894 }; 2895 2896 static struct clk_branch gcc_smmu_cfg_clk = { 2897 .halt_reg = 0x12038, 2898 .clkr = { 2899 .enable_reg = 0x4500c, 2900 .enable_mask = BIT(12), 2901 .hw.init = &(struct clk_init_data){ 2902 .name = "gcc_smmu_cfg_clk", 2903 .parent_names = (const char *[]){ 2904 "pcnoc_bfdcd_clk_src", 2905 }, 2906 .num_parents = 1, 2907 .flags = CLK_SET_RATE_PARENT, 2908 .ops = &clk_branch2_ops, 2909 }, 2910 }, 2911 }; 2912 2913 static struct clk_branch gcc_venus_tbu_clk = { 2914 .halt_reg = 0x12014, 2915 .clkr = { 2916 .enable_reg = 0x4500c, 2917 .enable_mask = BIT(5), 2918 .hw.init = &(struct clk_init_data){ 2919 .name = "gcc_venus_tbu_clk", 2920 .parent_names = (const char *[]){ 2921 "system_noc_bfdcd_clk_src", 2922 }, 2923 .num_parents = 1, 2924 .flags = CLK_SET_RATE_PARENT, 2925 .ops = &clk_branch2_ops, 2926 }, 2927 }, 2928 }; 2929 2930 static struct clk_branch gcc_vfe_tbu_clk = { 2931 .halt_reg = 0x1203c, 2932 .clkr = { 2933 .enable_reg = 0x4500c, 2934 .enable_mask = BIT(9), 2935 .hw.init = &(struct clk_init_data){ 2936 .name = "gcc_vfe_tbu_clk", 2937 .parent_names = (const char *[]){ 2938 "system_noc_bfdcd_clk_src", 2939 }, 2940 .num_parents = 1, 2941 .flags = CLK_SET_RATE_PARENT, 2942 .ops = &clk_branch2_ops, 2943 }, 2944 }, 2945 }; 2946 2947 static struct clk_branch gcc_usb2a_phy_sleep_clk = { 2948 .halt_reg = 0x4102c, 2949 .clkr = { 2950 .enable_reg = 0x4102c, 2951 .enable_mask = BIT(0), 2952 .hw.init = &(struct clk_init_data){ 2953 .name = "gcc_usb2a_phy_sleep_clk", 2954 .parent_names = (const char *[]){ 2955 "sleep_clk_src", 2956 }, 2957 .num_parents = 1, 2958 .flags = CLK_SET_RATE_PARENT, 2959 .ops = &clk_branch2_ops, 2960 }, 2961 }, 2962 }; 2963 2964 static struct clk_branch gcc_usb_hs_ahb_clk = { 2965 .halt_reg = 0x41008, 2966 .clkr = { 2967 .enable_reg = 0x41008, 2968 .enable_mask = BIT(0), 2969 .hw.init = &(struct clk_init_data){ 2970 .name = "gcc_usb_hs_ahb_clk", 2971 .parent_names = (const char *[]){ 2972 "pcnoc_bfdcd_clk_src", 2973 }, 2974 .num_parents = 1, 2975 .flags = CLK_SET_RATE_PARENT, 2976 .ops = &clk_branch2_ops, 2977 }, 2978 }, 2979 }; 2980 2981 static struct clk_branch gcc_usb_hs_system_clk = { 2982 .halt_reg = 0x41004, 2983 .clkr = { 2984 .enable_reg = 0x41004, 2985 .enable_mask = BIT(0), 2986 .hw.init = &(struct clk_init_data){ 2987 .name = "gcc_usb_hs_system_clk", 2988 .parent_names = (const char *[]){ 2989 "usb_hs_system_clk_src", 2990 }, 2991 .num_parents = 1, 2992 .flags = CLK_SET_RATE_PARENT, 2993 .ops = &clk_branch2_ops, 2994 }, 2995 }, 2996 }; 2997 2998 static struct clk_branch gcc_venus0_ahb_clk = { 2999 .halt_reg = 0x4c020, 3000 .clkr = { 3001 .enable_reg = 0x4c020, 3002 .enable_mask = BIT(0), 3003 .hw.init = &(struct clk_init_data){ 3004 .name = "gcc_venus0_ahb_clk", 3005 .parent_names = (const char *[]){ 3006 "pcnoc_bfdcd_clk_src", 3007 }, 3008 .num_parents = 1, 3009 .flags = CLK_SET_RATE_PARENT, 3010 .ops = &clk_branch2_ops, 3011 }, 3012 }, 3013 }; 3014 3015 static struct clk_branch gcc_venus0_axi_clk = { 3016 .halt_reg = 0x4c024, 3017 .clkr = { 3018 .enable_reg = 0x4c024, 3019 .enable_mask = BIT(0), 3020 .hw.init = &(struct clk_init_data){ 3021 .name = "gcc_venus0_axi_clk", 3022 .parent_names = (const char *[]){ 3023 "system_noc_bfdcd_clk_src", 3024 }, 3025 .num_parents = 1, 3026 .flags = CLK_SET_RATE_PARENT, 3027 .ops = &clk_branch2_ops, 3028 }, 3029 }, 3030 }; 3031 3032 static struct clk_branch gcc_venus0_vcodec0_clk = { 3033 .halt_reg = 0x4c01c, 3034 .clkr = { 3035 .enable_reg = 0x4c01c, 3036 .enable_mask = BIT(0), 3037 .hw.init = &(struct clk_init_data){ 3038 .name = "gcc_venus0_vcodec0_clk", 3039 .parent_names = (const char *[]){ 3040 "vcodec0_clk_src", 3041 }, 3042 .num_parents = 1, 3043 .flags = CLK_SET_RATE_PARENT, 3044 .ops = &clk_branch2_ops, 3045 }, 3046 }, 3047 }; 3048 3049 static struct gdsc venus_gdsc = { 3050 .gdscr = 0x4c018, 3051 .pd = { 3052 .name = "venus", 3053 }, 3054 .pwrsts = PWRSTS_OFF_ON, 3055 }; 3056 3057 static struct gdsc mdss_gdsc = { 3058 .gdscr = 0x4d078, 3059 .pd = { 3060 .name = "mdss", 3061 }, 3062 .pwrsts = PWRSTS_OFF_ON, 3063 }; 3064 3065 static struct gdsc jpeg_gdsc = { 3066 .gdscr = 0x5701c, 3067 .pd = { 3068 .name = "jpeg", 3069 }, 3070 .pwrsts = PWRSTS_OFF_ON, 3071 }; 3072 3073 static struct gdsc vfe_gdsc = { 3074 .gdscr = 0x58034, 3075 .pd = { 3076 .name = "vfe", 3077 }, 3078 .pwrsts = PWRSTS_OFF_ON, 3079 }; 3080 3081 static struct gdsc oxili_gdsc = { 3082 .gdscr = 0x5901c, 3083 .pd = { 3084 .name = "oxili", 3085 }, 3086 .pwrsts = PWRSTS_OFF_ON, 3087 }; 3088 3089 static struct clk_regmap *gcc_msm8916_clocks[] = { 3090 [GPLL0] = &gpll0.clkr, 3091 [GPLL0_VOTE] = &gpll0_vote, 3092 [BIMC_PLL] = &bimc_pll.clkr, 3093 [BIMC_PLL_VOTE] = &bimc_pll_vote, 3094 [GPLL1] = &gpll1.clkr, 3095 [GPLL1_VOTE] = &gpll1_vote, 3096 [GPLL2] = &gpll2.clkr, 3097 [GPLL2_VOTE] = &gpll2_vote, 3098 [PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr, 3099 [SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr, 3100 [CAMSS_AHB_CLK_SRC] = &camss_ahb_clk_src.clkr, 3101 [APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr, 3102 [CSI0_CLK_SRC] = &csi0_clk_src.clkr, 3103 [CSI1_CLK_SRC] = &csi1_clk_src.clkr, 3104 [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr, 3105 [VFE0_CLK_SRC] = &vfe0_clk_src.clkr, 3106 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr, 3107 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr, 3108 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr, 3109 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr, 3110 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr, 3111 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr, 3112 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr, 3113 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr, 3114 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr, 3115 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr, 3116 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr, 3117 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr, 3118 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr, 3119 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr, 3120 [CCI_CLK_SRC] = &cci_clk_src.clkr, 3121 [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr, 3122 [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr, 3123 [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr, 3124 [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr, 3125 [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr, 3126 [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr, 3127 [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr, 3128 [CPP_CLK_SRC] = &cpp_clk_src.clkr, 3129 [CRYPTO_CLK_SRC] = &crypto_clk_src.clkr, 3130 [GP1_CLK_SRC] = &gp1_clk_src.clkr, 3131 [GP2_CLK_SRC] = &gp2_clk_src.clkr, 3132 [GP3_CLK_SRC] = &gp3_clk_src.clkr, 3133 [BYTE0_CLK_SRC] = &byte0_clk_src.clkr, 3134 [ESC0_CLK_SRC] = &esc0_clk_src.clkr, 3135 [MDP_CLK_SRC] = &mdp_clk_src.clkr, 3136 [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr, 3137 [VSYNC_CLK_SRC] = &vsync_clk_src.clkr, 3138 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr, 3139 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr, 3140 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr, 3141 [APSS_TCU_CLK_SRC] = &apss_tcu_clk_src.clkr, 3142 [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr, 3143 [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr, 3144 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr, 3145 [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr, 3146 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr, 3147 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr, 3148 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr, 3149 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr, 3150 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr, 3151 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr, 3152 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr, 3153 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr, 3154 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr, 3155 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr, 3156 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr, 3157 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr, 3158 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, 3159 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr, 3160 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 3161 [GCC_CAMSS_CCI_AHB_CLK] = &gcc_camss_cci_ahb_clk.clkr, 3162 [GCC_CAMSS_CCI_CLK] = &gcc_camss_cci_clk.clkr, 3163 [GCC_CAMSS_CSI0_AHB_CLK] = &gcc_camss_csi0_ahb_clk.clkr, 3164 [GCC_CAMSS_CSI0_CLK] = &gcc_camss_csi0_clk.clkr, 3165 [GCC_CAMSS_CSI0PHY_CLK] = &gcc_camss_csi0phy_clk.clkr, 3166 [GCC_CAMSS_CSI0PIX_CLK] = &gcc_camss_csi0pix_clk.clkr, 3167 [GCC_CAMSS_CSI0RDI_CLK] = &gcc_camss_csi0rdi_clk.clkr, 3168 [GCC_CAMSS_CSI1_AHB_CLK] = &gcc_camss_csi1_ahb_clk.clkr, 3169 [GCC_CAMSS_CSI1_CLK] = &gcc_camss_csi1_clk.clkr, 3170 [GCC_CAMSS_CSI1PHY_CLK] = &gcc_camss_csi1phy_clk.clkr, 3171 [GCC_CAMSS_CSI1PIX_CLK] = &gcc_camss_csi1pix_clk.clkr, 3172 [GCC_CAMSS_CSI1RDI_CLK] = &gcc_camss_csi1rdi_clk.clkr, 3173 [GCC_CAMSS_CSI_VFE0_CLK] = &gcc_camss_csi_vfe0_clk.clkr, 3174 [GCC_CAMSS_GP0_CLK] = &gcc_camss_gp0_clk.clkr, 3175 [GCC_CAMSS_GP1_CLK] = &gcc_camss_gp1_clk.clkr, 3176 [GCC_CAMSS_ISPIF_AHB_CLK] = &gcc_camss_ispif_ahb_clk.clkr, 3177 [GCC_CAMSS_JPEG0_CLK] = &gcc_camss_jpeg0_clk.clkr, 3178 [GCC_CAMSS_JPEG_AHB_CLK] = &gcc_camss_jpeg_ahb_clk.clkr, 3179 [GCC_CAMSS_JPEG_AXI_CLK] = &gcc_camss_jpeg_axi_clk.clkr, 3180 [GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr, 3181 [GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr, 3182 [GCC_CAMSS_MICRO_AHB_CLK] = &gcc_camss_micro_ahb_clk.clkr, 3183 [GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr, 3184 [GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr, 3185 [GCC_CAMSS_AHB_CLK] = &gcc_camss_ahb_clk.clkr, 3186 [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr, 3187 [GCC_CAMSS_CPP_AHB_CLK] = &gcc_camss_cpp_ahb_clk.clkr, 3188 [GCC_CAMSS_CPP_CLK] = &gcc_camss_cpp_clk.clkr, 3189 [GCC_CAMSS_VFE0_CLK] = &gcc_camss_vfe0_clk.clkr, 3190 [GCC_CAMSS_VFE_AHB_CLK] = &gcc_camss_vfe_ahb_clk.clkr, 3191 [GCC_CAMSS_VFE_AXI_CLK] = &gcc_camss_vfe_axi_clk.clkr, 3192 [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr, 3193 [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr, 3194 [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr, 3195 [GCC_OXILI_GMEM_CLK] = &gcc_oxili_gmem_clk.clkr, 3196 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 3197 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 3198 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 3199 [GCC_MDSS_AHB_CLK] = &gcc_mdss_ahb_clk.clkr, 3200 [GCC_MDSS_AXI_CLK] = &gcc_mdss_axi_clk.clkr, 3201 [GCC_MDSS_BYTE0_CLK] = &gcc_mdss_byte0_clk.clkr, 3202 [GCC_MDSS_ESC0_CLK] = &gcc_mdss_esc0_clk.clkr, 3203 [GCC_MDSS_MDP_CLK] = &gcc_mdss_mdp_clk.clkr, 3204 [GCC_MDSS_PCLK0_CLK] = &gcc_mdss_pclk0_clk.clkr, 3205 [GCC_MDSS_VSYNC_CLK] = &gcc_mdss_vsync_clk.clkr, 3206 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr, 3207 [GCC_OXILI_AHB_CLK] = &gcc_oxili_ahb_clk.clkr, 3208 [GCC_OXILI_GFX3D_CLK] = &gcc_oxili_gfx3d_clk.clkr, 3209 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 3210 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 3211 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, 3212 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, 3213 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, 3214 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 3215 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 3216 [GCC_GTCU_AHB_CLK] = &gcc_gtcu_ahb_clk.clkr, 3217 [GCC_JPEG_TBU_CLK] = &gcc_jpeg_tbu_clk.clkr, 3218 [GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr, 3219 [GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr, 3220 [GCC_VENUS_TBU_CLK] = &gcc_venus_tbu_clk.clkr, 3221 [GCC_VFE_TBU_CLK] = &gcc_vfe_tbu_clk.clkr, 3222 [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr, 3223 [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr, 3224 [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr, 3225 [GCC_VENUS0_AHB_CLK] = &gcc_venus0_ahb_clk.clkr, 3226 [GCC_VENUS0_AXI_CLK] = &gcc_venus0_axi_clk.clkr, 3227 [GCC_VENUS0_VCODEC0_CLK] = &gcc_venus0_vcodec0_clk.clkr, 3228 [BIMC_DDR_CLK_SRC] = &bimc_ddr_clk_src.clkr, 3229 [GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr, 3230 [GCC_GFX_TCU_CLK] = &gcc_gfx_tcu_clk.clkr, 3231 [BIMC_GPU_CLK_SRC] = &bimc_gpu_clk_src.clkr, 3232 [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr, 3233 [GCC_BIMC_GPU_CLK] = &gcc_bimc_gpu_clk.clkr, 3234 [ULTAUDIO_AHBFABRIC_CLK_SRC] = &ultaudio_ahbfabric_clk_src.clkr, 3235 [ULTAUDIO_LPAIF_PRI_I2S_CLK_SRC] = &ultaudio_lpaif_pri_i2s_clk_src.clkr, 3236 [ULTAUDIO_LPAIF_SEC_I2S_CLK_SRC] = &ultaudio_lpaif_sec_i2s_clk_src.clkr, 3237 [ULTAUDIO_LPAIF_AUX_I2S_CLK_SRC] = &ultaudio_lpaif_aux_i2s_clk_src.clkr, 3238 [ULTAUDIO_XO_CLK_SRC] = &ultaudio_xo_clk_src.clkr, 3239 [CODEC_DIGCODEC_CLK_SRC] = &codec_digcodec_clk_src.clkr, 3240 [GCC_ULTAUDIO_PCNOC_MPORT_CLK] = &gcc_ultaudio_pcnoc_mport_clk.clkr, 3241 [GCC_ULTAUDIO_PCNOC_SWAY_CLK] = &gcc_ultaudio_pcnoc_sway_clk.clkr, 3242 [GCC_ULTAUDIO_AVSYNC_XO_CLK] = &gcc_ultaudio_avsync_xo_clk.clkr, 3243 [GCC_ULTAUDIO_STC_XO_CLK] = &gcc_ultaudio_stc_xo_clk.clkr, 3244 [GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK] = &gcc_ultaudio_ahbfabric_ixfabric_clk.clkr, 3245 [GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CLK] = &gcc_ultaudio_ahbfabric_ixfabric_lpm_clk.clkr, 3246 [GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK] = &gcc_ultaudio_lpaif_pri_i2s_clk.clkr, 3247 [GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK] = &gcc_ultaudio_lpaif_sec_i2s_clk.clkr, 3248 [GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK] = &gcc_ultaudio_lpaif_aux_i2s_clk.clkr, 3249 [GCC_CODEC_DIGCODEC_CLK] = &gcc_codec_digcodec_clk.clkr, 3250 [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr, 3251 }; 3252 3253 static struct gdsc *gcc_msm8916_gdscs[] = { 3254 [VENUS_GDSC] = &venus_gdsc, 3255 [MDSS_GDSC] = &mdss_gdsc, 3256 [JPEG_GDSC] = &jpeg_gdsc, 3257 [VFE_GDSC] = &vfe_gdsc, 3258 [OXILI_GDSC] = &oxili_gdsc, 3259 }; 3260 3261 static const struct qcom_reset_map gcc_msm8916_resets[] = { 3262 [GCC_BLSP1_BCR] = { 0x01000 }, 3263 [GCC_BLSP1_QUP1_BCR] = { 0x02000 }, 3264 [GCC_BLSP1_UART1_BCR] = { 0x02038 }, 3265 [GCC_BLSP1_QUP2_BCR] = { 0x03008 }, 3266 [GCC_BLSP1_UART2_BCR] = { 0x03028 }, 3267 [GCC_BLSP1_QUP3_BCR] = { 0x04018 }, 3268 [GCC_BLSP1_QUP4_BCR] = { 0x05018 }, 3269 [GCC_BLSP1_QUP5_BCR] = { 0x06018 }, 3270 [GCC_BLSP1_QUP6_BCR] = { 0x07018 }, 3271 [GCC_IMEM_BCR] = { 0x0e000 }, 3272 [GCC_SMMU_BCR] = { 0x12000 }, 3273 [GCC_APSS_TCU_BCR] = { 0x12050 }, 3274 [GCC_SMMU_XPU_BCR] = { 0x12054 }, 3275 [GCC_PCNOC_TBU_BCR] = { 0x12058 }, 3276 [GCC_PRNG_BCR] = { 0x13000 }, 3277 [GCC_BOOT_ROM_BCR] = { 0x13008 }, 3278 [GCC_CRYPTO_BCR] = { 0x16000 }, 3279 [GCC_SEC_CTRL_BCR] = { 0x1a000 }, 3280 [GCC_AUDIO_CORE_BCR] = { 0x1c008 }, 3281 [GCC_ULT_AUDIO_BCR] = { 0x1c0b4 }, 3282 [GCC_DEHR_BCR] = { 0x1f000 }, 3283 [GCC_SYSTEM_NOC_BCR] = { 0x26000 }, 3284 [GCC_PCNOC_BCR] = { 0x27018 }, 3285 [GCC_TCSR_BCR] = { 0x28000 }, 3286 [GCC_QDSS_BCR] = { 0x29000 }, 3287 [GCC_DCD_BCR] = { 0x2a000 }, 3288 [GCC_MSG_RAM_BCR] = { 0x2b000 }, 3289 [GCC_MPM_BCR] = { 0x2c000 }, 3290 [GCC_SPMI_BCR] = { 0x2e000 }, 3291 [GCC_SPDM_BCR] = { 0x2f000 }, 3292 [GCC_MM_SPDM_BCR] = { 0x2f024 }, 3293 [GCC_BIMC_BCR] = { 0x31000 }, 3294 [GCC_RBCPR_BCR] = { 0x33000 }, 3295 [GCC_TLMM_BCR] = { 0x34000 }, 3296 [GCC_USB_HS_BCR] = { 0x41000 }, 3297 [GCC_USB2A_PHY_BCR] = { 0x41028 }, 3298 [GCC_SDCC1_BCR] = { 0x42000 }, 3299 [GCC_SDCC2_BCR] = { 0x43000 }, 3300 [GCC_PDM_BCR] = { 0x44000 }, 3301 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000 }, 3302 [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000 }, 3303 [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008 }, 3304 [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010 }, 3305 [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018 }, 3306 [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020 }, 3307 [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028 }, 3308 [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030 }, 3309 [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038 }, 3310 [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040 }, 3311 [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048 }, 3312 [GCC_MMSS_BCR] = { 0x4b000 }, 3313 [GCC_VENUS0_BCR] = { 0x4c014 }, 3314 [GCC_MDSS_BCR] = { 0x4d074 }, 3315 [GCC_CAMSS_PHY0_BCR] = { 0x4e018 }, 3316 [GCC_CAMSS_CSI0_BCR] = { 0x4e038 }, 3317 [GCC_CAMSS_CSI0PHY_BCR] = { 0x4e044 }, 3318 [GCC_CAMSS_CSI0RDI_BCR] = { 0x4e04c }, 3319 [GCC_CAMSS_CSI0PIX_BCR] = { 0x4e054 }, 3320 [GCC_CAMSS_PHY1_BCR] = { 0x4f018 }, 3321 [GCC_CAMSS_CSI1_BCR] = { 0x4f038 }, 3322 [GCC_CAMSS_CSI1PHY_BCR] = { 0x4f044 }, 3323 [GCC_CAMSS_CSI1RDI_BCR] = { 0x4f04c }, 3324 [GCC_CAMSS_CSI1PIX_BCR] = { 0x4f054 }, 3325 [GCC_CAMSS_ISPIF_BCR] = { 0x50000 }, 3326 [GCC_CAMSS_CCI_BCR] = { 0x51014 }, 3327 [GCC_CAMSS_MCLK0_BCR] = { 0x52014 }, 3328 [GCC_CAMSS_MCLK1_BCR] = { 0x53014 }, 3329 [GCC_CAMSS_GP0_BCR] = { 0x54014 }, 3330 [GCC_CAMSS_GP1_BCR] = { 0x55014 }, 3331 [GCC_CAMSS_TOP_BCR] = { 0x56000 }, 3332 [GCC_CAMSS_MICRO_BCR] = { 0x56008 }, 3333 [GCC_CAMSS_JPEG_BCR] = { 0x57018 }, 3334 [GCC_CAMSS_VFE_BCR] = { 0x58030 }, 3335 [GCC_CAMSS_CSI_VFE0_BCR] = { 0x5804c }, 3336 [GCC_OXILI_BCR] = { 0x59018 }, 3337 [GCC_GMEM_BCR] = { 0x5902c }, 3338 [GCC_CAMSS_AHB_BCR] = { 0x5a018 }, 3339 [GCC_MDP_TBU_BCR] = { 0x62000 }, 3340 [GCC_GFX_TBU_BCR] = { 0x63000 }, 3341 [GCC_GFX_TCU_BCR] = { 0x64000 }, 3342 [GCC_MSS_TBU_AXI_BCR] = { 0x65000 }, 3343 [GCC_MSS_TBU_GSS_AXI_BCR] = { 0x66000 }, 3344 [GCC_MSS_TBU_Q6_AXI_BCR] = { 0x67000 }, 3345 [GCC_GTCU_AHB_BCR] = { 0x68000 }, 3346 [GCC_SMMU_CFG_BCR] = { 0x69000 }, 3347 [GCC_VFE_TBU_BCR] = { 0x6a000 }, 3348 [GCC_VENUS_TBU_BCR] = { 0x6b000 }, 3349 [GCC_JPEG_TBU_BCR] = { 0x6c000 }, 3350 [GCC_PRONTO_TBU_BCR] = { 0x6d000 }, 3351 [GCC_SMMU_CATS_BCR] = { 0x7c000 }, 3352 }; 3353 3354 static const struct regmap_config gcc_msm8916_regmap_config = { 3355 .reg_bits = 32, 3356 .reg_stride = 4, 3357 .val_bits = 32, 3358 .max_register = 0x80000, 3359 .fast_io = true, 3360 }; 3361 3362 static const struct qcom_cc_desc gcc_msm8916_desc = { 3363 .config = &gcc_msm8916_regmap_config, 3364 .clks = gcc_msm8916_clocks, 3365 .num_clks = ARRAY_SIZE(gcc_msm8916_clocks), 3366 .resets = gcc_msm8916_resets, 3367 .num_resets = ARRAY_SIZE(gcc_msm8916_resets), 3368 .gdscs = gcc_msm8916_gdscs, 3369 .num_gdscs = ARRAY_SIZE(gcc_msm8916_gdscs), 3370 }; 3371 3372 static const struct of_device_id gcc_msm8916_match_table[] = { 3373 { .compatible = "qcom,gcc-msm8916" }, 3374 { } 3375 }; 3376 MODULE_DEVICE_TABLE(of, gcc_msm8916_match_table); 3377 3378 static int gcc_msm8916_probe(struct platform_device *pdev) 3379 { 3380 int ret; 3381 struct device *dev = &pdev->dev; 3382 3383 ret = qcom_cc_register_board_clk(dev, "xo_board", "xo", 19200000); 3384 if (ret) 3385 return ret; 3386 3387 ret = qcom_cc_register_sleep_clk(dev); 3388 if (ret) 3389 return ret; 3390 3391 return qcom_cc_probe(pdev, &gcc_msm8916_desc); 3392 } 3393 3394 static struct platform_driver gcc_msm8916_driver = { 3395 .probe = gcc_msm8916_probe, 3396 .driver = { 3397 .name = "gcc-msm8916", 3398 .of_match_table = gcc_msm8916_match_table, 3399 }, 3400 }; 3401 3402 static int __init gcc_msm8916_init(void) 3403 { 3404 return platform_driver_register(&gcc_msm8916_driver); 3405 } 3406 core_initcall(gcc_msm8916_init); 3407 3408 static void __exit gcc_msm8916_exit(void) 3409 { 3410 platform_driver_unregister(&gcc_msm8916_driver); 3411 } 3412 module_exit(gcc_msm8916_exit); 3413 3414 MODULE_DESCRIPTION("Qualcomm GCC MSM8916 Driver"); 3415 MODULE_LICENSE("GPL v2"); 3416 MODULE_ALIAS("platform:gcc-msm8916"); 3417