1 /* 2 * Copyright (c) 2013, The Linux Foundation. All rights reserved. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include <linux/kernel.h> 15 #include <linux/bitops.h> 16 #include <linux/err.h> 17 #include <linux/platform_device.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/of_device.h> 21 #include <linux/clk-provider.h> 22 #include <linux/regmap.h> 23 #include <linux/reset-controller.h> 24 25 #include <dt-bindings/clock/qcom,gcc-msm8660.h> 26 #include <dt-bindings/reset/qcom,gcc-msm8660.h> 27 28 #include "clk-regmap.h" 29 #include "clk-pll.h" 30 #include "clk-rcg.h" 31 #include "clk-branch.h" 32 #include "reset.h" 33 34 static struct clk_pll pll8 = { 35 .l_reg = 0x3144, 36 .m_reg = 0x3148, 37 .n_reg = 0x314c, 38 .config_reg = 0x3154, 39 .mode_reg = 0x3140, 40 .status_reg = 0x3158, 41 .status_bit = 16, 42 .clkr.hw.init = &(struct clk_init_data){ 43 .name = "pll8", 44 .parent_names = (const char *[]){ "pxo" }, 45 .num_parents = 1, 46 .ops = &clk_pll_ops, 47 }, 48 }; 49 50 static struct clk_regmap pll8_vote = { 51 .enable_reg = 0x34c0, 52 .enable_mask = BIT(8), 53 .hw.init = &(struct clk_init_data){ 54 .name = "pll8_vote", 55 .parent_names = (const char *[]){ "pll8" }, 56 .num_parents = 1, 57 .ops = &clk_pll_vote_ops, 58 }, 59 }; 60 61 #define P_PXO 0 62 #define P_PLL8 1 63 #define P_CXO 2 64 65 static const u8 gcc_pxo_pll8_map[] = { 66 [P_PXO] = 0, 67 [P_PLL8] = 3, 68 }; 69 70 static const char *gcc_pxo_pll8[] = { 71 "pxo", 72 "pll8_vote", 73 }; 74 75 static const u8 gcc_pxo_pll8_cxo_map[] = { 76 [P_PXO] = 0, 77 [P_PLL8] = 3, 78 [P_CXO] = 5, 79 }; 80 81 static const char *gcc_pxo_pll8_cxo[] = { 82 "pxo", 83 "pll8_vote", 84 "cxo", 85 }; 86 87 static struct freq_tbl clk_tbl_gsbi_uart[] = { 88 { 1843200, P_PLL8, 2, 6, 625 }, 89 { 3686400, P_PLL8, 2, 12, 625 }, 90 { 7372800, P_PLL8, 2, 24, 625 }, 91 { 14745600, P_PLL8, 2, 48, 625 }, 92 { 16000000, P_PLL8, 4, 1, 6 }, 93 { 24000000, P_PLL8, 4, 1, 4 }, 94 { 32000000, P_PLL8, 4, 1, 3 }, 95 { 40000000, P_PLL8, 1, 5, 48 }, 96 { 46400000, P_PLL8, 1, 29, 240 }, 97 { 48000000, P_PLL8, 4, 1, 2 }, 98 { 51200000, P_PLL8, 1, 2, 15 }, 99 { 56000000, P_PLL8, 1, 7, 48 }, 100 { 58982400, P_PLL8, 1, 96, 625 }, 101 { 64000000, P_PLL8, 2, 1, 3 }, 102 { } 103 }; 104 105 static struct clk_rcg gsbi1_uart_src = { 106 .ns_reg = 0x29d4, 107 .md_reg = 0x29d0, 108 .mn = { 109 .mnctr_en_bit = 8, 110 .mnctr_reset_bit = 7, 111 .mnctr_mode_shift = 5, 112 .n_val_shift = 16, 113 .m_val_shift = 16, 114 .width = 16, 115 }, 116 .p = { 117 .pre_div_shift = 3, 118 .pre_div_width = 2, 119 }, 120 .s = { 121 .src_sel_shift = 0, 122 .parent_map = gcc_pxo_pll8_map, 123 }, 124 .freq_tbl = clk_tbl_gsbi_uart, 125 .clkr = { 126 .enable_reg = 0x29d4, 127 .enable_mask = BIT(11), 128 .hw.init = &(struct clk_init_data){ 129 .name = "gsbi1_uart_src", 130 .parent_names = gcc_pxo_pll8, 131 .num_parents = 2, 132 .ops = &clk_rcg_ops, 133 .flags = CLK_SET_PARENT_GATE, 134 }, 135 }, 136 }; 137 138 static struct clk_branch gsbi1_uart_clk = { 139 .halt_reg = 0x2fcc, 140 .halt_bit = 10, 141 .clkr = { 142 .enable_reg = 0x29d4, 143 .enable_mask = BIT(9), 144 .hw.init = &(struct clk_init_data){ 145 .name = "gsbi1_uart_clk", 146 .parent_names = (const char *[]){ 147 "gsbi1_uart_src", 148 }, 149 .num_parents = 1, 150 .ops = &clk_branch_ops, 151 .flags = CLK_SET_RATE_PARENT, 152 }, 153 }, 154 }; 155 156 static struct clk_rcg gsbi2_uart_src = { 157 .ns_reg = 0x29f4, 158 .md_reg = 0x29f0, 159 .mn = { 160 .mnctr_en_bit = 8, 161 .mnctr_reset_bit = 7, 162 .mnctr_mode_shift = 5, 163 .n_val_shift = 16, 164 .m_val_shift = 16, 165 .width = 16, 166 }, 167 .p = { 168 .pre_div_shift = 3, 169 .pre_div_width = 2, 170 }, 171 .s = { 172 .src_sel_shift = 0, 173 .parent_map = gcc_pxo_pll8_map, 174 }, 175 .freq_tbl = clk_tbl_gsbi_uart, 176 .clkr = { 177 .enable_reg = 0x29f4, 178 .enable_mask = BIT(11), 179 .hw.init = &(struct clk_init_data){ 180 .name = "gsbi2_uart_src", 181 .parent_names = gcc_pxo_pll8, 182 .num_parents = 2, 183 .ops = &clk_rcg_ops, 184 .flags = CLK_SET_PARENT_GATE, 185 }, 186 }, 187 }; 188 189 static struct clk_branch gsbi2_uart_clk = { 190 .halt_reg = 0x2fcc, 191 .halt_bit = 6, 192 .clkr = { 193 .enable_reg = 0x29f4, 194 .enable_mask = BIT(9), 195 .hw.init = &(struct clk_init_data){ 196 .name = "gsbi2_uart_clk", 197 .parent_names = (const char *[]){ 198 "gsbi2_uart_src", 199 }, 200 .num_parents = 1, 201 .ops = &clk_branch_ops, 202 .flags = CLK_SET_RATE_PARENT, 203 }, 204 }, 205 }; 206 207 static struct clk_rcg gsbi3_uart_src = { 208 .ns_reg = 0x2a14, 209 .md_reg = 0x2a10, 210 .mn = { 211 .mnctr_en_bit = 8, 212 .mnctr_reset_bit = 7, 213 .mnctr_mode_shift = 5, 214 .n_val_shift = 16, 215 .m_val_shift = 16, 216 .width = 16, 217 }, 218 .p = { 219 .pre_div_shift = 3, 220 .pre_div_width = 2, 221 }, 222 .s = { 223 .src_sel_shift = 0, 224 .parent_map = gcc_pxo_pll8_map, 225 }, 226 .freq_tbl = clk_tbl_gsbi_uart, 227 .clkr = { 228 .enable_reg = 0x2a14, 229 .enable_mask = BIT(11), 230 .hw.init = &(struct clk_init_data){ 231 .name = "gsbi3_uart_src", 232 .parent_names = gcc_pxo_pll8, 233 .num_parents = 2, 234 .ops = &clk_rcg_ops, 235 .flags = CLK_SET_PARENT_GATE, 236 }, 237 }, 238 }; 239 240 static struct clk_branch gsbi3_uart_clk = { 241 .halt_reg = 0x2fcc, 242 .halt_bit = 2, 243 .clkr = { 244 .enable_reg = 0x2a14, 245 .enable_mask = BIT(9), 246 .hw.init = &(struct clk_init_data){ 247 .name = "gsbi3_uart_clk", 248 .parent_names = (const char *[]){ 249 "gsbi3_uart_src", 250 }, 251 .num_parents = 1, 252 .ops = &clk_branch_ops, 253 .flags = CLK_SET_RATE_PARENT, 254 }, 255 }, 256 }; 257 258 static struct clk_rcg gsbi4_uart_src = { 259 .ns_reg = 0x2a34, 260 .md_reg = 0x2a30, 261 .mn = { 262 .mnctr_en_bit = 8, 263 .mnctr_reset_bit = 7, 264 .mnctr_mode_shift = 5, 265 .n_val_shift = 16, 266 .m_val_shift = 16, 267 .width = 16, 268 }, 269 .p = { 270 .pre_div_shift = 3, 271 .pre_div_width = 2, 272 }, 273 .s = { 274 .src_sel_shift = 0, 275 .parent_map = gcc_pxo_pll8_map, 276 }, 277 .freq_tbl = clk_tbl_gsbi_uart, 278 .clkr = { 279 .enable_reg = 0x2a34, 280 .enable_mask = BIT(11), 281 .hw.init = &(struct clk_init_data){ 282 .name = "gsbi4_uart_src", 283 .parent_names = gcc_pxo_pll8, 284 .num_parents = 2, 285 .ops = &clk_rcg_ops, 286 .flags = CLK_SET_PARENT_GATE, 287 }, 288 }, 289 }; 290 291 static struct clk_branch gsbi4_uart_clk = { 292 .halt_reg = 0x2fd0, 293 .halt_bit = 26, 294 .clkr = { 295 .enable_reg = 0x2a34, 296 .enable_mask = BIT(9), 297 .hw.init = &(struct clk_init_data){ 298 .name = "gsbi4_uart_clk", 299 .parent_names = (const char *[]){ 300 "gsbi4_uart_src", 301 }, 302 .num_parents = 1, 303 .ops = &clk_branch_ops, 304 .flags = CLK_SET_RATE_PARENT, 305 }, 306 }, 307 }; 308 309 static struct clk_rcg gsbi5_uart_src = { 310 .ns_reg = 0x2a54, 311 .md_reg = 0x2a50, 312 .mn = { 313 .mnctr_en_bit = 8, 314 .mnctr_reset_bit = 7, 315 .mnctr_mode_shift = 5, 316 .n_val_shift = 16, 317 .m_val_shift = 16, 318 .width = 16, 319 }, 320 .p = { 321 .pre_div_shift = 3, 322 .pre_div_width = 2, 323 }, 324 .s = { 325 .src_sel_shift = 0, 326 .parent_map = gcc_pxo_pll8_map, 327 }, 328 .freq_tbl = clk_tbl_gsbi_uart, 329 .clkr = { 330 .enable_reg = 0x2a54, 331 .enable_mask = BIT(11), 332 .hw.init = &(struct clk_init_data){ 333 .name = "gsbi5_uart_src", 334 .parent_names = gcc_pxo_pll8, 335 .num_parents = 2, 336 .ops = &clk_rcg_ops, 337 .flags = CLK_SET_PARENT_GATE, 338 }, 339 }, 340 }; 341 342 static struct clk_branch gsbi5_uart_clk = { 343 .halt_reg = 0x2fd0, 344 .halt_bit = 22, 345 .clkr = { 346 .enable_reg = 0x2a54, 347 .enable_mask = BIT(9), 348 .hw.init = &(struct clk_init_data){ 349 .name = "gsbi5_uart_clk", 350 .parent_names = (const char *[]){ 351 "gsbi5_uart_src", 352 }, 353 .num_parents = 1, 354 .ops = &clk_branch_ops, 355 .flags = CLK_SET_RATE_PARENT, 356 }, 357 }, 358 }; 359 360 static struct clk_rcg gsbi6_uart_src = { 361 .ns_reg = 0x2a74, 362 .md_reg = 0x2a70, 363 .mn = { 364 .mnctr_en_bit = 8, 365 .mnctr_reset_bit = 7, 366 .mnctr_mode_shift = 5, 367 .n_val_shift = 16, 368 .m_val_shift = 16, 369 .width = 16, 370 }, 371 .p = { 372 .pre_div_shift = 3, 373 .pre_div_width = 2, 374 }, 375 .s = { 376 .src_sel_shift = 0, 377 .parent_map = gcc_pxo_pll8_map, 378 }, 379 .freq_tbl = clk_tbl_gsbi_uart, 380 .clkr = { 381 .enable_reg = 0x2a74, 382 .enable_mask = BIT(11), 383 .hw.init = &(struct clk_init_data){ 384 .name = "gsbi6_uart_src", 385 .parent_names = gcc_pxo_pll8, 386 .num_parents = 2, 387 .ops = &clk_rcg_ops, 388 .flags = CLK_SET_PARENT_GATE, 389 }, 390 }, 391 }; 392 393 static struct clk_branch gsbi6_uart_clk = { 394 .halt_reg = 0x2fd0, 395 .halt_bit = 18, 396 .clkr = { 397 .enable_reg = 0x2a74, 398 .enable_mask = BIT(9), 399 .hw.init = &(struct clk_init_data){ 400 .name = "gsbi6_uart_clk", 401 .parent_names = (const char *[]){ 402 "gsbi6_uart_src", 403 }, 404 .num_parents = 1, 405 .ops = &clk_branch_ops, 406 .flags = CLK_SET_RATE_PARENT, 407 }, 408 }, 409 }; 410 411 static struct clk_rcg gsbi7_uart_src = { 412 .ns_reg = 0x2a94, 413 .md_reg = 0x2a90, 414 .mn = { 415 .mnctr_en_bit = 8, 416 .mnctr_reset_bit = 7, 417 .mnctr_mode_shift = 5, 418 .n_val_shift = 16, 419 .m_val_shift = 16, 420 .width = 16, 421 }, 422 .p = { 423 .pre_div_shift = 3, 424 .pre_div_width = 2, 425 }, 426 .s = { 427 .src_sel_shift = 0, 428 .parent_map = gcc_pxo_pll8_map, 429 }, 430 .freq_tbl = clk_tbl_gsbi_uart, 431 .clkr = { 432 .enable_reg = 0x2a94, 433 .enable_mask = BIT(11), 434 .hw.init = &(struct clk_init_data){ 435 .name = "gsbi7_uart_src", 436 .parent_names = gcc_pxo_pll8, 437 .num_parents = 2, 438 .ops = &clk_rcg_ops, 439 .flags = CLK_SET_PARENT_GATE, 440 }, 441 }, 442 }; 443 444 static struct clk_branch gsbi7_uart_clk = { 445 .halt_reg = 0x2fd0, 446 .halt_bit = 14, 447 .clkr = { 448 .enable_reg = 0x2a94, 449 .enable_mask = BIT(9), 450 .hw.init = &(struct clk_init_data){ 451 .name = "gsbi7_uart_clk", 452 .parent_names = (const char *[]){ 453 "gsbi7_uart_src", 454 }, 455 .num_parents = 1, 456 .ops = &clk_branch_ops, 457 .flags = CLK_SET_RATE_PARENT, 458 }, 459 }, 460 }; 461 462 static struct clk_rcg gsbi8_uart_src = { 463 .ns_reg = 0x2ab4, 464 .md_reg = 0x2ab0, 465 .mn = { 466 .mnctr_en_bit = 8, 467 .mnctr_reset_bit = 7, 468 .mnctr_mode_shift = 5, 469 .n_val_shift = 16, 470 .m_val_shift = 16, 471 .width = 16, 472 }, 473 .p = { 474 .pre_div_shift = 3, 475 .pre_div_width = 2, 476 }, 477 .s = { 478 .src_sel_shift = 0, 479 .parent_map = gcc_pxo_pll8_map, 480 }, 481 .freq_tbl = clk_tbl_gsbi_uart, 482 .clkr = { 483 .enable_reg = 0x2ab4, 484 .enable_mask = BIT(11), 485 .hw.init = &(struct clk_init_data){ 486 .name = "gsbi8_uart_src", 487 .parent_names = gcc_pxo_pll8, 488 .num_parents = 2, 489 .ops = &clk_rcg_ops, 490 .flags = CLK_SET_PARENT_GATE, 491 }, 492 }, 493 }; 494 495 static struct clk_branch gsbi8_uart_clk = { 496 .halt_reg = 0x2fd0, 497 .halt_bit = 10, 498 .clkr = { 499 .enable_reg = 0x2ab4, 500 .enable_mask = BIT(9), 501 .hw.init = &(struct clk_init_data){ 502 .name = "gsbi8_uart_clk", 503 .parent_names = (const char *[]){ "gsbi8_uart_src" }, 504 .num_parents = 1, 505 .ops = &clk_branch_ops, 506 .flags = CLK_SET_RATE_PARENT, 507 }, 508 }, 509 }; 510 511 static struct clk_rcg gsbi9_uart_src = { 512 .ns_reg = 0x2ad4, 513 .md_reg = 0x2ad0, 514 .mn = { 515 .mnctr_en_bit = 8, 516 .mnctr_reset_bit = 7, 517 .mnctr_mode_shift = 5, 518 .n_val_shift = 16, 519 .m_val_shift = 16, 520 .width = 16, 521 }, 522 .p = { 523 .pre_div_shift = 3, 524 .pre_div_width = 2, 525 }, 526 .s = { 527 .src_sel_shift = 0, 528 .parent_map = gcc_pxo_pll8_map, 529 }, 530 .freq_tbl = clk_tbl_gsbi_uart, 531 .clkr = { 532 .enable_reg = 0x2ad4, 533 .enable_mask = BIT(11), 534 .hw.init = &(struct clk_init_data){ 535 .name = "gsbi9_uart_src", 536 .parent_names = gcc_pxo_pll8, 537 .num_parents = 2, 538 .ops = &clk_rcg_ops, 539 .flags = CLK_SET_PARENT_GATE, 540 }, 541 }, 542 }; 543 544 static struct clk_branch gsbi9_uart_clk = { 545 .halt_reg = 0x2fd0, 546 .halt_bit = 6, 547 .clkr = { 548 .enable_reg = 0x2ad4, 549 .enable_mask = BIT(9), 550 .hw.init = &(struct clk_init_data){ 551 .name = "gsbi9_uart_clk", 552 .parent_names = (const char *[]){ "gsbi9_uart_src" }, 553 .num_parents = 1, 554 .ops = &clk_branch_ops, 555 .flags = CLK_SET_RATE_PARENT, 556 }, 557 }, 558 }; 559 560 static struct clk_rcg gsbi10_uart_src = { 561 .ns_reg = 0x2af4, 562 .md_reg = 0x2af0, 563 .mn = { 564 .mnctr_en_bit = 8, 565 .mnctr_reset_bit = 7, 566 .mnctr_mode_shift = 5, 567 .n_val_shift = 16, 568 .m_val_shift = 16, 569 .width = 16, 570 }, 571 .p = { 572 .pre_div_shift = 3, 573 .pre_div_width = 2, 574 }, 575 .s = { 576 .src_sel_shift = 0, 577 .parent_map = gcc_pxo_pll8_map, 578 }, 579 .freq_tbl = clk_tbl_gsbi_uart, 580 .clkr = { 581 .enable_reg = 0x2af4, 582 .enable_mask = BIT(11), 583 .hw.init = &(struct clk_init_data){ 584 .name = "gsbi10_uart_src", 585 .parent_names = gcc_pxo_pll8, 586 .num_parents = 2, 587 .ops = &clk_rcg_ops, 588 .flags = CLK_SET_PARENT_GATE, 589 }, 590 }, 591 }; 592 593 static struct clk_branch gsbi10_uart_clk = { 594 .halt_reg = 0x2fd0, 595 .halt_bit = 2, 596 .clkr = { 597 .enable_reg = 0x2af4, 598 .enable_mask = BIT(9), 599 .hw.init = &(struct clk_init_data){ 600 .name = "gsbi10_uart_clk", 601 .parent_names = (const char *[]){ "gsbi10_uart_src" }, 602 .num_parents = 1, 603 .ops = &clk_branch_ops, 604 .flags = CLK_SET_RATE_PARENT, 605 }, 606 }, 607 }; 608 609 static struct clk_rcg gsbi11_uart_src = { 610 .ns_reg = 0x2b14, 611 .md_reg = 0x2b10, 612 .mn = { 613 .mnctr_en_bit = 8, 614 .mnctr_reset_bit = 7, 615 .mnctr_mode_shift = 5, 616 .n_val_shift = 16, 617 .m_val_shift = 16, 618 .width = 16, 619 }, 620 .p = { 621 .pre_div_shift = 3, 622 .pre_div_width = 2, 623 }, 624 .s = { 625 .src_sel_shift = 0, 626 .parent_map = gcc_pxo_pll8_map, 627 }, 628 .freq_tbl = clk_tbl_gsbi_uart, 629 .clkr = { 630 .enable_reg = 0x2b14, 631 .enable_mask = BIT(11), 632 .hw.init = &(struct clk_init_data){ 633 .name = "gsbi11_uart_src", 634 .parent_names = gcc_pxo_pll8, 635 .num_parents = 2, 636 .ops = &clk_rcg_ops, 637 .flags = CLK_SET_PARENT_GATE, 638 }, 639 }, 640 }; 641 642 static struct clk_branch gsbi11_uart_clk = { 643 .halt_reg = 0x2fd4, 644 .halt_bit = 17, 645 .clkr = { 646 .enable_reg = 0x2b14, 647 .enable_mask = BIT(9), 648 .hw.init = &(struct clk_init_data){ 649 .name = "gsbi11_uart_clk", 650 .parent_names = (const char *[]){ "gsbi11_uart_src" }, 651 .num_parents = 1, 652 .ops = &clk_branch_ops, 653 .flags = CLK_SET_RATE_PARENT, 654 }, 655 }, 656 }; 657 658 static struct clk_rcg gsbi12_uart_src = { 659 .ns_reg = 0x2b34, 660 .md_reg = 0x2b30, 661 .mn = { 662 .mnctr_en_bit = 8, 663 .mnctr_reset_bit = 7, 664 .mnctr_mode_shift = 5, 665 .n_val_shift = 16, 666 .m_val_shift = 16, 667 .width = 16, 668 }, 669 .p = { 670 .pre_div_shift = 3, 671 .pre_div_width = 2, 672 }, 673 .s = { 674 .src_sel_shift = 0, 675 .parent_map = gcc_pxo_pll8_map, 676 }, 677 .freq_tbl = clk_tbl_gsbi_uart, 678 .clkr = { 679 .enable_reg = 0x2b34, 680 .enable_mask = BIT(11), 681 .hw.init = &(struct clk_init_data){ 682 .name = "gsbi12_uart_src", 683 .parent_names = gcc_pxo_pll8, 684 .num_parents = 2, 685 .ops = &clk_rcg_ops, 686 .flags = CLK_SET_PARENT_GATE, 687 }, 688 }, 689 }; 690 691 static struct clk_branch gsbi12_uart_clk = { 692 .halt_reg = 0x2fd4, 693 .halt_bit = 13, 694 .clkr = { 695 .enable_reg = 0x2b34, 696 .enable_mask = BIT(9), 697 .hw.init = &(struct clk_init_data){ 698 .name = "gsbi12_uart_clk", 699 .parent_names = (const char *[]){ "gsbi12_uart_src" }, 700 .num_parents = 1, 701 .ops = &clk_branch_ops, 702 .flags = CLK_SET_RATE_PARENT, 703 }, 704 }, 705 }; 706 707 static struct freq_tbl clk_tbl_gsbi_qup[] = { 708 { 1100000, P_PXO, 1, 2, 49 }, 709 { 5400000, P_PXO, 1, 1, 5 }, 710 { 10800000, P_PXO, 1, 2, 5 }, 711 { 15060000, P_PLL8, 1, 2, 51 }, 712 { 24000000, P_PLL8, 4, 1, 4 }, 713 { 25600000, P_PLL8, 1, 1, 15 }, 714 { 27000000, P_PXO, 1, 0, 0 }, 715 { 48000000, P_PLL8, 4, 1, 2 }, 716 { 51200000, P_PLL8, 1, 2, 15 }, 717 { } 718 }; 719 720 static struct clk_rcg gsbi1_qup_src = { 721 .ns_reg = 0x29cc, 722 .md_reg = 0x29c8, 723 .mn = { 724 .mnctr_en_bit = 8, 725 .mnctr_reset_bit = 7, 726 .mnctr_mode_shift = 5, 727 .n_val_shift = 16, 728 .m_val_shift = 16, 729 .width = 8, 730 }, 731 .p = { 732 .pre_div_shift = 3, 733 .pre_div_width = 2, 734 }, 735 .s = { 736 .src_sel_shift = 0, 737 .parent_map = gcc_pxo_pll8_map, 738 }, 739 .freq_tbl = clk_tbl_gsbi_qup, 740 .clkr = { 741 .enable_reg = 0x29cc, 742 .enable_mask = BIT(11), 743 .hw.init = &(struct clk_init_data){ 744 .name = "gsbi1_qup_src", 745 .parent_names = gcc_pxo_pll8, 746 .num_parents = 2, 747 .ops = &clk_rcg_ops, 748 .flags = CLK_SET_PARENT_GATE, 749 }, 750 }, 751 }; 752 753 static struct clk_branch gsbi1_qup_clk = { 754 .halt_reg = 0x2fcc, 755 .halt_bit = 9, 756 .clkr = { 757 .enable_reg = 0x29cc, 758 .enable_mask = BIT(9), 759 .hw.init = &(struct clk_init_data){ 760 .name = "gsbi1_qup_clk", 761 .parent_names = (const char *[]){ "gsbi1_qup_src" }, 762 .num_parents = 1, 763 .ops = &clk_branch_ops, 764 .flags = CLK_SET_RATE_PARENT, 765 }, 766 }, 767 }; 768 769 static struct clk_rcg gsbi2_qup_src = { 770 .ns_reg = 0x29ec, 771 .md_reg = 0x29e8, 772 .mn = { 773 .mnctr_en_bit = 8, 774 .mnctr_reset_bit = 7, 775 .mnctr_mode_shift = 5, 776 .n_val_shift = 16, 777 .m_val_shift = 16, 778 .width = 8, 779 }, 780 .p = { 781 .pre_div_shift = 3, 782 .pre_div_width = 2, 783 }, 784 .s = { 785 .src_sel_shift = 0, 786 .parent_map = gcc_pxo_pll8_map, 787 }, 788 .freq_tbl = clk_tbl_gsbi_qup, 789 .clkr = { 790 .enable_reg = 0x29ec, 791 .enable_mask = BIT(11), 792 .hw.init = &(struct clk_init_data){ 793 .name = "gsbi2_qup_src", 794 .parent_names = gcc_pxo_pll8, 795 .num_parents = 2, 796 .ops = &clk_rcg_ops, 797 .flags = CLK_SET_PARENT_GATE, 798 }, 799 }, 800 }; 801 802 static struct clk_branch gsbi2_qup_clk = { 803 .halt_reg = 0x2fcc, 804 .halt_bit = 4, 805 .clkr = { 806 .enable_reg = 0x29ec, 807 .enable_mask = BIT(9), 808 .hw.init = &(struct clk_init_data){ 809 .name = "gsbi2_qup_clk", 810 .parent_names = (const char *[]){ "gsbi2_qup_src" }, 811 .num_parents = 1, 812 .ops = &clk_branch_ops, 813 .flags = CLK_SET_RATE_PARENT, 814 }, 815 }, 816 }; 817 818 static struct clk_rcg gsbi3_qup_src = { 819 .ns_reg = 0x2a0c, 820 .md_reg = 0x2a08, 821 .mn = { 822 .mnctr_en_bit = 8, 823 .mnctr_reset_bit = 7, 824 .mnctr_mode_shift = 5, 825 .n_val_shift = 16, 826 .m_val_shift = 16, 827 .width = 8, 828 }, 829 .p = { 830 .pre_div_shift = 3, 831 .pre_div_width = 2, 832 }, 833 .s = { 834 .src_sel_shift = 0, 835 .parent_map = gcc_pxo_pll8_map, 836 }, 837 .freq_tbl = clk_tbl_gsbi_qup, 838 .clkr = { 839 .enable_reg = 0x2a0c, 840 .enable_mask = BIT(11), 841 .hw.init = &(struct clk_init_data){ 842 .name = "gsbi3_qup_src", 843 .parent_names = gcc_pxo_pll8, 844 .num_parents = 2, 845 .ops = &clk_rcg_ops, 846 .flags = CLK_SET_PARENT_GATE, 847 }, 848 }, 849 }; 850 851 static struct clk_branch gsbi3_qup_clk = { 852 .halt_reg = 0x2fcc, 853 .halt_bit = 0, 854 .clkr = { 855 .enable_reg = 0x2a0c, 856 .enable_mask = BIT(9), 857 .hw.init = &(struct clk_init_data){ 858 .name = "gsbi3_qup_clk", 859 .parent_names = (const char *[]){ "gsbi3_qup_src" }, 860 .num_parents = 1, 861 .ops = &clk_branch_ops, 862 .flags = CLK_SET_RATE_PARENT, 863 }, 864 }, 865 }; 866 867 static struct clk_rcg gsbi4_qup_src = { 868 .ns_reg = 0x2a2c, 869 .md_reg = 0x2a28, 870 .mn = { 871 .mnctr_en_bit = 8, 872 .mnctr_reset_bit = 7, 873 .mnctr_mode_shift = 5, 874 .n_val_shift = 16, 875 .m_val_shift = 16, 876 .width = 8, 877 }, 878 .p = { 879 .pre_div_shift = 3, 880 .pre_div_width = 2, 881 }, 882 .s = { 883 .src_sel_shift = 0, 884 .parent_map = gcc_pxo_pll8_map, 885 }, 886 .freq_tbl = clk_tbl_gsbi_qup, 887 .clkr = { 888 .enable_reg = 0x2a2c, 889 .enable_mask = BIT(11), 890 .hw.init = &(struct clk_init_data){ 891 .name = "gsbi4_qup_src", 892 .parent_names = gcc_pxo_pll8, 893 .num_parents = 2, 894 .ops = &clk_rcg_ops, 895 .flags = CLK_SET_PARENT_GATE, 896 }, 897 }, 898 }; 899 900 static struct clk_branch gsbi4_qup_clk = { 901 .halt_reg = 0x2fd0, 902 .halt_bit = 24, 903 .clkr = { 904 .enable_reg = 0x2a2c, 905 .enable_mask = BIT(9), 906 .hw.init = &(struct clk_init_data){ 907 .name = "gsbi4_qup_clk", 908 .parent_names = (const char *[]){ "gsbi4_qup_src" }, 909 .num_parents = 1, 910 .ops = &clk_branch_ops, 911 .flags = CLK_SET_RATE_PARENT, 912 }, 913 }, 914 }; 915 916 static struct clk_rcg gsbi5_qup_src = { 917 .ns_reg = 0x2a4c, 918 .md_reg = 0x2a48, 919 .mn = { 920 .mnctr_en_bit = 8, 921 .mnctr_reset_bit = 7, 922 .mnctr_mode_shift = 5, 923 .n_val_shift = 16, 924 .m_val_shift = 16, 925 .width = 8, 926 }, 927 .p = { 928 .pre_div_shift = 3, 929 .pre_div_width = 2, 930 }, 931 .s = { 932 .src_sel_shift = 0, 933 .parent_map = gcc_pxo_pll8_map, 934 }, 935 .freq_tbl = clk_tbl_gsbi_qup, 936 .clkr = { 937 .enable_reg = 0x2a4c, 938 .enable_mask = BIT(11), 939 .hw.init = &(struct clk_init_data){ 940 .name = "gsbi5_qup_src", 941 .parent_names = gcc_pxo_pll8, 942 .num_parents = 2, 943 .ops = &clk_rcg_ops, 944 .flags = CLK_SET_PARENT_GATE, 945 }, 946 }, 947 }; 948 949 static struct clk_branch gsbi5_qup_clk = { 950 .halt_reg = 0x2fd0, 951 .halt_bit = 20, 952 .clkr = { 953 .enable_reg = 0x2a4c, 954 .enable_mask = BIT(9), 955 .hw.init = &(struct clk_init_data){ 956 .name = "gsbi5_qup_clk", 957 .parent_names = (const char *[]){ "gsbi5_qup_src" }, 958 .num_parents = 1, 959 .ops = &clk_branch_ops, 960 .flags = CLK_SET_RATE_PARENT, 961 }, 962 }, 963 }; 964 965 static struct clk_rcg gsbi6_qup_src = { 966 .ns_reg = 0x2a6c, 967 .md_reg = 0x2a68, 968 .mn = { 969 .mnctr_en_bit = 8, 970 .mnctr_reset_bit = 7, 971 .mnctr_mode_shift = 5, 972 .n_val_shift = 16, 973 .m_val_shift = 16, 974 .width = 8, 975 }, 976 .p = { 977 .pre_div_shift = 3, 978 .pre_div_width = 2, 979 }, 980 .s = { 981 .src_sel_shift = 0, 982 .parent_map = gcc_pxo_pll8_map, 983 }, 984 .freq_tbl = clk_tbl_gsbi_qup, 985 .clkr = { 986 .enable_reg = 0x2a6c, 987 .enable_mask = BIT(11), 988 .hw.init = &(struct clk_init_data){ 989 .name = "gsbi6_qup_src", 990 .parent_names = gcc_pxo_pll8, 991 .num_parents = 2, 992 .ops = &clk_rcg_ops, 993 .flags = CLK_SET_PARENT_GATE, 994 }, 995 }, 996 }; 997 998 static struct clk_branch gsbi6_qup_clk = { 999 .halt_reg = 0x2fd0, 1000 .halt_bit = 16, 1001 .clkr = { 1002 .enable_reg = 0x2a6c, 1003 .enable_mask = BIT(9), 1004 .hw.init = &(struct clk_init_data){ 1005 .name = "gsbi6_qup_clk", 1006 .parent_names = (const char *[]){ "gsbi6_qup_src" }, 1007 .num_parents = 1, 1008 .ops = &clk_branch_ops, 1009 .flags = CLK_SET_RATE_PARENT, 1010 }, 1011 }, 1012 }; 1013 1014 static struct clk_rcg gsbi7_qup_src = { 1015 .ns_reg = 0x2a8c, 1016 .md_reg = 0x2a88, 1017 .mn = { 1018 .mnctr_en_bit = 8, 1019 .mnctr_reset_bit = 7, 1020 .mnctr_mode_shift = 5, 1021 .n_val_shift = 16, 1022 .m_val_shift = 16, 1023 .width = 8, 1024 }, 1025 .p = { 1026 .pre_div_shift = 3, 1027 .pre_div_width = 2, 1028 }, 1029 .s = { 1030 .src_sel_shift = 0, 1031 .parent_map = gcc_pxo_pll8_map, 1032 }, 1033 .freq_tbl = clk_tbl_gsbi_qup, 1034 .clkr = { 1035 .enable_reg = 0x2a8c, 1036 .enable_mask = BIT(11), 1037 .hw.init = &(struct clk_init_data){ 1038 .name = "gsbi7_qup_src", 1039 .parent_names = gcc_pxo_pll8, 1040 .num_parents = 2, 1041 .ops = &clk_rcg_ops, 1042 .flags = CLK_SET_PARENT_GATE, 1043 }, 1044 }, 1045 }; 1046 1047 static struct clk_branch gsbi7_qup_clk = { 1048 .halt_reg = 0x2fd0, 1049 .halt_bit = 12, 1050 .clkr = { 1051 .enable_reg = 0x2a8c, 1052 .enable_mask = BIT(9), 1053 .hw.init = &(struct clk_init_data){ 1054 .name = "gsbi7_qup_clk", 1055 .parent_names = (const char *[]){ "gsbi7_qup_src" }, 1056 .num_parents = 1, 1057 .ops = &clk_branch_ops, 1058 .flags = CLK_SET_RATE_PARENT, 1059 }, 1060 }, 1061 }; 1062 1063 static struct clk_rcg gsbi8_qup_src = { 1064 .ns_reg = 0x2aac, 1065 .md_reg = 0x2aa8, 1066 .mn = { 1067 .mnctr_en_bit = 8, 1068 .mnctr_reset_bit = 7, 1069 .mnctr_mode_shift = 5, 1070 .n_val_shift = 16, 1071 .m_val_shift = 16, 1072 .width = 8, 1073 }, 1074 .p = { 1075 .pre_div_shift = 3, 1076 .pre_div_width = 2, 1077 }, 1078 .s = { 1079 .src_sel_shift = 0, 1080 .parent_map = gcc_pxo_pll8_map, 1081 }, 1082 .freq_tbl = clk_tbl_gsbi_qup, 1083 .clkr = { 1084 .enable_reg = 0x2aac, 1085 .enable_mask = BIT(11), 1086 .hw.init = &(struct clk_init_data){ 1087 .name = "gsbi8_qup_src", 1088 .parent_names = gcc_pxo_pll8, 1089 .num_parents = 2, 1090 .ops = &clk_rcg_ops, 1091 .flags = CLK_SET_PARENT_GATE, 1092 }, 1093 }, 1094 }; 1095 1096 static struct clk_branch gsbi8_qup_clk = { 1097 .halt_reg = 0x2fd0, 1098 .halt_bit = 8, 1099 .clkr = { 1100 .enable_reg = 0x2aac, 1101 .enable_mask = BIT(9), 1102 .hw.init = &(struct clk_init_data){ 1103 .name = "gsbi8_qup_clk", 1104 .parent_names = (const char *[]){ "gsbi8_qup_src" }, 1105 .num_parents = 1, 1106 .ops = &clk_branch_ops, 1107 .flags = CLK_SET_RATE_PARENT, 1108 }, 1109 }, 1110 }; 1111 1112 static struct clk_rcg gsbi9_qup_src = { 1113 .ns_reg = 0x2acc, 1114 .md_reg = 0x2ac8, 1115 .mn = { 1116 .mnctr_en_bit = 8, 1117 .mnctr_reset_bit = 7, 1118 .mnctr_mode_shift = 5, 1119 .n_val_shift = 16, 1120 .m_val_shift = 16, 1121 .width = 8, 1122 }, 1123 .p = { 1124 .pre_div_shift = 3, 1125 .pre_div_width = 2, 1126 }, 1127 .s = { 1128 .src_sel_shift = 0, 1129 .parent_map = gcc_pxo_pll8_map, 1130 }, 1131 .freq_tbl = clk_tbl_gsbi_qup, 1132 .clkr = { 1133 .enable_reg = 0x2acc, 1134 .enable_mask = BIT(11), 1135 .hw.init = &(struct clk_init_data){ 1136 .name = "gsbi9_qup_src", 1137 .parent_names = gcc_pxo_pll8, 1138 .num_parents = 2, 1139 .ops = &clk_rcg_ops, 1140 .flags = CLK_SET_PARENT_GATE, 1141 }, 1142 }, 1143 }; 1144 1145 static struct clk_branch gsbi9_qup_clk = { 1146 .halt_reg = 0x2fd0, 1147 .halt_bit = 4, 1148 .clkr = { 1149 .enable_reg = 0x2acc, 1150 .enable_mask = BIT(9), 1151 .hw.init = &(struct clk_init_data){ 1152 .name = "gsbi9_qup_clk", 1153 .parent_names = (const char *[]){ "gsbi9_qup_src" }, 1154 .num_parents = 1, 1155 .ops = &clk_branch_ops, 1156 .flags = CLK_SET_RATE_PARENT, 1157 }, 1158 }, 1159 }; 1160 1161 static struct clk_rcg gsbi10_qup_src = { 1162 .ns_reg = 0x2aec, 1163 .md_reg = 0x2ae8, 1164 .mn = { 1165 .mnctr_en_bit = 8, 1166 .mnctr_reset_bit = 7, 1167 .mnctr_mode_shift = 5, 1168 .n_val_shift = 16, 1169 .m_val_shift = 16, 1170 .width = 8, 1171 }, 1172 .p = { 1173 .pre_div_shift = 3, 1174 .pre_div_width = 2, 1175 }, 1176 .s = { 1177 .src_sel_shift = 0, 1178 .parent_map = gcc_pxo_pll8_map, 1179 }, 1180 .freq_tbl = clk_tbl_gsbi_qup, 1181 .clkr = { 1182 .enable_reg = 0x2aec, 1183 .enable_mask = BIT(11), 1184 .hw.init = &(struct clk_init_data){ 1185 .name = "gsbi10_qup_src", 1186 .parent_names = gcc_pxo_pll8, 1187 .num_parents = 2, 1188 .ops = &clk_rcg_ops, 1189 .flags = CLK_SET_PARENT_GATE, 1190 }, 1191 }, 1192 }; 1193 1194 static struct clk_branch gsbi10_qup_clk = { 1195 .halt_reg = 0x2fd0, 1196 .halt_bit = 0, 1197 .clkr = { 1198 .enable_reg = 0x2aec, 1199 .enable_mask = BIT(9), 1200 .hw.init = &(struct clk_init_data){ 1201 .name = "gsbi10_qup_clk", 1202 .parent_names = (const char *[]){ "gsbi10_qup_src" }, 1203 .num_parents = 1, 1204 .ops = &clk_branch_ops, 1205 .flags = CLK_SET_RATE_PARENT, 1206 }, 1207 }, 1208 }; 1209 1210 static struct clk_rcg gsbi11_qup_src = { 1211 .ns_reg = 0x2b0c, 1212 .md_reg = 0x2b08, 1213 .mn = { 1214 .mnctr_en_bit = 8, 1215 .mnctr_reset_bit = 7, 1216 .mnctr_mode_shift = 5, 1217 .n_val_shift = 16, 1218 .m_val_shift = 16, 1219 .width = 8, 1220 }, 1221 .p = { 1222 .pre_div_shift = 3, 1223 .pre_div_width = 2, 1224 }, 1225 .s = { 1226 .src_sel_shift = 0, 1227 .parent_map = gcc_pxo_pll8_map, 1228 }, 1229 .freq_tbl = clk_tbl_gsbi_qup, 1230 .clkr = { 1231 .enable_reg = 0x2b0c, 1232 .enable_mask = BIT(11), 1233 .hw.init = &(struct clk_init_data){ 1234 .name = "gsbi11_qup_src", 1235 .parent_names = gcc_pxo_pll8, 1236 .num_parents = 2, 1237 .ops = &clk_rcg_ops, 1238 .flags = CLK_SET_PARENT_GATE, 1239 }, 1240 }, 1241 }; 1242 1243 static struct clk_branch gsbi11_qup_clk = { 1244 .halt_reg = 0x2fd4, 1245 .halt_bit = 15, 1246 .clkr = { 1247 .enable_reg = 0x2b0c, 1248 .enable_mask = BIT(9), 1249 .hw.init = &(struct clk_init_data){ 1250 .name = "gsbi11_qup_clk", 1251 .parent_names = (const char *[]){ "gsbi11_qup_src" }, 1252 .num_parents = 1, 1253 .ops = &clk_branch_ops, 1254 .flags = CLK_SET_RATE_PARENT, 1255 }, 1256 }, 1257 }; 1258 1259 static struct clk_rcg gsbi12_qup_src = { 1260 .ns_reg = 0x2b2c, 1261 .md_reg = 0x2b28, 1262 .mn = { 1263 .mnctr_en_bit = 8, 1264 .mnctr_reset_bit = 7, 1265 .mnctr_mode_shift = 5, 1266 .n_val_shift = 16, 1267 .m_val_shift = 16, 1268 .width = 8, 1269 }, 1270 .p = { 1271 .pre_div_shift = 3, 1272 .pre_div_width = 2, 1273 }, 1274 .s = { 1275 .src_sel_shift = 0, 1276 .parent_map = gcc_pxo_pll8_map, 1277 }, 1278 .freq_tbl = clk_tbl_gsbi_qup, 1279 .clkr = { 1280 .enable_reg = 0x2b2c, 1281 .enable_mask = BIT(11), 1282 .hw.init = &(struct clk_init_data){ 1283 .name = "gsbi12_qup_src", 1284 .parent_names = gcc_pxo_pll8, 1285 .num_parents = 2, 1286 .ops = &clk_rcg_ops, 1287 .flags = CLK_SET_PARENT_GATE, 1288 }, 1289 }, 1290 }; 1291 1292 static struct clk_branch gsbi12_qup_clk = { 1293 .halt_reg = 0x2fd4, 1294 .halt_bit = 11, 1295 .clkr = { 1296 .enable_reg = 0x2b2c, 1297 .enable_mask = BIT(9), 1298 .hw.init = &(struct clk_init_data){ 1299 .name = "gsbi12_qup_clk", 1300 .parent_names = (const char *[]){ "gsbi12_qup_src" }, 1301 .num_parents = 1, 1302 .ops = &clk_branch_ops, 1303 .flags = CLK_SET_RATE_PARENT, 1304 }, 1305 }, 1306 }; 1307 1308 static const struct freq_tbl clk_tbl_gp[] = { 1309 { 9600000, P_CXO, 2, 0, 0 }, 1310 { 13500000, P_PXO, 2, 0, 0 }, 1311 { 19200000, P_CXO, 1, 0, 0 }, 1312 { 27000000, P_PXO, 1, 0, 0 }, 1313 { 64000000, P_PLL8, 2, 1, 3 }, 1314 { 76800000, P_PLL8, 1, 1, 5 }, 1315 { 96000000, P_PLL8, 4, 0, 0 }, 1316 { 128000000, P_PLL8, 3, 0, 0 }, 1317 { 192000000, P_PLL8, 2, 0, 0 }, 1318 { } 1319 }; 1320 1321 static struct clk_rcg gp0_src = { 1322 .ns_reg = 0x2d24, 1323 .md_reg = 0x2d00, 1324 .mn = { 1325 .mnctr_en_bit = 8, 1326 .mnctr_reset_bit = 7, 1327 .mnctr_mode_shift = 5, 1328 .n_val_shift = 16, 1329 .m_val_shift = 16, 1330 .width = 8, 1331 }, 1332 .p = { 1333 .pre_div_shift = 3, 1334 .pre_div_width = 2, 1335 }, 1336 .s = { 1337 .src_sel_shift = 0, 1338 .parent_map = gcc_pxo_pll8_cxo_map, 1339 }, 1340 .freq_tbl = clk_tbl_gp, 1341 .clkr = { 1342 .enable_reg = 0x2d24, 1343 .enable_mask = BIT(11), 1344 .hw.init = &(struct clk_init_data){ 1345 .name = "gp0_src", 1346 .parent_names = gcc_pxo_pll8_cxo, 1347 .num_parents = 3, 1348 .ops = &clk_rcg_ops, 1349 .flags = CLK_SET_PARENT_GATE, 1350 }, 1351 } 1352 }; 1353 1354 static struct clk_branch gp0_clk = { 1355 .halt_reg = 0x2fd8, 1356 .halt_bit = 7, 1357 .clkr = { 1358 .enable_reg = 0x2d24, 1359 .enable_mask = BIT(9), 1360 .hw.init = &(struct clk_init_data){ 1361 .name = "gp0_clk", 1362 .parent_names = (const char *[]){ "gp0_src" }, 1363 .num_parents = 1, 1364 .ops = &clk_branch_ops, 1365 .flags = CLK_SET_RATE_PARENT, 1366 }, 1367 }, 1368 }; 1369 1370 static struct clk_rcg gp1_src = { 1371 .ns_reg = 0x2d44, 1372 .md_reg = 0x2d40, 1373 .mn = { 1374 .mnctr_en_bit = 8, 1375 .mnctr_reset_bit = 7, 1376 .mnctr_mode_shift = 5, 1377 .n_val_shift = 16, 1378 .m_val_shift = 16, 1379 .width = 8, 1380 }, 1381 .p = { 1382 .pre_div_shift = 3, 1383 .pre_div_width = 2, 1384 }, 1385 .s = { 1386 .src_sel_shift = 0, 1387 .parent_map = gcc_pxo_pll8_cxo_map, 1388 }, 1389 .freq_tbl = clk_tbl_gp, 1390 .clkr = { 1391 .enable_reg = 0x2d44, 1392 .enable_mask = BIT(11), 1393 .hw.init = &(struct clk_init_data){ 1394 .name = "gp1_src", 1395 .parent_names = gcc_pxo_pll8_cxo, 1396 .num_parents = 3, 1397 .ops = &clk_rcg_ops, 1398 .flags = CLK_SET_RATE_GATE, 1399 }, 1400 } 1401 }; 1402 1403 static struct clk_branch gp1_clk = { 1404 .halt_reg = 0x2fd8, 1405 .halt_bit = 6, 1406 .clkr = { 1407 .enable_reg = 0x2d44, 1408 .enable_mask = BIT(9), 1409 .hw.init = &(struct clk_init_data){ 1410 .name = "gp1_clk", 1411 .parent_names = (const char *[]){ "gp1_src" }, 1412 .num_parents = 1, 1413 .ops = &clk_branch_ops, 1414 .flags = CLK_SET_RATE_PARENT, 1415 }, 1416 }, 1417 }; 1418 1419 static struct clk_rcg gp2_src = { 1420 .ns_reg = 0x2d64, 1421 .md_reg = 0x2d60, 1422 .mn = { 1423 .mnctr_en_bit = 8, 1424 .mnctr_reset_bit = 7, 1425 .mnctr_mode_shift = 5, 1426 .n_val_shift = 16, 1427 .m_val_shift = 16, 1428 .width = 8, 1429 }, 1430 .p = { 1431 .pre_div_shift = 3, 1432 .pre_div_width = 2, 1433 }, 1434 .s = { 1435 .src_sel_shift = 0, 1436 .parent_map = gcc_pxo_pll8_cxo_map, 1437 }, 1438 .freq_tbl = clk_tbl_gp, 1439 .clkr = { 1440 .enable_reg = 0x2d64, 1441 .enable_mask = BIT(11), 1442 .hw.init = &(struct clk_init_data){ 1443 .name = "gp2_src", 1444 .parent_names = gcc_pxo_pll8_cxo, 1445 .num_parents = 3, 1446 .ops = &clk_rcg_ops, 1447 .flags = CLK_SET_RATE_GATE, 1448 }, 1449 } 1450 }; 1451 1452 static struct clk_branch gp2_clk = { 1453 .halt_reg = 0x2fd8, 1454 .halt_bit = 5, 1455 .clkr = { 1456 .enable_reg = 0x2d64, 1457 .enable_mask = BIT(9), 1458 .hw.init = &(struct clk_init_data){ 1459 .name = "gp2_clk", 1460 .parent_names = (const char *[]){ "gp2_src" }, 1461 .num_parents = 1, 1462 .ops = &clk_branch_ops, 1463 .flags = CLK_SET_RATE_PARENT, 1464 }, 1465 }, 1466 }; 1467 1468 static struct clk_branch pmem_clk = { 1469 .hwcg_reg = 0x25a0, 1470 .hwcg_bit = 6, 1471 .halt_reg = 0x2fc8, 1472 .halt_bit = 20, 1473 .clkr = { 1474 .enable_reg = 0x25a0, 1475 .enable_mask = BIT(4), 1476 .hw.init = &(struct clk_init_data){ 1477 .name = "pmem_clk", 1478 .ops = &clk_branch_ops, 1479 .flags = CLK_IS_ROOT, 1480 }, 1481 }, 1482 }; 1483 1484 static struct clk_rcg prng_src = { 1485 .ns_reg = 0x2e80, 1486 .p = { 1487 .pre_div_shift = 3, 1488 .pre_div_width = 4, 1489 }, 1490 .s = { 1491 .src_sel_shift = 0, 1492 .parent_map = gcc_pxo_pll8_map, 1493 }, 1494 .clkr.hw = { 1495 .init = &(struct clk_init_data){ 1496 .name = "prng_src", 1497 .parent_names = gcc_pxo_pll8, 1498 .num_parents = 2, 1499 .ops = &clk_rcg_ops, 1500 }, 1501 }, 1502 }; 1503 1504 static struct clk_branch prng_clk = { 1505 .halt_reg = 0x2fd8, 1506 .halt_check = BRANCH_HALT_VOTED, 1507 .halt_bit = 10, 1508 .clkr = { 1509 .enable_reg = 0x3080, 1510 .enable_mask = BIT(10), 1511 .hw.init = &(struct clk_init_data){ 1512 .name = "prng_clk", 1513 .parent_names = (const char *[]){ "prng_src" }, 1514 .num_parents = 1, 1515 .ops = &clk_branch_ops, 1516 }, 1517 }, 1518 }; 1519 1520 static const struct freq_tbl clk_tbl_sdc[] = { 1521 { 144000, P_PXO, 3, 2, 125 }, 1522 { 400000, P_PLL8, 4, 1, 240 }, 1523 { 16000000, P_PLL8, 4, 1, 6 }, 1524 { 17070000, P_PLL8, 1, 2, 45 }, 1525 { 20210000, P_PLL8, 1, 1, 19 }, 1526 { 24000000, P_PLL8, 4, 1, 4 }, 1527 { 48000000, P_PLL8, 4, 1, 2 }, 1528 { } 1529 }; 1530 1531 static struct clk_rcg sdc1_src = { 1532 .ns_reg = 0x282c, 1533 .md_reg = 0x2828, 1534 .mn = { 1535 .mnctr_en_bit = 8, 1536 .mnctr_reset_bit = 7, 1537 .mnctr_mode_shift = 5, 1538 .n_val_shift = 16, 1539 .m_val_shift = 16, 1540 .width = 8, 1541 }, 1542 .p = { 1543 .pre_div_shift = 3, 1544 .pre_div_width = 2, 1545 }, 1546 .s = { 1547 .src_sel_shift = 0, 1548 .parent_map = gcc_pxo_pll8_map, 1549 }, 1550 .freq_tbl = clk_tbl_sdc, 1551 .clkr = { 1552 .enable_reg = 0x282c, 1553 .enable_mask = BIT(11), 1554 .hw.init = &(struct clk_init_data){ 1555 .name = "sdc1_src", 1556 .parent_names = gcc_pxo_pll8, 1557 .num_parents = 2, 1558 .ops = &clk_rcg_ops, 1559 .flags = CLK_SET_RATE_GATE, 1560 }, 1561 } 1562 }; 1563 1564 static struct clk_branch sdc1_clk = { 1565 .halt_reg = 0x2fc8, 1566 .halt_bit = 6, 1567 .clkr = { 1568 .enable_reg = 0x282c, 1569 .enable_mask = BIT(9), 1570 .hw.init = &(struct clk_init_data){ 1571 .name = "sdc1_clk", 1572 .parent_names = (const char *[]){ "sdc1_src" }, 1573 .num_parents = 1, 1574 .ops = &clk_branch_ops, 1575 .flags = CLK_SET_RATE_PARENT, 1576 }, 1577 }, 1578 }; 1579 1580 static struct clk_rcg sdc2_src = { 1581 .ns_reg = 0x284c, 1582 .md_reg = 0x2848, 1583 .mn = { 1584 .mnctr_en_bit = 8, 1585 .mnctr_reset_bit = 7, 1586 .mnctr_mode_shift = 5, 1587 .n_val_shift = 16, 1588 .m_val_shift = 16, 1589 .width = 8, 1590 }, 1591 .p = { 1592 .pre_div_shift = 3, 1593 .pre_div_width = 2, 1594 }, 1595 .s = { 1596 .src_sel_shift = 0, 1597 .parent_map = gcc_pxo_pll8_map, 1598 }, 1599 .freq_tbl = clk_tbl_sdc, 1600 .clkr = { 1601 .enable_reg = 0x284c, 1602 .enable_mask = BIT(11), 1603 .hw.init = &(struct clk_init_data){ 1604 .name = "sdc2_src", 1605 .parent_names = gcc_pxo_pll8, 1606 .num_parents = 2, 1607 .ops = &clk_rcg_ops, 1608 .flags = CLK_SET_RATE_GATE, 1609 }, 1610 } 1611 }; 1612 1613 static struct clk_branch sdc2_clk = { 1614 .halt_reg = 0x2fc8, 1615 .halt_bit = 5, 1616 .clkr = { 1617 .enable_reg = 0x284c, 1618 .enable_mask = BIT(9), 1619 .hw.init = &(struct clk_init_data){ 1620 .name = "sdc2_clk", 1621 .parent_names = (const char *[]){ "sdc2_src" }, 1622 .num_parents = 1, 1623 .ops = &clk_branch_ops, 1624 .flags = CLK_SET_RATE_PARENT, 1625 }, 1626 }, 1627 }; 1628 1629 static struct clk_rcg sdc3_src = { 1630 .ns_reg = 0x286c, 1631 .md_reg = 0x2868, 1632 .mn = { 1633 .mnctr_en_bit = 8, 1634 .mnctr_reset_bit = 7, 1635 .mnctr_mode_shift = 5, 1636 .n_val_shift = 16, 1637 .m_val_shift = 16, 1638 .width = 8, 1639 }, 1640 .p = { 1641 .pre_div_shift = 3, 1642 .pre_div_width = 2, 1643 }, 1644 .s = { 1645 .src_sel_shift = 0, 1646 .parent_map = gcc_pxo_pll8_map, 1647 }, 1648 .freq_tbl = clk_tbl_sdc, 1649 .clkr = { 1650 .enable_reg = 0x286c, 1651 .enable_mask = BIT(11), 1652 .hw.init = &(struct clk_init_data){ 1653 .name = "sdc3_src", 1654 .parent_names = gcc_pxo_pll8, 1655 .num_parents = 2, 1656 .ops = &clk_rcg_ops, 1657 .flags = CLK_SET_RATE_GATE, 1658 }, 1659 } 1660 }; 1661 1662 static struct clk_branch sdc3_clk = { 1663 .halt_reg = 0x2fc8, 1664 .halt_bit = 4, 1665 .clkr = { 1666 .enable_reg = 0x286c, 1667 .enable_mask = BIT(9), 1668 .hw.init = &(struct clk_init_data){ 1669 .name = "sdc3_clk", 1670 .parent_names = (const char *[]){ "sdc3_src" }, 1671 .num_parents = 1, 1672 .ops = &clk_branch_ops, 1673 .flags = CLK_SET_RATE_PARENT, 1674 }, 1675 }, 1676 }; 1677 1678 static struct clk_rcg sdc4_src = { 1679 .ns_reg = 0x288c, 1680 .md_reg = 0x2888, 1681 .mn = { 1682 .mnctr_en_bit = 8, 1683 .mnctr_reset_bit = 7, 1684 .mnctr_mode_shift = 5, 1685 .n_val_shift = 16, 1686 .m_val_shift = 16, 1687 .width = 8, 1688 }, 1689 .p = { 1690 .pre_div_shift = 3, 1691 .pre_div_width = 2, 1692 }, 1693 .s = { 1694 .src_sel_shift = 0, 1695 .parent_map = gcc_pxo_pll8_map, 1696 }, 1697 .freq_tbl = clk_tbl_sdc, 1698 .clkr = { 1699 .enable_reg = 0x288c, 1700 .enable_mask = BIT(11), 1701 .hw.init = &(struct clk_init_data){ 1702 .name = "sdc4_src", 1703 .parent_names = gcc_pxo_pll8, 1704 .num_parents = 2, 1705 .ops = &clk_rcg_ops, 1706 .flags = CLK_SET_RATE_GATE, 1707 }, 1708 } 1709 }; 1710 1711 static struct clk_branch sdc4_clk = { 1712 .halt_reg = 0x2fc8, 1713 .halt_bit = 3, 1714 .clkr = { 1715 .enable_reg = 0x288c, 1716 .enable_mask = BIT(9), 1717 .hw.init = &(struct clk_init_data){ 1718 .name = "sdc4_clk", 1719 .parent_names = (const char *[]){ "sdc4_src" }, 1720 .num_parents = 1, 1721 .ops = &clk_branch_ops, 1722 .flags = CLK_SET_RATE_PARENT, 1723 }, 1724 }, 1725 }; 1726 1727 static struct clk_rcg sdc5_src = { 1728 .ns_reg = 0x28ac, 1729 .md_reg = 0x28a8, 1730 .mn = { 1731 .mnctr_en_bit = 8, 1732 .mnctr_reset_bit = 7, 1733 .mnctr_mode_shift = 5, 1734 .n_val_shift = 16, 1735 .m_val_shift = 16, 1736 .width = 8, 1737 }, 1738 .p = { 1739 .pre_div_shift = 3, 1740 .pre_div_width = 2, 1741 }, 1742 .s = { 1743 .src_sel_shift = 0, 1744 .parent_map = gcc_pxo_pll8_map, 1745 }, 1746 .freq_tbl = clk_tbl_sdc, 1747 .clkr = { 1748 .enable_reg = 0x28ac, 1749 .enable_mask = BIT(11), 1750 .hw.init = &(struct clk_init_data){ 1751 .name = "sdc5_src", 1752 .parent_names = gcc_pxo_pll8, 1753 .num_parents = 2, 1754 .ops = &clk_rcg_ops, 1755 .flags = CLK_SET_RATE_GATE, 1756 }, 1757 } 1758 }; 1759 1760 static struct clk_branch sdc5_clk = { 1761 .halt_reg = 0x2fc8, 1762 .halt_bit = 2, 1763 .clkr = { 1764 .enable_reg = 0x28ac, 1765 .enable_mask = BIT(9), 1766 .hw.init = &(struct clk_init_data){ 1767 .name = "sdc5_clk", 1768 .parent_names = (const char *[]){ "sdc5_src" }, 1769 .num_parents = 1, 1770 .ops = &clk_branch_ops, 1771 .flags = CLK_SET_RATE_PARENT, 1772 }, 1773 }, 1774 }; 1775 1776 static const struct freq_tbl clk_tbl_tsif_ref[] = { 1777 { 105000, P_PXO, 1, 1, 256 }, 1778 { } 1779 }; 1780 1781 static struct clk_rcg tsif_ref_src = { 1782 .ns_reg = 0x2710, 1783 .md_reg = 0x270c, 1784 .mn = { 1785 .mnctr_en_bit = 8, 1786 .mnctr_reset_bit = 7, 1787 .mnctr_mode_shift = 5, 1788 .n_val_shift = 16, 1789 .m_val_shift = 16, 1790 .width = 16, 1791 }, 1792 .p = { 1793 .pre_div_shift = 3, 1794 .pre_div_width = 2, 1795 }, 1796 .s = { 1797 .src_sel_shift = 0, 1798 .parent_map = gcc_pxo_pll8_map, 1799 }, 1800 .freq_tbl = clk_tbl_tsif_ref, 1801 .clkr = { 1802 .enable_reg = 0x2710, 1803 .enable_mask = BIT(11), 1804 .hw.init = &(struct clk_init_data){ 1805 .name = "tsif_ref_src", 1806 .parent_names = gcc_pxo_pll8, 1807 .num_parents = 2, 1808 .ops = &clk_rcg_ops, 1809 .flags = CLK_SET_RATE_GATE, 1810 }, 1811 } 1812 }; 1813 1814 static struct clk_branch tsif_ref_clk = { 1815 .halt_reg = 0x2fd4, 1816 .halt_bit = 5, 1817 .clkr = { 1818 .enable_reg = 0x2710, 1819 .enable_mask = BIT(9), 1820 .hw.init = &(struct clk_init_data){ 1821 .name = "tsif_ref_clk", 1822 .parent_names = (const char *[]){ "tsif_ref_src" }, 1823 .num_parents = 1, 1824 .ops = &clk_branch_ops, 1825 .flags = CLK_SET_RATE_PARENT, 1826 }, 1827 }, 1828 }; 1829 1830 static const struct freq_tbl clk_tbl_usb[] = { 1831 { 60000000, P_PLL8, 1, 5, 32 }, 1832 { } 1833 }; 1834 1835 static struct clk_rcg usb_hs1_xcvr_src = { 1836 .ns_reg = 0x290c, 1837 .md_reg = 0x2908, 1838 .mn = { 1839 .mnctr_en_bit = 8, 1840 .mnctr_reset_bit = 7, 1841 .mnctr_mode_shift = 5, 1842 .n_val_shift = 16, 1843 .m_val_shift = 16, 1844 .width = 8, 1845 }, 1846 .p = { 1847 .pre_div_shift = 3, 1848 .pre_div_width = 2, 1849 }, 1850 .s = { 1851 .src_sel_shift = 0, 1852 .parent_map = gcc_pxo_pll8_map, 1853 }, 1854 .freq_tbl = clk_tbl_usb, 1855 .clkr = { 1856 .enable_reg = 0x290c, 1857 .enable_mask = BIT(11), 1858 .hw.init = &(struct clk_init_data){ 1859 .name = "usb_hs1_xcvr_src", 1860 .parent_names = gcc_pxo_pll8, 1861 .num_parents = 2, 1862 .ops = &clk_rcg_ops, 1863 .flags = CLK_SET_RATE_GATE, 1864 }, 1865 } 1866 }; 1867 1868 static struct clk_branch usb_hs1_xcvr_clk = { 1869 .halt_reg = 0x2fc8, 1870 .halt_bit = 0, 1871 .clkr = { 1872 .enable_reg = 0x290c, 1873 .enable_mask = BIT(9), 1874 .hw.init = &(struct clk_init_data){ 1875 .name = "usb_hs1_xcvr_clk", 1876 .parent_names = (const char *[]){ "usb_hs1_xcvr_src" }, 1877 .num_parents = 1, 1878 .ops = &clk_branch_ops, 1879 .flags = CLK_SET_RATE_PARENT, 1880 }, 1881 }, 1882 }; 1883 1884 static struct clk_rcg usb_fs1_xcvr_fs_src = { 1885 .ns_reg = 0x2968, 1886 .md_reg = 0x2964, 1887 .mn = { 1888 .mnctr_en_bit = 8, 1889 .mnctr_reset_bit = 7, 1890 .mnctr_mode_shift = 5, 1891 .n_val_shift = 16, 1892 .m_val_shift = 16, 1893 .width = 8, 1894 }, 1895 .p = { 1896 .pre_div_shift = 3, 1897 .pre_div_width = 2, 1898 }, 1899 .s = { 1900 .src_sel_shift = 0, 1901 .parent_map = gcc_pxo_pll8_map, 1902 }, 1903 .freq_tbl = clk_tbl_usb, 1904 .clkr = { 1905 .enable_reg = 0x2968, 1906 .enable_mask = BIT(11), 1907 .hw.init = &(struct clk_init_data){ 1908 .name = "usb_fs1_xcvr_fs_src", 1909 .parent_names = gcc_pxo_pll8, 1910 .num_parents = 2, 1911 .ops = &clk_rcg_ops, 1912 .flags = CLK_SET_RATE_GATE, 1913 }, 1914 } 1915 }; 1916 1917 static const char *usb_fs1_xcvr_fs_src_p[] = { "usb_fs1_xcvr_fs_src" }; 1918 1919 static struct clk_branch usb_fs1_xcvr_fs_clk = { 1920 .halt_reg = 0x2fcc, 1921 .halt_bit = 15, 1922 .clkr = { 1923 .enable_reg = 0x2968, 1924 .enable_mask = BIT(9), 1925 .hw.init = &(struct clk_init_data){ 1926 .name = "usb_fs1_xcvr_fs_clk", 1927 .parent_names = usb_fs1_xcvr_fs_src_p, 1928 .num_parents = 1, 1929 .ops = &clk_branch_ops, 1930 .flags = CLK_SET_RATE_PARENT, 1931 }, 1932 }, 1933 }; 1934 1935 static struct clk_branch usb_fs1_system_clk = { 1936 .halt_reg = 0x2fcc, 1937 .halt_bit = 16, 1938 .clkr = { 1939 .enable_reg = 0x296c, 1940 .enable_mask = BIT(4), 1941 .hw.init = &(struct clk_init_data){ 1942 .parent_names = usb_fs1_xcvr_fs_src_p, 1943 .num_parents = 1, 1944 .name = "usb_fs1_system_clk", 1945 .ops = &clk_branch_ops, 1946 .flags = CLK_SET_RATE_PARENT, 1947 }, 1948 }, 1949 }; 1950 1951 static struct clk_rcg usb_fs2_xcvr_fs_src = { 1952 .ns_reg = 0x2988, 1953 .md_reg = 0x2984, 1954 .mn = { 1955 .mnctr_en_bit = 8, 1956 .mnctr_reset_bit = 7, 1957 .mnctr_mode_shift = 5, 1958 .n_val_shift = 16, 1959 .m_val_shift = 16, 1960 .width = 8, 1961 }, 1962 .p = { 1963 .pre_div_shift = 3, 1964 .pre_div_width = 2, 1965 }, 1966 .s = { 1967 .src_sel_shift = 0, 1968 .parent_map = gcc_pxo_pll8_map, 1969 }, 1970 .freq_tbl = clk_tbl_usb, 1971 .clkr = { 1972 .enable_reg = 0x2988, 1973 .enable_mask = BIT(11), 1974 .hw.init = &(struct clk_init_data){ 1975 .name = "usb_fs2_xcvr_fs_src", 1976 .parent_names = gcc_pxo_pll8, 1977 .num_parents = 2, 1978 .ops = &clk_rcg_ops, 1979 .flags = CLK_SET_RATE_GATE, 1980 }, 1981 } 1982 }; 1983 1984 static const char *usb_fs2_xcvr_fs_src_p[] = { "usb_fs2_xcvr_fs_src" }; 1985 1986 static struct clk_branch usb_fs2_xcvr_fs_clk = { 1987 .halt_reg = 0x2fcc, 1988 .halt_bit = 12, 1989 .clkr = { 1990 .enable_reg = 0x2988, 1991 .enable_mask = BIT(9), 1992 .hw.init = &(struct clk_init_data){ 1993 .name = "usb_fs2_xcvr_fs_clk", 1994 .parent_names = usb_fs2_xcvr_fs_src_p, 1995 .num_parents = 1, 1996 .ops = &clk_branch_ops, 1997 .flags = CLK_SET_RATE_PARENT, 1998 }, 1999 }, 2000 }; 2001 2002 static struct clk_branch usb_fs2_system_clk = { 2003 .halt_reg = 0x2fcc, 2004 .halt_bit = 13, 2005 .clkr = { 2006 .enable_reg = 0x298c, 2007 .enable_mask = BIT(4), 2008 .hw.init = &(struct clk_init_data){ 2009 .name = "usb_fs2_system_clk", 2010 .parent_names = usb_fs2_xcvr_fs_src_p, 2011 .num_parents = 1, 2012 .ops = &clk_branch_ops, 2013 .flags = CLK_SET_RATE_PARENT, 2014 }, 2015 }, 2016 }; 2017 2018 static struct clk_branch gsbi1_h_clk = { 2019 .halt_reg = 0x2fcc, 2020 .halt_bit = 11, 2021 .clkr = { 2022 .enable_reg = 0x29c0, 2023 .enable_mask = BIT(4), 2024 .hw.init = &(struct clk_init_data){ 2025 .name = "gsbi1_h_clk", 2026 .ops = &clk_branch_ops, 2027 .flags = CLK_IS_ROOT, 2028 }, 2029 }, 2030 }; 2031 2032 static struct clk_branch gsbi2_h_clk = { 2033 .halt_reg = 0x2fcc, 2034 .halt_bit = 7, 2035 .clkr = { 2036 .enable_reg = 0x29e0, 2037 .enable_mask = BIT(4), 2038 .hw.init = &(struct clk_init_data){ 2039 .name = "gsbi2_h_clk", 2040 .ops = &clk_branch_ops, 2041 .flags = CLK_IS_ROOT, 2042 }, 2043 }, 2044 }; 2045 2046 static struct clk_branch gsbi3_h_clk = { 2047 .halt_reg = 0x2fcc, 2048 .halt_bit = 3, 2049 .clkr = { 2050 .enable_reg = 0x2a00, 2051 .enable_mask = BIT(4), 2052 .hw.init = &(struct clk_init_data){ 2053 .name = "gsbi3_h_clk", 2054 .ops = &clk_branch_ops, 2055 .flags = CLK_IS_ROOT, 2056 }, 2057 }, 2058 }; 2059 2060 static struct clk_branch gsbi4_h_clk = { 2061 .halt_reg = 0x2fd0, 2062 .halt_bit = 27, 2063 .clkr = { 2064 .enable_reg = 0x2a20, 2065 .enable_mask = BIT(4), 2066 .hw.init = &(struct clk_init_data){ 2067 .name = "gsbi4_h_clk", 2068 .ops = &clk_branch_ops, 2069 .flags = CLK_IS_ROOT, 2070 }, 2071 }, 2072 }; 2073 2074 static struct clk_branch gsbi5_h_clk = { 2075 .halt_reg = 0x2fd0, 2076 .halt_bit = 23, 2077 .clkr = { 2078 .enable_reg = 0x2a40, 2079 .enable_mask = BIT(4), 2080 .hw.init = &(struct clk_init_data){ 2081 .name = "gsbi5_h_clk", 2082 .ops = &clk_branch_ops, 2083 .flags = CLK_IS_ROOT, 2084 }, 2085 }, 2086 }; 2087 2088 static struct clk_branch gsbi6_h_clk = { 2089 .halt_reg = 0x2fd0, 2090 .halt_bit = 19, 2091 .clkr = { 2092 .enable_reg = 0x2a60, 2093 .enable_mask = BIT(4), 2094 .hw.init = &(struct clk_init_data){ 2095 .name = "gsbi6_h_clk", 2096 .ops = &clk_branch_ops, 2097 .flags = CLK_IS_ROOT, 2098 }, 2099 }, 2100 }; 2101 2102 static struct clk_branch gsbi7_h_clk = { 2103 .halt_reg = 0x2fd0, 2104 .halt_bit = 15, 2105 .clkr = { 2106 .enable_reg = 0x2a80, 2107 .enable_mask = BIT(4), 2108 .hw.init = &(struct clk_init_data){ 2109 .name = "gsbi7_h_clk", 2110 .ops = &clk_branch_ops, 2111 .flags = CLK_IS_ROOT, 2112 }, 2113 }, 2114 }; 2115 2116 static struct clk_branch gsbi8_h_clk = { 2117 .halt_reg = 0x2fd0, 2118 .halt_bit = 11, 2119 .clkr = { 2120 .enable_reg = 0x2aa0, 2121 .enable_mask = BIT(4), 2122 .hw.init = &(struct clk_init_data){ 2123 .name = "gsbi8_h_clk", 2124 .ops = &clk_branch_ops, 2125 .flags = CLK_IS_ROOT, 2126 }, 2127 }, 2128 }; 2129 2130 static struct clk_branch gsbi9_h_clk = { 2131 .halt_reg = 0x2fd0, 2132 .halt_bit = 7, 2133 .clkr = { 2134 .enable_reg = 0x2ac0, 2135 .enable_mask = BIT(4), 2136 .hw.init = &(struct clk_init_data){ 2137 .name = "gsbi9_h_clk", 2138 .ops = &clk_branch_ops, 2139 .flags = CLK_IS_ROOT, 2140 }, 2141 }, 2142 }; 2143 2144 static struct clk_branch gsbi10_h_clk = { 2145 .halt_reg = 0x2fd0, 2146 .halt_bit = 3, 2147 .clkr = { 2148 .enable_reg = 0x2ae0, 2149 .enable_mask = BIT(4), 2150 .hw.init = &(struct clk_init_data){ 2151 .name = "gsbi10_h_clk", 2152 .ops = &clk_branch_ops, 2153 .flags = CLK_IS_ROOT, 2154 }, 2155 }, 2156 }; 2157 2158 static struct clk_branch gsbi11_h_clk = { 2159 .halt_reg = 0x2fd4, 2160 .halt_bit = 18, 2161 .clkr = { 2162 .enable_reg = 0x2b00, 2163 .enable_mask = BIT(4), 2164 .hw.init = &(struct clk_init_data){ 2165 .name = "gsbi11_h_clk", 2166 .ops = &clk_branch_ops, 2167 .flags = CLK_IS_ROOT, 2168 }, 2169 }, 2170 }; 2171 2172 static struct clk_branch gsbi12_h_clk = { 2173 .halt_reg = 0x2fd4, 2174 .halt_bit = 14, 2175 .clkr = { 2176 .enable_reg = 0x2b20, 2177 .enable_mask = BIT(4), 2178 .hw.init = &(struct clk_init_data){ 2179 .name = "gsbi12_h_clk", 2180 .ops = &clk_branch_ops, 2181 .flags = CLK_IS_ROOT, 2182 }, 2183 }, 2184 }; 2185 2186 static struct clk_branch tsif_h_clk = { 2187 .halt_reg = 0x2fd4, 2188 .halt_bit = 7, 2189 .clkr = { 2190 .enable_reg = 0x2700, 2191 .enable_mask = BIT(4), 2192 .hw.init = &(struct clk_init_data){ 2193 .name = "tsif_h_clk", 2194 .ops = &clk_branch_ops, 2195 .flags = CLK_IS_ROOT, 2196 }, 2197 }, 2198 }; 2199 2200 static struct clk_branch usb_fs1_h_clk = { 2201 .halt_reg = 0x2fcc, 2202 .halt_bit = 17, 2203 .clkr = { 2204 .enable_reg = 0x2960, 2205 .enable_mask = BIT(4), 2206 .hw.init = &(struct clk_init_data){ 2207 .name = "usb_fs1_h_clk", 2208 .ops = &clk_branch_ops, 2209 .flags = CLK_IS_ROOT, 2210 }, 2211 }, 2212 }; 2213 2214 static struct clk_branch usb_fs2_h_clk = { 2215 .halt_reg = 0x2fcc, 2216 .halt_bit = 14, 2217 .clkr = { 2218 .enable_reg = 0x2980, 2219 .enable_mask = BIT(4), 2220 .hw.init = &(struct clk_init_data){ 2221 .name = "usb_fs2_h_clk", 2222 .ops = &clk_branch_ops, 2223 .flags = CLK_IS_ROOT, 2224 }, 2225 }, 2226 }; 2227 2228 static struct clk_branch usb_hs1_h_clk = { 2229 .halt_reg = 0x2fc8, 2230 .halt_bit = 1, 2231 .clkr = { 2232 .enable_reg = 0x2900, 2233 .enable_mask = BIT(4), 2234 .hw.init = &(struct clk_init_data){ 2235 .name = "usb_hs1_h_clk", 2236 .ops = &clk_branch_ops, 2237 .flags = CLK_IS_ROOT, 2238 }, 2239 }, 2240 }; 2241 2242 static struct clk_branch sdc1_h_clk = { 2243 .halt_reg = 0x2fc8, 2244 .halt_bit = 11, 2245 .clkr = { 2246 .enable_reg = 0x2820, 2247 .enable_mask = BIT(4), 2248 .hw.init = &(struct clk_init_data){ 2249 .name = "sdc1_h_clk", 2250 .ops = &clk_branch_ops, 2251 .flags = CLK_IS_ROOT, 2252 }, 2253 }, 2254 }; 2255 2256 static struct clk_branch sdc2_h_clk = { 2257 .halt_reg = 0x2fc8, 2258 .halt_bit = 10, 2259 .clkr = { 2260 .enable_reg = 0x2840, 2261 .enable_mask = BIT(4), 2262 .hw.init = &(struct clk_init_data){ 2263 .name = "sdc2_h_clk", 2264 .ops = &clk_branch_ops, 2265 .flags = CLK_IS_ROOT, 2266 }, 2267 }, 2268 }; 2269 2270 static struct clk_branch sdc3_h_clk = { 2271 .halt_reg = 0x2fc8, 2272 .halt_bit = 9, 2273 .clkr = { 2274 .enable_reg = 0x2860, 2275 .enable_mask = BIT(4), 2276 .hw.init = &(struct clk_init_data){ 2277 .name = "sdc3_h_clk", 2278 .ops = &clk_branch_ops, 2279 .flags = CLK_IS_ROOT, 2280 }, 2281 }, 2282 }; 2283 2284 static struct clk_branch sdc4_h_clk = { 2285 .halt_reg = 0x2fc8, 2286 .halt_bit = 8, 2287 .clkr = { 2288 .enable_reg = 0x2880, 2289 .enable_mask = BIT(4), 2290 .hw.init = &(struct clk_init_data){ 2291 .name = "sdc4_h_clk", 2292 .ops = &clk_branch_ops, 2293 .flags = CLK_IS_ROOT, 2294 }, 2295 }, 2296 }; 2297 2298 static struct clk_branch sdc5_h_clk = { 2299 .halt_reg = 0x2fc8, 2300 .halt_bit = 7, 2301 .clkr = { 2302 .enable_reg = 0x28a0, 2303 .enable_mask = BIT(4), 2304 .hw.init = &(struct clk_init_data){ 2305 .name = "sdc5_h_clk", 2306 .ops = &clk_branch_ops, 2307 .flags = CLK_IS_ROOT, 2308 }, 2309 }, 2310 }; 2311 2312 static struct clk_branch adm0_clk = { 2313 .halt_reg = 0x2fdc, 2314 .halt_check = BRANCH_HALT_VOTED, 2315 .halt_bit = 14, 2316 .clkr = { 2317 .enable_reg = 0x3080, 2318 .enable_mask = BIT(2), 2319 .hw.init = &(struct clk_init_data){ 2320 .name = "adm0_clk", 2321 .ops = &clk_branch_ops, 2322 .flags = CLK_IS_ROOT, 2323 }, 2324 }, 2325 }; 2326 2327 static struct clk_branch adm0_pbus_clk = { 2328 .halt_reg = 0x2fdc, 2329 .halt_check = BRANCH_HALT_VOTED, 2330 .halt_bit = 13, 2331 .clkr = { 2332 .enable_reg = 0x3080, 2333 .enable_mask = BIT(3), 2334 .hw.init = &(struct clk_init_data){ 2335 .name = "adm0_pbus_clk", 2336 .ops = &clk_branch_ops, 2337 .flags = CLK_IS_ROOT, 2338 }, 2339 }, 2340 }; 2341 2342 static struct clk_branch adm1_clk = { 2343 .halt_reg = 0x2fdc, 2344 .halt_bit = 12, 2345 .halt_check = BRANCH_HALT_VOTED, 2346 .clkr = { 2347 .enable_reg = 0x3080, 2348 .enable_mask = BIT(4), 2349 .hw.init = &(struct clk_init_data){ 2350 .name = "adm1_clk", 2351 .ops = &clk_branch_ops, 2352 .flags = CLK_IS_ROOT, 2353 }, 2354 }, 2355 }; 2356 2357 static struct clk_branch adm1_pbus_clk = { 2358 .halt_reg = 0x2fdc, 2359 .halt_bit = 11, 2360 .halt_check = BRANCH_HALT_VOTED, 2361 .clkr = { 2362 .enable_reg = 0x3080, 2363 .enable_mask = BIT(5), 2364 .hw.init = &(struct clk_init_data){ 2365 .name = "adm1_pbus_clk", 2366 .ops = &clk_branch_ops, 2367 .flags = CLK_IS_ROOT, 2368 }, 2369 }, 2370 }; 2371 2372 static struct clk_branch modem_ahb1_h_clk = { 2373 .halt_reg = 0x2fdc, 2374 .halt_bit = 8, 2375 .halt_check = BRANCH_HALT_VOTED, 2376 .clkr = { 2377 .enable_reg = 0x3080, 2378 .enable_mask = BIT(0), 2379 .hw.init = &(struct clk_init_data){ 2380 .name = "modem_ahb1_h_clk", 2381 .ops = &clk_branch_ops, 2382 .flags = CLK_IS_ROOT, 2383 }, 2384 }, 2385 }; 2386 2387 static struct clk_branch modem_ahb2_h_clk = { 2388 .halt_reg = 0x2fdc, 2389 .halt_bit = 7, 2390 .halt_check = BRANCH_HALT_VOTED, 2391 .clkr = { 2392 .enable_reg = 0x3080, 2393 .enable_mask = BIT(1), 2394 .hw.init = &(struct clk_init_data){ 2395 .name = "modem_ahb2_h_clk", 2396 .ops = &clk_branch_ops, 2397 .flags = CLK_IS_ROOT, 2398 }, 2399 }, 2400 }; 2401 2402 static struct clk_branch pmic_arb0_h_clk = { 2403 .halt_reg = 0x2fd8, 2404 .halt_check = BRANCH_HALT_VOTED, 2405 .halt_bit = 22, 2406 .clkr = { 2407 .enable_reg = 0x3080, 2408 .enable_mask = BIT(8), 2409 .hw.init = &(struct clk_init_data){ 2410 .name = "pmic_arb0_h_clk", 2411 .ops = &clk_branch_ops, 2412 .flags = CLK_IS_ROOT, 2413 }, 2414 }, 2415 }; 2416 2417 static struct clk_branch pmic_arb1_h_clk = { 2418 .halt_reg = 0x2fd8, 2419 .halt_check = BRANCH_HALT_VOTED, 2420 .halt_bit = 21, 2421 .clkr = { 2422 .enable_reg = 0x3080, 2423 .enable_mask = BIT(9), 2424 .hw.init = &(struct clk_init_data){ 2425 .name = "pmic_arb1_h_clk", 2426 .ops = &clk_branch_ops, 2427 .flags = CLK_IS_ROOT, 2428 }, 2429 }, 2430 }; 2431 2432 static struct clk_branch pmic_ssbi2_clk = { 2433 .halt_reg = 0x2fd8, 2434 .halt_check = BRANCH_HALT_VOTED, 2435 .halt_bit = 23, 2436 .clkr = { 2437 .enable_reg = 0x3080, 2438 .enable_mask = BIT(7), 2439 .hw.init = &(struct clk_init_data){ 2440 .name = "pmic_ssbi2_clk", 2441 .ops = &clk_branch_ops, 2442 .flags = CLK_IS_ROOT, 2443 }, 2444 }, 2445 }; 2446 2447 static struct clk_branch rpm_msg_ram_h_clk = { 2448 .hwcg_reg = 0x27e0, 2449 .hwcg_bit = 6, 2450 .halt_reg = 0x2fd8, 2451 .halt_check = BRANCH_HALT_VOTED, 2452 .halt_bit = 12, 2453 .clkr = { 2454 .enable_reg = 0x3080, 2455 .enable_mask = BIT(6), 2456 .hw.init = &(struct clk_init_data){ 2457 .name = "rpm_msg_ram_h_clk", 2458 .ops = &clk_branch_ops, 2459 .flags = CLK_IS_ROOT, 2460 }, 2461 }, 2462 }; 2463 2464 static struct clk_regmap *gcc_msm8660_clks[] = { 2465 [PLL8] = &pll8.clkr, 2466 [PLL8_VOTE] = &pll8_vote, 2467 [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr, 2468 [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr, 2469 [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr, 2470 [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr, 2471 [GSBI3_UART_SRC] = &gsbi3_uart_src.clkr, 2472 [GSBI3_UART_CLK] = &gsbi3_uart_clk.clkr, 2473 [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr, 2474 [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr, 2475 [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr, 2476 [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr, 2477 [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr, 2478 [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr, 2479 [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr, 2480 [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr, 2481 [GSBI8_UART_SRC] = &gsbi8_uart_src.clkr, 2482 [GSBI8_UART_CLK] = &gsbi8_uart_clk.clkr, 2483 [GSBI9_UART_SRC] = &gsbi9_uart_src.clkr, 2484 [GSBI9_UART_CLK] = &gsbi9_uart_clk.clkr, 2485 [GSBI10_UART_SRC] = &gsbi10_uart_src.clkr, 2486 [GSBI10_UART_CLK] = &gsbi10_uart_clk.clkr, 2487 [GSBI11_UART_SRC] = &gsbi11_uart_src.clkr, 2488 [GSBI11_UART_CLK] = &gsbi11_uart_clk.clkr, 2489 [GSBI12_UART_SRC] = &gsbi12_uart_src.clkr, 2490 [GSBI12_UART_CLK] = &gsbi12_uart_clk.clkr, 2491 [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr, 2492 [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr, 2493 [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr, 2494 [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr, 2495 [GSBI3_QUP_SRC] = &gsbi3_qup_src.clkr, 2496 [GSBI3_QUP_CLK] = &gsbi3_qup_clk.clkr, 2497 [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr, 2498 [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr, 2499 [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr, 2500 [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr, 2501 [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr, 2502 [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr, 2503 [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr, 2504 [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr, 2505 [GSBI8_QUP_SRC] = &gsbi8_qup_src.clkr, 2506 [GSBI8_QUP_CLK] = &gsbi8_qup_clk.clkr, 2507 [GSBI9_QUP_SRC] = &gsbi9_qup_src.clkr, 2508 [GSBI9_QUP_CLK] = &gsbi9_qup_clk.clkr, 2509 [GSBI10_QUP_SRC] = &gsbi10_qup_src.clkr, 2510 [GSBI10_QUP_CLK] = &gsbi10_qup_clk.clkr, 2511 [GSBI11_QUP_SRC] = &gsbi11_qup_src.clkr, 2512 [GSBI11_QUP_CLK] = &gsbi11_qup_clk.clkr, 2513 [GSBI12_QUP_SRC] = &gsbi12_qup_src.clkr, 2514 [GSBI12_QUP_CLK] = &gsbi12_qup_clk.clkr, 2515 [GP0_SRC] = &gp0_src.clkr, 2516 [GP0_CLK] = &gp0_clk.clkr, 2517 [GP1_SRC] = &gp1_src.clkr, 2518 [GP1_CLK] = &gp1_clk.clkr, 2519 [GP2_SRC] = &gp2_src.clkr, 2520 [GP2_CLK] = &gp2_clk.clkr, 2521 [PMEM_CLK] = &pmem_clk.clkr, 2522 [PRNG_SRC] = &prng_src.clkr, 2523 [PRNG_CLK] = &prng_clk.clkr, 2524 [SDC1_SRC] = &sdc1_src.clkr, 2525 [SDC1_CLK] = &sdc1_clk.clkr, 2526 [SDC2_SRC] = &sdc2_src.clkr, 2527 [SDC2_CLK] = &sdc2_clk.clkr, 2528 [SDC3_SRC] = &sdc3_src.clkr, 2529 [SDC3_CLK] = &sdc3_clk.clkr, 2530 [SDC4_SRC] = &sdc4_src.clkr, 2531 [SDC4_CLK] = &sdc4_clk.clkr, 2532 [SDC5_SRC] = &sdc5_src.clkr, 2533 [SDC5_CLK] = &sdc5_clk.clkr, 2534 [TSIF_REF_SRC] = &tsif_ref_src.clkr, 2535 [TSIF_REF_CLK] = &tsif_ref_clk.clkr, 2536 [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_src.clkr, 2537 [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr, 2538 [USB_FS1_XCVR_FS_SRC] = &usb_fs1_xcvr_fs_src.clkr, 2539 [USB_FS1_XCVR_FS_CLK] = &usb_fs1_xcvr_fs_clk.clkr, 2540 [USB_FS1_SYSTEM_CLK] = &usb_fs1_system_clk.clkr, 2541 [USB_FS2_XCVR_FS_SRC] = &usb_fs2_xcvr_fs_src.clkr, 2542 [USB_FS2_XCVR_FS_CLK] = &usb_fs2_xcvr_fs_clk.clkr, 2543 [USB_FS2_SYSTEM_CLK] = &usb_fs2_system_clk.clkr, 2544 [GSBI1_H_CLK] = &gsbi1_h_clk.clkr, 2545 [GSBI2_H_CLK] = &gsbi2_h_clk.clkr, 2546 [GSBI3_H_CLK] = &gsbi3_h_clk.clkr, 2547 [GSBI4_H_CLK] = &gsbi4_h_clk.clkr, 2548 [GSBI5_H_CLK] = &gsbi5_h_clk.clkr, 2549 [GSBI6_H_CLK] = &gsbi6_h_clk.clkr, 2550 [GSBI7_H_CLK] = &gsbi7_h_clk.clkr, 2551 [GSBI8_H_CLK] = &gsbi8_h_clk.clkr, 2552 [GSBI9_H_CLK] = &gsbi9_h_clk.clkr, 2553 [GSBI10_H_CLK] = &gsbi10_h_clk.clkr, 2554 [GSBI11_H_CLK] = &gsbi11_h_clk.clkr, 2555 [GSBI12_H_CLK] = &gsbi12_h_clk.clkr, 2556 [TSIF_H_CLK] = &tsif_h_clk.clkr, 2557 [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr, 2558 [USB_FS2_H_CLK] = &usb_fs2_h_clk.clkr, 2559 [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr, 2560 [SDC1_H_CLK] = &sdc1_h_clk.clkr, 2561 [SDC2_H_CLK] = &sdc2_h_clk.clkr, 2562 [SDC3_H_CLK] = &sdc3_h_clk.clkr, 2563 [SDC4_H_CLK] = &sdc4_h_clk.clkr, 2564 [SDC5_H_CLK] = &sdc5_h_clk.clkr, 2565 [ADM0_CLK] = &adm0_clk.clkr, 2566 [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr, 2567 [ADM1_CLK] = &adm1_clk.clkr, 2568 [ADM1_PBUS_CLK] = &adm1_pbus_clk.clkr, 2569 [MODEM_AHB1_H_CLK] = &modem_ahb1_h_clk.clkr, 2570 [MODEM_AHB2_H_CLK] = &modem_ahb2_h_clk.clkr, 2571 [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr, 2572 [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr, 2573 [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr, 2574 [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr, 2575 }; 2576 2577 static const struct qcom_reset_map gcc_msm8660_resets[] = { 2578 [AFAB_CORE_RESET] = { 0x2080, 7 }, 2579 [SCSS_SYS_RESET] = { 0x20b4, 1 }, 2580 [SCSS_SYS_POR_RESET] = { 0x20b4 }, 2581 [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 }, 2582 [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 }, 2583 [AFAB_SMPSS_M0_RESET] = { 0x20b8 }, 2584 [AFAB_EBI1_S_RESET] = { 0x20c0, 7 }, 2585 [SFAB_CORE_RESET] = { 0x2120, 7 }, 2586 [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 }, 2587 [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 }, 2588 [SFAB_ADM0_M2_RESET] = { 0x21e4, 7 }, 2589 [ADM0_C2_RESET] = { 0x220c, 4 }, 2590 [ADM0_C1_RESET] = { 0x220c, 3 }, 2591 [ADM0_C0_RESET] = { 0x220c, 2 }, 2592 [ADM0_PBUS_RESET] = { 0x220c, 1 }, 2593 [ADM0_RESET] = { 0x220c }, 2594 [SFAB_ADM1_M0_RESET] = { 0x2220, 7 }, 2595 [SFAB_ADM1_M1_RESET] = { 0x2224, 7 }, 2596 [SFAB_ADM1_M2_RESET] = { 0x2228, 7 }, 2597 [MMFAB_ADM1_M3_RESET] = { 0x2240, 7 }, 2598 [ADM1_C3_RESET] = { 0x226c, 5 }, 2599 [ADM1_C2_RESET] = { 0x226c, 4 }, 2600 [ADM1_C1_RESET] = { 0x226c, 3 }, 2601 [ADM1_C0_RESET] = { 0x226c, 2 }, 2602 [ADM1_PBUS_RESET] = { 0x226c, 1 }, 2603 [ADM1_RESET] = { 0x226c }, 2604 [IMEM0_RESET] = { 0x2280, 7 }, 2605 [SFAB_LPASS_Q6_RESET] = { 0x23a0, 7 }, 2606 [SFAB_AFAB_M_RESET] = { 0x23e0, 7 }, 2607 [AFAB_SFAB_M0_RESET] = { 0x2420, 7 }, 2608 [AFAB_SFAB_M1_RESET] = { 0x2424, 7 }, 2609 [DFAB_CORE_RESET] = { 0x24ac, 7 }, 2610 [SFAB_DFAB_M_RESET] = { 0x2500, 7 }, 2611 [DFAB_SFAB_M_RESET] = { 0x2520, 7 }, 2612 [DFAB_SWAY0_RESET] = { 0x2540, 7 }, 2613 [DFAB_SWAY1_RESET] = { 0x2544, 7 }, 2614 [DFAB_ARB0_RESET] = { 0x2560, 7 }, 2615 [DFAB_ARB1_RESET] = { 0x2564, 7 }, 2616 [PPSS_PROC_RESET] = { 0x2594, 1 }, 2617 [PPSS_RESET] = { 0x2594 }, 2618 [PMEM_RESET] = { 0x25a0, 7 }, 2619 [DMA_BAM_RESET] = { 0x25c0, 7 }, 2620 [SIC_RESET] = { 0x25e0, 7 }, 2621 [SPS_TIC_RESET] = { 0x2600, 7 }, 2622 [CFBP0_RESET] = { 0x2650, 7 }, 2623 [CFBP1_RESET] = { 0x2654, 7 }, 2624 [CFBP2_RESET] = { 0x2658, 7 }, 2625 [EBI2_RESET] = { 0x2664, 7 }, 2626 [SFAB_CFPB_M_RESET] = { 0x2680, 7 }, 2627 [CFPB_MASTER_RESET] = { 0x26a0, 7 }, 2628 [SFAB_CFPB_S_RESET] = { 0x26c0, 7 }, 2629 [CFPB_SPLITTER_RESET] = { 0x26e0, 7 }, 2630 [TSIF_RESET] = { 0x2700, 7 }, 2631 [CE1_RESET] = { 0x2720, 7 }, 2632 [CE2_RESET] = { 0x2740, 7 }, 2633 [SFAB_SFPB_M_RESET] = { 0x2780, 7 }, 2634 [SFAB_SFPB_S_RESET] = { 0x27a0, 7 }, 2635 [RPM_PROC_RESET] = { 0x27c0, 7 }, 2636 [RPM_BUS_RESET] = { 0x27c4, 7 }, 2637 [RPM_MSG_RAM_RESET] = { 0x27e0, 7 }, 2638 [PMIC_ARB0_RESET] = { 0x2800, 7 }, 2639 [PMIC_ARB1_RESET] = { 0x2804, 7 }, 2640 [PMIC_SSBI2_RESET] = { 0x280c, 12 }, 2641 [SDC1_RESET] = { 0x2830 }, 2642 [SDC2_RESET] = { 0x2850 }, 2643 [SDC3_RESET] = { 0x2870 }, 2644 [SDC4_RESET] = { 0x2890 }, 2645 [SDC5_RESET] = { 0x28b0 }, 2646 [USB_HS1_RESET] = { 0x2910 }, 2647 [USB_HS2_XCVR_RESET] = { 0x2934, 1 }, 2648 [USB_HS2_RESET] = { 0x2934 }, 2649 [USB_FS1_XCVR_RESET] = { 0x2974, 1 }, 2650 [USB_FS1_RESET] = { 0x2974 }, 2651 [USB_FS2_XCVR_RESET] = { 0x2994, 1 }, 2652 [USB_FS2_RESET] = { 0x2994 }, 2653 [GSBI1_RESET] = { 0x29dc }, 2654 [GSBI2_RESET] = { 0x29fc }, 2655 [GSBI3_RESET] = { 0x2a1c }, 2656 [GSBI4_RESET] = { 0x2a3c }, 2657 [GSBI5_RESET] = { 0x2a5c }, 2658 [GSBI6_RESET] = { 0x2a7c }, 2659 [GSBI7_RESET] = { 0x2a9c }, 2660 [GSBI8_RESET] = { 0x2abc }, 2661 [GSBI9_RESET] = { 0x2adc }, 2662 [GSBI10_RESET] = { 0x2afc }, 2663 [GSBI11_RESET] = { 0x2b1c }, 2664 [GSBI12_RESET] = { 0x2b3c }, 2665 [SPDM_RESET] = { 0x2b6c }, 2666 [SEC_CTRL_RESET] = { 0x2b80, 7 }, 2667 [TLMM_H_RESET] = { 0x2ba0, 7 }, 2668 [TLMM_RESET] = { 0x2ba4, 7 }, 2669 [MARRM_PWRON_RESET] = { 0x2bd4, 1 }, 2670 [MARM_RESET] = { 0x2bd4 }, 2671 [MAHB1_RESET] = { 0x2be4, 7 }, 2672 [SFAB_MSS_S_RESET] = { 0x2c00, 7 }, 2673 [MAHB2_RESET] = { 0x2c20, 7 }, 2674 [MODEM_SW_AHB_RESET] = { 0x2c48, 1 }, 2675 [MODEM_RESET] = { 0x2c48 }, 2676 [SFAB_MSS_MDM1_RESET] = { 0x2c4c, 1 }, 2677 [SFAB_MSS_MDM0_RESET] = { 0x2c4c }, 2678 [MSS_SLP_RESET] = { 0x2c60, 7 }, 2679 [MSS_MARM_SAW_RESET] = { 0x2c68, 1 }, 2680 [MSS_WDOG_RESET] = { 0x2c68 }, 2681 [TSSC_RESET] = { 0x2ca0, 7 }, 2682 [PDM_RESET] = { 0x2cc0, 12 }, 2683 [SCSS_CORE0_RESET] = { 0x2d60, 1 }, 2684 [SCSS_CORE0_POR_RESET] = { 0x2d60 }, 2685 [SCSS_CORE1_RESET] = { 0x2d80, 1 }, 2686 [SCSS_CORE1_POR_RESET] = { 0x2d80 }, 2687 [MPM_RESET] = { 0x2da4, 1 }, 2688 [EBI1_1X_DIV_RESET] = { 0x2dec, 9 }, 2689 [EBI1_RESET] = { 0x2dec, 7 }, 2690 [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 }, 2691 [USB_PHY0_RESET] = { 0x2e20 }, 2692 [USB_PHY1_RESET] = { 0x2e40 }, 2693 [PRNG_RESET] = { 0x2e80, 12 }, 2694 }; 2695 2696 static const struct regmap_config gcc_msm8660_regmap_config = { 2697 .reg_bits = 32, 2698 .reg_stride = 4, 2699 .val_bits = 32, 2700 .max_register = 0x363c, 2701 .fast_io = true, 2702 }; 2703 2704 static const struct of_device_id gcc_msm8660_match_table[] = { 2705 { .compatible = "qcom,gcc-msm8660" }, 2706 { } 2707 }; 2708 MODULE_DEVICE_TABLE(of, gcc_msm8660_match_table); 2709 2710 struct qcom_cc { 2711 struct qcom_reset_controller reset; 2712 struct clk_onecell_data data; 2713 struct clk *clks[]; 2714 }; 2715 2716 static int gcc_msm8660_probe(struct platform_device *pdev) 2717 { 2718 void __iomem *base; 2719 struct resource *res; 2720 int i, ret; 2721 struct device *dev = &pdev->dev; 2722 struct clk *clk; 2723 struct clk_onecell_data *data; 2724 struct clk **clks; 2725 struct regmap *regmap; 2726 size_t num_clks; 2727 struct qcom_reset_controller *reset; 2728 struct qcom_cc *cc; 2729 2730 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2731 base = devm_ioremap_resource(dev, res); 2732 if (IS_ERR(base)) 2733 return PTR_ERR(base); 2734 2735 regmap = devm_regmap_init_mmio(dev, base, &gcc_msm8660_regmap_config); 2736 if (IS_ERR(regmap)) 2737 return PTR_ERR(regmap); 2738 2739 num_clks = ARRAY_SIZE(gcc_msm8660_clks); 2740 cc = devm_kzalloc(dev, sizeof(*cc) + sizeof(*clks) * num_clks, 2741 GFP_KERNEL); 2742 if (!cc) 2743 return -ENOMEM; 2744 2745 clks = cc->clks; 2746 data = &cc->data; 2747 data->clks = clks; 2748 data->clk_num = num_clks; 2749 2750 /* Temporary until RPM clocks supported */ 2751 clk = clk_register_fixed_rate(dev, "cxo", NULL, CLK_IS_ROOT, 19200000); 2752 if (IS_ERR(clk)) 2753 return PTR_ERR(clk); 2754 2755 clk = clk_register_fixed_rate(dev, "pxo", NULL, CLK_IS_ROOT, 27000000); 2756 if (IS_ERR(clk)) 2757 return PTR_ERR(clk); 2758 2759 for (i = 0; i < num_clks; i++) { 2760 if (!gcc_msm8660_clks[i]) 2761 continue; 2762 clk = devm_clk_register_regmap(dev, gcc_msm8660_clks[i]); 2763 if (IS_ERR(clk)) 2764 return PTR_ERR(clk); 2765 clks[i] = clk; 2766 } 2767 2768 ret = of_clk_add_provider(dev->of_node, of_clk_src_onecell_get, data); 2769 if (ret) 2770 return ret; 2771 2772 reset = &cc->reset; 2773 reset->rcdev.of_node = dev->of_node; 2774 reset->rcdev.ops = &qcom_reset_ops, 2775 reset->rcdev.owner = THIS_MODULE, 2776 reset->rcdev.nr_resets = ARRAY_SIZE(gcc_msm8660_resets), 2777 reset->regmap = regmap; 2778 reset->reset_map = gcc_msm8660_resets, 2779 platform_set_drvdata(pdev, &reset->rcdev); 2780 2781 ret = reset_controller_register(&reset->rcdev); 2782 if (ret) 2783 of_clk_del_provider(dev->of_node); 2784 2785 return ret; 2786 } 2787 2788 static int gcc_msm8660_remove(struct platform_device *pdev) 2789 { 2790 of_clk_del_provider(pdev->dev.of_node); 2791 reset_controller_unregister(platform_get_drvdata(pdev)); 2792 return 0; 2793 } 2794 2795 static struct platform_driver gcc_msm8660_driver = { 2796 .probe = gcc_msm8660_probe, 2797 .remove = gcc_msm8660_remove, 2798 .driver = { 2799 .name = "gcc-msm8660", 2800 .owner = THIS_MODULE, 2801 .of_match_table = gcc_msm8660_match_table, 2802 }, 2803 }; 2804 2805 static int __init gcc_msm8660_init(void) 2806 { 2807 return platform_driver_register(&gcc_msm8660_driver); 2808 } 2809 core_initcall(gcc_msm8660_init); 2810 2811 static void __exit gcc_msm8660_exit(void) 2812 { 2813 platform_driver_unregister(&gcc_msm8660_driver); 2814 } 2815 module_exit(gcc_msm8660_exit); 2816 2817 MODULE_DESCRIPTION("GCC MSM 8660 Driver"); 2818 MODULE_LICENSE("GPL v2"); 2819 MODULE_ALIAS("platform:gcc-msm8660"); 2820