1 /* 2 * Copyright (c) 2013, The Linux Foundation. All rights reserved. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include <linux/kernel.h> 15 #include <linux/bitops.h> 16 #include <linux/err.h> 17 #include <linux/platform_device.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/of_device.h> 21 #include <linux/clk-provider.h> 22 #include <linux/regmap.h> 23 #include <linux/reset-controller.h> 24 25 #include <dt-bindings/clock/qcom,gcc-msm8660.h> 26 #include <dt-bindings/reset/qcom,gcc-msm8660.h> 27 28 #include "common.h" 29 #include "clk-regmap.h" 30 #include "clk-pll.h" 31 #include "clk-rcg.h" 32 #include "clk-branch.h" 33 #include "reset.h" 34 35 static struct clk_pll pll8 = { 36 .l_reg = 0x3144, 37 .m_reg = 0x3148, 38 .n_reg = 0x314c, 39 .config_reg = 0x3154, 40 .mode_reg = 0x3140, 41 .status_reg = 0x3158, 42 .status_bit = 16, 43 .clkr.hw.init = &(struct clk_init_data){ 44 .name = "pll8", 45 .parent_names = (const char *[]){ "pxo" }, 46 .num_parents = 1, 47 .ops = &clk_pll_ops, 48 }, 49 }; 50 51 static struct clk_regmap pll8_vote = { 52 .enable_reg = 0x34c0, 53 .enable_mask = BIT(8), 54 .hw.init = &(struct clk_init_data){ 55 .name = "pll8_vote", 56 .parent_names = (const char *[]){ "pll8" }, 57 .num_parents = 1, 58 .ops = &clk_pll_vote_ops, 59 }, 60 }; 61 62 enum { 63 P_PXO, 64 P_PLL8, 65 P_CXO, 66 }; 67 68 static const struct parent_map gcc_pxo_pll8_map[] = { 69 { P_PXO, 0 }, 70 { P_PLL8, 3 } 71 }; 72 73 static const char * const gcc_pxo_pll8[] = { 74 "pxo", 75 "pll8_vote", 76 }; 77 78 static const struct parent_map gcc_pxo_pll8_cxo_map[] = { 79 { P_PXO, 0 }, 80 { P_PLL8, 3 }, 81 { P_CXO, 5 } 82 }; 83 84 static const char * const gcc_pxo_pll8_cxo[] = { 85 "pxo", 86 "pll8_vote", 87 "cxo", 88 }; 89 90 static struct freq_tbl clk_tbl_gsbi_uart[] = { 91 { 1843200, P_PLL8, 2, 6, 625 }, 92 { 3686400, P_PLL8, 2, 12, 625 }, 93 { 7372800, P_PLL8, 2, 24, 625 }, 94 { 14745600, P_PLL8, 2, 48, 625 }, 95 { 16000000, P_PLL8, 4, 1, 6 }, 96 { 24000000, P_PLL8, 4, 1, 4 }, 97 { 32000000, P_PLL8, 4, 1, 3 }, 98 { 40000000, P_PLL8, 1, 5, 48 }, 99 { 46400000, P_PLL8, 1, 29, 240 }, 100 { 48000000, P_PLL8, 4, 1, 2 }, 101 { 51200000, P_PLL8, 1, 2, 15 }, 102 { 56000000, P_PLL8, 1, 7, 48 }, 103 { 58982400, P_PLL8, 1, 96, 625 }, 104 { 64000000, P_PLL8, 2, 1, 3 }, 105 { } 106 }; 107 108 static struct clk_rcg gsbi1_uart_src = { 109 .ns_reg = 0x29d4, 110 .md_reg = 0x29d0, 111 .mn = { 112 .mnctr_en_bit = 8, 113 .mnctr_reset_bit = 7, 114 .mnctr_mode_shift = 5, 115 .n_val_shift = 16, 116 .m_val_shift = 16, 117 .width = 16, 118 }, 119 .p = { 120 .pre_div_shift = 3, 121 .pre_div_width = 2, 122 }, 123 .s = { 124 .src_sel_shift = 0, 125 .parent_map = gcc_pxo_pll8_map, 126 }, 127 .freq_tbl = clk_tbl_gsbi_uart, 128 .clkr = { 129 .enable_reg = 0x29d4, 130 .enable_mask = BIT(11), 131 .hw.init = &(struct clk_init_data){ 132 .name = "gsbi1_uart_src", 133 .parent_names = gcc_pxo_pll8, 134 .num_parents = 2, 135 .ops = &clk_rcg_ops, 136 .flags = CLK_SET_PARENT_GATE, 137 }, 138 }, 139 }; 140 141 static struct clk_branch gsbi1_uart_clk = { 142 .halt_reg = 0x2fcc, 143 .halt_bit = 10, 144 .clkr = { 145 .enable_reg = 0x29d4, 146 .enable_mask = BIT(9), 147 .hw.init = &(struct clk_init_data){ 148 .name = "gsbi1_uart_clk", 149 .parent_names = (const char *[]){ 150 "gsbi1_uart_src", 151 }, 152 .num_parents = 1, 153 .ops = &clk_branch_ops, 154 .flags = CLK_SET_RATE_PARENT, 155 }, 156 }, 157 }; 158 159 static struct clk_rcg gsbi2_uart_src = { 160 .ns_reg = 0x29f4, 161 .md_reg = 0x29f0, 162 .mn = { 163 .mnctr_en_bit = 8, 164 .mnctr_reset_bit = 7, 165 .mnctr_mode_shift = 5, 166 .n_val_shift = 16, 167 .m_val_shift = 16, 168 .width = 16, 169 }, 170 .p = { 171 .pre_div_shift = 3, 172 .pre_div_width = 2, 173 }, 174 .s = { 175 .src_sel_shift = 0, 176 .parent_map = gcc_pxo_pll8_map, 177 }, 178 .freq_tbl = clk_tbl_gsbi_uart, 179 .clkr = { 180 .enable_reg = 0x29f4, 181 .enable_mask = BIT(11), 182 .hw.init = &(struct clk_init_data){ 183 .name = "gsbi2_uart_src", 184 .parent_names = gcc_pxo_pll8, 185 .num_parents = 2, 186 .ops = &clk_rcg_ops, 187 .flags = CLK_SET_PARENT_GATE, 188 }, 189 }, 190 }; 191 192 static struct clk_branch gsbi2_uart_clk = { 193 .halt_reg = 0x2fcc, 194 .halt_bit = 6, 195 .clkr = { 196 .enable_reg = 0x29f4, 197 .enable_mask = BIT(9), 198 .hw.init = &(struct clk_init_data){ 199 .name = "gsbi2_uart_clk", 200 .parent_names = (const char *[]){ 201 "gsbi2_uart_src", 202 }, 203 .num_parents = 1, 204 .ops = &clk_branch_ops, 205 .flags = CLK_SET_RATE_PARENT, 206 }, 207 }, 208 }; 209 210 static struct clk_rcg gsbi3_uart_src = { 211 .ns_reg = 0x2a14, 212 .md_reg = 0x2a10, 213 .mn = { 214 .mnctr_en_bit = 8, 215 .mnctr_reset_bit = 7, 216 .mnctr_mode_shift = 5, 217 .n_val_shift = 16, 218 .m_val_shift = 16, 219 .width = 16, 220 }, 221 .p = { 222 .pre_div_shift = 3, 223 .pre_div_width = 2, 224 }, 225 .s = { 226 .src_sel_shift = 0, 227 .parent_map = gcc_pxo_pll8_map, 228 }, 229 .freq_tbl = clk_tbl_gsbi_uart, 230 .clkr = { 231 .enable_reg = 0x2a14, 232 .enable_mask = BIT(11), 233 .hw.init = &(struct clk_init_data){ 234 .name = "gsbi3_uart_src", 235 .parent_names = gcc_pxo_pll8, 236 .num_parents = 2, 237 .ops = &clk_rcg_ops, 238 .flags = CLK_SET_PARENT_GATE, 239 }, 240 }, 241 }; 242 243 static struct clk_branch gsbi3_uart_clk = { 244 .halt_reg = 0x2fcc, 245 .halt_bit = 2, 246 .clkr = { 247 .enable_reg = 0x2a14, 248 .enable_mask = BIT(9), 249 .hw.init = &(struct clk_init_data){ 250 .name = "gsbi3_uart_clk", 251 .parent_names = (const char *[]){ 252 "gsbi3_uart_src", 253 }, 254 .num_parents = 1, 255 .ops = &clk_branch_ops, 256 .flags = CLK_SET_RATE_PARENT, 257 }, 258 }, 259 }; 260 261 static struct clk_rcg gsbi4_uart_src = { 262 .ns_reg = 0x2a34, 263 .md_reg = 0x2a30, 264 .mn = { 265 .mnctr_en_bit = 8, 266 .mnctr_reset_bit = 7, 267 .mnctr_mode_shift = 5, 268 .n_val_shift = 16, 269 .m_val_shift = 16, 270 .width = 16, 271 }, 272 .p = { 273 .pre_div_shift = 3, 274 .pre_div_width = 2, 275 }, 276 .s = { 277 .src_sel_shift = 0, 278 .parent_map = gcc_pxo_pll8_map, 279 }, 280 .freq_tbl = clk_tbl_gsbi_uart, 281 .clkr = { 282 .enable_reg = 0x2a34, 283 .enable_mask = BIT(11), 284 .hw.init = &(struct clk_init_data){ 285 .name = "gsbi4_uart_src", 286 .parent_names = gcc_pxo_pll8, 287 .num_parents = 2, 288 .ops = &clk_rcg_ops, 289 .flags = CLK_SET_PARENT_GATE, 290 }, 291 }, 292 }; 293 294 static struct clk_branch gsbi4_uart_clk = { 295 .halt_reg = 0x2fd0, 296 .halt_bit = 26, 297 .clkr = { 298 .enable_reg = 0x2a34, 299 .enable_mask = BIT(9), 300 .hw.init = &(struct clk_init_data){ 301 .name = "gsbi4_uart_clk", 302 .parent_names = (const char *[]){ 303 "gsbi4_uart_src", 304 }, 305 .num_parents = 1, 306 .ops = &clk_branch_ops, 307 .flags = CLK_SET_RATE_PARENT, 308 }, 309 }, 310 }; 311 312 static struct clk_rcg gsbi5_uart_src = { 313 .ns_reg = 0x2a54, 314 .md_reg = 0x2a50, 315 .mn = { 316 .mnctr_en_bit = 8, 317 .mnctr_reset_bit = 7, 318 .mnctr_mode_shift = 5, 319 .n_val_shift = 16, 320 .m_val_shift = 16, 321 .width = 16, 322 }, 323 .p = { 324 .pre_div_shift = 3, 325 .pre_div_width = 2, 326 }, 327 .s = { 328 .src_sel_shift = 0, 329 .parent_map = gcc_pxo_pll8_map, 330 }, 331 .freq_tbl = clk_tbl_gsbi_uart, 332 .clkr = { 333 .enable_reg = 0x2a54, 334 .enable_mask = BIT(11), 335 .hw.init = &(struct clk_init_data){ 336 .name = "gsbi5_uart_src", 337 .parent_names = gcc_pxo_pll8, 338 .num_parents = 2, 339 .ops = &clk_rcg_ops, 340 .flags = CLK_SET_PARENT_GATE, 341 }, 342 }, 343 }; 344 345 static struct clk_branch gsbi5_uart_clk = { 346 .halt_reg = 0x2fd0, 347 .halt_bit = 22, 348 .clkr = { 349 .enable_reg = 0x2a54, 350 .enable_mask = BIT(9), 351 .hw.init = &(struct clk_init_data){ 352 .name = "gsbi5_uart_clk", 353 .parent_names = (const char *[]){ 354 "gsbi5_uart_src", 355 }, 356 .num_parents = 1, 357 .ops = &clk_branch_ops, 358 .flags = CLK_SET_RATE_PARENT, 359 }, 360 }, 361 }; 362 363 static struct clk_rcg gsbi6_uart_src = { 364 .ns_reg = 0x2a74, 365 .md_reg = 0x2a70, 366 .mn = { 367 .mnctr_en_bit = 8, 368 .mnctr_reset_bit = 7, 369 .mnctr_mode_shift = 5, 370 .n_val_shift = 16, 371 .m_val_shift = 16, 372 .width = 16, 373 }, 374 .p = { 375 .pre_div_shift = 3, 376 .pre_div_width = 2, 377 }, 378 .s = { 379 .src_sel_shift = 0, 380 .parent_map = gcc_pxo_pll8_map, 381 }, 382 .freq_tbl = clk_tbl_gsbi_uart, 383 .clkr = { 384 .enable_reg = 0x2a74, 385 .enable_mask = BIT(11), 386 .hw.init = &(struct clk_init_data){ 387 .name = "gsbi6_uart_src", 388 .parent_names = gcc_pxo_pll8, 389 .num_parents = 2, 390 .ops = &clk_rcg_ops, 391 .flags = CLK_SET_PARENT_GATE, 392 }, 393 }, 394 }; 395 396 static struct clk_branch gsbi6_uart_clk = { 397 .halt_reg = 0x2fd0, 398 .halt_bit = 18, 399 .clkr = { 400 .enable_reg = 0x2a74, 401 .enable_mask = BIT(9), 402 .hw.init = &(struct clk_init_data){ 403 .name = "gsbi6_uart_clk", 404 .parent_names = (const char *[]){ 405 "gsbi6_uart_src", 406 }, 407 .num_parents = 1, 408 .ops = &clk_branch_ops, 409 .flags = CLK_SET_RATE_PARENT, 410 }, 411 }, 412 }; 413 414 static struct clk_rcg gsbi7_uart_src = { 415 .ns_reg = 0x2a94, 416 .md_reg = 0x2a90, 417 .mn = { 418 .mnctr_en_bit = 8, 419 .mnctr_reset_bit = 7, 420 .mnctr_mode_shift = 5, 421 .n_val_shift = 16, 422 .m_val_shift = 16, 423 .width = 16, 424 }, 425 .p = { 426 .pre_div_shift = 3, 427 .pre_div_width = 2, 428 }, 429 .s = { 430 .src_sel_shift = 0, 431 .parent_map = gcc_pxo_pll8_map, 432 }, 433 .freq_tbl = clk_tbl_gsbi_uart, 434 .clkr = { 435 .enable_reg = 0x2a94, 436 .enable_mask = BIT(11), 437 .hw.init = &(struct clk_init_data){ 438 .name = "gsbi7_uart_src", 439 .parent_names = gcc_pxo_pll8, 440 .num_parents = 2, 441 .ops = &clk_rcg_ops, 442 .flags = CLK_SET_PARENT_GATE, 443 }, 444 }, 445 }; 446 447 static struct clk_branch gsbi7_uart_clk = { 448 .halt_reg = 0x2fd0, 449 .halt_bit = 14, 450 .clkr = { 451 .enable_reg = 0x2a94, 452 .enable_mask = BIT(9), 453 .hw.init = &(struct clk_init_data){ 454 .name = "gsbi7_uart_clk", 455 .parent_names = (const char *[]){ 456 "gsbi7_uart_src", 457 }, 458 .num_parents = 1, 459 .ops = &clk_branch_ops, 460 .flags = CLK_SET_RATE_PARENT, 461 }, 462 }, 463 }; 464 465 static struct clk_rcg gsbi8_uart_src = { 466 .ns_reg = 0x2ab4, 467 .md_reg = 0x2ab0, 468 .mn = { 469 .mnctr_en_bit = 8, 470 .mnctr_reset_bit = 7, 471 .mnctr_mode_shift = 5, 472 .n_val_shift = 16, 473 .m_val_shift = 16, 474 .width = 16, 475 }, 476 .p = { 477 .pre_div_shift = 3, 478 .pre_div_width = 2, 479 }, 480 .s = { 481 .src_sel_shift = 0, 482 .parent_map = gcc_pxo_pll8_map, 483 }, 484 .freq_tbl = clk_tbl_gsbi_uart, 485 .clkr = { 486 .enable_reg = 0x2ab4, 487 .enable_mask = BIT(11), 488 .hw.init = &(struct clk_init_data){ 489 .name = "gsbi8_uart_src", 490 .parent_names = gcc_pxo_pll8, 491 .num_parents = 2, 492 .ops = &clk_rcg_ops, 493 .flags = CLK_SET_PARENT_GATE, 494 }, 495 }, 496 }; 497 498 static struct clk_branch gsbi8_uart_clk = { 499 .halt_reg = 0x2fd0, 500 .halt_bit = 10, 501 .clkr = { 502 .enable_reg = 0x2ab4, 503 .enable_mask = BIT(9), 504 .hw.init = &(struct clk_init_data){ 505 .name = "gsbi8_uart_clk", 506 .parent_names = (const char *[]){ "gsbi8_uart_src" }, 507 .num_parents = 1, 508 .ops = &clk_branch_ops, 509 .flags = CLK_SET_RATE_PARENT, 510 }, 511 }, 512 }; 513 514 static struct clk_rcg gsbi9_uart_src = { 515 .ns_reg = 0x2ad4, 516 .md_reg = 0x2ad0, 517 .mn = { 518 .mnctr_en_bit = 8, 519 .mnctr_reset_bit = 7, 520 .mnctr_mode_shift = 5, 521 .n_val_shift = 16, 522 .m_val_shift = 16, 523 .width = 16, 524 }, 525 .p = { 526 .pre_div_shift = 3, 527 .pre_div_width = 2, 528 }, 529 .s = { 530 .src_sel_shift = 0, 531 .parent_map = gcc_pxo_pll8_map, 532 }, 533 .freq_tbl = clk_tbl_gsbi_uart, 534 .clkr = { 535 .enable_reg = 0x2ad4, 536 .enable_mask = BIT(11), 537 .hw.init = &(struct clk_init_data){ 538 .name = "gsbi9_uart_src", 539 .parent_names = gcc_pxo_pll8, 540 .num_parents = 2, 541 .ops = &clk_rcg_ops, 542 .flags = CLK_SET_PARENT_GATE, 543 }, 544 }, 545 }; 546 547 static struct clk_branch gsbi9_uart_clk = { 548 .halt_reg = 0x2fd0, 549 .halt_bit = 6, 550 .clkr = { 551 .enable_reg = 0x2ad4, 552 .enable_mask = BIT(9), 553 .hw.init = &(struct clk_init_data){ 554 .name = "gsbi9_uart_clk", 555 .parent_names = (const char *[]){ "gsbi9_uart_src" }, 556 .num_parents = 1, 557 .ops = &clk_branch_ops, 558 .flags = CLK_SET_RATE_PARENT, 559 }, 560 }, 561 }; 562 563 static struct clk_rcg gsbi10_uart_src = { 564 .ns_reg = 0x2af4, 565 .md_reg = 0x2af0, 566 .mn = { 567 .mnctr_en_bit = 8, 568 .mnctr_reset_bit = 7, 569 .mnctr_mode_shift = 5, 570 .n_val_shift = 16, 571 .m_val_shift = 16, 572 .width = 16, 573 }, 574 .p = { 575 .pre_div_shift = 3, 576 .pre_div_width = 2, 577 }, 578 .s = { 579 .src_sel_shift = 0, 580 .parent_map = gcc_pxo_pll8_map, 581 }, 582 .freq_tbl = clk_tbl_gsbi_uart, 583 .clkr = { 584 .enable_reg = 0x2af4, 585 .enable_mask = BIT(11), 586 .hw.init = &(struct clk_init_data){ 587 .name = "gsbi10_uart_src", 588 .parent_names = gcc_pxo_pll8, 589 .num_parents = 2, 590 .ops = &clk_rcg_ops, 591 .flags = CLK_SET_PARENT_GATE, 592 }, 593 }, 594 }; 595 596 static struct clk_branch gsbi10_uart_clk = { 597 .halt_reg = 0x2fd0, 598 .halt_bit = 2, 599 .clkr = { 600 .enable_reg = 0x2af4, 601 .enable_mask = BIT(9), 602 .hw.init = &(struct clk_init_data){ 603 .name = "gsbi10_uart_clk", 604 .parent_names = (const char *[]){ "gsbi10_uart_src" }, 605 .num_parents = 1, 606 .ops = &clk_branch_ops, 607 .flags = CLK_SET_RATE_PARENT, 608 }, 609 }, 610 }; 611 612 static struct clk_rcg gsbi11_uart_src = { 613 .ns_reg = 0x2b14, 614 .md_reg = 0x2b10, 615 .mn = { 616 .mnctr_en_bit = 8, 617 .mnctr_reset_bit = 7, 618 .mnctr_mode_shift = 5, 619 .n_val_shift = 16, 620 .m_val_shift = 16, 621 .width = 16, 622 }, 623 .p = { 624 .pre_div_shift = 3, 625 .pre_div_width = 2, 626 }, 627 .s = { 628 .src_sel_shift = 0, 629 .parent_map = gcc_pxo_pll8_map, 630 }, 631 .freq_tbl = clk_tbl_gsbi_uart, 632 .clkr = { 633 .enable_reg = 0x2b14, 634 .enable_mask = BIT(11), 635 .hw.init = &(struct clk_init_data){ 636 .name = "gsbi11_uart_src", 637 .parent_names = gcc_pxo_pll8, 638 .num_parents = 2, 639 .ops = &clk_rcg_ops, 640 .flags = CLK_SET_PARENT_GATE, 641 }, 642 }, 643 }; 644 645 static struct clk_branch gsbi11_uart_clk = { 646 .halt_reg = 0x2fd4, 647 .halt_bit = 17, 648 .clkr = { 649 .enable_reg = 0x2b14, 650 .enable_mask = BIT(9), 651 .hw.init = &(struct clk_init_data){ 652 .name = "gsbi11_uart_clk", 653 .parent_names = (const char *[]){ "gsbi11_uart_src" }, 654 .num_parents = 1, 655 .ops = &clk_branch_ops, 656 .flags = CLK_SET_RATE_PARENT, 657 }, 658 }, 659 }; 660 661 static struct clk_rcg gsbi12_uart_src = { 662 .ns_reg = 0x2b34, 663 .md_reg = 0x2b30, 664 .mn = { 665 .mnctr_en_bit = 8, 666 .mnctr_reset_bit = 7, 667 .mnctr_mode_shift = 5, 668 .n_val_shift = 16, 669 .m_val_shift = 16, 670 .width = 16, 671 }, 672 .p = { 673 .pre_div_shift = 3, 674 .pre_div_width = 2, 675 }, 676 .s = { 677 .src_sel_shift = 0, 678 .parent_map = gcc_pxo_pll8_map, 679 }, 680 .freq_tbl = clk_tbl_gsbi_uart, 681 .clkr = { 682 .enable_reg = 0x2b34, 683 .enable_mask = BIT(11), 684 .hw.init = &(struct clk_init_data){ 685 .name = "gsbi12_uart_src", 686 .parent_names = gcc_pxo_pll8, 687 .num_parents = 2, 688 .ops = &clk_rcg_ops, 689 .flags = CLK_SET_PARENT_GATE, 690 }, 691 }, 692 }; 693 694 static struct clk_branch gsbi12_uart_clk = { 695 .halt_reg = 0x2fd4, 696 .halt_bit = 13, 697 .clkr = { 698 .enable_reg = 0x2b34, 699 .enable_mask = BIT(9), 700 .hw.init = &(struct clk_init_data){ 701 .name = "gsbi12_uart_clk", 702 .parent_names = (const char *[]){ "gsbi12_uart_src" }, 703 .num_parents = 1, 704 .ops = &clk_branch_ops, 705 .flags = CLK_SET_RATE_PARENT, 706 }, 707 }, 708 }; 709 710 static struct freq_tbl clk_tbl_gsbi_qup[] = { 711 { 1100000, P_PXO, 1, 2, 49 }, 712 { 5400000, P_PXO, 1, 1, 5 }, 713 { 10800000, P_PXO, 1, 2, 5 }, 714 { 15060000, P_PLL8, 1, 2, 51 }, 715 { 24000000, P_PLL8, 4, 1, 4 }, 716 { 25600000, P_PLL8, 1, 1, 15 }, 717 { 27000000, P_PXO, 1, 0, 0 }, 718 { 48000000, P_PLL8, 4, 1, 2 }, 719 { 51200000, P_PLL8, 1, 2, 15 }, 720 { } 721 }; 722 723 static struct clk_rcg gsbi1_qup_src = { 724 .ns_reg = 0x29cc, 725 .md_reg = 0x29c8, 726 .mn = { 727 .mnctr_en_bit = 8, 728 .mnctr_reset_bit = 7, 729 .mnctr_mode_shift = 5, 730 .n_val_shift = 16, 731 .m_val_shift = 16, 732 .width = 8, 733 }, 734 .p = { 735 .pre_div_shift = 3, 736 .pre_div_width = 2, 737 }, 738 .s = { 739 .src_sel_shift = 0, 740 .parent_map = gcc_pxo_pll8_map, 741 }, 742 .freq_tbl = clk_tbl_gsbi_qup, 743 .clkr = { 744 .enable_reg = 0x29cc, 745 .enable_mask = BIT(11), 746 .hw.init = &(struct clk_init_data){ 747 .name = "gsbi1_qup_src", 748 .parent_names = gcc_pxo_pll8, 749 .num_parents = 2, 750 .ops = &clk_rcg_ops, 751 .flags = CLK_SET_PARENT_GATE, 752 }, 753 }, 754 }; 755 756 static struct clk_branch gsbi1_qup_clk = { 757 .halt_reg = 0x2fcc, 758 .halt_bit = 9, 759 .clkr = { 760 .enable_reg = 0x29cc, 761 .enable_mask = BIT(9), 762 .hw.init = &(struct clk_init_data){ 763 .name = "gsbi1_qup_clk", 764 .parent_names = (const char *[]){ "gsbi1_qup_src" }, 765 .num_parents = 1, 766 .ops = &clk_branch_ops, 767 .flags = CLK_SET_RATE_PARENT, 768 }, 769 }, 770 }; 771 772 static struct clk_rcg gsbi2_qup_src = { 773 .ns_reg = 0x29ec, 774 .md_reg = 0x29e8, 775 .mn = { 776 .mnctr_en_bit = 8, 777 .mnctr_reset_bit = 7, 778 .mnctr_mode_shift = 5, 779 .n_val_shift = 16, 780 .m_val_shift = 16, 781 .width = 8, 782 }, 783 .p = { 784 .pre_div_shift = 3, 785 .pre_div_width = 2, 786 }, 787 .s = { 788 .src_sel_shift = 0, 789 .parent_map = gcc_pxo_pll8_map, 790 }, 791 .freq_tbl = clk_tbl_gsbi_qup, 792 .clkr = { 793 .enable_reg = 0x29ec, 794 .enable_mask = BIT(11), 795 .hw.init = &(struct clk_init_data){ 796 .name = "gsbi2_qup_src", 797 .parent_names = gcc_pxo_pll8, 798 .num_parents = 2, 799 .ops = &clk_rcg_ops, 800 .flags = CLK_SET_PARENT_GATE, 801 }, 802 }, 803 }; 804 805 static struct clk_branch gsbi2_qup_clk = { 806 .halt_reg = 0x2fcc, 807 .halt_bit = 4, 808 .clkr = { 809 .enable_reg = 0x29ec, 810 .enable_mask = BIT(9), 811 .hw.init = &(struct clk_init_data){ 812 .name = "gsbi2_qup_clk", 813 .parent_names = (const char *[]){ "gsbi2_qup_src" }, 814 .num_parents = 1, 815 .ops = &clk_branch_ops, 816 .flags = CLK_SET_RATE_PARENT, 817 }, 818 }, 819 }; 820 821 static struct clk_rcg gsbi3_qup_src = { 822 .ns_reg = 0x2a0c, 823 .md_reg = 0x2a08, 824 .mn = { 825 .mnctr_en_bit = 8, 826 .mnctr_reset_bit = 7, 827 .mnctr_mode_shift = 5, 828 .n_val_shift = 16, 829 .m_val_shift = 16, 830 .width = 8, 831 }, 832 .p = { 833 .pre_div_shift = 3, 834 .pre_div_width = 2, 835 }, 836 .s = { 837 .src_sel_shift = 0, 838 .parent_map = gcc_pxo_pll8_map, 839 }, 840 .freq_tbl = clk_tbl_gsbi_qup, 841 .clkr = { 842 .enable_reg = 0x2a0c, 843 .enable_mask = BIT(11), 844 .hw.init = &(struct clk_init_data){ 845 .name = "gsbi3_qup_src", 846 .parent_names = gcc_pxo_pll8, 847 .num_parents = 2, 848 .ops = &clk_rcg_ops, 849 .flags = CLK_SET_PARENT_GATE, 850 }, 851 }, 852 }; 853 854 static struct clk_branch gsbi3_qup_clk = { 855 .halt_reg = 0x2fcc, 856 .halt_bit = 0, 857 .clkr = { 858 .enable_reg = 0x2a0c, 859 .enable_mask = BIT(9), 860 .hw.init = &(struct clk_init_data){ 861 .name = "gsbi3_qup_clk", 862 .parent_names = (const char *[]){ "gsbi3_qup_src" }, 863 .num_parents = 1, 864 .ops = &clk_branch_ops, 865 .flags = CLK_SET_RATE_PARENT, 866 }, 867 }, 868 }; 869 870 static struct clk_rcg gsbi4_qup_src = { 871 .ns_reg = 0x2a2c, 872 .md_reg = 0x2a28, 873 .mn = { 874 .mnctr_en_bit = 8, 875 .mnctr_reset_bit = 7, 876 .mnctr_mode_shift = 5, 877 .n_val_shift = 16, 878 .m_val_shift = 16, 879 .width = 8, 880 }, 881 .p = { 882 .pre_div_shift = 3, 883 .pre_div_width = 2, 884 }, 885 .s = { 886 .src_sel_shift = 0, 887 .parent_map = gcc_pxo_pll8_map, 888 }, 889 .freq_tbl = clk_tbl_gsbi_qup, 890 .clkr = { 891 .enable_reg = 0x2a2c, 892 .enable_mask = BIT(11), 893 .hw.init = &(struct clk_init_data){ 894 .name = "gsbi4_qup_src", 895 .parent_names = gcc_pxo_pll8, 896 .num_parents = 2, 897 .ops = &clk_rcg_ops, 898 .flags = CLK_SET_PARENT_GATE, 899 }, 900 }, 901 }; 902 903 static struct clk_branch gsbi4_qup_clk = { 904 .halt_reg = 0x2fd0, 905 .halt_bit = 24, 906 .clkr = { 907 .enable_reg = 0x2a2c, 908 .enable_mask = BIT(9), 909 .hw.init = &(struct clk_init_data){ 910 .name = "gsbi4_qup_clk", 911 .parent_names = (const char *[]){ "gsbi4_qup_src" }, 912 .num_parents = 1, 913 .ops = &clk_branch_ops, 914 .flags = CLK_SET_RATE_PARENT, 915 }, 916 }, 917 }; 918 919 static struct clk_rcg gsbi5_qup_src = { 920 .ns_reg = 0x2a4c, 921 .md_reg = 0x2a48, 922 .mn = { 923 .mnctr_en_bit = 8, 924 .mnctr_reset_bit = 7, 925 .mnctr_mode_shift = 5, 926 .n_val_shift = 16, 927 .m_val_shift = 16, 928 .width = 8, 929 }, 930 .p = { 931 .pre_div_shift = 3, 932 .pre_div_width = 2, 933 }, 934 .s = { 935 .src_sel_shift = 0, 936 .parent_map = gcc_pxo_pll8_map, 937 }, 938 .freq_tbl = clk_tbl_gsbi_qup, 939 .clkr = { 940 .enable_reg = 0x2a4c, 941 .enable_mask = BIT(11), 942 .hw.init = &(struct clk_init_data){ 943 .name = "gsbi5_qup_src", 944 .parent_names = gcc_pxo_pll8, 945 .num_parents = 2, 946 .ops = &clk_rcg_ops, 947 .flags = CLK_SET_PARENT_GATE, 948 }, 949 }, 950 }; 951 952 static struct clk_branch gsbi5_qup_clk = { 953 .halt_reg = 0x2fd0, 954 .halt_bit = 20, 955 .clkr = { 956 .enable_reg = 0x2a4c, 957 .enable_mask = BIT(9), 958 .hw.init = &(struct clk_init_data){ 959 .name = "gsbi5_qup_clk", 960 .parent_names = (const char *[]){ "gsbi5_qup_src" }, 961 .num_parents = 1, 962 .ops = &clk_branch_ops, 963 .flags = CLK_SET_RATE_PARENT, 964 }, 965 }, 966 }; 967 968 static struct clk_rcg gsbi6_qup_src = { 969 .ns_reg = 0x2a6c, 970 .md_reg = 0x2a68, 971 .mn = { 972 .mnctr_en_bit = 8, 973 .mnctr_reset_bit = 7, 974 .mnctr_mode_shift = 5, 975 .n_val_shift = 16, 976 .m_val_shift = 16, 977 .width = 8, 978 }, 979 .p = { 980 .pre_div_shift = 3, 981 .pre_div_width = 2, 982 }, 983 .s = { 984 .src_sel_shift = 0, 985 .parent_map = gcc_pxo_pll8_map, 986 }, 987 .freq_tbl = clk_tbl_gsbi_qup, 988 .clkr = { 989 .enable_reg = 0x2a6c, 990 .enable_mask = BIT(11), 991 .hw.init = &(struct clk_init_data){ 992 .name = "gsbi6_qup_src", 993 .parent_names = gcc_pxo_pll8, 994 .num_parents = 2, 995 .ops = &clk_rcg_ops, 996 .flags = CLK_SET_PARENT_GATE, 997 }, 998 }, 999 }; 1000 1001 static struct clk_branch gsbi6_qup_clk = { 1002 .halt_reg = 0x2fd0, 1003 .halt_bit = 16, 1004 .clkr = { 1005 .enable_reg = 0x2a6c, 1006 .enable_mask = BIT(9), 1007 .hw.init = &(struct clk_init_data){ 1008 .name = "gsbi6_qup_clk", 1009 .parent_names = (const char *[]){ "gsbi6_qup_src" }, 1010 .num_parents = 1, 1011 .ops = &clk_branch_ops, 1012 .flags = CLK_SET_RATE_PARENT, 1013 }, 1014 }, 1015 }; 1016 1017 static struct clk_rcg gsbi7_qup_src = { 1018 .ns_reg = 0x2a8c, 1019 .md_reg = 0x2a88, 1020 .mn = { 1021 .mnctr_en_bit = 8, 1022 .mnctr_reset_bit = 7, 1023 .mnctr_mode_shift = 5, 1024 .n_val_shift = 16, 1025 .m_val_shift = 16, 1026 .width = 8, 1027 }, 1028 .p = { 1029 .pre_div_shift = 3, 1030 .pre_div_width = 2, 1031 }, 1032 .s = { 1033 .src_sel_shift = 0, 1034 .parent_map = gcc_pxo_pll8_map, 1035 }, 1036 .freq_tbl = clk_tbl_gsbi_qup, 1037 .clkr = { 1038 .enable_reg = 0x2a8c, 1039 .enable_mask = BIT(11), 1040 .hw.init = &(struct clk_init_data){ 1041 .name = "gsbi7_qup_src", 1042 .parent_names = gcc_pxo_pll8, 1043 .num_parents = 2, 1044 .ops = &clk_rcg_ops, 1045 .flags = CLK_SET_PARENT_GATE, 1046 }, 1047 }, 1048 }; 1049 1050 static struct clk_branch gsbi7_qup_clk = { 1051 .halt_reg = 0x2fd0, 1052 .halt_bit = 12, 1053 .clkr = { 1054 .enable_reg = 0x2a8c, 1055 .enable_mask = BIT(9), 1056 .hw.init = &(struct clk_init_data){ 1057 .name = "gsbi7_qup_clk", 1058 .parent_names = (const char *[]){ "gsbi7_qup_src" }, 1059 .num_parents = 1, 1060 .ops = &clk_branch_ops, 1061 .flags = CLK_SET_RATE_PARENT, 1062 }, 1063 }, 1064 }; 1065 1066 static struct clk_rcg gsbi8_qup_src = { 1067 .ns_reg = 0x2aac, 1068 .md_reg = 0x2aa8, 1069 .mn = { 1070 .mnctr_en_bit = 8, 1071 .mnctr_reset_bit = 7, 1072 .mnctr_mode_shift = 5, 1073 .n_val_shift = 16, 1074 .m_val_shift = 16, 1075 .width = 8, 1076 }, 1077 .p = { 1078 .pre_div_shift = 3, 1079 .pre_div_width = 2, 1080 }, 1081 .s = { 1082 .src_sel_shift = 0, 1083 .parent_map = gcc_pxo_pll8_map, 1084 }, 1085 .freq_tbl = clk_tbl_gsbi_qup, 1086 .clkr = { 1087 .enable_reg = 0x2aac, 1088 .enable_mask = BIT(11), 1089 .hw.init = &(struct clk_init_data){ 1090 .name = "gsbi8_qup_src", 1091 .parent_names = gcc_pxo_pll8, 1092 .num_parents = 2, 1093 .ops = &clk_rcg_ops, 1094 .flags = CLK_SET_PARENT_GATE, 1095 }, 1096 }, 1097 }; 1098 1099 static struct clk_branch gsbi8_qup_clk = { 1100 .halt_reg = 0x2fd0, 1101 .halt_bit = 8, 1102 .clkr = { 1103 .enable_reg = 0x2aac, 1104 .enable_mask = BIT(9), 1105 .hw.init = &(struct clk_init_data){ 1106 .name = "gsbi8_qup_clk", 1107 .parent_names = (const char *[]){ "gsbi8_qup_src" }, 1108 .num_parents = 1, 1109 .ops = &clk_branch_ops, 1110 .flags = CLK_SET_RATE_PARENT, 1111 }, 1112 }, 1113 }; 1114 1115 static struct clk_rcg gsbi9_qup_src = { 1116 .ns_reg = 0x2acc, 1117 .md_reg = 0x2ac8, 1118 .mn = { 1119 .mnctr_en_bit = 8, 1120 .mnctr_reset_bit = 7, 1121 .mnctr_mode_shift = 5, 1122 .n_val_shift = 16, 1123 .m_val_shift = 16, 1124 .width = 8, 1125 }, 1126 .p = { 1127 .pre_div_shift = 3, 1128 .pre_div_width = 2, 1129 }, 1130 .s = { 1131 .src_sel_shift = 0, 1132 .parent_map = gcc_pxo_pll8_map, 1133 }, 1134 .freq_tbl = clk_tbl_gsbi_qup, 1135 .clkr = { 1136 .enable_reg = 0x2acc, 1137 .enable_mask = BIT(11), 1138 .hw.init = &(struct clk_init_data){ 1139 .name = "gsbi9_qup_src", 1140 .parent_names = gcc_pxo_pll8, 1141 .num_parents = 2, 1142 .ops = &clk_rcg_ops, 1143 .flags = CLK_SET_PARENT_GATE, 1144 }, 1145 }, 1146 }; 1147 1148 static struct clk_branch gsbi9_qup_clk = { 1149 .halt_reg = 0x2fd0, 1150 .halt_bit = 4, 1151 .clkr = { 1152 .enable_reg = 0x2acc, 1153 .enable_mask = BIT(9), 1154 .hw.init = &(struct clk_init_data){ 1155 .name = "gsbi9_qup_clk", 1156 .parent_names = (const char *[]){ "gsbi9_qup_src" }, 1157 .num_parents = 1, 1158 .ops = &clk_branch_ops, 1159 .flags = CLK_SET_RATE_PARENT, 1160 }, 1161 }, 1162 }; 1163 1164 static struct clk_rcg gsbi10_qup_src = { 1165 .ns_reg = 0x2aec, 1166 .md_reg = 0x2ae8, 1167 .mn = { 1168 .mnctr_en_bit = 8, 1169 .mnctr_reset_bit = 7, 1170 .mnctr_mode_shift = 5, 1171 .n_val_shift = 16, 1172 .m_val_shift = 16, 1173 .width = 8, 1174 }, 1175 .p = { 1176 .pre_div_shift = 3, 1177 .pre_div_width = 2, 1178 }, 1179 .s = { 1180 .src_sel_shift = 0, 1181 .parent_map = gcc_pxo_pll8_map, 1182 }, 1183 .freq_tbl = clk_tbl_gsbi_qup, 1184 .clkr = { 1185 .enable_reg = 0x2aec, 1186 .enable_mask = BIT(11), 1187 .hw.init = &(struct clk_init_data){ 1188 .name = "gsbi10_qup_src", 1189 .parent_names = gcc_pxo_pll8, 1190 .num_parents = 2, 1191 .ops = &clk_rcg_ops, 1192 .flags = CLK_SET_PARENT_GATE, 1193 }, 1194 }, 1195 }; 1196 1197 static struct clk_branch gsbi10_qup_clk = { 1198 .halt_reg = 0x2fd0, 1199 .halt_bit = 0, 1200 .clkr = { 1201 .enable_reg = 0x2aec, 1202 .enable_mask = BIT(9), 1203 .hw.init = &(struct clk_init_data){ 1204 .name = "gsbi10_qup_clk", 1205 .parent_names = (const char *[]){ "gsbi10_qup_src" }, 1206 .num_parents = 1, 1207 .ops = &clk_branch_ops, 1208 .flags = CLK_SET_RATE_PARENT, 1209 }, 1210 }, 1211 }; 1212 1213 static struct clk_rcg gsbi11_qup_src = { 1214 .ns_reg = 0x2b0c, 1215 .md_reg = 0x2b08, 1216 .mn = { 1217 .mnctr_en_bit = 8, 1218 .mnctr_reset_bit = 7, 1219 .mnctr_mode_shift = 5, 1220 .n_val_shift = 16, 1221 .m_val_shift = 16, 1222 .width = 8, 1223 }, 1224 .p = { 1225 .pre_div_shift = 3, 1226 .pre_div_width = 2, 1227 }, 1228 .s = { 1229 .src_sel_shift = 0, 1230 .parent_map = gcc_pxo_pll8_map, 1231 }, 1232 .freq_tbl = clk_tbl_gsbi_qup, 1233 .clkr = { 1234 .enable_reg = 0x2b0c, 1235 .enable_mask = BIT(11), 1236 .hw.init = &(struct clk_init_data){ 1237 .name = "gsbi11_qup_src", 1238 .parent_names = gcc_pxo_pll8, 1239 .num_parents = 2, 1240 .ops = &clk_rcg_ops, 1241 .flags = CLK_SET_PARENT_GATE, 1242 }, 1243 }, 1244 }; 1245 1246 static struct clk_branch gsbi11_qup_clk = { 1247 .halt_reg = 0x2fd4, 1248 .halt_bit = 15, 1249 .clkr = { 1250 .enable_reg = 0x2b0c, 1251 .enable_mask = BIT(9), 1252 .hw.init = &(struct clk_init_data){ 1253 .name = "gsbi11_qup_clk", 1254 .parent_names = (const char *[]){ "gsbi11_qup_src" }, 1255 .num_parents = 1, 1256 .ops = &clk_branch_ops, 1257 .flags = CLK_SET_RATE_PARENT, 1258 }, 1259 }, 1260 }; 1261 1262 static struct clk_rcg gsbi12_qup_src = { 1263 .ns_reg = 0x2b2c, 1264 .md_reg = 0x2b28, 1265 .mn = { 1266 .mnctr_en_bit = 8, 1267 .mnctr_reset_bit = 7, 1268 .mnctr_mode_shift = 5, 1269 .n_val_shift = 16, 1270 .m_val_shift = 16, 1271 .width = 8, 1272 }, 1273 .p = { 1274 .pre_div_shift = 3, 1275 .pre_div_width = 2, 1276 }, 1277 .s = { 1278 .src_sel_shift = 0, 1279 .parent_map = gcc_pxo_pll8_map, 1280 }, 1281 .freq_tbl = clk_tbl_gsbi_qup, 1282 .clkr = { 1283 .enable_reg = 0x2b2c, 1284 .enable_mask = BIT(11), 1285 .hw.init = &(struct clk_init_data){ 1286 .name = "gsbi12_qup_src", 1287 .parent_names = gcc_pxo_pll8, 1288 .num_parents = 2, 1289 .ops = &clk_rcg_ops, 1290 .flags = CLK_SET_PARENT_GATE, 1291 }, 1292 }, 1293 }; 1294 1295 static struct clk_branch gsbi12_qup_clk = { 1296 .halt_reg = 0x2fd4, 1297 .halt_bit = 11, 1298 .clkr = { 1299 .enable_reg = 0x2b2c, 1300 .enable_mask = BIT(9), 1301 .hw.init = &(struct clk_init_data){ 1302 .name = "gsbi12_qup_clk", 1303 .parent_names = (const char *[]){ "gsbi12_qup_src" }, 1304 .num_parents = 1, 1305 .ops = &clk_branch_ops, 1306 .flags = CLK_SET_RATE_PARENT, 1307 }, 1308 }, 1309 }; 1310 1311 static const struct freq_tbl clk_tbl_gp[] = { 1312 { 9600000, P_CXO, 2, 0, 0 }, 1313 { 13500000, P_PXO, 2, 0, 0 }, 1314 { 19200000, P_CXO, 1, 0, 0 }, 1315 { 27000000, P_PXO, 1, 0, 0 }, 1316 { 64000000, P_PLL8, 2, 1, 3 }, 1317 { 76800000, P_PLL8, 1, 1, 5 }, 1318 { 96000000, P_PLL8, 4, 0, 0 }, 1319 { 128000000, P_PLL8, 3, 0, 0 }, 1320 { 192000000, P_PLL8, 2, 0, 0 }, 1321 { } 1322 }; 1323 1324 static struct clk_rcg gp0_src = { 1325 .ns_reg = 0x2d24, 1326 .md_reg = 0x2d00, 1327 .mn = { 1328 .mnctr_en_bit = 8, 1329 .mnctr_reset_bit = 7, 1330 .mnctr_mode_shift = 5, 1331 .n_val_shift = 16, 1332 .m_val_shift = 16, 1333 .width = 8, 1334 }, 1335 .p = { 1336 .pre_div_shift = 3, 1337 .pre_div_width = 2, 1338 }, 1339 .s = { 1340 .src_sel_shift = 0, 1341 .parent_map = gcc_pxo_pll8_cxo_map, 1342 }, 1343 .freq_tbl = clk_tbl_gp, 1344 .clkr = { 1345 .enable_reg = 0x2d24, 1346 .enable_mask = BIT(11), 1347 .hw.init = &(struct clk_init_data){ 1348 .name = "gp0_src", 1349 .parent_names = gcc_pxo_pll8_cxo, 1350 .num_parents = 3, 1351 .ops = &clk_rcg_ops, 1352 .flags = CLK_SET_PARENT_GATE, 1353 }, 1354 } 1355 }; 1356 1357 static struct clk_branch gp0_clk = { 1358 .halt_reg = 0x2fd8, 1359 .halt_bit = 7, 1360 .clkr = { 1361 .enable_reg = 0x2d24, 1362 .enable_mask = BIT(9), 1363 .hw.init = &(struct clk_init_data){ 1364 .name = "gp0_clk", 1365 .parent_names = (const char *[]){ "gp0_src" }, 1366 .num_parents = 1, 1367 .ops = &clk_branch_ops, 1368 .flags = CLK_SET_RATE_PARENT, 1369 }, 1370 }, 1371 }; 1372 1373 static struct clk_rcg gp1_src = { 1374 .ns_reg = 0x2d44, 1375 .md_reg = 0x2d40, 1376 .mn = { 1377 .mnctr_en_bit = 8, 1378 .mnctr_reset_bit = 7, 1379 .mnctr_mode_shift = 5, 1380 .n_val_shift = 16, 1381 .m_val_shift = 16, 1382 .width = 8, 1383 }, 1384 .p = { 1385 .pre_div_shift = 3, 1386 .pre_div_width = 2, 1387 }, 1388 .s = { 1389 .src_sel_shift = 0, 1390 .parent_map = gcc_pxo_pll8_cxo_map, 1391 }, 1392 .freq_tbl = clk_tbl_gp, 1393 .clkr = { 1394 .enable_reg = 0x2d44, 1395 .enable_mask = BIT(11), 1396 .hw.init = &(struct clk_init_data){ 1397 .name = "gp1_src", 1398 .parent_names = gcc_pxo_pll8_cxo, 1399 .num_parents = 3, 1400 .ops = &clk_rcg_ops, 1401 .flags = CLK_SET_RATE_GATE, 1402 }, 1403 } 1404 }; 1405 1406 static struct clk_branch gp1_clk = { 1407 .halt_reg = 0x2fd8, 1408 .halt_bit = 6, 1409 .clkr = { 1410 .enable_reg = 0x2d44, 1411 .enable_mask = BIT(9), 1412 .hw.init = &(struct clk_init_data){ 1413 .name = "gp1_clk", 1414 .parent_names = (const char *[]){ "gp1_src" }, 1415 .num_parents = 1, 1416 .ops = &clk_branch_ops, 1417 .flags = CLK_SET_RATE_PARENT, 1418 }, 1419 }, 1420 }; 1421 1422 static struct clk_rcg gp2_src = { 1423 .ns_reg = 0x2d64, 1424 .md_reg = 0x2d60, 1425 .mn = { 1426 .mnctr_en_bit = 8, 1427 .mnctr_reset_bit = 7, 1428 .mnctr_mode_shift = 5, 1429 .n_val_shift = 16, 1430 .m_val_shift = 16, 1431 .width = 8, 1432 }, 1433 .p = { 1434 .pre_div_shift = 3, 1435 .pre_div_width = 2, 1436 }, 1437 .s = { 1438 .src_sel_shift = 0, 1439 .parent_map = gcc_pxo_pll8_cxo_map, 1440 }, 1441 .freq_tbl = clk_tbl_gp, 1442 .clkr = { 1443 .enable_reg = 0x2d64, 1444 .enable_mask = BIT(11), 1445 .hw.init = &(struct clk_init_data){ 1446 .name = "gp2_src", 1447 .parent_names = gcc_pxo_pll8_cxo, 1448 .num_parents = 3, 1449 .ops = &clk_rcg_ops, 1450 .flags = CLK_SET_RATE_GATE, 1451 }, 1452 } 1453 }; 1454 1455 static struct clk_branch gp2_clk = { 1456 .halt_reg = 0x2fd8, 1457 .halt_bit = 5, 1458 .clkr = { 1459 .enable_reg = 0x2d64, 1460 .enable_mask = BIT(9), 1461 .hw.init = &(struct clk_init_data){ 1462 .name = "gp2_clk", 1463 .parent_names = (const char *[]){ "gp2_src" }, 1464 .num_parents = 1, 1465 .ops = &clk_branch_ops, 1466 .flags = CLK_SET_RATE_PARENT, 1467 }, 1468 }, 1469 }; 1470 1471 static struct clk_branch pmem_clk = { 1472 .hwcg_reg = 0x25a0, 1473 .hwcg_bit = 6, 1474 .halt_reg = 0x2fc8, 1475 .halt_bit = 20, 1476 .clkr = { 1477 .enable_reg = 0x25a0, 1478 .enable_mask = BIT(4), 1479 .hw.init = &(struct clk_init_data){ 1480 .name = "pmem_clk", 1481 .ops = &clk_branch_ops, 1482 }, 1483 }, 1484 }; 1485 1486 static struct clk_rcg prng_src = { 1487 .ns_reg = 0x2e80, 1488 .p = { 1489 .pre_div_shift = 3, 1490 .pre_div_width = 4, 1491 }, 1492 .s = { 1493 .src_sel_shift = 0, 1494 .parent_map = gcc_pxo_pll8_map, 1495 }, 1496 .clkr.hw = { 1497 .init = &(struct clk_init_data){ 1498 .name = "prng_src", 1499 .parent_names = gcc_pxo_pll8, 1500 .num_parents = 2, 1501 .ops = &clk_rcg_ops, 1502 }, 1503 }, 1504 }; 1505 1506 static struct clk_branch prng_clk = { 1507 .halt_reg = 0x2fd8, 1508 .halt_check = BRANCH_HALT_VOTED, 1509 .halt_bit = 10, 1510 .clkr = { 1511 .enable_reg = 0x3080, 1512 .enable_mask = BIT(10), 1513 .hw.init = &(struct clk_init_data){ 1514 .name = "prng_clk", 1515 .parent_names = (const char *[]){ "prng_src" }, 1516 .num_parents = 1, 1517 .ops = &clk_branch_ops, 1518 }, 1519 }, 1520 }; 1521 1522 static const struct freq_tbl clk_tbl_sdc[] = { 1523 { 144000, P_PXO, 3, 2, 125 }, 1524 { 400000, P_PLL8, 4, 1, 240 }, 1525 { 16000000, P_PLL8, 4, 1, 6 }, 1526 { 17070000, P_PLL8, 1, 2, 45 }, 1527 { 20210000, P_PLL8, 1, 1, 19 }, 1528 { 24000000, P_PLL8, 4, 1, 4 }, 1529 { 48000000, P_PLL8, 4, 1, 2 }, 1530 { } 1531 }; 1532 1533 static struct clk_rcg sdc1_src = { 1534 .ns_reg = 0x282c, 1535 .md_reg = 0x2828, 1536 .mn = { 1537 .mnctr_en_bit = 8, 1538 .mnctr_reset_bit = 7, 1539 .mnctr_mode_shift = 5, 1540 .n_val_shift = 16, 1541 .m_val_shift = 16, 1542 .width = 8, 1543 }, 1544 .p = { 1545 .pre_div_shift = 3, 1546 .pre_div_width = 2, 1547 }, 1548 .s = { 1549 .src_sel_shift = 0, 1550 .parent_map = gcc_pxo_pll8_map, 1551 }, 1552 .freq_tbl = clk_tbl_sdc, 1553 .clkr = { 1554 .enable_reg = 0x282c, 1555 .enable_mask = BIT(11), 1556 .hw.init = &(struct clk_init_data){ 1557 .name = "sdc1_src", 1558 .parent_names = gcc_pxo_pll8, 1559 .num_parents = 2, 1560 .ops = &clk_rcg_ops, 1561 .flags = CLK_SET_RATE_GATE, 1562 }, 1563 } 1564 }; 1565 1566 static struct clk_branch sdc1_clk = { 1567 .halt_reg = 0x2fc8, 1568 .halt_bit = 6, 1569 .clkr = { 1570 .enable_reg = 0x282c, 1571 .enable_mask = BIT(9), 1572 .hw.init = &(struct clk_init_data){ 1573 .name = "sdc1_clk", 1574 .parent_names = (const char *[]){ "sdc1_src" }, 1575 .num_parents = 1, 1576 .ops = &clk_branch_ops, 1577 .flags = CLK_SET_RATE_PARENT, 1578 }, 1579 }, 1580 }; 1581 1582 static struct clk_rcg sdc2_src = { 1583 .ns_reg = 0x284c, 1584 .md_reg = 0x2848, 1585 .mn = { 1586 .mnctr_en_bit = 8, 1587 .mnctr_reset_bit = 7, 1588 .mnctr_mode_shift = 5, 1589 .n_val_shift = 16, 1590 .m_val_shift = 16, 1591 .width = 8, 1592 }, 1593 .p = { 1594 .pre_div_shift = 3, 1595 .pre_div_width = 2, 1596 }, 1597 .s = { 1598 .src_sel_shift = 0, 1599 .parent_map = gcc_pxo_pll8_map, 1600 }, 1601 .freq_tbl = clk_tbl_sdc, 1602 .clkr = { 1603 .enable_reg = 0x284c, 1604 .enable_mask = BIT(11), 1605 .hw.init = &(struct clk_init_data){ 1606 .name = "sdc2_src", 1607 .parent_names = gcc_pxo_pll8, 1608 .num_parents = 2, 1609 .ops = &clk_rcg_ops, 1610 .flags = CLK_SET_RATE_GATE, 1611 }, 1612 } 1613 }; 1614 1615 static struct clk_branch sdc2_clk = { 1616 .halt_reg = 0x2fc8, 1617 .halt_bit = 5, 1618 .clkr = { 1619 .enable_reg = 0x284c, 1620 .enable_mask = BIT(9), 1621 .hw.init = &(struct clk_init_data){ 1622 .name = "sdc2_clk", 1623 .parent_names = (const char *[]){ "sdc2_src" }, 1624 .num_parents = 1, 1625 .ops = &clk_branch_ops, 1626 .flags = CLK_SET_RATE_PARENT, 1627 }, 1628 }, 1629 }; 1630 1631 static struct clk_rcg sdc3_src = { 1632 .ns_reg = 0x286c, 1633 .md_reg = 0x2868, 1634 .mn = { 1635 .mnctr_en_bit = 8, 1636 .mnctr_reset_bit = 7, 1637 .mnctr_mode_shift = 5, 1638 .n_val_shift = 16, 1639 .m_val_shift = 16, 1640 .width = 8, 1641 }, 1642 .p = { 1643 .pre_div_shift = 3, 1644 .pre_div_width = 2, 1645 }, 1646 .s = { 1647 .src_sel_shift = 0, 1648 .parent_map = gcc_pxo_pll8_map, 1649 }, 1650 .freq_tbl = clk_tbl_sdc, 1651 .clkr = { 1652 .enable_reg = 0x286c, 1653 .enable_mask = BIT(11), 1654 .hw.init = &(struct clk_init_data){ 1655 .name = "sdc3_src", 1656 .parent_names = gcc_pxo_pll8, 1657 .num_parents = 2, 1658 .ops = &clk_rcg_ops, 1659 .flags = CLK_SET_RATE_GATE, 1660 }, 1661 } 1662 }; 1663 1664 static struct clk_branch sdc3_clk = { 1665 .halt_reg = 0x2fc8, 1666 .halt_bit = 4, 1667 .clkr = { 1668 .enable_reg = 0x286c, 1669 .enable_mask = BIT(9), 1670 .hw.init = &(struct clk_init_data){ 1671 .name = "sdc3_clk", 1672 .parent_names = (const char *[]){ "sdc3_src" }, 1673 .num_parents = 1, 1674 .ops = &clk_branch_ops, 1675 .flags = CLK_SET_RATE_PARENT, 1676 }, 1677 }, 1678 }; 1679 1680 static struct clk_rcg sdc4_src = { 1681 .ns_reg = 0x288c, 1682 .md_reg = 0x2888, 1683 .mn = { 1684 .mnctr_en_bit = 8, 1685 .mnctr_reset_bit = 7, 1686 .mnctr_mode_shift = 5, 1687 .n_val_shift = 16, 1688 .m_val_shift = 16, 1689 .width = 8, 1690 }, 1691 .p = { 1692 .pre_div_shift = 3, 1693 .pre_div_width = 2, 1694 }, 1695 .s = { 1696 .src_sel_shift = 0, 1697 .parent_map = gcc_pxo_pll8_map, 1698 }, 1699 .freq_tbl = clk_tbl_sdc, 1700 .clkr = { 1701 .enable_reg = 0x288c, 1702 .enable_mask = BIT(11), 1703 .hw.init = &(struct clk_init_data){ 1704 .name = "sdc4_src", 1705 .parent_names = gcc_pxo_pll8, 1706 .num_parents = 2, 1707 .ops = &clk_rcg_ops, 1708 .flags = CLK_SET_RATE_GATE, 1709 }, 1710 } 1711 }; 1712 1713 static struct clk_branch sdc4_clk = { 1714 .halt_reg = 0x2fc8, 1715 .halt_bit = 3, 1716 .clkr = { 1717 .enable_reg = 0x288c, 1718 .enable_mask = BIT(9), 1719 .hw.init = &(struct clk_init_data){ 1720 .name = "sdc4_clk", 1721 .parent_names = (const char *[]){ "sdc4_src" }, 1722 .num_parents = 1, 1723 .ops = &clk_branch_ops, 1724 .flags = CLK_SET_RATE_PARENT, 1725 }, 1726 }, 1727 }; 1728 1729 static struct clk_rcg sdc5_src = { 1730 .ns_reg = 0x28ac, 1731 .md_reg = 0x28a8, 1732 .mn = { 1733 .mnctr_en_bit = 8, 1734 .mnctr_reset_bit = 7, 1735 .mnctr_mode_shift = 5, 1736 .n_val_shift = 16, 1737 .m_val_shift = 16, 1738 .width = 8, 1739 }, 1740 .p = { 1741 .pre_div_shift = 3, 1742 .pre_div_width = 2, 1743 }, 1744 .s = { 1745 .src_sel_shift = 0, 1746 .parent_map = gcc_pxo_pll8_map, 1747 }, 1748 .freq_tbl = clk_tbl_sdc, 1749 .clkr = { 1750 .enable_reg = 0x28ac, 1751 .enable_mask = BIT(11), 1752 .hw.init = &(struct clk_init_data){ 1753 .name = "sdc5_src", 1754 .parent_names = gcc_pxo_pll8, 1755 .num_parents = 2, 1756 .ops = &clk_rcg_ops, 1757 .flags = CLK_SET_RATE_GATE, 1758 }, 1759 } 1760 }; 1761 1762 static struct clk_branch sdc5_clk = { 1763 .halt_reg = 0x2fc8, 1764 .halt_bit = 2, 1765 .clkr = { 1766 .enable_reg = 0x28ac, 1767 .enable_mask = BIT(9), 1768 .hw.init = &(struct clk_init_data){ 1769 .name = "sdc5_clk", 1770 .parent_names = (const char *[]){ "sdc5_src" }, 1771 .num_parents = 1, 1772 .ops = &clk_branch_ops, 1773 .flags = CLK_SET_RATE_PARENT, 1774 }, 1775 }, 1776 }; 1777 1778 static const struct freq_tbl clk_tbl_tsif_ref[] = { 1779 { 105000, P_PXO, 1, 1, 256 }, 1780 { } 1781 }; 1782 1783 static struct clk_rcg tsif_ref_src = { 1784 .ns_reg = 0x2710, 1785 .md_reg = 0x270c, 1786 .mn = { 1787 .mnctr_en_bit = 8, 1788 .mnctr_reset_bit = 7, 1789 .mnctr_mode_shift = 5, 1790 .n_val_shift = 16, 1791 .m_val_shift = 16, 1792 .width = 16, 1793 }, 1794 .p = { 1795 .pre_div_shift = 3, 1796 .pre_div_width = 2, 1797 }, 1798 .s = { 1799 .src_sel_shift = 0, 1800 .parent_map = gcc_pxo_pll8_map, 1801 }, 1802 .freq_tbl = clk_tbl_tsif_ref, 1803 .clkr = { 1804 .enable_reg = 0x2710, 1805 .enable_mask = BIT(11), 1806 .hw.init = &(struct clk_init_data){ 1807 .name = "tsif_ref_src", 1808 .parent_names = gcc_pxo_pll8, 1809 .num_parents = 2, 1810 .ops = &clk_rcg_ops, 1811 .flags = CLK_SET_RATE_GATE, 1812 }, 1813 } 1814 }; 1815 1816 static struct clk_branch tsif_ref_clk = { 1817 .halt_reg = 0x2fd4, 1818 .halt_bit = 5, 1819 .clkr = { 1820 .enable_reg = 0x2710, 1821 .enable_mask = BIT(9), 1822 .hw.init = &(struct clk_init_data){ 1823 .name = "tsif_ref_clk", 1824 .parent_names = (const char *[]){ "tsif_ref_src" }, 1825 .num_parents = 1, 1826 .ops = &clk_branch_ops, 1827 .flags = CLK_SET_RATE_PARENT, 1828 }, 1829 }, 1830 }; 1831 1832 static const struct freq_tbl clk_tbl_usb[] = { 1833 { 60000000, P_PLL8, 1, 5, 32 }, 1834 { } 1835 }; 1836 1837 static struct clk_rcg usb_hs1_xcvr_src = { 1838 .ns_reg = 0x290c, 1839 .md_reg = 0x2908, 1840 .mn = { 1841 .mnctr_en_bit = 8, 1842 .mnctr_reset_bit = 7, 1843 .mnctr_mode_shift = 5, 1844 .n_val_shift = 16, 1845 .m_val_shift = 16, 1846 .width = 8, 1847 }, 1848 .p = { 1849 .pre_div_shift = 3, 1850 .pre_div_width = 2, 1851 }, 1852 .s = { 1853 .src_sel_shift = 0, 1854 .parent_map = gcc_pxo_pll8_map, 1855 }, 1856 .freq_tbl = clk_tbl_usb, 1857 .clkr = { 1858 .enable_reg = 0x290c, 1859 .enable_mask = BIT(11), 1860 .hw.init = &(struct clk_init_data){ 1861 .name = "usb_hs1_xcvr_src", 1862 .parent_names = gcc_pxo_pll8, 1863 .num_parents = 2, 1864 .ops = &clk_rcg_ops, 1865 .flags = CLK_SET_RATE_GATE, 1866 }, 1867 } 1868 }; 1869 1870 static struct clk_branch usb_hs1_xcvr_clk = { 1871 .halt_reg = 0x2fc8, 1872 .halt_bit = 0, 1873 .clkr = { 1874 .enable_reg = 0x290c, 1875 .enable_mask = BIT(9), 1876 .hw.init = &(struct clk_init_data){ 1877 .name = "usb_hs1_xcvr_clk", 1878 .parent_names = (const char *[]){ "usb_hs1_xcvr_src" }, 1879 .num_parents = 1, 1880 .ops = &clk_branch_ops, 1881 .flags = CLK_SET_RATE_PARENT, 1882 }, 1883 }, 1884 }; 1885 1886 static struct clk_rcg usb_fs1_xcvr_fs_src = { 1887 .ns_reg = 0x2968, 1888 .md_reg = 0x2964, 1889 .mn = { 1890 .mnctr_en_bit = 8, 1891 .mnctr_reset_bit = 7, 1892 .mnctr_mode_shift = 5, 1893 .n_val_shift = 16, 1894 .m_val_shift = 16, 1895 .width = 8, 1896 }, 1897 .p = { 1898 .pre_div_shift = 3, 1899 .pre_div_width = 2, 1900 }, 1901 .s = { 1902 .src_sel_shift = 0, 1903 .parent_map = gcc_pxo_pll8_map, 1904 }, 1905 .freq_tbl = clk_tbl_usb, 1906 .clkr = { 1907 .enable_reg = 0x2968, 1908 .enable_mask = BIT(11), 1909 .hw.init = &(struct clk_init_data){ 1910 .name = "usb_fs1_xcvr_fs_src", 1911 .parent_names = gcc_pxo_pll8, 1912 .num_parents = 2, 1913 .ops = &clk_rcg_ops, 1914 .flags = CLK_SET_RATE_GATE, 1915 }, 1916 } 1917 }; 1918 1919 static const char * const usb_fs1_xcvr_fs_src_p[] = { "usb_fs1_xcvr_fs_src" }; 1920 1921 static struct clk_branch usb_fs1_xcvr_fs_clk = { 1922 .halt_reg = 0x2fcc, 1923 .halt_bit = 15, 1924 .clkr = { 1925 .enable_reg = 0x2968, 1926 .enable_mask = BIT(9), 1927 .hw.init = &(struct clk_init_data){ 1928 .name = "usb_fs1_xcvr_fs_clk", 1929 .parent_names = usb_fs1_xcvr_fs_src_p, 1930 .num_parents = 1, 1931 .ops = &clk_branch_ops, 1932 .flags = CLK_SET_RATE_PARENT, 1933 }, 1934 }, 1935 }; 1936 1937 static struct clk_branch usb_fs1_system_clk = { 1938 .halt_reg = 0x2fcc, 1939 .halt_bit = 16, 1940 .clkr = { 1941 .enable_reg = 0x296c, 1942 .enable_mask = BIT(4), 1943 .hw.init = &(struct clk_init_data){ 1944 .parent_names = usb_fs1_xcvr_fs_src_p, 1945 .num_parents = 1, 1946 .name = "usb_fs1_system_clk", 1947 .ops = &clk_branch_ops, 1948 .flags = CLK_SET_RATE_PARENT, 1949 }, 1950 }, 1951 }; 1952 1953 static struct clk_rcg usb_fs2_xcvr_fs_src = { 1954 .ns_reg = 0x2988, 1955 .md_reg = 0x2984, 1956 .mn = { 1957 .mnctr_en_bit = 8, 1958 .mnctr_reset_bit = 7, 1959 .mnctr_mode_shift = 5, 1960 .n_val_shift = 16, 1961 .m_val_shift = 16, 1962 .width = 8, 1963 }, 1964 .p = { 1965 .pre_div_shift = 3, 1966 .pre_div_width = 2, 1967 }, 1968 .s = { 1969 .src_sel_shift = 0, 1970 .parent_map = gcc_pxo_pll8_map, 1971 }, 1972 .freq_tbl = clk_tbl_usb, 1973 .clkr = { 1974 .enable_reg = 0x2988, 1975 .enable_mask = BIT(11), 1976 .hw.init = &(struct clk_init_data){ 1977 .name = "usb_fs2_xcvr_fs_src", 1978 .parent_names = gcc_pxo_pll8, 1979 .num_parents = 2, 1980 .ops = &clk_rcg_ops, 1981 .flags = CLK_SET_RATE_GATE, 1982 }, 1983 } 1984 }; 1985 1986 static const char * const usb_fs2_xcvr_fs_src_p[] = { "usb_fs2_xcvr_fs_src" }; 1987 1988 static struct clk_branch usb_fs2_xcvr_fs_clk = { 1989 .halt_reg = 0x2fcc, 1990 .halt_bit = 12, 1991 .clkr = { 1992 .enable_reg = 0x2988, 1993 .enable_mask = BIT(9), 1994 .hw.init = &(struct clk_init_data){ 1995 .name = "usb_fs2_xcvr_fs_clk", 1996 .parent_names = usb_fs2_xcvr_fs_src_p, 1997 .num_parents = 1, 1998 .ops = &clk_branch_ops, 1999 .flags = CLK_SET_RATE_PARENT, 2000 }, 2001 }, 2002 }; 2003 2004 static struct clk_branch usb_fs2_system_clk = { 2005 .halt_reg = 0x2fcc, 2006 .halt_bit = 13, 2007 .clkr = { 2008 .enable_reg = 0x298c, 2009 .enable_mask = BIT(4), 2010 .hw.init = &(struct clk_init_data){ 2011 .name = "usb_fs2_system_clk", 2012 .parent_names = usb_fs2_xcvr_fs_src_p, 2013 .num_parents = 1, 2014 .ops = &clk_branch_ops, 2015 .flags = CLK_SET_RATE_PARENT, 2016 }, 2017 }, 2018 }; 2019 2020 static struct clk_branch gsbi1_h_clk = { 2021 .halt_reg = 0x2fcc, 2022 .halt_bit = 11, 2023 .clkr = { 2024 .enable_reg = 0x29c0, 2025 .enable_mask = BIT(4), 2026 .hw.init = &(struct clk_init_data){ 2027 .name = "gsbi1_h_clk", 2028 .ops = &clk_branch_ops, 2029 }, 2030 }, 2031 }; 2032 2033 static struct clk_branch gsbi2_h_clk = { 2034 .halt_reg = 0x2fcc, 2035 .halt_bit = 7, 2036 .clkr = { 2037 .enable_reg = 0x29e0, 2038 .enable_mask = BIT(4), 2039 .hw.init = &(struct clk_init_data){ 2040 .name = "gsbi2_h_clk", 2041 .ops = &clk_branch_ops, 2042 }, 2043 }, 2044 }; 2045 2046 static struct clk_branch gsbi3_h_clk = { 2047 .halt_reg = 0x2fcc, 2048 .halt_bit = 3, 2049 .clkr = { 2050 .enable_reg = 0x2a00, 2051 .enable_mask = BIT(4), 2052 .hw.init = &(struct clk_init_data){ 2053 .name = "gsbi3_h_clk", 2054 .ops = &clk_branch_ops, 2055 }, 2056 }, 2057 }; 2058 2059 static struct clk_branch gsbi4_h_clk = { 2060 .halt_reg = 0x2fd0, 2061 .halt_bit = 27, 2062 .clkr = { 2063 .enable_reg = 0x2a20, 2064 .enable_mask = BIT(4), 2065 .hw.init = &(struct clk_init_data){ 2066 .name = "gsbi4_h_clk", 2067 .ops = &clk_branch_ops, 2068 }, 2069 }, 2070 }; 2071 2072 static struct clk_branch gsbi5_h_clk = { 2073 .halt_reg = 0x2fd0, 2074 .halt_bit = 23, 2075 .clkr = { 2076 .enable_reg = 0x2a40, 2077 .enable_mask = BIT(4), 2078 .hw.init = &(struct clk_init_data){ 2079 .name = "gsbi5_h_clk", 2080 .ops = &clk_branch_ops, 2081 }, 2082 }, 2083 }; 2084 2085 static struct clk_branch gsbi6_h_clk = { 2086 .halt_reg = 0x2fd0, 2087 .halt_bit = 19, 2088 .clkr = { 2089 .enable_reg = 0x2a60, 2090 .enable_mask = BIT(4), 2091 .hw.init = &(struct clk_init_data){ 2092 .name = "gsbi6_h_clk", 2093 .ops = &clk_branch_ops, 2094 }, 2095 }, 2096 }; 2097 2098 static struct clk_branch gsbi7_h_clk = { 2099 .halt_reg = 0x2fd0, 2100 .halt_bit = 15, 2101 .clkr = { 2102 .enable_reg = 0x2a80, 2103 .enable_mask = BIT(4), 2104 .hw.init = &(struct clk_init_data){ 2105 .name = "gsbi7_h_clk", 2106 .ops = &clk_branch_ops, 2107 }, 2108 }, 2109 }; 2110 2111 static struct clk_branch gsbi8_h_clk = { 2112 .halt_reg = 0x2fd0, 2113 .halt_bit = 11, 2114 .clkr = { 2115 .enable_reg = 0x2aa0, 2116 .enable_mask = BIT(4), 2117 .hw.init = &(struct clk_init_data){ 2118 .name = "gsbi8_h_clk", 2119 .ops = &clk_branch_ops, 2120 }, 2121 }, 2122 }; 2123 2124 static struct clk_branch gsbi9_h_clk = { 2125 .halt_reg = 0x2fd0, 2126 .halt_bit = 7, 2127 .clkr = { 2128 .enable_reg = 0x2ac0, 2129 .enable_mask = BIT(4), 2130 .hw.init = &(struct clk_init_data){ 2131 .name = "gsbi9_h_clk", 2132 .ops = &clk_branch_ops, 2133 }, 2134 }, 2135 }; 2136 2137 static struct clk_branch gsbi10_h_clk = { 2138 .halt_reg = 0x2fd0, 2139 .halt_bit = 3, 2140 .clkr = { 2141 .enable_reg = 0x2ae0, 2142 .enable_mask = BIT(4), 2143 .hw.init = &(struct clk_init_data){ 2144 .name = "gsbi10_h_clk", 2145 .ops = &clk_branch_ops, 2146 }, 2147 }, 2148 }; 2149 2150 static struct clk_branch gsbi11_h_clk = { 2151 .halt_reg = 0x2fd4, 2152 .halt_bit = 18, 2153 .clkr = { 2154 .enable_reg = 0x2b00, 2155 .enable_mask = BIT(4), 2156 .hw.init = &(struct clk_init_data){ 2157 .name = "gsbi11_h_clk", 2158 .ops = &clk_branch_ops, 2159 }, 2160 }, 2161 }; 2162 2163 static struct clk_branch gsbi12_h_clk = { 2164 .halt_reg = 0x2fd4, 2165 .halt_bit = 14, 2166 .clkr = { 2167 .enable_reg = 0x2b20, 2168 .enable_mask = BIT(4), 2169 .hw.init = &(struct clk_init_data){ 2170 .name = "gsbi12_h_clk", 2171 .ops = &clk_branch_ops, 2172 }, 2173 }, 2174 }; 2175 2176 static struct clk_branch tsif_h_clk = { 2177 .halt_reg = 0x2fd4, 2178 .halt_bit = 7, 2179 .clkr = { 2180 .enable_reg = 0x2700, 2181 .enable_mask = BIT(4), 2182 .hw.init = &(struct clk_init_data){ 2183 .name = "tsif_h_clk", 2184 .ops = &clk_branch_ops, 2185 }, 2186 }, 2187 }; 2188 2189 static struct clk_branch usb_fs1_h_clk = { 2190 .halt_reg = 0x2fcc, 2191 .halt_bit = 17, 2192 .clkr = { 2193 .enable_reg = 0x2960, 2194 .enable_mask = BIT(4), 2195 .hw.init = &(struct clk_init_data){ 2196 .name = "usb_fs1_h_clk", 2197 .ops = &clk_branch_ops, 2198 }, 2199 }, 2200 }; 2201 2202 static struct clk_branch usb_fs2_h_clk = { 2203 .halt_reg = 0x2fcc, 2204 .halt_bit = 14, 2205 .clkr = { 2206 .enable_reg = 0x2980, 2207 .enable_mask = BIT(4), 2208 .hw.init = &(struct clk_init_data){ 2209 .name = "usb_fs2_h_clk", 2210 .ops = &clk_branch_ops, 2211 }, 2212 }, 2213 }; 2214 2215 static struct clk_branch usb_hs1_h_clk = { 2216 .halt_reg = 0x2fc8, 2217 .halt_bit = 1, 2218 .clkr = { 2219 .enable_reg = 0x2900, 2220 .enable_mask = BIT(4), 2221 .hw.init = &(struct clk_init_data){ 2222 .name = "usb_hs1_h_clk", 2223 .ops = &clk_branch_ops, 2224 }, 2225 }, 2226 }; 2227 2228 static struct clk_branch sdc1_h_clk = { 2229 .halt_reg = 0x2fc8, 2230 .halt_bit = 11, 2231 .clkr = { 2232 .enable_reg = 0x2820, 2233 .enable_mask = BIT(4), 2234 .hw.init = &(struct clk_init_data){ 2235 .name = "sdc1_h_clk", 2236 .ops = &clk_branch_ops, 2237 }, 2238 }, 2239 }; 2240 2241 static struct clk_branch sdc2_h_clk = { 2242 .halt_reg = 0x2fc8, 2243 .halt_bit = 10, 2244 .clkr = { 2245 .enable_reg = 0x2840, 2246 .enable_mask = BIT(4), 2247 .hw.init = &(struct clk_init_data){ 2248 .name = "sdc2_h_clk", 2249 .ops = &clk_branch_ops, 2250 }, 2251 }, 2252 }; 2253 2254 static struct clk_branch sdc3_h_clk = { 2255 .halt_reg = 0x2fc8, 2256 .halt_bit = 9, 2257 .clkr = { 2258 .enable_reg = 0x2860, 2259 .enable_mask = BIT(4), 2260 .hw.init = &(struct clk_init_data){ 2261 .name = "sdc3_h_clk", 2262 .ops = &clk_branch_ops, 2263 }, 2264 }, 2265 }; 2266 2267 static struct clk_branch sdc4_h_clk = { 2268 .halt_reg = 0x2fc8, 2269 .halt_bit = 8, 2270 .clkr = { 2271 .enable_reg = 0x2880, 2272 .enable_mask = BIT(4), 2273 .hw.init = &(struct clk_init_data){ 2274 .name = "sdc4_h_clk", 2275 .ops = &clk_branch_ops, 2276 }, 2277 }, 2278 }; 2279 2280 static struct clk_branch sdc5_h_clk = { 2281 .halt_reg = 0x2fc8, 2282 .halt_bit = 7, 2283 .clkr = { 2284 .enable_reg = 0x28a0, 2285 .enable_mask = BIT(4), 2286 .hw.init = &(struct clk_init_data){ 2287 .name = "sdc5_h_clk", 2288 .ops = &clk_branch_ops, 2289 }, 2290 }, 2291 }; 2292 2293 static struct clk_branch ebi2_2x_clk = { 2294 .halt_reg = 0x2fcc, 2295 .halt_bit = 18, 2296 .clkr = { 2297 .enable_reg = 0x2660, 2298 .enable_mask = BIT(4), 2299 .hw.init = &(struct clk_init_data){ 2300 .name = "ebi2_2x_clk", 2301 .ops = &clk_branch_ops, 2302 }, 2303 }, 2304 }; 2305 2306 static struct clk_branch ebi2_clk = { 2307 .halt_reg = 0x2fcc, 2308 .halt_bit = 19, 2309 .clkr = { 2310 .enable_reg = 0x2664, 2311 .enable_mask = BIT(4), 2312 .hw.init = &(struct clk_init_data){ 2313 .name = "ebi2_clk", 2314 .ops = &clk_branch_ops, 2315 }, 2316 }, 2317 }; 2318 2319 static struct clk_branch adm0_clk = { 2320 .halt_reg = 0x2fdc, 2321 .halt_check = BRANCH_HALT_VOTED, 2322 .halt_bit = 14, 2323 .clkr = { 2324 .enable_reg = 0x3080, 2325 .enable_mask = BIT(2), 2326 .hw.init = &(struct clk_init_data){ 2327 .name = "adm0_clk", 2328 .ops = &clk_branch_ops, 2329 }, 2330 }, 2331 }; 2332 2333 static struct clk_branch adm0_pbus_clk = { 2334 .halt_reg = 0x2fdc, 2335 .halt_check = BRANCH_HALT_VOTED, 2336 .halt_bit = 13, 2337 .clkr = { 2338 .enable_reg = 0x3080, 2339 .enable_mask = BIT(3), 2340 .hw.init = &(struct clk_init_data){ 2341 .name = "adm0_pbus_clk", 2342 .ops = &clk_branch_ops, 2343 }, 2344 }, 2345 }; 2346 2347 static struct clk_branch adm1_clk = { 2348 .halt_reg = 0x2fdc, 2349 .halt_bit = 12, 2350 .halt_check = BRANCH_HALT_VOTED, 2351 .clkr = { 2352 .enable_reg = 0x3080, 2353 .enable_mask = BIT(4), 2354 .hw.init = &(struct clk_init_data){ 2355 .name = "adm1_clk", 2356 .ops = &clk_branch_ops, 2357 }, 2358 }, 2359 }; 2360 2361 static struct clk_branch adm1_pbus_clk = { 2362 .halt_reg = 0x2fdc, 2363 .halt_bit = 11, 2364 .halt_check = BRANCH_HALT_VOTED, 2365 .clkr = { 2366 .enable_reg = 0x3080, 2367 .enable_mask = BIT(5), 2368 .hw.init = &(struct clk_init_data){ 2369 .name = "adm1_pbus_clk", 2370 .ops = &clk_branch_ops, 2371 }, 2372 }, 2373 }; 2374 2375 static struct clk_branch modem_ahb1_h_clk = { 2376 .halt_reg = 0x2fdc, 2377 .halt_bit = 8, 2378 .halt_check = BRANCH_HALT_VOTED, 2379 .clkr = { 2380 .enable_reg = 0x3080, 2381 .enable_mask = BIT(0), 2382 .hw.init = &(struct clk_init_data){ 2383 .name = "modem_ahb1_h_clk", 2384 .ops = &clk_branch_ops, 2385 }, 2386 }, 2387 }; 2388 2389 static struct clk_branch modem_ahb2_h_clk = { 2390 .halt_reg = 0x2fdc, 2391 .halt_bit = 7, 2392 .halt_check = BRANCH_HALT_VOTED, 2393 .clkr = { 2394 .enable_reg = 0x3080, 2395 .enable_mask = BIT(1), 2396 .hw.init = &(struct clk_init_data){ 2397 .name = "modem_ahb2_h_clk", 2398 .ops = &clk_branch_ops, 2399 }, 2400 }, 2401 }; 2402 2403 static struct clk_branch pmic_arb0_h_clk = { 2404 .halt_reg = 0x2fd8, 2405 .halt_check = BRANCH_HALT_VOTED, 2406 .halt_bit = 22, 2407 .clkr = { 2408 .enable_reg = 0x3080, 2409 .enable_mask = BIT(8), 2410 .hw.init = &(struct clk_init_data){ 2411 .name = "pmic_arb0_h_clk", 2412 .ops = &clk_branch_ops, 2413 }, 2414 }, 2415 }; 2416 2417 static struct clk_branch pmic_arb1_h_clk = { 2418 .halt_reg = 0x2fd8, 2419 .halt_check = BRANCH_HALT_VOTED, 2420 .halt_bit = 21, 2421 .clkr = { 2422 .enable_reg = 0x3080, 2423 .enable_mask = BIT(9), 2424 .hw.init = &(struct clk_init_data){ 2425 .name = "pmic_arb1_h_clk", 2426 .ops = &clk_branch_ops, 2427 }, 2428 }, 2429 }; 2430 2431 static struct clk_branch pmic_ssbi2_clk = { 2432 .halt_reg = 0x2fd8, 2433 .halt_check = BRANCH_HALT_VOTED, 2434 .halt_bit = 23, 2435 .clkr = { 2436 .enable_reg = 0x3080, 2437 .enable_mask = BIT(7), 2438 .hw.init = &(struct clk_init_data){ 2439 .name = "pmic_ssbi2_clk", 2440 .ops = &clk_branch_ops, 2441 }, 2442 }, 2443 }; 2444 2445 static struct clk_branch rpm_msg_ram_h_clk = { 2446 .hwcg_reg = 0x27e0, 2447 .hwcg_bit = 6, 2448 .halt_reg = 0x2fd8, 2449 .halt_check = BRANCH_HALT_VOTED, 2450 .halt_bit = 12, 2451 .clkr = { 2452 .enable_reg = 0x3080, 2453 .enable_mask = BIT(6), 2454 .hw.init = &(struct clk_init_data){ 2455 .name = "rpm_msg_ram_h_clk", 2456 .ops = &clk_branch_ops, 2457 }, 2458 }, 2459 }; 2460 2461 static struct clk_regmap *gcc_msm8660_clks[] = { 2462 [PLL8] = &pll8.clkr, 2463 [PLL8_VOTE] = &pll8_vote, 2464 [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr, 2465 [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr, 2466 [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr, 2467 [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr, 2468 [GSBI3_UART_SRC] = &gsbi3_uart_src.clkr, 2469 [GSBI3_UART_CLK] = &gsbi3_uart_clk.clkr, 2470 [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr, 2471 [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr, 2472 [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr, 2473 [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr, 2474 [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr, 2475 [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr, 2476 [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr, 2477 [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr, 2478 [GSBI8_UART_SRC] = &gsbi8_uart_src.clkr, 2479 [GSBI8_UART_CLK] = &gsbi8_uart_clk.clkr, 2480 [GSBI9_UART_SRC] = &gsbi9_uart_src.clkr, 2481 [GSBI9_UART_CLK] = &gsbi9_uart_clk.clkr, 2482 [GSBI10_UART_SRC] = &gsbi10_uart_src.clkr, 2483 [GSBI10_UART_CLK] = &gsbi10_uart_clk.clkr, 2484 [GSBI11_UART_SRC] = &gsbi11_uart_src.clkr, 2485 [GSBI11_UART_CLK] = &gsbi11_uart_clk.clkr, 2486 [GSBI12_UART_SRC] = &gsbi12_uart_src.clkr, 2487 [GSBI12_UART_CLK] = &gsbi12_uart_clk.clkr, 2488 [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr, 2489 [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr, 2490 [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr, 2491 [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr, 2492 [GSBI3_QUP_SRC] = &gsbi3_qup_src.clkr, 2493 [GSBI3_QUP_CLK] = &gsbi3_qup_clk.clkr, 2494 [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr, 2495 [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr, 2496 [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr, 2497 [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr, 2498 [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr, 2499 [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr, 2500 [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr, 2501 [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr, 2502 [GSBI8_QUP_SRC] = &gsbi8_qup_src.clkr, 2503 [GSBI8_QUP_CLK] = &gsbi8_qup_clk.clkr, 2504 [GSBI9_QUP_SRC] = &gsbi9_qup_src.clkr, 2505 [GSBI9_QUP_CLK] = &gsbi9_qup_clk.clkr, 2506 [GSBI10_QUP_SRC] = &gsbi10_qup_src.clkr, 2507 [GSBI10_QUP_CLK] = &gsbi10_qup_clk.clkr, 2508 [GSBI11_QUP_SRC] = &gsbi11_qup_src.clkr, 2509 [GSBI11_QUP_CLK] = &gsbi11_qup_clk.clkr, 2510 [GSBI12_QUP_SRC] = &gsbi12_qup_src.clkr, 2511 [GSBI12_QUP_CLK] = &gsbi12_qup_clk.clkr, 2512 [GP0_SRC] = &gp0_src.clkr, 2513 [GP0_CLK] = &gp0_clk.clkr, 2514 [GP1_SRC] = &gp1_src.clkr, 2515 [GP1_CLK] = &gp1_clk.clkr, 2516 [GP2_SRC] = &gp2_src.clkr, 2517 [GP2_CLK] = &gp2_clk.clkr, 2518 [PMEM_CLK] = &pmem_clk.clkr, 2519 [PRNG_SRC] = &prng_src.clkr, 2520 [PRNG_CLK] = &prng_clk.clkr, 2521 [SDC1_SRC] = &sdc1_src.clkr, 2522 [SDC1_CLK] = &sdc1_clk.clkr, 2523 [SDC2_SRC] = &sdc2_src.clkr, 2524 [SDC2_CLK] = &sdc2_clk.clkr, 2525 [SDC3_SRC] = &sdc3_src.clkr, 2526 [SDC3_CLK] = &sdc3_clk.clkr, 2527 [SDC4_SRC] = &sdc4_src.clkr, 2528 [SDC4_CLK] = &sdc4_clk.clkr, 2529 [SDC5_SRC] = &sdc5_src.clkr, 2530 [SDC5_CLK] = &sdc5_clk.clkr, 2531 [TSIF_REF_SRC] = &tsif_ref_src.clkr, 2532 [TSIF_REF_CLK] = &tsif_ref_clk.clkr, 2533 [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_src.clkr, 2534 [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr, 2535 [USB_FS1_XCVR_FS_SRC] = &usb_fs1_xcvr_fs_src.clkr, 2536 [USB_FS1_XCVR_FS_CLK] = &usb_fs1_xcvr_fs_clk.clkr, 2537 [USB_FS1_SYSTEM_CLK] = &usb_fs1_system_clk.clkr, 2538 [USB_FS2_XCVR_FS_SRC] = &usb_fs2_xcvr_fs_src.clkr, 2539 [USB_FS2_XCVR_FS_CLK] = &usb_fs2_xcvr_fs_clk.clkr, 2540 [USB_FS2_SYSTEM_CLK] = &usb_fs2_system_clk.clkr, 2541 [GSBI1_H_CLK] = &gsbi1_h_clk.clkr, 2542 [GSBI2_H_CLK] = &gsbi2_h_clk.clkr, 2543 [GSBI3_H_CLK] = &gsbi3_h_clk.clkr, 2544 [GSBI4_H_CLK] = &gsbi4_h_clk.clkr, 2545 [GSBI5_H_CLK] = &gsbi5_h_clk.clkr, 2546 [GSBI6_H_CLK] = &gsbi6_h_clk.clkr, 2547 [GSBI7_H_CLK] = &gsbi7_h_clk.clkr, 2548 [GSBI8_H_CLK] = &gsbi8_h_clk.clkr, 2549 [GSBI9_H_CLK] = &gsbi9_h_clk.clkr, 2550 [GSBI10_H_CLK] = &gsbi10_h_clk.clkr, 2551 [GSBI11_H_CLK] = &gsbi11_h_clk.clkr, 2552 [GSBI12_H_CLK] = &gsbi12_h_clk.clkr, 2553 [TSIF_H_CLK] = &tsif_h_clk.clkr, 2554 [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr, 2555 [USB_FS2_H_CLK] = &usb_fs2_h_clk.clkr, 2556 [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr, 2557 [SDC1_H_CLK] = &sdc1_h_clk.clkr, 2558 [SDC2_H_CLK] = &sdc2_h_clk.clkr, 2559 [SDC3_H_CLK] = &sdc3_h_clk.clkr, 2560 [SDC4_H_CLK] = &sdc4_h_clk.clkr, 2561 [SDC5_H_CLK] = &sdc5_h_clk.clkr, 2562 [EBI2_2X_CLK] = &ebi2_2x_clk.clkr, 2563 [EBI2_CLK] = &ebi2_clk.clkr, 2564 [ADM0_CLK] = &adm0_clk.clkr, 2565 [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr, 2566 [ADM1_CLK] = &adm1_clk.clkr, 2567 [ADM1_PBUS_CLK] = &adm1_pbus_clk.clkr, 2568 [MODEM_AHB1_H_CLK] = &modem_ahb1_h_clk.clkr, 2569 [MODEM_AHB2_H_CLK] = &modem_ahb2_h_clk.clkr, 2570 [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr, 2571 [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr, 2572 [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr, 2573 [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr, 2574 }; 2575 2576 static const struct qcom_reset_map gcc_msm8660_resets[] = { 2577 [AFAB_CORE_RESET] = { 0x2080, 7 }, 2578 [SCSS_SYS_RESET] = { 0x20b4, 1 }, 2579 [SCSS_SYS_POR_RESET] = { 0x20b4 }, 2580 [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 }, 2581 [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 }, 2582 [AFAB_SMPSS_M0_RESET] = { 0x20b8 }, 2583 [AFAB_EBI1_S_RESET] = { 0x20c0, 7 }, 2584 [SFAB_CORE_RESET] = { 0x2120, 7 }, 2585 [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 }, 2586 [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 }, 2587 [SFAB_ADM0_M2_RESET] = { 0x21e4, 7 }, 2588 [ADM0_C2_RESET] = { 0x220c, 4 }, 2589 [ADM0_C1_RESET] = { 0x220c, 3 }, 2590 [ADM0_C0_RESET] = { 0x220c, 2 }, 2591 [ADM0_PBUS_RESET] = { 0x220c, 1 }, 2592 [ADM0_RESET] = { 0x220c }, 2593 [SFAB_ADM1_M0_RESET] = { 0x2220, 7 }, 2594 [SFAB_ADM1_M1_RESET] = { 0x2224, 7 }, 2595 [SFAB_ADM1_M2_RESET] = { 0x2228, 7 }, 2596 [MMFAB_ADM1_M3_RESET] = { 0x2240, 7 }, 2597 [ADM1_C3_RESET] = { 0x226c, 5 }, 2598 [ADM1_C2_RESET] = { 0x226c, 4 }, 2599 [ADM1_C1_RESET] = { 0x226c, 3 }, 2600 [ADM1_C0_RESET] = { 0x226c, 2 }, 2601 [ADM1_PBUS_RESET] = { 0x226c, 1 }, 2602 [ADM1_RESET] = { 0x226c }, 2603 [IMEM0_RESET] = { 0x2280, 7 }, 2604 [SFAB_LPASS_Q6_RESET] = { 0x23a0, 7 }, 2605 [SFAB_AFAB_M_RESET] = { 0x23e0, 7 }, 2606 [AFAB_SFAB_M0_RESET] = { 0x2420, 7 }, 2607 [AFAB_SFAB_M1_RESET] = { 0x2424, 7 }, 2608 [DFAB_CORE_RESET] = { 0x24ac, 7 }, 2609 [SFAB_DFAB_M_RESET] = { 0x2500, 7 }, 2610 [DFAB_SFAB_M_RESET] = { 0x2520, 7 }, 2611 [DFAB_SWAY0_RESET] = { 0x2540, 7 }, 2612 [DFAB_SWAY1_RESET] = { 0x2544, 7 }, 2613 [DFAB_ARB0_RESET] = { 0x2560, 7 }, 2614 [DFAB_ARB1_RESET] = { 0x2564, 7 }, 2615 [PPSS_PROC_RESET] = { 0x2594, 1 }, 2616 [PPSS_RESET] = { 0x2594 }, 2617 [PMEM_RESET] = { 0x25a0, 7 }, 2618 [DMA_BAM_RESET] = { 0x25c0, 7 }, 2619 [SIC_RESET] = { 0x25e0, 7 }, 2620 [SPS_TIC_RESET] = { 0x2600, 7 }, 2621 [CFBP0_RESET] = { 0x2650, 7 }, 2622 [CFBP1_RESET] = { 0x2654, 7 }, 2623 [CFBP2_RESET] = { 0x2658, 7 }, 2624 [EBI2_RESET] = { 0x2664, 7 }, 2625 [SFAB_CFPB_M_RESET] = { 0x2680, 7 }, 2626 [CFPB_MASTER_RESET] = { 0x26a0, 7 }, 2627 [SFAB_CFPB_S_RESET] = { 0x26c0, 7 }, 2628 [CFPB_SPLITTER_RESET] = { 0x26e0, 7 }, 2629 [TSIF_RESET] = { 0x2700, 7 }, 2630 [CE1_RESET] = { 0x2720, 7 }, 2631 [CE2_RESET] = { 0x2740, 7 }, 2632 [SFAB_SFPB_M_RESET] = { 0x2780, 7 }, 2633 [SFAB_SFPB_S_RESET] = { 0x27a0, 7 }, 2634 [RPM_PROC_RESET] = { 0x27c0, 7 }, 2635 [RPM_BUS_RESET] = { 0x27c4, 7 }, 2636 [RPM_MSG_RAM_RESET] = { 0x27e0, 7 }, 2637 [PMIC_ARB0_RESET] = { 0x2800, 7 }, 2638 [PMIC_ARB1_RESET] = { 0x2804, 7 }, 2639 [PMIC_SSBI2_RESET] = { 0x280c, 12 }, 2640 [SDC1_RESET] = { 0x2830 }, 2641 [SDC2_RESET] = { 0x2850 }, 2642 [SDC3_RESET] = { 0x2870 }, 2643 [SDC4_RESET] = { 0x2890 }, 2644 [SDC5_RESET] = { 0x28b0 }, 2645 [USB_HS1_RESET] = { 0x2910 }, 2646 [USB_HS2_XCVR_RESET] = { 0x2934, 1 }, 2647 [USB_HS2_RESET] = { 0x2934 }, 2648 [USB_FS1_XCVR_RESET] = { 0x2974, 1 }, 2649 [USB_FS1_RESET] = { 0x2974 }, 2650 [USB_FS2_XCVR_RESET] = { 0x2994, 1 }, 2651 [USB_FS2_RESET] = { 0x2994 }, 2652 [GSBI1_RESET] = { 0x29dc }, 2653 [GSBI2_RESET] = { 0x29fc }, 2654 [GSBI3_RESET] = { 0x2a1c }, 2655 [GSBI4_RESET] = { 0x2a3c }, 2656 [GSBI5_RESET] = { 0x2a5c }, 2657 [GSBI6_RESET] = { 0x2a7c }, 2658 [GSBI7_RESET] = { 0x2a9c }, 2659 [GSBI8_RESET] = { 0x2abc }, 2660 [GSBI9_RESET] = { 0x2adc }, 2661 [GSBI10_RESET] = { 0x2afc }, 2662 [GSBI11_RESET] = { 0x2b1c }, 2663 [GSBI12_RESET] = { 0x2b3c }, 2664 [SPDM_RESET] = { 0x2b6c }, 2665 [SEC_CTRL_RESET] = { 0x2b80, 7 }, 2666 [TLMM_H_RESET] = { 0x2ba0, 7 }, 2667 [TLMM_RESET] = { 0x2ba4, 7 }, 2668 [MARRM_PWRON_RESET] = { 0x2bd4, 1 }, 2669 [MARM_RESET] = { 0x2bd4 }, 2670 [MAHB1_RESET] = { 0x2be4, 7 }, 2671 [SFAB_MSS_S_RESET] = { 0x2c00, 7 }, 2672 [MAHB2_RESET] = { 0x2c20, 7 }, 2673 [MODEM_SW_AHB_RESET] = { 0x2c48, 1 }, 2674 [MODEM_RESET] = { 0x2c48 }, 2675 [SFAB_MSS_MDM1_RESET] = { 0x2c4c, 1 }, 2676 [SFAB_MSS_MDM0_RESET] = { 0x2c4c }, 2677 [MSS_SLP_RESET] = { 0x2c60, 7 }, 2678 [MSS_MARM_SAW_RESET] = { 0x2c68, 1 }, 2679 [MSS_WDOG_RESET] = { 0x2c68 }, 2680 [TSSC_RESET] = { 0x2ca0, 7 }, 2681 [PDM_RESET] = { 0x2cc0, 12 }, 2682 [SCSS_CORE0_RESET] = { 0x2d60, 1 }, 2683 [SCSS_CORE0_POR_RESET] = { 0x2d60 }, 2684 [SCSS_CORE1_RESET] = { 0x2d80, 1 }, 2685 [SCSS_CORE1_POR_RESET] = { 0x2d80 }, 2686 [MPM_RESET] = { 0x2da4, 1 }, 2687 [EBI1_1X_DIV_RESET] = { 0x2dec, 9 }, 2688 [EBI1_RESET] = { 0x2dec, 7 }, 2689 [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 }, 2690 [USB_PHY0_RESET] = { 0x2e20 }, 2691 [USB_PHY1_RESET] = { 0x2e40 }, 2692 [PRNG_RESET] = { 0x2e80, 12 }, 2693 }; 2694 2695 static const struct regmap_config gcc_msm8660_regmap_config = { 2696 .reg_bits = 32, 2697 .reg_stride = 4, 2698 .val_bits = 32, 2699 .max_register = 0x363c, 2700 .fast_io = true, 2701 }; 2702 2703 static const struct qcom_cc_desc gcc_msm8660_desc = { 2704 .config = &gcc_msm8660_regmap_config, 2705 .clks = gcc_msm8660_clks, 2706 .num_clks = ARRAY_SIZE(gcc_msm8660_clks), 2707 .resets = gcc_msm8660_resets, 2708 .num_resets = ARRAY_SIZE(gcc_msm8660_resets), 2709 }; 2710 2711 static const struct of_device_id gcc_msm8660_match_table[] = { 2712 { .compatible = "qcom,gcc-msm8660" }, 2713 { } 2714 }; 2715 MODULE_DEVICE_TABLE(of, gcc_msm8660_match_table); 2716 2717 static int gcc_msm8660_probe(struct platform_device *pdev) 2718 { 2719 int ret; 2720 struct device *dev = &pdev->dev; 2721 2722 ret = qcom_cc_register_board_clk(dev, "cxo_board", "cxo", 19200000); 2723 if (ret) 2724 return ret; 2725 2726 ret = qcom_cc_register_board_clk(dev, "pxo_board", "pxo", 27000000); 2727 if (ret) 2728 return ret; 2729 2730 return qcom_cc_probe(pdev, &gcc_msm8660_desc); 2731 } 2732 2733 static struct platform_driver gcc_msm8660_driver = { 2734 .probe = gcc_msm8660_probe, 2735 .driver = { 2736 .name = "gcc-msm8660", 2737 .of_match_table = gcc_msm8660_match_table, 2738 }, 2739 }; 2740 2741 static int __init gcc_msm8660_init(void) 2742 { 2743 return platform_driver_register(&gcc_msm8660_driver); 2744 } 2745 core_initcall(gcc_msm8660_init); 2746 2747 static void __exit gcc_msm8660_exit(void) 2748 { 2749 platform_driver_unregister(&gcc_msm8660_driver); 2750 } 2751 module_exit(gcc_msm8660_exit); 2752 2753 MODULE_DESCRIPTION("GCC MSM 8660 Driver"); 2754 MODULE_LICENSE("GPL v2"); 2755 MODULE_ALIAS("platform:gcc-msm8660"); 2756