1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 /* 3 * Copyright (c) 2023 The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/kernel.h> 8 #include <linux/module.h> 9 #include <linux/of.h> 10 #include <linux/platform_device.h> 11 #include <linux/regmap.h> 12 13 #include <dt-bindings/clock/qcom,ipq9574-gcc.h> 14 #include <dt-bindings/reset/qcom,ipq9574-gcc.h> 15 16 #include "clk-alpha-pll.h" 17 #include "clk-branch.h" 18 #include "clk-rcg.h" 19 #include "clk-regmap.h" 20 #include "clk-regmap-divider.h" 21 #include "clk-regmap-mux.h" 22 #include "clk-regmap-phy-mux.h" 23 #include "common.h" 24 #include "reset.h" 25 26 /* Need to match the order of clocks in DT binding */ 27 enum { 28 DT_XO, 29 DT_SLEEP_CLK, 30 DT_BIAS_PLL_UBI_NC_CLK, 31 DT_PCIE30_PHY0_PIPE_CLK, 32 DT_PCIE30_PHY1_PIPE_CLK, 33 DT_PCIE30_PHY2_PIPE_CLK, 34 DT_PCIE30_PHY3_PIPE_CLK, 35 DT_USB3PHY_0_CC_PIPE_CLK, 36 }; 37 38 enum { 39 P_XO, 40 P_PCIE30_PHY0_PIPE, 41 P_PCIE30_PHY1_PIPE, 42 P_PCIE30_PHY2_PIPE, 43 P_PCIE30_PHY3_PIPE, 44 P_USB3PHY_0_PIPE, 45 P_GPLL0, 46 P_GPLL0_DIV2, 47 P_GPLL0_OUT_AUX, 48 P_GPLL2, 49 P_GPLL4, 50 P_PI_SLEEP, 51 P_BIAS_PLL_UBI_NC_CLK, 52 }; 53 54 static const struct parent_map gcc_xo_map[] = { 55 { P_XO, 0 }, 56 }; 57 58 static const struct clk_parent_data gcc_xo_data[] = { 59 { .index = DT_XO }, 60 }; 61 62 static const struct clk_parent_data gcc_sleep_clk_data[] = { 63 { .index = DT_SLEEP_CLK }, 64 }; 65 66 static struct clk_alpha_pll gpll0_main = { 67 .offset = 0x20000, 68 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 69 .clkr = { 70 .enable_reg = 0x0b000, 71 .enable_mask = BIT(0), 72 .hw.init = &(const struct clk_init_data) { 73 .name = "gpll0_main", 74 .parent_data = gcc_xo_data, 75 .num_parents = ARRAY_SIZE(gcc_xo_data), 76 .ops = &clk_alpha_pll_ops, 77 }, 78 }, 79 }; 80 81 static struct clk_fixed_factor gpll0_out_main_div2 = { 82 .mult = 1, 83 .div = 2, 84 .hw.init = &(const struct clk_init_data) { 85 .name = "gpll0_out_main_div2", 86 .parent_hws = (const struct clk_hw *[]) { 87 &gpll0_main.clkr.hw 88 }, 89 .num_parents = 1, 90 .ops = &clk_fixed_factor_ops, 91 }, 92 }; 93 94 static struct clk_alpha_pll_postdiv gpll0 = { 95 .offset = 0x20000, 96 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 97 .width = 4, 98 .clkr.hw.init = &(const struct clk_init_data) { 99 .name = "gpll0", 100 .parent_hws = (const struct clk_hw *[]) { 101 &gpll0_main.clkr.hw 102 }, 103 .num_parents = 1, 104 .ops = &clk_alpha_pll_postdiv_ro_ops, 105 }, 106 }; 107 108 static struct clk_alpha_pll gpll4_main = { 109 .offset = 0x22000, 110 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 111 .clkr = { 112 .enable_reg = 0x0b000, 113 .enable_mask = BIT(2), 114 .hw.init = &(const struct clk_init_data) { 115 .name = "gpll4_main", 116 .parent_data = gcc_xo_data, 117 .num_parents = ARRAY_SIZE(gcc_xo_data), 118 .ops = &clk_alpha_pll_ops, 119 }, 120 }, 121 }; 122 123 static struct clk_alpha_pll_postdiv gpll4 = { 124 .offset = 0x22000, 125 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 126 .width = 4, 127 .clkr.hw.init = &(const struct clk_init_data) { 128 .name = "gpll4", 129 .parent_hws = (const struct clk_hw *[]) { 130 &gpll4_main.clkr.hw 131 }, 132 .num_parents = 1, 133 .ops = &clk_alpha_pll_postdiv_ro_ops, 134 }, 135 }; 136 137 static struct clk_alpha_pll gpll2_main = { 138 .offset = 0x21000, 139 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 140 .clkr = { 141 .enable_reg = 0x0b000, 142 .enable_mask = BIT(1), 143 .hw.init = &(const struct clk_init_data) { 144 .name = "gpll2_main", 145 .parent_data = gcc_xo_data, 146 .num_parents = ARRAY_SIZE(gcc_xo_data), 147 .ops = &clk_alpha_pll_ops, 148 }, 149 }, 150 }; 151 152 static struct clk_alpha_pll_postdiv gpll2 = { 153 .offset = 0x21000, 154 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 155 .width = 4, 156 .clkr.hw.init = &(const struct clk_init_data) { 157 .name = "gpll2", 158 .parent_hws = (const struct clk_hw *[]) { 159 &gpll2_main.clkr.hw 160 }, 161 .num_parents = 1, 162 .ops = &clk_alpha_pll_postdiv_ro_ops, 163 }, 164 }; 165 166 static struct clk_branch gcc_sleep_clk_src = { 167 .halt_reg = 0x3400c, 168 .clkr = { 169 .enable_reg = 0x3400c, 170 .enable_mask = BIT(1), 171 .hw.init = &(const struct clk_init_data) { 172 .name = "gcc_sleep_clk_src", 173 .parent_data = gcc_sleep_clk_data, 174 .num_parents = ARRAY_SIZE(gcc_sleep_clk_data), 175 .flags = CLK_IS_CRITICAL, 176 .ops = &clk_branch2_ops, 177 }, 178 }, 179 }; 180 181 static const struct clk_parent_data gcc_xo_gpll0_gpll0_out_main_div2[] = { 182 { .index = DT_XO }, 183 { .hw = &gpll0.clkr.hw }, 184 { .hw = &gpll0_out_main_div2.hw }, 185 }; 186 187 static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = { 188 { P_XO, 0 }, 189 { P_GPLL0, 1 }, 190 { P_GPLL0_DIV2, 4 }, 191 }; 192 193 static const struct clk_parent_data gcc_xo_gpll0[] = { 194 { .index = DT_XO }, 195 { .hw = &gpll0.clkr.hw }, 196 }; 197 198 static const struct parent_map gcc_xo_gpll0_map[] = { 199 { P_XO, 0 }, 200 { P_GPLL0, 1 }, 201 }; 202 203 static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = { 204 { .index = DT_XO }, 205 { .hw = &gpll0.clkr.hw }, 206 { .hw = &gpll4.clkr.hw }, 207 }; 208 209 static const struct parent_map gcc_xo_gpll0_gpll4_map[] = { 210 { P_XO, 0 }, 211 { P_GPLL0, 1 }, 212 { P_GPLL4, 2 }, 213 }; 214 215 static const struct clk_parent_data gcc_xo_gpll0_gpll0_div2_gpll0[] = { 216 { .index = DT_XO }, 217 { .hw = &gpll0.clkr.hw }, 218 { .hw = &gpll0_out_main_div2.hw }, 219 { .hw = &gpll0.clkr.hw }, 220 }; 221 222 static const struct parent_map gcc_xo_gpll0_gpll0_div2_gpll0_map[] = { 223 { P_XO, 0 }, 224 { P_GPLL0, 1 }, 225 { P_GPLL0_DIV2, 4 }, 226 { P_GPLL0, 5 }, 227 }; 228 229 static const struct clk_parent_data gcc_xo_gpll0_gpll0_sleep_clk[] = { 230 { .index = DT_XO }, 231 { .hw = &gpll0.clkr.hw }, 232 { .hw = &gpll0_out_main_div2.hw }, 233 { .index = DT_SLEEP_CLK }, 234 }; 235 236 static const struct parent_map gcc_xo_gpll0_gpll0_sleep_clk_map[] = { 237 { P_XO, 0 }, 238 { P_GPLL0, 1 }, 239 { P_GPLL0_DIV2, 4 }, 240 { P_PI_SLEEP, 6 }, 241 }; 242 243 static const struct clk_parent_data gcc_xo_gpll0_core_pi_sleep_clk[] = { 244 { .index = DT_XO }, 245 { .hw = &gpll0.clkr.hw }, 246 { .index = DT_SLEEP_CLK }, 247 }; 248 249 static const struct parent_map gcc_xo_gpll0_core_pi_sleep_clk_map[] = { 250 { P_XO, 0 }, 251 { P_GPLL0, 2 }, 252 { P_PI_SLEEP, 6 }, 253 }; 254 255 static const struct clk_parent_data gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk[] = { 256 { .index = DT_XO }, 257 { .hw = &gpll0.clkr.hw }, 258 { .hw = &gpll4.clkr.hw }, 259 { .index = DT_BIAS_PLL_UBI_NC_CLK }, 260 }; 261 262 static const struct parent_map gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk_map[] = { 263 { P_XO, 0 }, 264 { P_GPLL0, 1 }, 265 { P_GPLL4, 2 }, 266 { P_BIAS_PLL_UBI_NC_CLK, 3 }, 267 }; 268 269 static const struct clk_parent_data 270 gcc_xo_gpll0_gpll0_aux_core_pi_sleep_clk[] = { 271 { .index = DT_XO }, 272 { .hw = &gpll0.clkr.hw }, 273 { .hw = &gpll0.clkr.hw }, 274 { .index = DT_SLEEP_CLK }, 275 }; 276 277 static const struct parent_map 278 gcc_xo_gpll0_gpll0_aux_core_pi_sleep_clk_map[] = { 279 { P_XO, 0 }, 280 { P_GPLL0, 1 }, 281 { P_GPLL0_OUT_AUX, 2 }, 282 { P_PI_SLEEP, 6 }, 283 }; 284 285 static const struct clk_parent_data gcc_xo_gpll0_out_main_div2_gpll0[] = { 286 { .index = DT_XO }, 287 { .hw = &gpll0.clkr.hw }, 288 { .hw = &gpll0_out_main_div2.hw }, 289 }; 290 291 static const struct parent_map gcc_xo_gpll0_out_main_div2_gpll0_map[] = { 292 { P_XO, 0 }, 293 { P_GPLL0, 1 }, 294 { P_GPLL0_DIV2, 4 }, 295 }; 296 297 static const struct clk_parent_data 298 gcc_xo_gpll4_gpll0_gpll0_out_main_div2[] = { 299 { .index = DT_XO }, 300 { .hw = &gpll4.clkr.hw }, 301 { .hw = &gpll0.clkr.hw }, 302 { .hw = &gpll0_out_main_div2.hw }, 303 }; 304 305 static const struct parent_map gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map[] = { 306 { P_XO, 0 }, 307 { P_GPLL4, 1 }, 308 { P_GPLL0, 3 }, 309 { P_GPLL0_DIV2, 4 }, 310 }; 311 312 static const struct clk_parent_data gcc_usb3phy_0_cc_pipe_clk_xo[] = { 313 { .index = DT_USB3PHY_0_CC_PIPE_CLK }, 314 { .index = DT_XO }, 315 }; 316 317 static const struct parent_map gcc_usb3phy_0_cc_pipe_clk_xo_map[] = { 318 { P_USB3PHY_0_PIPE, 0 }, 319 { P_XO, 2 }, 320 }; 321 322 static const struct clk_parent_data 323 gcc_xo_gpll0_gpll2_gpll0_out_main_div2[] = { 324 { .index = DT_XO }, 325 { .hw = &gpll0.clkr.hw }, 326 { .hw = &gpll2.clkr.hw }, 327 { .hw = &gpll0_out_main_div2.hw }, 328 }; 329 330 static const struct parent_map gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map[] = { 331 { P_XO, 0 }, 332 { P_GPLL0, 1 }, 333 { P_GPLL2, 2 }, 334 { P_GPLL0_DIV2, 4 }, 335 }; 336 337 static const struct clk_parent_data gcc_xo_gpll0_gpll4_gpll0_div2[] = { 338 { .index = DT_XO}, 339 { .hw = &gpll0.clkr.hw }, 340 { .hw = &gpll4.clkr.hw }, 341 { .hw = &gpll0_out_main_div2.hw }, 342 }; 343 344 static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_div2_map[] = { 345 { P_XO, 0 }, 346 { P_GPLL0, 1 }, 347 { P_GPLL4, 2 }, 348 { P_GPLL0_DIV2, 4 }, 349 }; 350 351 static const struct clk_parent_data gcc_xo_gpll4_gpll0_gpll0_div2[] = { 352 { .index = DT_XO }, 353 { .hw = &gpll4.clkr.hw }, 354 { .hw = &gpll0.clkr.hw }, 355 { .hw = &gpll0_out_main_div2.hw }, 356 }; 357 358 static const struct parent_map gcc_xo_gpll4_gpll0_gpll0_div2_map[] = { 359 { P_XO, 0 }, 360 { P_GPLL4, 1 }, 361 { P_GPLL0, 2 }, 362 { P_GPLL0_DIV2, 4 }, 363 }; 364 365 static const struct clk_parent_data gcc_xo_gpll0_gpll2[] = { 366 { .index = DT_XO }, 367 { .hw = &gpll0.clkr.hw }, 368 { .hw = &gpll2.clkr.hw }, 369 }; 370 371 static const struct parent_map gcc_xo_gpll0_gpll2_map[] = { 372 { P_XO, 0 }, 373 { P_GPLL0, 1 }, 374 { P_GPLL2, 2 }, 375 }; 376 377 static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll4_pi_sleep[] = { 378 { .index = DT_XO }, 379 { .hw = &gpll0.clkr.hw }, 380 { .hw = &gpll2.clkr.hw }, 381 { .hw = &gpll4.clkr.hw }, 382 { .index = DT_SLEEP_CLK }, 383 }; 384 385 static const struct parent_map gcc_xo_gpll0_gpll2_gpll4_pi_sleep_map[] = { 386 { P_XO, 0 }, 387 { P_GPLL0, 1 }, 388 { P_GPLL2, 2 }, 389 { P_GPLL4, 3 }, 390 { P_PI_SLEEP, 6 }, 391 }; 392 393 static const struct clk_parent_data gcc_xo_gpll0_gpll0_aux_gpll2[] = { 394 { .index = DT_XO }, 395 { .hw = &gpll0.clkr.hw }, 396 { .hw = &gpll0.clkr.hw }, 397 { .hw = &gpll2.clkr.hw }, 398 }; 399 400 static const struct parent_map gcc_xo_gpll0_gpll0_aux_gpll2_map[] = { 401 { P_XO, 0 }, 402 { P_GPLL0, 1 }, 403 { P_GPLL0_OUT_AUX, 2 }, 404 { P_GPLL2, 3 }, 405 }; 406 407 static const struct freq_tbl ftbl_apss_ahb_clk_src[] = { 408 F(24000000, P_XO, 1, 0, 0), 409 F(50000000, P_GPLL0, 16, 0, 0), 410 F(100000000, P_GPLL0, 8, 0, 0), 411 { } 412 }; 413 414 static struct clk_rcg2 apss_ahb_clk_src = { 415 .cmd_rcgr = 0x2400c, 416 .freq_tbl = ftbl_apss_ahb_clk_src, 417 .hid_width = 5, 418 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 419 .clkr.hw.init = &(const struct clk_init_data) { 420 .name = "apss_ahb_clk_src", 421 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, 422 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), 423 .ops = &clk_rcg2_ops, 424 }, 425 }; 426 427 static const struct freq_tbl ftbl_apss_axi_clk_src[] = { 428 F(533000000, P_GPLL0, 1.5, 0, 0), 429 { } 430 }; 431 432 static struct clk_rcg2 apss_axi_clk_src = { 433 .cmd_rcgr = 0x24004, 434 .freq_tbl = ftbl_apss_axi_clk_src, 435 .hid_width = 5, 436 .parent_map = gcc_xo_gpll0_gpll0_div2_gpll0_map, 437 .clkr.hw.init = &(const struct clk_init_data) { 438 .name = "apss_axi_clk_src", 439 .parent_data = gcc_xo_gpll0_gpll0_div2_gpll0, 440 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_div2_gpll0), 441 .ops = &clk_rcg2_ops, 442 }, 443 }; 444 445 static const struct freq_tbl ftbl_blsp1_qup_i2c_apps_clk_src[] = { 446 F(9600000, P_XO, 2.5, 0, 0), 447 F(24000000, P_XO, 1, 0, 0), 448 F(50000000, P_GPLL0, 16, 0, 0), 449 { } 450 }; 451 452 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { 453 .cmd_rcgr = 0x02018, 454 .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src, 455 .hid_width = 5, 456 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 457 .clkr.hw.init = &(const struct clk_init_data) { 458 .name = "blsp1_qup1_i2c_apps_clk_src", 459 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, 460 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), 461 .ops = &clk_rcg2_ops, 462 }, 463 }; 464 465 static const struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src[] = { 466 F(960000, P_XO, 10, 2, 5), 467 F(4800000, P_XO, 5, 0, 0), 468 F(9600000, P_XO, 2, 4, 5), 469 F(16000000, P_GPLL0, 10, 1, 5), 470 F(24000000, P_XO, 1, 0, 0), 471 F(25000000, P_GPLL0, 16, 1, 2), 472 F(50000000, P_GPLL0, 16, 0, 0), 473 { } 474 }; 475 476 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { 477 .cmd_rcgr = 0x02004, 478 .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src, 479 .mnd_width = 8, 480 .hid_width = 5, 481 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 482 .clkr.hw.init = &(const struct clk_init_data) { 483 .name = "blsp1_qup1_spi_apps_clk_src", 484 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, 485 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), 486 .ops = &clk_rcg2_ops, 487 }, 488 }; 489 490 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { 491 .cmd_rcgr = 0x03018, 492 .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src, 493 .hid_width = 5, 494 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 495 .clkr.hw.init = &(const struct clk_init_data) { 496 .name = "blsp1_qup2_i2c_apps_clk_src", 497 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, 498 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), 499 .ops = &clk_rcg2_ops, 500 }, 501 }; 502 503 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { 504 .cmd_rcgr = 0x03004, 505 .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src, 506 .mnd_width = 8, 507 .hid_width = 5, 508 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 509 .clkr.hw.init = &(const struct clk_init_data) { 510 .name = "blsp1_qup2_spi_apps_clk_src", 511 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, 512 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), 513 .ops = &clk_rcg2_ops, 514 }, 515 }; 516 517 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { 518 .cmd_rcgr = 0x04018, 519 .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src, 520 .hid_width = 5, 521 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 522 .clkr.hw.init = &(const struct clk_init_data) { 523 .name = "blsp1_qup3_i2c_apps_clk_src", 524 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, 525 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), 526 .ops = &clk_rcg2_ops, 527 }, 528 }; 529 530 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { 531 .cmd_rcgr = 0x04004, 532 .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src, 533 .mnd_width = 8, 534 .hid_width = 5, 535 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 536 .clkr.hw.init = &(const struct clk_init_data) { 537 .name = "blsp1_qup3_spi_apps_clk_src", 538 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, 539 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), 540 .ops = &clk_rcg2_ops, 541 }, 542 }; 543 544 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { 545 .cmd_rcgr = 0x05018, 546 .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src, 547 .hid_width = 5, 548 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 549 .clkr.hw.init = &(const struct clk_init_data) { 550 .name = "blsp1_qup4_i2c_apps_clk_src", 551 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, 552 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), 553 .ops = &clk_rcg2_ops, 554 }, 555 }; 556 557 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { 558 .cmd_rcgr = 0x05004, 559 .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src, 560 .mnd_width = 8, 561 .hid_width = 5, 562 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 563 .clkr.hw.init = &(const struct clk_init_data) { 564 .name = "blsp1_qup4_spi_apps_clk_src", 565 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, 566 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), 567 .ops = &clk_rcg2_ops, 568 }, 569 }; 570 571 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = { 572 .cmd_rcgr = 0x06018, 573 .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src, 574 .hid_width = 5, 575 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 576 .clkr.hw.init = &(const struct clk_init_data) { 577 .name = "blsp1_qup5_i2c_apps_clk_src", 578 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, 579 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), 580 .ops = &clk_rcg2_ops, 581 }, 582 }; 583 584 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = { 585 .cmd_rcgr = 0x06004, 586 .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src, 587 .mnd_width = 8, 588 .hid_width = 5, 589 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 590 .clkr.hw.init = &(const struct clk_init_data) { 591 .name = "blsp1_qup5_spi_apps_clk_src", 592 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, 593 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), 594 .ops = &clk_rcg2_ops, 595 }, 596 }; 597 598 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = { 599 .cmd_rcgr = 0x07018, 600 .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src, 601 .hid_width = 5, 602 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 603 .clkr.hw.init = &(const struct clk_init_data) { 604 .name = "blsp1_qup6_i2c_apps_clk_src", 605 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, 606 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), 607 .ops = &clk_rcg2_ops, 608 }, 609 }; 610 611 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = { 612 .cmd_rcgr = 0x07004, 613 .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src, 614 .mnd_width = 8, 615 .hid_width = 5, 616 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 617 .clkr.hw.init = &(const struct clk_init_data) { 618 .name = "blsp1_qup6_spi_apps_clk_src", 619 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, 620 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), 621 .ops = &clk_rcg2_ops, 622 }, 623 }; 624 625 static const struct freq_tbl ftbl_blsp1_uart_apps_clk_src[] = { 626 F(3686400, P_GPLL0_DIV2, 1, 144, 15625), 627 F(7372800, P_GPLL0_DIV2, 1, 288, 15625), 628 F(14745600, P_GPLL0_DIV2, 1, 576, 15625), 629 F(24000000, P_XO, 1, 0, 0), 630 F(25000000, P_GPLL0, 16, 1, 2), 631 F(32000000, P_GPLL0, 1, 1, 25), 632 F(40000000, P_GPLL0, 1, 1, 20), 633 F(46400000, P_GPLL0, 1, 29, 500), 634 F(48000000, P_GPLL0, 1, 3, 50), 635 F(51200000, P_GPLL0, 1, 8, 125), 636 F(56000000, P_GPLL0, 1, 7, 100), 637 F(58982400, P_GPLL0, 1, 1152, 15625), 638 F(60000000, P_GPLL0, 1, 3, 40), 639 F(64000000, P_GPLL0, 12.5, 0, 0), 640 { } 641 }; 642 643 static struct clk_rcg2 blsp1_uart1_apps_clk_src = { 644 .cmd_rcgr = 0x0202c, 645 .freq_tbl = ftbl_blsp1_uart_apps_clk_src, 646 .mnd_width = 16, 647 .hid_width = 5, 648 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 649 .clkr.hw.init = &(const struct clk_init_data) { 650 .name = "blsp1_uart1_apps_clk_src", 651 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, 652 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), 653 .ops = &clk_rcg2_ops, 654 }, 655 }; 656 657 static struct clk_rcg2 blsp1_uart2_apps_clk_src = { 658 .cmd_rcgr = 0x0302c, 659 .freq_tbl = ftbl_blsp1_uart_apps_clk_src, 660 .mnd_width = 16, 661 .hid_width = 5, 662 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 663 .clkr.hw.init = &(const struct clk_init_data) { 664 .name = "blsp1_uart2_apps_clk_src", 665 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, 666 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), 667 .ops = &clk_rcg2_ops, 668 }, 669 }; 670 671 static struct clk_rcg2 blsp1_uart3_apps_clk_src = { 672 .cmd_rcgr = 0x0402c, 673 .freq_tbl = ftbl_blsp1_uart_apps_clk_src, 674 .mnd_width = 16, 675 .hid_width = 5, 676 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 677 .clkr.hw.init = &(const struct clk_init_data) { 678 .name = "blsp1_uart3_apps_clk_src", 679 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, 680 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), 681 .ops = &clk_rcg2_ops, 682 }, 683 }; 684 685 static struct clk_rcg2 blsp1_uart4_apps_clk_src = { 686 .cmd_rcgr = 0x0502c, 687 .freq_tbl = ftbl_blsp1_uart_apps_clk_src, 688 .mnd_width = 16, 689 .hid_width = 5, 690 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 691 .clkr.hw.init = &(const struct clk_init_data) { 692 .name = "blsp1_uart4_apps_clk_src", 693 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, 694 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), 695 .ops = &clk_rcg2_ops, 696 }, 697 }; 698 699 static struct clk_rcg2 blsp1_uart5_apps_clk_src = { 700 .cmd_rcgr = 0x0602c, 701 .freq_tbl = ftbl_blsp1_uart_apps_clk_src, 702 .mnd_width = 16, 703 .hid_width = 5, 704 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 705 .clkr.hw.init = &(const struct clk_init_data) { 706 .name = "blsp1_uart5_apps_clk_src", 707 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, 708 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), 709 .ops = &clk_rcg2_ops, 710 }, 711 }; 712 713 static struct clk_rcg2 blsp1_uart6_apps_clk_src = { 714 .cmd_rcgr = 0x0702c, 715 .freq_tbl = ftbl_blsp1_uart_apps_clk_src, 716 .mnd_width = 16, 717 .hid_width = 5, 718 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 719 .clkr.hw.init = &(const struct clk_init_data) { 720 .name = "blsp1_uart6_apps_clk_src", 721 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, 722 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), 723 .ops = &clk_rcg2_ops, 724 }, 725 }; 726 727 static const struct freq_tbl ftbl_gcc_crypto_clk_src[] = { 728 F(160000000, P_GPLL0, 5, 0, 0), 729 { } 730 }; 731 732 static struct clk_rcg2 gcc_crypto_clk_src = { 733 .cmd_rcgr = 0x16004, 734 .freq_tbl = ftbl_gcc_crypto_clk_src, 735 .hid_width = 5, 736 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 737 .clkr.hw.init = &(const struct clk_init_data) { 738 .name = "gcc_crypto_clk_src", 739 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, 740 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), 741 .ops = &clk_rcg2_ops, 742 }, 743 }; 744 745 static struct clk_branch gcc_crypto_clk = { 746 .halt_reg = 0x1600c, 747 .halt_check = BRANCH_HALT_VOTED, 748 .clkr = { 749 .enable_reg = 0x0b004, 750 .enable_mask = BIT(14), 751 .hw.init = &(const struct clk_init_data) { 752 .name = "gcc_crypto_clk", 753 .parent_hws = (const struct clk_hw *[]) { 754 &gcc_crypto_clk_src.clkr.hw }, 755 .num_parents = 1, 756 .flags = CLK_SET_RATE_PARENT, 757 .ops = &clk_branch2_ops, 758 }, 759 }, 760 }; 761 762 static struct clk_branch gcc_apss_ahb_clk = { 763 .halt_reg = 0x24018, 764 .halt_check = BRANCH_HALT_VOTED, 765 .clkr = { 766 .enable_reg = 0x0b004, 767 .enable_mask = BIT(0), 768 .hw.init = &(const struct clk_init_data) { 769 .name = "gcc_apss_ahb_clk", 770 .parent_hws = (const struct clk_hw *[]) { 771 &apss_ahb_clk_src.clkr.hw 772 }, 773 .num_parents = 1, 774 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 775 .ops = &clk_branch2_ops, 776 }, 777 }, 778 }; 779 780 static struct clk_branch gcc_apss_axi_clk = { 781 .halt_reg = 0x2401c, 782 .halt_check = BRANCH_HALT_VOTED, 783 .clkr = { 784 .enable_reg = 0x0b004, 785 .enable_mask = BIT(1), 786 .hw.init = &(const struct clk_init_data) { 787 .name = "gcc_apss_axi_clk", 788 .parent_hws = (const struct clk_hw *[]) { 789 &apss_axi_clk_src.clkr.hw 790 }, 791 .num_parents = 1, 792 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 793 .ops = &clk_branch2_ops, 794 }, 795 }, 796 }; 797 798 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { 799 .halt_reg = 0x2024, 800 .clkr = { 801 .enable_reg = 0x2024, 802 .enable_mask = BIT(0), 803 .hw.init = &(const struct clk_init_data) { 804 .name = "gcc_blsp1_qup1_i2c_apps_clk", 805 .parent_hws = (const struct clk_hw *[]) { 806 &blsp1_qup1_i2c_apps_clk_src.clkr.hw 807 }, 808 .num_parents = 1, 809 .flags = CLK_SET_RATE_PARENT, 810 .ops = &clk_branch2_ops, 811 }, 812 }, 813 }; 814 815 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { 816 .halt_reg = 0x02020, 817 .clkr = { 818 .enable_reg = 0x02020, 819 .enable_mask = BIT(0), 820 .hw.init = &(const struct clk_init_data) { 821 .name = "gcc_blsp1_qup1_spi_apps_clk", 822 .parent_hws = (const struct clk_hw *[]) { 823 &blsp1_qup1_spi_apps_clk_src.clkr.hw 824 }, 825 .num_parents = 1, 826 .flags = CLK_SET_RATE_PARENT, 827 .ops = &clk_branch2_ops, 828 }, 829 }, 830 }; 831 832 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { 833 .halt_reg = 0x03024, 834 .clkr = { 835 .enable_reg = 0x03024, 836 .enable_mask = BIT(0), 837 .hw.init = &(const struct clk_init_data) { 838 .name = "gcc_blsp1_qup2_i2c_apps_clk", 839 .parent_hws = (const struct clk_hw *[]) { 840 &blsp1_qup2_i2c_apps_clk_src.clkr.hw 841 }, 842 .num_parents = 1, 843 .flags = CLK_SET_RATE_PARENT, 844 .ops = &clk_branch2_ops, 845 }, 846 }, 847 }; 848 849 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { 850 .halt_reg = 0x03020, 851 .clkr = { 852 .enable_reg = 0x03020, 853 .enable_mask = BIT(0), 854 .hw.init = &(const struct clk_init_data) { 855 .name = "gcc_blsp1_qup2_spi_apps_clk", 856 .parent_hws = (const struct clk_hw *[]) { 857 &blsp1_qup2_spi_apps_clk_src.clkr.hw 858 }, 859 .num_parents = 1, 860 .flags = CLK_SET_RATE_PARENT, 861 .ops = &clk_branch2_ops, 862 }, 863 }, 864 }; 865 866 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = { 867 .halt_reg = 0x04024, 868 .clkr = { 869 .enable_reg = 0x04024, 870 .enable_mask = BIT(0), 871 .hw.init = &(const struct clk_init_data) { 872 .name = "gcc_blsp1_qup3_i2c_apps_clk", 873 .parent_hws = (const struct clk_hw *[]) { 874 &blsp1_qup3_i2c_apps_clk_src.clkr.hw 875 }, 876 .num_parents = 1, 877 .flags = CLK_SET_RATE_PARENT, 878 .ops = &clk_branch2_ops, 879 }, 880 }, 881 }; 882 883 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = { 884 .halt_reg = 0x04020, 885 .clkr = { 886 .enable_reg = 0x04020, 887 .enable_mask = BIT(0), 888 .hw.init = &(const struct clk_init_data) { 889 .name = "gcc_blsp1_qup3_spi_apps_clk", 890 .parent_hws = (const struct clk_hw *[]) { 891 &blsp1_qup3_spi_apps_clk_src.clkr.hw 892 }, 893 .num_parents = 1, 894 .flags = CLK_SET_RATE_PARENT, 895 .ops = &clk_branch2_ops, 896 }, 897 }, 898 }; 899 900 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = { 901 .halt_reg = 0x05024, 902 .clkr = { 903 .enable_reg = 0x05024, 904 .enable_mask = BIT(0), 905 .hw.init = &(const struct clk_init_data) { 906 .name = "gcc_blsp1_qup4_i2c_apps_clk", 907 .parent_hws = (const struct clk_hw *[]) { 908 &blsp1_qup4_i2c_apps_clk_src.clkr.hw 909 }, 910 .num_parents = 1, 911 .flags = CLK_SET_RATE_PARENT, 912 .ops = &clk_branch2_ops, 913 }, 914 }, 915 }; 916 917 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = { 918 .halt_reg = 0x05020, 919 .clkr = { 920 .enable_reg = 0x05020, 921 .enable_mask = BIT(0), 922 .hw.init = &(const struct clk_init_data) { 923 .name = "gcc_blsp1_qup4_spi_apps_clk", 924 .parent_hws = (const struct clk_hw *[]) { 925 &blsp1_qup4_spi_apps_clk_src.clkr.hw 926 }, 927 .num_parents = 1, 928 .flags = CLK_SET_RATE_PARENT, 929 .ops = &clk_branch2_ops, 930 }, 931 }, 932 }; 933 934 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = { 935 .halt_reg = 0x06024, 936 .clkr = { 937 .enable_reg = 0x06024, 938 .enable_mask = BIT(0), 939 .hw.init = &(const struct clk_init_data) { 940 .name = "gcc_blsp1_qup5_i2c_apps_clk", 941 .parent_hws = (const struct clk_hw *[]) { 942 &blsp1_qup5_i2c_apps_clk_src.clkr.hw 943 }, 944 .num_parents = 1, 945 .flags = CLK_SET_RATE_PARENT, 946 .ops = &clk_branch2_ops, 947 }, 948 }, 949 }; 950 951 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = { 952 .halt_reg = 0x06020, 953 .clkr = { 954 .enable_reg = 0x06020, 955 .enable_mask = BIT(0), 956 .hw.init = &(const struct clk_init_data) { 957 .name = "gcc_blsp1_qup5_spi_apps_clk", 958 .parent_hws = (const struct clk_hw *[]) { 959 &blsp1_qup5_spi_apps_clk_src.clkr.hw 960 }, 961 .num_parents = 1, 962 .flags = CLK_SET_RATE_PARENT, 963 .ops = &clk_branch2_ops, 964 }, 965 }, 966 }; 967 968 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = { 969 .halt_reg = 0x07024, 970 .clkr = { 971 .enable_reg = 0x07024, 972 .enable_mask = BIT(0), 973 .hw.init = &(const struct clk_init_data) { 974 .name = "gcc_blsp1_qup6_i2c_apps_clk", 975 .parent_hws = (const struct clk_hw *[]) { 976 &blsp1_qup6_i2c_apps_clk_src.clkr.hw 977 }, 978 .num_parents = 1, 979 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 980 .ops = &clk_branch2_ops, 981 }, 982 }, 983 }; 984 985 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = { 986 .halt_reg = 0x07020, 987 .clkr = { 988 .enable_reg = 0x07020, 989 .enable_mask = BIT(0), 990 .hw.init = &(const struct clk_init_data) { 991 .name = "gcc_blsp1_qup6_spi_apps_clk", 992 .parent_hws = (const struct clk_hw *[]) { 993 &blsp1_qup6_spi_apps_clk_src.clkr.hw 994 }, 995 .num_parents = 1, 996 .flags = CLK_SET_RATE_PARENT, 997 .ops = &clk_branch2_ops, 998 }, 999 }, 1000 }; 1001 1002 static struct clk_branch gcc_blsp1_uart1_apps_clk = { 1003 .halt_reg = 0x02040, 1004 .clkr = { 1005 .enable_reg = 0x02040, 1006 .enable_mask = BIT(0), 1007 .hw.init = &(const struct clk_init_data) { 1008 .name = "gcc_blsp1_uart1_apps_clk", 1009 .parent_hws = (const struct clk_hw *[]) { 1010 &blsp1_uart1_apps_clk_src.clkr.hw 1011 }, 1012 .num_parents = 1, 1013 .flags = CLK_SET_RATE_PARENT, 1014 .ops = &clk_branch2_ops, 1015 }, 1016 }, 1017 }; 1018 1019 static struct clk_branch gcc_blsp1_uart2_apps_clk = { 1020 .halt_reg = 0x03040, 1021 .clkr = { 1022 .enable_reg = 0x03040, 1023 .enable_mask = BIT(0), 1024 .hw.init = &(const struct clk_init_data) { 1025 .name = "gcc_blsp1_uart2_apps_clk", 1026 .parent_hws = (const struct clk_hw *[]) { 1027 &blsp1_uart2_apps_clk_src.clkr.hw 1028 }, 1029 .num_parents = 1, 1030 .flags = CLK_SET_RATE_PARENT, 1031 .ops = &clk_branch2_ops, 1032 }, 1033 }, 1034 }; 1035 1036 static struct clk_branch gcc_blsp1_uart3_apps_clk = { 1037 .halt_reg = 0x04054, 1038 .clkr = { 1039 .enable_reg = 0x04054, 1040 .enable_mask = BIT(0), 1041 .hw.init = &(const struct clk_init_data) { 1042 .name = "gcc_blsp1_uart3_apps_clk", 1043 .parent_hws = (const struct clk_hw *[]) { 1044 &blsp1_uart3_apps_clk_src.clkr.hw 1045 }, 1046 .num_parents = 1, 1047 .flags = CLK_SET_RATE_PARENT, 1048 .ops = &clk_branch2_ops, 1049 }, 1050 }, 1051 }; 1052 1053 static struct clk_branch gcc_blsp1_uart4_apps_clk = { 1054 .halt_reg = 0x05040, 1055 .clkr = { 1056 .enable_reg = 0x05040, 1057 .enable_mask = BIT(0), 1058 .hw.init = &(const struct clk_init_data) { 1059 .name = "gcc_blsp1_uart4_apps_clk", 1060 .parent_hws = (const struct clk_hw *[]) { 1061 &blsp1_uart4_apps_clk_src.clkr.hw 1062 }, 1063 .num_parents = 1, 1064 .flags = CLK_SET_RATE_PARENT, 1065 .ops = &clk_branch2_ops, 1066 }, 1067 }, 1068 }; 1069 1070 static struct clk_branch gcc_blsp1_uart5_apps_clk = { 1071 .halt_reg = 0x06040, 1072 .clkr = { 1073 .enable_reg = 0x06040, 1074 .enable_mask = BIT(0), 1075 .hw.init = &(const struct clk_init_data) { 1076 .name = "gcc_blsp1_uart5_apps_clk", 1077 .parent_hws = (const struct clk_hw *[]) { 1078 &blsp1_uart5_apps_clk_src.clkr.hw 1079 }, 1080 .num_parents = 1, 1081 .flags = CLK_SET_RATE_PARENT, 1082 .ops = &clk_branch2_ops, 1083 }, 1084 }, 1085 }; 1086 1087 static struct clk_branch gcc_blsp1_uart6_apps_clk = { 1088 .halt_reg = 0x07040, 1089 .clkr = { 1090 .enable_reg = 0x07040, 1091 .enable_mask = BIT(0), 1092 .hw.init = &(const struct clk_init_data) { 1093 .name = "gcc_blsp1_uart6_apps_clk", 1094 .parent_hws = (const struct clk_hw *[]) { 1095 &blsp1_uart6_apps_clk_src.clkr.hw 1096 }, 1097 .num_parents = 1, 1098 .flags = CLK_SET_RATE_PARENT, 1099 .ops = &clk_branch2_ops, 1100 }, 1101 }, 1102 }; 1103 1104 static const struct freq_tbl ftbl_pcie0_axi_m_clk_src[] = { 1105 F(240000000, P_GPLL4, 5, 0, 0), 1106 { } 1107 }; 1108 1109 static struct clk_rcg2 pcie0_axi_m_clk_src = { 1110 .cmd_rcgr = 0x28018, 1111 .freq_tbl = ftbl_pcie0_axi_m_clk_src, 1112 .hid_width = 5, 1113 .parent_map = gcc_xo_gpll0_gpll4_map, 1114 .clkr.hw.init = &(const struct clk_init_data) { 1115 .name = "pcie0_axi_m_clk_src", 1116 .parent_data = gcc_xo_gpll0_gpll4, 1117 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4), 1118 .ops = &clk_rcg2_ops, 1119 }, 1120 }; 1121 1122 static struct clk_branch gcc_pcie0_axi_m_clk = { 1123 .halt_reg = 0x28038, 1124 .clkr = { 1125 .enable_reg = 0x28038, 1126 .enable_mask = BIT(0), 1127 .hw.init = &(const struct clk_init_data) { 1128 .name = "gcc_pcie0_axi_m_clk", 1129 .parent_hws = (const struct clk_hw *[]) { 1130 &pcie0_axi_m_clk_src.clkr.hw 1131 }, 1132 .num_parents = 1, 1133 .flags = CLK_SET_RATE_PARENT, 1134 .ops = &clk_branch2_ops, 1135 }, 1136 }, 1137 }; 1138 1139 static struct clk_branch gcc_anoc_pcie0_1lane_m_clk = { 1140 .halt_reg = 0x2e07c, 1141 .clkr = { 1142 .enable_reg = 0x2e07c, 1143 .enable_mask = BIT(0), 1144 .hw.init = &(const struct clk_init_data) { 1145 .name = "gcc_anoc_pcie0_1lane_m_clk", 1146 .parent_hws = (const struct clk_hw *[]) { 1147 &pcie0_axi_m_clk_src.clkr.hw 1148 }, 1149 .num_parents = 1, 1150 .flags = CLK_SET_RATE_PARENT, 1151 .ops = &clk_branch2_ops, 1152 }, 1153 }, 1154 }; 1155 1156 static struct clk_rcg2 pcie1_axi_m_clk_src = { 1157 .cmd_rcgr = 0x29018, 1158 .freq_tbl = ftbl_pcie0_axi_m_clk_src, 1159 .hid_width = 5, 1160 .parent_map = gcc_xo_gpll0_gpll4_map, 1161 .clkr.hw.init = &(const struct clk_init_data) { 1162 .name = "pcie1_axi_m_clk_src", 1163 .parent_data = gcc_xo_gpll0_gpll4, 1164 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4), 1165 .ops = &clk_rcg2_ops, 1166 }, 1167 }; 1168 1169 static struct clk_branch gcc_pcie1_axi_m_clk = { 1170 .halt_reg = 0x29038, 1171 .clkr = { 1172 .enable_reg = 0x29038, 1173 .enable_mask = BIT(0), 1174 .hw.init = &(const struct clk_init_data) { 1175 .name = "gcc_pcie1_axi_m_clk", 1176 .parent_hws = (const struct clk_hw *[]) { 1177 &pcie1_axi_m_clk_src.clkr.hw 1178 }, 1179 .num_parents = 1, 1180 .flags = CLK_SET_RATE_PARENT, 1181 .ops = &clk_branch2_ops, 1182 }, 1183 }, 1184 }; 1185 1186 static struct clk_branch gcc_anoc_pcie1_1lane_m_clk = { 1187 .halt_reg = 0x2e08c, 1188 .clkr = { 1189 .enable_reg = 0x2e08c, 1190 .enable_mask = BIT(0), 1191 .hw.init = &(const struct clk_init_data) { 1192 .name = "gcc_anoc_pcie1_1lane_m_clk", 1193 .parent_hws = (const struct clk_hw *[]) { 1194 &pcie1_axi_m_clk_src.clkr.hw 1195 }, 1196 .num_parents = 1, 1197 .flags = CLK_SET_RATE_PARENT, 1198 .ops = &clk_branch2_ops, 1199 }, 1200 }, 1201 }; 1202 1203 static const struct freq_tbl ftbl_pcie2_axi_m_clk_src[] = { 1204 F(342857143, P_GPLL4, 3.5, 0, 0), 1205 { } 1206 }; 1207 1208 static struct clk_rcg2 pcie2_axi_m_clk_src = { 1209 .cmd_rcgr = 0x2a018, 1210 .freq_tbl = ftbl_pcie2_axi_m_clk_src, 1211 .hid_width = 5, 1212 .parent_map = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk_map, 1213 .clkr.hw.init = &(const struct clk_init_data) { 1214 .name = "pcie2_axi_m_clk_src", 1215 .parent_data = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk, 1216 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk), 1217 .ops = &clk_rcg2_ops, 1218 }, 1219 }; 1220 1221 static struct clk_branch gcc_pcie2_axi_m_clk = { 1222 .halt_reg = 0x2a038, 1223 .clkr = { 1224 .enable_reg = 0x2a038, 1225 .enable_mask = BIT(0), 1226 .hw.init = &(const struct clk_init_data) { 1227 .name = "gcc_pcie2_axi_m_clk", 1228 .parent_hws = (const struct clk_hw *[]) { 1229 &pcie2_axi_m_clk_src.clkr.hw 1230 }, 1231 .num_parents = 1, 1232 .flags = CLK_SET_RATE_PARENT, 1233 .ops = &clk_branch2_ops, 1234 }, 1235 }, 1236 }; 1237 1238 static struct clk_branch gcc_anoc_pcie2_2lane_m_clk = { 1239 .halt_reg = 0x2e080, 1240 .clkr = { 1241 .enable_reg = 0x2e080, 1242 .enable_mask = BIT(0), 1243 .hw.init = &(const struct clk_init_data) { 1244 .name = "gcc_anoc_pcie2_2lane_m_clk", 1245 .parent_hws = (const struct clk_hw *[]) { 1246 &pcie2_axi_m_clk_src.clkr.hw 1247 }, 1248 .num_parents = 1, 1249 .flags = CLK_SET_RATE_PARENT, 1250 .ops = &clk_branch2_ops, 1251 }, 1252 }, 1253 }; 1254 1255 static struct clk_rcg2 pcie3_axi_m_clk_src = { 1256 .cmd_rcgr = 0x2b018, 1257 .freq_tbl = ftbl_pcie2_axi_m_clk_src, 1258 .hid_width = 5, 1259 .parent_map = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk_map, 1260 .clkr.hw.init = &(const struct clk_init_data) { 1261 .name = "pcie3_axi_m_clk_src", 1262 .parent_data = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk, 1263 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk), 1264 .ops = &clk_rcg2_ops, 1265 }, 1266 }; 1267 1268 static struct clk_branch gcc_pcie3_axi_m_clk = { 1269 .halt_reg = 0x2b038, 1270 .clkr = { 1271 .enable_reg = 0x2b038, 1272 .enable_mask = BIT(0), 1273 .hw.init = &(const struct clk_init_data) { 1274 .name = "gcc_pcie3_axi_m_clk", 1275 .parent_hws = (const struct clk_hw *[]) { 1276 &pcie3_axi_m_clk_src.clkr.hw 1277 }, 1278 .num_parents = 1, 1279 .flags = CLK_SET_RATE_PARENT, 1280 .ops = &clk_branch2_ops, 1281 }, 1282 }, 1283 }; 1284 1285 static struct clk_branch gcc_anoc_pcie3_2lane_m_clk = { 1286 .halt_reg = 0x2e090, 1287 .clkr = { 1288 .enable_reg = 0x2e090, 1289 .enable_mask = BIT(0), 1290 .hw.init = &(const struct clk_init_data) { 1291 .name = "gcc_anoc_pcie3_2lane_m_clk", 1292 .parent_hws = (const struct clk_hw *[]) { 1293 &pcie3_axi_m_clk_src.clkr.hw 1294 }, 1295 .num_parents = 1, 1296 .flags = CLK_SET_RATE_PARENT, 1297 .ops = &clk_branch2_ops, 1298 }, 1299 }, 1300 }; 1301 1302 static struct clk_rcg2 pcie0_axi_s_clk_src = { 1303 .cmd_rcgr = 0x28020, 1304 .freq_tbl = ftbl_pcie0_axi_m_clk_src, 1305 .hid_width = 5, 1306 .parent_map = gcc_xo_gpll0_gpll4_map, 1307 .clkr.hw.init = &(const struct clk_init_data) { 1308 .name = "pcie0_axi_s_clk_src", 1309 .parent_data = gcc_xo_gpll0_gpll4, 1310 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4), 1311 .ops = &clk_rcg2_ops, 1312 }, 1313 }; 1314 1315 static struct clk_branch gcc_pcie0_axi_s_clk = { 1316 .halt_reg = 0x2803c, 1317 .clkr = { 1318 .enable_reg = 0x2803c, 1319 .enable_mask = BIT(0), 1320 .hw.init = &(const struct clk_init_data) { 1321 .name = "gcc_pcie0_axi_s_clk", 1322 .parent_hws = (const struct clk_hw *[]) { 1323 &pcie0_axi_s_clk_src.clkr.hw 1324 }, 1325 .num_parents = 1, 1326 .flags = CLK_SET_RATE_PARENT, 1327 .ops = &clk_branch2_ops, 1328 }, 1329 }, 1330 }; 1331 1332 static struct clk_branch gcc_pcie0_axi_s_bridge_clk = { 1333 .halt_reg = 0x28040, 1334 .clkr = { 1335 .enable_reg = 0x28040, 1336 .enable_mask = BIT(0), 1337 .hw.init = &(const struct clk_init_data) { 1338 .name = "gcc_pcie0_axi_s_bridge_clk", 1339 .parent_hws = (const struct clk_hw *[]) { 1340 &pcie0_axi_s_clk_src.clkr.hw 1341 }, 1342 .num_parents = 1, 1343 .flags = CLK_SET_RATE_PARENT, 1344 .ops = &clk_branch2_ops, 1345 }, 1346 }, 1347 }; 1348 1349 static struct clk_branch gcc_snoc_pcie0_1lane_s_clk = { 1350 .halt_reg = 0x2e048, 1351 .clkr = { 1352 .enable_reg = 0x2e048, 1353 .enable_mask = BIT(0), 1354 .hw.init = &(const struct clk_init_data) { 1355 .name = "gcc_snoc_pcie0_1lane_s_clk", 1356 .parent_hws = (const struct clk_hw *[]) { 1357 &pcie0_axi_s_clk_src.clkr.hw 1358 }, 1359 .num_parents = 1, 1360 .flags = CLK_SET_RATE_PARENT, 1361 .ops = &clk_branch2_ops, 1362 }, 1363 }, 1364 }; 1365 1366 static struct clk_rcg2 pcie1_axi_s_clk_src = { 1367 .cmd_rcgr = 0x29020, 1368 .freq_tbl = ftbl_pcie0_axi_m_clk_src, 1369 .hid_width = 5, 1370 .parent_map = gcc_xo_gpll0_gpll4_map, 1371 .clkr.hw.init = &(const struct clk_init_data) { 1372 .name = "pcie1_axi_s_clk_src", 1373 .parent_data = gcc_xo_gpll0_gpll4, 1374 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4), 1375 .ops = &clk_rcg2_ops, 1376 }, 1377 }; 1378 1379 static struct clk_branch gcc_pcie1_axi_s_clk = { 1380 .halt_reg = 0x2903c, 1381 .clkr = { 1382 .enable_reg = 0x2903c, 1383 .enable_mask = BIT(0), 1384 .hw.init = &(const struct clk_init_data) { 1385 .name = "gcc_pcie1_axi_s_clk", 1386 .parent_hws = (const struct clk_hw *[]) { 1387 &pcie1_axi_s_clk_src.clkr.hw 1388 }, 1389 .num_parents = 1, 1390 .flags = CLK_SET_RATE_PARENT, 1391 .ops = &clk_branch2_ops, 1392 }, 1393 }, 1394 }; 1395 1396 static struct clk_branch gcc_pcie1_axi_s_bridge_clk = { 1397 .halt_reg = 0x29040, 1398 .clkr = { 1399 .enable_reg = 0x29040, 1400 .enable_mask = BIT(0), 1401 .hw.init = &(const struct clk_init_data) { 1402 .name = "gcc_pcie1_axi_s_bridge_clk", 1403 .parent_hws = (const struct clk_hw *[]) { 1404 &pcie1_axi_s_clk_src.clkr.hw 1405 }, 1406 .num_parents = 1, 1407 .flags = CLK_SET_RATE_PARENT, 1408 .ops = &clk_branch2_ops, 1409 }, 1410 }, 1411 }; 1412 1413 static struct clk_branch gcc_snoc_pcie1_1lane_s_clk = { 1414 .halt_reg = 0x2e04c, 1415 .clkr = { 1416 .enable_reg = 0x2e04c, 1417 .enable_mask = BIT(0), 1418 .hw.init = &(const struct clk_init_data) { 1419 .name = "gcc_snoc_pcie1_1lane_s_clk", 1420 .parent_hws = (const struct clk_hw *[]) { 1421 &pcie1_axi_s_clk_src.clkr.hw 1422 }, 1423 .num_parents = 1, 1424 .flags = CLK_SET_RATE_PARENT, 1425 .ops = &clk_branch2_ops, 1426 }, 1427 }, 1428 }; 1429 1430 static struct clk_rcg2 pcie2_axi_s_clk_src = { 1431 .cmd_rcgr = 0x2a020, 1432 .freq_tbl = ftbl_pcie0_axi_m_clk_src, 1433 .hid_width = 5, 1434 .parent_map = gcc_xo_gpll0_gpll4_map, 1435 .clkr.hw.init = &(const struct clk_init_data) { 1436 .name = "pcie2_axi_s_clk_src", 1437 .parent_data = gcc_xo_gpll0_gpll4, 1438 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4), 1439 .ops = &clk_rcg2_ops, 1440 }, 1441 }; 1442 1443 static struct clk_branch gcc_pcie2_axi_s_clk = { 1444 .halt_reg = 0x2a03c, 1445 .clkr = { 1446 .enable_reg = 0x2a03c, 1447 .enable_mask = BIT(0), 1448 .hw.init = &(const struct clk_init_data) { 1449 .name = "gcc_pcie2_axi_s_clk", 1450 .parent_hws = (const struct clk_hw *[]) { 1451 &pcie2_axi_s_clk_src.clkr.hw 1452 }, 1453 .num_parents = 1, 1454 .flags = CLK_SET_RATE_PARENT, 1455 .ops = &clk_branch2_ops, 1456 }, 1457 }, 1458 }; 1459 1460 static struct clk_branch gcc_pcie2_axi_s_bridge_clk = { 1461 .halt_reg = 0x2a040, 1462 .clkr = { 1463 .enable_reg = 0x2a040, 1464 .enable_mask = BIT(0), 1465 .hw.init = &(const struct clk_init_data) { 1466 .name = "gcc_pcie2_axi_s_bridge_clk", 1467 .parent_hws = (const struct clk_hw *[]) { 1468 &pcie2_axi_s_clk_src.clkr.hw 1469 }, 1470 .num_parents = 1, 1471 .flags = CLK_SET_RATE_PARENT, 1472 .ops = &clk_branch2_ops, 1473 }, 1474 }, 1475 }; 1476 1477 static struct clk_branch gcc_snoc_pcie2_2lane_s_clk = { 1478 .halt_reg = 0x2e050, 1479 .clkr = { 1480 .enable_reg = 0x2e050, 1481 .enable_mask = BIT(0), 1482 .hw.init = &(const struct clk_init_data) { 1483 .name = "gcc_snoc_pcie2_2lane_s_clk", 1484 .parent_hws = (const struct clk_hw *[]) { 1485 &pcie2_axi_s_clk_src.clkr.hw 1486 }, 1487 .num_parents = 1, 1488 .flags = CLK_SET_RATE_PARENT, 1489 .ops = &clk_branch2_ops, 1490 }, 1491 }, 1492 }; 1493 1494 static struct clk_rcg2 pcie3_axi_s_clk_src = { 1495 .cmd_rcgr = 0x2b020, 1496 .freq_tbl = ftbl_pcie0_axi_m_clk_src, 1497 .hid_width = 5, 1498 .parent_map = gcc_xo_gpll0_gpll4_map, 1499 .clkr.hw.init = &(const struct clk_init_data) { 1500 .name = "pcie3_axi_s_clk_src", 1501 .parent_data = gcc_xo_gpll0_gpll4, 1502 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4), 1503 .ops = &clk_rcg2_ops, 1504 }, 1505 }; 1506 1507 static struct clk_branch gcc_pcie3_axi_s_clk = { 1508 .halt_reg = 0x2b03c, 1509 .clkr = { 1510 .enable_reg = 0x2b03c, 1511 .enable_mask = BIT(0), 1512 .hw.init = &(const struct clk_init_data) { 1513 .name = "gcc_pcie3_axi_s_clk", 1514 .parent_hws = (const struct clk_hw *[]) { 1515 &pcie3_axi_s_clk_src.clkr.hw 1516 }, 1517 .num_parents = 1, 1518 .flags = CLK_SET_RATE_PARENT, 1519 .ops = &clk_branch2_ops, 1520 }, 1521 }, 1522 }; 1523 1524 static struct clk_branch gcc_pcie3_axi_s_bridge_clk = { 1525 .halt_reg = 0x2b040, 1526 .clkr = { 1527 .enable_reg = 0x2b040, 1528 .enable_mask = BIT(0), 1529 .hw.init = &(const struct clk_init_data) { 1530 .name = "gcc_pcie3_axi_s_bridge_clk", 1531 .parent_hws = (const struct clk_hw *[]) { 1532 &pcie3_axi_s_clk_src.clkr.hw 1533 }, 1534 .num_parents = 1, 1535 .flags = CLK_SET_RATE_PARENT, 1536 .ops = &clk_branch2_ops, 1537 }, 1538 }, 1539 }; 1540 1541 static struct clk_branch gcc_snoc_pcie3_2lane_s_clk = { 1542 .halt_reg = 0x2e054, 1543 .clkr = { 1544 .enable_reg = 0x2e054, 1545 .enable_mask = BIT(0), 1546 .hw.init = &(const struct clk_init_data) { 1547 .name = "gcc_snoc_pcie3_2lane_s_clk", 1548 .parent_hws = (const struct clk_hw *[]) { 1549 &pcie3_axi_s_clk_src.clkr.hw 1550 }, 1551 .num_parents = 1, 1552 .flags = CLK_SET_RATE_PARENT, 1553 .ops = &clk_branch2_ops, 1554 }, 1555 }, 1556 }; 1557 1558 static struct clk_regmap_phy_mux pcie0_pipe_clk_src = { 1559 .reg = 0x28064, 1560 .clkr = { 1561 .hw.init = &(const struct clk_init_data) { 1562 .name = "pcie0_pipe_clk_src", 1563 .parent_data = &(const struct clk_parent_data) { 1564 .index = DT_PCIE30_PHY0_PIPE_CLK, 1565 }, 1566 .num_parents = 1, 1567 .ops = &clk_regmap_phy_mux_ops, 1568 }, 1569 }, 1570 }; 1571 1572 static struct clk_regmap_phy_mux pcie1_pipe_clk_src = { 1573 .reg = 0x29064, 1574 .clkr = { 1575 .hw.init = &(const struct clk_init_data) { 1576 .name = "pcie1_pipe_clk_src", 1577 .parent_data = &(const struct clk_parent_data) { 1578 .index = DT_PCIE30_PHY1_PIPE_CLK, 1579 }, 1580 .num_parents = 1, 1581 .ops = &clk_regmap_phy_mux_ops, 1582 }, 1583 }, 1584 }; 1585 1586 static struct clk_regmap_phy_mux pcie2_pipe_clk_src = { 1587 .reg = 0x2a064, 1588 .clkr = { 1589 .hw.init = &(const struct clk_init_data) { 1590 .name = "pcie2_pipe_clk_src", 1591 .parent_data = &(const struct clk_parent_data) { 1592 .index = DT_PCIE30_PHY2_PIPE_CLK, 1593 }, 1594 .num_parents = 1, 1595 .ops = &clk_regmap_phy_mux_ops, 1596 }, 1597 }, 1598 }; 1599 1600 static struct clk_regmap_phy_mux pcie3_pipe_clk_src = { 1601 .reg = 0x2b064, 1602 .clkr = { 1603 .hw.init = &(const struct clk_init_data) { 1604 .name = "pcie3_pipe_clk_src", 1605 .parent_data = &(const struct clk_parent_data) { 1606 .index = DT_PCIE30_PHY3_PIPE_CLK, 1607 }, 1608 .num_parents = 1, 1609 .ops = &clk_regmap_phy_mux_ops, 1610 }, 1611 }, 1612 }; 1613 1614 static const struct freq_tbl ftbl_pcie_rchng_clk_src[] = { 1615 F(24000000, P_XO, 1, 0, 0), 1616 F(100000000, P_GPLL0, 8, 0, 0), 1617 { } 1618 }; 1619 1620 static struct clk_rcg2 pcie0_rchng_clk_src = { 1621 .cmd_rcgr = 0x28028, 1622 .freq_tbl = ftbl_pcie_rchng_clk_src, 1623 .hid_width = 5, 1624 .parent_map = gcc_xo_gpll0_map, 1625 .clkr.hw.init = &(const struct clk_init_data) { 1626 .name = "pcie0_rchng_clk_src", 1627 .parent_data = gcc_xo_gpll0, 1628 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1629 .ops = &clk_rcg2_ops, 1630 }, 1631 }; 1632 1633 static struct clk_branch gcc_pcie0_rchng_clk = { 1634 .halt_reg = 0x28028, 1635 .clkr = { 1636 .enable_reg = 0x28028, 1637 .enable_mask = BIT(1), 1638 .hw.init = &(const struct clk_init_data) { 1639 .name = "gcc_pcie0_rchng_clk", 1640 .parent_hws = (const struct clk_hw *[]) { 1641 &pcie0_rchng_clk_src.clkr.hw 1642 1643 }, 1644 .num_parents = 1, 1645 .flags = CLK_SET_RATE_PARENT, 1646 .ops = &clk_branch2_ops, 1647 }, 1648 }, 1649 }; 1650 1651 static struct clk_rcg2 pcie1_rchng_clk_src = { 1652 .cmd_rcgr = 0x29028, 1653 .freq_tbl = ftbl_pcie_rchng_clk_src, 1654 .hid_width = 5, 1655 .parent_map = gcc_xo_gpll0_map, 1656 .clkr.hw.init = &(const struct clk_init_data) { 1657 .name = "pcie1_rchng_clk_src", 1658 .parent_data = gcc_xo_gpll0, 1659 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1660 .ops = &clk_rcg2_ops, 1661 }, 1662 }; 1663 1664 static struct clk_branch gcc_pcie1_rchng_clk = { 1665 .halt_reg = 0x29028, 1666 .clkr = { 1667 .enable_reg = 0x29028, 1668 .enable_mask = BIT(1), 1669 .hw.init = &(const struct clk_init_data) { 1670 .name = "gcc_pcie1_rchng_clk", 1671 .parent_hws = (const struct clk_hw *[]) { 1672 &pcie1_rchng_clk_src.clkr.hw 1673 }, 1674 .num_parents = 1, 1675 .flags = CLK_SET_RATE_PARENT, 1676 .ops = &clk_branch2_ops, 1677 }, 1678 }, 1679 }; 1680 1681 static struct clk_rcg2 pcie2_rchng_clk_src = { 1682 .cmd_rcgr = 0x2a028, 1683 .freq_tbl = ftbl_pcie_rchng_clk_src, 1684 .hid_width = 5, 1685 .parent_map = gcc_xo_gpll0_map, 1686 .clkr.hw.init = &(const struct clk_init_data) { 1687 .name = "pcie2_rchng_clk_src", 1688 .parent_data = gcc_xo_gpll0, 1689 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1690 .ops = &clk_rcg2_ops, 1691 }, 1692 }; 1693 1694 static struct clk_branch gcc_pcie2_rchng_clk = { 1695 .halt_reg = 0x2a028, 1696 .clkr = { 1697 .enable_reg = 0x2a028, 1698 .enable_mask = BIT(1), 1699 .hw.init = &(const struct clk_init_data) { 1700 .name = "gcc_pcie2_rchng_clk", 1701 .parent_hws = (const struct clk_hw *[]) { 1702 &pcie2_rchng_clk_src.clkr.hw 1703 }, 1704 .num_parents = 1, 1705 .flags = CLK_SET_RATE_PARENT, 1706 .ops = &clk_branch2_ops, 1707 }, 1708 }, 1709 }; 1710 1711 static struct clk_rcg2 pcie3_rchng_clk_src = { 1712 .cmd_rcgr = 0x2b028, 1713 .freq_tbl = ftbl_pcie_rchng_clk_src, 1714 .hid_width = 5, 1715 .parent_map = gcc_xo_gpll0_map, 1716 .clkr.hw.init = &(const struct clk_init_data) { 1717 .name = "pcie3_rchng_clk_src", 1718 .parent_data = gcc_xo_gpll0, 1719 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1720 .ops = &clk_rcg2_ops, 1721 }, 1722 }; 1723 1724 static struct clk_branch gcc_pcie3_rchng_clk = { 1725 .halt_reg = 0x2b028, 1726 .clkr = { 1727 .enable_reg = 0x2b028, 1728 .enable_mask = BIT(1), 1729 .hw.init = &(const struct clk_init_data) { 1730 .name = "gcc_pcie3_rchng_clk", 1731 .parent_hws = (const struct clk_hw *[]) { 1732 &pcie3_rchng_clk_src.clkr.hw 1733 }, 1734 .num_parents = 1, 1735 .flags = CLK_SET_RATE_PARENT, 1736 .ops = &clk_branch2_ops, 1737 }, 1738 }, 1739 }; 1740 1741 static const struct freq_tbl ftbl_pcie_aux_clk_src[] = { 1742 F(20000000, P_GPLL0, 10, 1, 4), 1743 { } 1744 }; 1745 1746 static struct clk_rcg2 pcie_aux_clk_src = { 1747 .cmd_rcgr = 0x28004, 1748 .freq_tbl = ftbl_pcie_aux_clk_src, 1749 .mnd_width = 16, 1750 .hid_width = 5, 1751 .parent_map = gcc_xo_gpll0_gpll0_aux_core_pi_sleep_clk_map, 1752 .clkr.hw.init = &(const struct clk_init_data) { 1753 .name = "pcie_aux_clk_src", 1754 .parent_data = gcc_xo_gpll0_gpll0_aux_core_pi_sleep_clk, 1755 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_aux_core_pi_sleep_clk), 1756 .ops = &clk_rcg2_ops, 1757 }, 1758 }; 1759 1760 static struct clk_branch gcc_pcie0_aux_clk = { 1761 .halt_reg = 0x28034, 1762 .clkr = { 1763 .enable_reg = 0x28034, 1764 .enable_mask = BIT(0), 1765 .hw.init = &(const struct clk_init_data) { 1766 .name = "gcc_pcie0_aux_clk", 1767 .parent_hws = (const struct clk_hw *[]) { 1768 &pcie_aux_clk_src.clkr.hw 1769 }, 1770 .num_parents = 1, 1771 .flags = CLK_SET_RATE_PARENT, 1772 .ops = &clk_branch2_ops, 1773 }, 1774 }, 1775 }; 1776 1777 static struct clk_branch gcc_pcie1_aux_clk = { 1778 .halt_reg = 0x29034, 1779 .clkr = { 1780 .enable_reg = 0x29034, 1781 .enable_mask = BIT(0), 1782 .hw.init = &(const struct clk_init_data) { 1783 .name = "gcc_pcie1_aux_clk", 1784 .parent_hws = (const struct clk_hw *[]) { 1785 &pcie_aux_clk_src.clkr.hw 1786 }, 1787 .num_parents = 1, 1788 .flags = CLK_SET_RATE_PARENT, 1789 .ops = &clk_branch2_ops, 1790 }, 1791 }, 1792 }; 1793 1794 static struct clk_branch gcc_pcie2_aux_clk = { 1795 .halt_reg = 0x2a034, 1796 .clkr = { 1797 .enable_reg = 0x2a034, 1798 .enable_mask = BIT(0), 1799 .hw.init = &(const struct clk_init_data) { 1800 .name = "gcc_pcie2_aux_clk", 1801 .parent_hws = (const struct clk_hw *[]) { 1802 &pcie_aux_clk_src.clkr.hw 1803 }, 1804 .num_parents = 1, 1805 .flags = CLK_SET_RATE_PARENT, 1806 .ops = &clk_branch2_ops, 1807 }, 1808 }, 1809 }; 1810 1811 static struct clk_branch gcc_pcie3_aux_clk = { 1812 .halt_reg = 0x2b034, 1813 .clkr = { 1814 .enable_reg = 0x2b034, 1815 .enable_mask = BIT(0), 1816 .hw.init = &(const struct clk_init_data) { 1817 .name = "gcc_pcie3_aux_clk", 1818 .parent_hws = (const struct clk_hw *[]) { 1819 &pcie_aux_clk_src.clkr.hw 1820 }, 1821 .num_parents = 1, 1822 .flags = CLK_SET_RATE_PARENT, 1823 .ops = &clk_branch2_ops, 1824 }, 1825 }, 1826 }; 1827 1828 static const struct freq_tbl ftbl_usb_aux_clk_src[] = { 1829 F(24000000, P_XO, 1, 0, 0), 1830 { } 1831 }; 1832 1833 static struct clk_rcg2 usb0_aux_clk_src = { 1834 .cmd_rcgr = 0x2c018, 1835 .freq_tbl = ftbl_usb_aux_clk_src, 1836 .mnd_width = 16, 1837 .hid_width = 5, 1838 .parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map, 1839 .clkr.hw.init = &(const struct clk_init_data) { 1840 .name = "usb0_aux_clk_src", 1841 .parent_data = gcc_xo_gpll0_core_pi_sleep_clk, 1842 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_core_pi_sleep_clk), 1843 .ops = &clk_rcg2_ops, 1844 }, 1845 }; 1846 1847 static struct clk_branch gcc_usb0_aux_clk = { 1848 .halt_reg = 0x2c048, 1849 .clkr = { 1850 .enable_reg = 0x2c048, 1851 .enable_mask = BIT(0), 1852 .hw.init = &(const struct clk_init_data) { 1853 .name = "gcc_usb0_aux_clk", 1854 .parent_hws = (const struct clk_hw *[]) { 1855 &usb0_aux_clk_src.clkr.hw 1856 }, 1857 .num_parents = 1, 1858 .flags = CLK_SET_RATE_PARENT, 1859 .ops = &clk_branch2_ops, 1860 }, 1861 }, 1862 }; 1863 1864 static const struct freq_tbl ftbl_usb0_master_clk_src[] = { 1865 F(100000000, P_GPLL0, 8, 0, 0), 1866 F(200000000, P_GPLL0, 4, 0, 0), 1867 { } 1868 }; 1869 1870 static struct clk_rcg2 usb0_master_clk_src = { 1871 .cmd_rcgr = 0x2c004, 1872 .freq_tbl = ftbl_usb0_master_clk_src, 1873 .mnd_width = 8, 1874 .hid_width = 5, 1875 .parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map, 1876 .clkr.hw.init = &(const struct clk_init_data) { 1877 .name = "usb0_master_clk_src", 1878 .parent_data = gcc_xo_gpll0_out_main_div2_gpll0, 1879 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_out_main_div2_gpll0), 1880 .ops = &clk_rcg2_ops, 1881 }, 1882 }; 1883 1884 static struct clk_branch gcc_usb0_master_clk = { 1885 .halt_reg = 0x2c044, 1886 .clkr = { 1887 .enable_reg = 0x2c044, 1888 .enable_mask = BIT(0), 1889 .hw.init = &(const struct clk_init_data) { 1890 .name = "gcc_usb0_master_clk", 1891 .parent_hws = (const struct clk_hw *[]) { 1892 &usb0_master_clk_src.clkr.hw 1893 }, 1894 .num_parents = 1, 1895 .flags = CLK_SET_RATE_PARENT, 1896 .ops = &clk_branch2_ops, 1897 }, 1898 }, 1899 }; 1900 1901 static struct clk_branch gcc_snoc_usb_clk = { 1902 .halt_reg = 0x2e058, 1903 .clkr = { 1904 .enable_reg = 0x2e058, 1905 .enable_mask = BIT(0), 1906 .hw.init = &(const struct clk_init_data) { 1907 .name = "gcc_snoc_usb_clk", 1908 .parent_hws = (const struct clk_hw *[]) { 1909 &usb0_master_clk_src.clkr.hw 1910 }, 1911 .num_parents = 1, 1912 .flags = CLK_SET_RATE_PARENT, 1913 .ops = &clk_branch2_ops, 1914 }, 1915 }, 1916 }; 1917 1918 static struct clk_branch gcc_anoc_usb_axi_clk = { 1919 .halt_reg = 0x2e084, 1920 .clkr = { 1921 .enable_reg = 0x2e084, 1922 .enable_mask = BIT(0), 1923 .hw.init = &(const struct clk_init_data) { 1924 .name = "gcc_anoc_usb_axi_clk", 1925 .parent_hws = (const struct clk_hw *[]) { 1926 &usb0_master_clk_src.clkr.hw 1927 }, 1928 .num_parents = 1, 1929 .flags = CLK_SET_RATE_PARENT, 1930 .ops = &clk_branch2_ops, 1931 }, 1932 }, 1933 }; 1934 1935 static const struct freq_tbl ftbl_usb0_mock_utmi_clk_src[] = { 1936 F(24000000, P_XO, 1, 0, 0), 1937 F(60000000, P_GPLL4, 10, 1, 2), 1938 { } 1939 }; 1940 1941 static struct clk_rcg2 usb0_mock_utmi_clk_src = { 1942 .cmd_rcgr = 0x2c02c, 1943 .freq_tbl = ftbl_usb0_mock_utmi_clk_src, 1944 .mnd_width = 8, 1945 .hid_width = 5, 1946 .parent_map = gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map, 1947 .clkr.hw.init = &(const struct clk_init_data) { 1948 .name = "usb0_mock_utmi_clk_src", 1949 .parent_data = gcc_xo_gpll4_gpll0_gpll0_out_main_div2, 1950 .num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_out_main_div2), 1951 .ops = &clk_rcg2_ops, 1952 }, 1953 }; 1954 1955 static struct clk_regmap_div usb0_mock_utmi_div_clk_src = { 1956 .reg = 0x2c040, 1957 .shift = 0, 1958 .width = 2, 1959 .clkr.hw.init = &(const struct clk_init_data) { 1960 .name = "usb0_mock_utmi_div_clk_src", 1961 .parent_data = &(const struct clk_parent_data) { 1962 .hw = &usb0_mock_utmi_clk_src.clkr.hw, 1963 }, 1964 .num_parents = 1, 1965 .flags = CLK_SET_RATE_PARENT, 1966 .ops = &clk_regmap_div_ro_ops, 1967 }, 1968 }; 1969 1970 static struct clk_branch gcc_usb0_mock_utmi_clk = { 1971 .halt_reg = 0x2c04c, 1972 .clkr = { 1973 .enable_reg = 0x2c04c, 1974 .enable_mask = BIT(0), 1975 .hw.init = &(const struct clk_init_data) { 1976 .name = "gcc_usb0_mock_utmi_clk", 1977 .parent_hws = (const struct clk_hw *[]) { 1978 &usb0_mock_utmi_div_clk_src.clkr.hw 1979 }, 1980 .num_parents = 1, 1981 .flags = CLK_SET_RATE_PARENT, 1982 .ops = &clk_branch2_ops, 1983 }, 1984 }, 1985 }; 1986 1987 static struct clk_regmap_mux usb0_pipe_clk_src = { 1988 .reg = 0x2C074, 1989 .shift = 8, 1990 .width = 2, 1991 .parent_map = gcc_usb3phy_0_cc_pipe_clk_xo_map, 1992 .clkr = { 1993 .hw.init = &(const struct clk_init_data) { 1994 .name = "usb0_pipe_clk_src", 1995 .parent_data = gcc_usb3phy_0_cc_pipe_clk_xo, 1996 .num_parents = ARRAY_SIZE(gcc_usb3phy_0_cc_pipe_clk_xo), 1997 .flags = CLK_SET_RATE_PARENT, 1998 .ops = &clk_regmap_mux_closest_ops, 1999 }, 2000 }, 2001 }; 2002 2003 static struct clk_branch gcc_usb0_pipe_clk = { 2004 .halt_reg = 0x2c054, 2005 .halt_check = BRANCH_HALT_DELAY, 2006 .clkr = { 2007 .enable_reg = 0x2c054, 2008 .enable_mask = BIT(0), 2009 .hw.init = &(const struct clk_init_data){ 2010 .name = "gcc_usb0_pipe_clk", 2011 .parent_hws = (const struct clk_hw *[]) { 2012 &usb0_pipe_clk_src.clkr.hw 2013 }, 2014 .num_parents = 1, 2015 .flags = CLK_SET_RATE_PARENT, 2016 .ops = &clk_branch2_ops, 2017 }, 2018 }, 2019 }; 2020 2021 static struct clk_branch gcc_usb0_sleep_clk = { 2022 .halt_reg = 0x2c058, 2023 .clkr = { 2024 .enable_reg = 0x2c058, 2025 .enable_mask = BIT(0), 2026 .hw.init = &(const struct clk_init_data){ 2027 .name = "gcc_usb0_sleep_clk", 2028 .parent_hws = (const struct clk_hw *[]) { 2029 &gcc_sleep_clk_src.clkr.hw 2030 }, 2031 .num_parents = 1, 2032 .flags = CLK_SET_RATE_PARENT, 2033 .ops = &clk_branch2_ops, 2034 }, 2035 }, 2036 }; 2037 2038 static const struct freq_tbl ftbl_sdcc_apps_clk_src[] = { 2039 F(144000, P_XO, 16, 12, 125), 2040 F(400000, P_XO, 12, 1, 5), 2041 F(24000000, P_GPLL2, 12, 1, 4), 2042 F(48000000, P_GPLL2, 12, 1, 2), 2043 F(96000000, P_GPLL2, 12, 0, 0), 2044 F(177777778, P_GPLL0, 4.5, 0, 0), 2045 F(192000000, P_GPLL2, 6, 0, 0), 2046 F(384000000, P_GPLL2, 3, 0, 0), 2047 F(400000000, P_GPLL0, 2, 0, 0), 2048 { } 2049 }; 2050 2051 static struct clk_rcg2 sdcc1_apps_clk_src = { 2052 .cmd_rcgr = 0x33004, 2053 .freq_tbl = ftbl_sdcc_apps_clk_src, 2054 .mnd_width = 8, 2055 .hid_width = 5, 2056 .parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map, 2057 .clkr.hw.init = &(const struct clk_init_data) { 2058 .name = "sdcc1_apps_clk_src", 2059 .parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2, 2060 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll0_out_main_div2), 2061 .ops = &clk_rcg2_floor_ops, 2062 }, 2063 }; 2064 2065 static struct clk_branch gcc_sdcc1_apps_clk = { 2066 .halt_reg = 0x3302c, 2067 .clkr = { 2068 .enable_reg = 0x3302c, 2069 .enable_mask = BIT(0), 2070 .hw.init = &(const struct clk_init_data) { 2071 .name = "gcc_sdcc1_apps_clk", 2072 .parent_hws = (const struct clk_hw *[]) { 2073 &sdcc1_apps_clk_src.clkr.hw 2074 }, 2075 .num_parents = 1, 2076 .flags = CLK_SET_RATE_PARENT, 2077 .ops = &clk_branch2_ops, 2078 }, 2079 }, 2080 }; 2081 2082 static const struct freq_tbl ftbl_sdcc_ice_core_clk_src[] = { 2083 F(150000000, P_GPLL4, 8, 0, 0), 2084 F(300000000, P_GPLL4, 4, 0, 0), 2085 { } 2086 }; 2087 2088 static struct clk_rcg2 sdcc1_ice_core_clk_src = { 2089 .cmd_rcgr = 0x33018, 2090 .freq_tbl = ftbl_sdcc_ice_core_clk_src, 2091 .mnd_width = 8, 2092 .hid_width = 5, 2093 .parent_map = gcc_xo_gpll0_gpll4_gpll0_div2_map, 2094 .clkr.hw.init = &(const struct clk_init_data) { 2095 .name = "sdcc1_ice_core_clk_src", 2096 .parent_data = gcc_xo_gpll0_gpll4_gpll0_div2, 2097 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_div2), 2098 .ops = &clk_rcg2_ops, 2099 }, 2100 }; 2101 2102 static struct clk_branch gcc_sdcc1_ice_core_clk = { 2103 .halt_reg = 0x33030, 2104 .clkr = { 2105 .enable_reg = 0x33030, 2106 .enable_mask = BIT(0), 2107 .hw.init = &(const struct clk_init_data) { 2108 .name = "gcc_sdcc1_ice_core_clk", 2109 .parent_hws = (const struct clk_hw *[]) { 2110 &sdcc1_ice_core_clk_src.clkr.hw 2111 }, 2112 .num_parents = 1, 2113 .flags = CLK_SET_RATE_PARENT, 2114 .ops = &clk_branch2_ops, 2115 }, 2116 }, 2117 }; 2118 2119 static const struct freq_tbl ftbl_pcnoc_bfdcd_clk_src[] = { 2120 F(24000000, P_XO, 1, 0, 0), 2121 F(50000000, P_GPLL0, 16, 0, 0), 2122 F(80000000, P_GPLL0, 10, 0, 0), 2123 F(100000000, P_GPLL0, 8, 0, 0), 2124 { } 2125 }; 2126 2127 static struct clk_rcg2 pcnoc_bfdcd_clk_src = { 2128 .cmd_rcgr = 0x31004, 2129 .freq_tbl = ftbl_pcnoc_bfdcd_clk_src, 2130 .hid_width = 5, 2131 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 2132 .clkr.hw.init = &(const struct clk_init_data) { 2133 .name = "pcnoc_bfdcd_clk_src", 2134 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, 2135 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), 2136 .flags = CLK_IS_CRITICAL, 2137 .ops = &clk_rcg2_ops, 2138 }, 2139 }; 2140 2141 static struct clk_branch gcc_crypto_axi_clk = { 2142 .halt_reg = 0x16010, 2143 .halt_check = BRANCH_HALT_VOTED, 2144 .clkr = { 2145 .enable_reg = 0xb004, 2146 .enable_mask = BIT(15), 2147 .hw.init = &(const struct clk_init_data) { 2148 .name = "gcc_crypto_axi_clk", 2149 .parent_hws = (const struct clk_hw *[]) { 2150 &pcnoc_bfdcd_clk_src.clkr.hw }, 2151 .num_parents = 1, 2152 .flags = CLK_SET_RATE_PARENT, 2153 .ops = &clk_branch2_ops, 2154 }, 2155 }, 2156 }; 2157 2158 static struct clk_branch gcc_crypto_ahb_clk = { 2159 .halt_reg = 0x16014, 2160 .halt_check = BRANCH_HALT_VOTED, 2161 .clkr = { 2162 .enable_reg = 0xb004, 2163 .enable_mask = BIT(16), 2164 .hw.init = &(const struct clk_init_data) { 2165 .name = "gcc_crypto_ahb_clk", 2166 .parent_hws = (const struct clk_hw *[]) { 2167 &pcnoc_bfdcd_clk_src.clkr.hw }, 2168 .num_parents = 1, 2169 .flags = CLK_SET_RATE_PARENT, 2170 .ops = &clk_branch2_ops, 2171 }, 2172 }, 2173 }; 2174 2175 static struct clk_branch gcc_nsscfg_clk = { 2176 .halt_reg = 0x1702c, 2177 .clkr = { 2178 .enable_reg = 0x1702c, 2179 .enable_mask = BIT(0), 2180 .hw.init = &(const struct clk_init_data) { 2181 .name = "gcc_nsscfg_clk", 2182 .parent_hws = (const struct clk_hw *[]) { 2183 &pcnoc_bfdcd_clk_src.clkr.hw 2184 }, 2185 .num_parents = 1, 2186 .flags = CLK_SET_RATE_PARENT, 2187 .ops = &clk_branch2_ops, 2188 }, 2189 }, 2190 }; 2191 2192 static struct clk_branch gcc_nssnoc_nsscc_clk = { 2193 .halt_reg = 0x17030, 2194 .clkr = { 2195 .enable_reg = 0x17030, 2196 .enable_mask = BIT(0), 2197 .hw.init = &(const struct clk_init_data) { 2198 .name = "gcc_nssnoc_nsscc_clk", 2199 .parent_hws = (const struct clk_hw *[]) { 2200 &pcnoc_bfdcd_clk_src.clkr.hw 2201 }, 2202 .num_parents = 1, 2203 .flags = CLK_SET_RATE_PARENT, 2204 .ops = &clk_branch2_ops, 2205 }, 2206 }, 2207 }; 2208 2209 static struct clk_branch gcc_nsscc_clk = { 2210 .halt_reg = 0x17034, 2211 .clkr = { 2212 .enable_reg = 0x17034, 2213 .enable_mask = BIT(0), 2214 .hw.init = &(const struct clk_init_data) { 2215 .name = "gcc_nsscc_clk", 2216 .parent_hws = (const struct clk_hw *[]) { 2217 &pcnoc_bfdcd_clk_src.clkr.hw 2218 }, 2219 .num_parents = 1, 2220 .flags = CLK_SET_RATE_PARENT, 2221 .ops = &clk_branch2_ops, 2222 }, 2223 }, 2224 }; 2225 2226 static struct clk_branch gcc_nssnoc_pcnoc_1_clk = { 2227 .halt_reg = 0x17080, 2228 .clkr = { 2229 .enable_reg = 0x17080, 2230 .enable_mask = BIT(0), 2231 .hw.init = &(const struct clk_init_data) { 2232 .name = "gcc_nssnoc_pcnoc_1_clk", 2233 .parent_hws = (const struct clk_hw *[]) { 2234 &pcnoc_bfdcd_clk_src.clkr.hw 2235 }, 2236 .num_parents = 1, 2237 .flags = CLK_SET_RATE_PARENT, 2238 .ops = &clk_branch2_ops, 2239 }, 2240 }, 2241 }; 2242 2243 static struct clk_branch gcc_qdss_dap_ahb_clk = { 2244 .halt_reg = 0x2d064, 2245 .clkr = { 2246 .enable_reg = 0x2d064, 2247 .enable_mask = BIT(0), 2248 .hw.init = &(const struct clk_init_data) { 2249 .name = "gcc_qdss_dap_ahb_clk", 2250 .parent_hws = (const struct clk_hw *[]) { 2251 &pcnoc_bfdcd_clk_src.clkr.hw 2252 }, 2253 .num_parents = 1, 2254 .flags = CLK_SET_RATE_PARENT, 2255 .ops = &clk_branch2_ops, 2256 }, 2257 }, 2258 }; 2259 2260 static struct clk_branch gcc_qdss_cfg_ahb_clk = { 2261 .halt_reg = 0x2d068, 2262 .clkr = { 2263 .enable_reg = 0x2d068, 2264 .enable_mask = BIT(0), 2265 .hw.init = &(const struct clk_init_data) { 2266 .name = "gcc_qdss_cfg_ahb_clk", 2267 .parent_hws = (const struct clk_hw *[]) { 2268 &pcnoc_bfdcd_clk_src.clkr.hw 2269 }, 2270 .num_parents = 1, 2271 .flags = CLK_SET_RATE_PARENT, 2272 .ops = &clk_branch2_ops, 2273 }, 2274 }, 2275 }; 2276 2277 static struct clk_branch gcc_qpic_ahb_clk = { 2278 .halt_reg = 0x32010, 2279 .clkr = { 2280 .enable_reg = 0x32010, 2281 .enable_mask = BIT(0), 2282 .hw.init = &(const struct clk_init_data) { 2283 .name = "gcc_qpic_ahb_clk", 2284 .parent_hws = (const struct clk_hw *[]) { 2285 &pcnoc_bfdcd_clk_src.clkr.hw 2286 }, 2287 .num_parents = 1, 2288 .flags = CLK_SET_RATE_PARENT, 2289 .ops = &clk_branch2_ops, 2290 }, 2291 }, 2292 }; 2293 2294 static struct clk_branch gcc_qpic_clk = { 2295 .halt_reg = 0x32014, 2296 .clkr = { 2297 .enable_reg = 0x32014, 2298 .enable_mask = BIT(0), 2299 .hw.init = &(const struct clk_init_data) { 2300 .name = "gcc_qpic_clk", 2301 .parent_hws = (const struct clk_hw *[]) { 2302 &pcnoc_bfdcd_clk_src.clkr.hw 2303 }, 2304 .num_parents = 1, 2305 .flags = CLK_SET_RATE_PARENT, 2306 .ops = &clk_branch2_ops, 2307 }, 2308 }, 2309 }; 2310 2311 static struct clk_branch gcc_blsp1_ahb_clk = { 2312 .halt_reg = 0x01004, 2313 .halt_check = BRANCH_HALT_VOTED, 2314 .clkr = { 2315 .enable_reg = 0x0b004, 2316 .enable_mask = BIT(4), 2317 .hw.init = &(const struct clk_init_data) { 2318 .name = "gcc_blsp1_ahb_clk", 2319 .parent_hws = (const struct clk_hw *[]) { 2320 &pcnoc_bfdcd_clk_src.clkr.hw 2321 }, 2322 .num_parents = 1, 2323 .flags = CLK_SET_RATE_PARENT, 2324 .ops = &clk_branch2_ops, 2325 }, 2326 }, 2327 }; 2328 2329 static struct clk_branch gcc_mdio_ahb_clk = { 2330 .halt_reg = 0x17040, 2331 .clkr = { 2332 .enable_reg = 0x17040, 2333 .enable_mask = BIT(0), 2334 .hw.init = &(const struct clk_init_data) { 2335 .name = "gcc_mdio_ahb_clk", 2336 .parent_hws = (const struct clk_hw *[]) { 2337 &pcnoc_bfdcd_clk_src.clkr.hw 2338 }, 2339 .num_parents = 1, 2340 .flags = CLK_SET_RATE_PARENT, 2341 .ops = &clk_branch2_ops, 2342 }, 2343 }, 2344 }; 2345 2346 static struct clk_branch gcc_prng_ahb_clk = { 2347 .halt_reg = 0x13024, 2348 .halt_check = BRANCH_HALT_VOTED, 2349 .clkr = { 2350 .enable_reg = 0x0b004, 2351 .enable_mask = BIT(10), 2352 .hw.init = &(const struct clk_init_data) { 2353 .name = "gcc_prng_ahb_clk", 2354 .parent_hws = (const struct clk_hw *[]) { 2355 &pcnoc_bfdcd_clk_src.clkr.hw 2356 }, 2357 .num_parents = 1, 2358 .flags = CLK_SET_RATE_PARENT, 2359 .ops = &clk_branch2_ops, 2360 }, 2361 }, 2362 }; 2363 2364 static struct clk_branch gcc_uniphy0_ahb_clk = { 2365 .halt_reg = 0x1704c, 2366 .clkr = { 2367 .enable_reg = 0x1704c, 2368 .enable_mask = BIT(0), 2369 .hw.init = &(const struct clk_init_data) { 2370 .name = "gcc_uniphy0_ahb_clk", 2371 .parent_hws = (const struct clk_hw *[]) { 2372 &pcnoc_bfdcd_clk_src.clkr.hw 2373 }, 2374 .num_parents = 1, 2375 .flags = CLK_SET_RATE_PARENT, 2376 .ops = &clk_branch2_ops, 2377 }, 2378 }, 2379 }; 2380 2381 static struct clk_branch gcc_uniphy1_ahb_clk = { 2382 .halt_reg = 0x1705c, 2383 .clkr = { 2384 .enable_reg = 0x1705c, 2385 .enable_mask = BIT(0), 2386 .hw.init = &(const struct clk_init_data) { 2387 .name = "gcc_uniphy1_ahb_clk", 2388 .parent_hws = (const struct clk_hw *[]) { 2389 &pcnoc_bfdcd_clk_src.clkr.hw 2390 }, 2391 .num_parents = 1, 2392 .flags = CLK_SET_RATE_PARENT, 2393 .ops = &clk_branch2_ops, 2394 }, 2395 }, 2396 }; 2397 2398 static struct clk_branch gcc_uniphy2_ahb_clk = { 2399 .halt_reg = 0x1706c, 2400 .clkr = { 2401 .enable_reg = 0x1706c, 2402 .enable_mask = BIT(0), 2403 .hw.init = &(const struct clk_init_data) { 2404 .name = "gcc_uniphy2_ahb_clk", 2405 .parent_hws = (const struct clk_hw *[]) { 2406 &pcnoc_bfdcd_clk_src.clkr.hw 2407 }, 2408 .num_parents = 1, 2409 .flags = CLK_SET_RATE_PARENT, 2410 .ops = &clk_branch2_ops, 2411 }, 2412 }, 2413 }; 2414 2415 static struct clk_branch gcc_cmn_12gpll_ahb_clk = { 2416 .halt_reg = 0x3a004, 2417 .clkr = { 2418 .enable_reg = 0x3a004, 2419 .enable_mask = BIT(0), 2420 .hw.init = &(const struct clk_init_data) { 2421 .name = "gcc_cmn_12gpll_ahb_clk", 2422 .parent_hws = (const struct clk_hw *[]) { 2423 &pcnoc_bfdcd_clk_src.clkr.hw 2424 }, 2425 .num_parents = 1, 2426 .flags = CLK_SET_RATE_PARENT, 2427 .ops = &clk_branch2_ops, 2428 }, 2429 }, 2430 }; 2431 2432 static struct clk_branch gcc_cmn_12gpll_apu_clk = { 2433 .halt_reg = 0x3a00c, 2434 .clkr = { 2435 .enable_reg = 0x3a00c, 2436 .enable_mask = BIT(0), 2437 .hw.init = &(const struct clk_init_data) { 2438 .name = "gcc_cmn_12gpll_apu_clk", 2439 .parent_hws = (const struct clk_hw *[]) { 2440 &pcnoc_bfdcd_clk_src.clkr.hw 2441 }, 2442 .num_parents = 1, 2443 .flags = CLK_SET_RATE_PARENT, 2444 .ops = &clk_branch2_ops, 2445 }, 2446 }, 2447 }; 2448 2449 static struct clk_branch gcc_pcie0_ahb_clk = { 2450 .halt_reg = 0x28030, 2451 .clkr = { 2452 .enable_reg = 0x28030, 2453 .enable_mask = BIT(0), 2454 .hw.init = &(const struct clk_init_data) { 2455 .name = "gcc_pcie0_ahb_clk", 2456 .parent_hws = (const struct clk_hw *[]) { 2457 &pcnoc_bfdcd_clk_src.clkr.hw 2458 }, 2459 .num_parents = 1, 2460 .flags = CLK_SET_RATE_PARENT, 2461 .ops = &clk_branch2_ops, 2462 }, 2463 }, 2464 }; 2465 2466 static struct clk_branch gcc_pcie1_ahb_clk = { 2467 .halt_reg = 0x29030, 2468 .clkr = { 2469 .enable_reg = 0x29030, 2470 .enable_mask = BIT(0), 2471 .hw.init = &(const struct clk_init_data) { 2472 .name = "gcc_pcie1_ahb_clk", 2473 .parent_hws = (const struct clk_hw *[]) { 2474 &pcnoc_bfdcd_clk_src.clkr.hw 2475 }, 2476 .num_parents = 1, 2477 .flags = CLK_SET_RATE_PARENT, 2478 .ops = &clk_branch2_ops, 2479 }, 2480 }, 2481 }; 2482 2483 static struct clk_branch gcc_pcie2_ahb_clk = { 2484 .halt_reg = 0x2a030, 2485 .clkr = { 2486 .enable_reg = 0x2a030, 2487 .enable_mask = BIT(0), 2488 .hw.init = &(const struct clk_init_data) { 2489 .name = "gcc_pcie2_ahb_clk", 2490 .parent_hws = (const struct clk_hw *[]) { 2491 &pcnoc_bfdcd_clk_src.clkr.hw 2492 }, 2493 .num_parents = 1, 2494 .flags = CLK_SET_RATE_PARENT, 2495 .ops = &clk_branch2_ops, 2496 }, 2497 }, 2498 }; 2499 2500 static struct clk_branch gcc_pcie3_ahb_clk = { 2501 .halt_reg = 0x2b030, 2502 .clkr = { 2503 .enable_reg = 0x2b030, 2504 .enable_mask = BIT(0), 2505 .hw.init = &(const struct clk_init_data) { 2506 .name = "gcc_pcie3_ahb_clk", 2507 .parent_hws = (const struct clk_hw *[]) { 2508 &pcnoc_bfdcd_clk_src.clkr.hw 2509 }, 2510 .num_parents = 1, 2511 .flags = CLK_SET_RATE_PARENT, 2512 .ops = &clk_branch2_ops, 2513 }, 2514 }, 2515 }; 2516 2517 static struct clk_branch gcc_usb0_phy_cfg_ahb_clk = { 2518 .halt_reg = 0x2c05c, 2519 .clkr = { 2520 .enable_reg = 0x2c05c, 2521 .enable_mask = BIT(0), 2522 .hw.init = &(const struct clk_init_data) { 2523 .name = "gcc_usb0_phy_cfg_ahb_clk", 2524 .parent_hws = (const struct clk_hw *[]) { 2525 &pcnoc_bfdcd_clk_src.clkr.hw 2526 }, 2527 .num_parents = 1, 2528 .flags = CLK_SET_RATE_PARENT, 2529 .ops = &clk_branch2_ops, 2530 }, 2531 }, 2532 }; 2533 2534 static struct clk_branch gcc_sdcc1_ahb_clk = { 2535 .halt_reg = 0x33034, 2536 .clkr = { 2537 .enable_reg = 0x33034, 2538 .enable_mask = BIT(0), 2539 .hw.init = &(const struct clk_init_data) { 2540 .name = "gcc_sdcc1_ahb_clk", 2541 .parent_hws = (const struct clk_hw *[]) { 2542 &pcnoc_bfdcd_clk_src.clkr.hw 2543 }, 2544 .num_parents = 1, 2545 .flags = CLK_SET_RATE_PARENT, 2546 .ops = &clk_branch2_ops, 2547 }, 2548 }, 2549 }; 2550 2551 static const struct freq_tbl ftbl_system_noc_bfdcd_clk_src[] = { 2552 F(24000000, P_XO, 1, 0, 0), 2553 F(133333333, P_GPLL0, 6, 0, 0), 2554 F(200000000, P_GPLL0, 4, 0, 0), 2555 F(342850000, P_GPLL4, 3.5, 0, 0), 2556 { } 2557 }; 2558 2559 static struct clk_rcg2 system_noc_bfdcd_clk_src = { 2560 .cmd_rcgr = 0x2e004, 2561 .freq_tbl = ftbl_system_noc_bfdcd_clk_src, 2562 .hid_width = 5, 2563 .parent_map = gcc_xo_gpll0_gpll4_map, 2564 .clkr.hw.init = &(const struct clk_init_data) { 2565 .name = "system_noc_bfdcd_clk_src", 2566 .parent_data = gcc_xo_gpll0_gpll4, 2567 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4), 2568 .flags = CLK_IS_CRITICAL, 2569 .ops = &clk_rcg2_ops, 2570 }, 2571 }; 2572 2573 static struct clk_branch gcc_q6ss_boot_clk = { 2574 .halt_reg = 0x25080, 2575 .halt_check = BRANCH_HALT_SKIP, 2576 .clkr = { 2577 .enable_reg = 0x25080, 2578 .enable_mask = BIT(0), 2579 .hw.init = &(const struct clk_init_data) { 2580 .name = "gcc_q6ss_boot_clk", 2581 .parent_hws = (const struct clk_hw *[]) { 2582 &system_noc_bfdcd_clk_src.clkr.hw 2583 }, 2584 .num_parents = 1, 2585 .flags = CLK_SET_RATE_PARENT, 2586 .ops = &clk_branch2_ops, 2587 }, 2588 }, 2589 }; 2590 2591 static struct clk_branch gcc_nssnoc_snoc_clk = { 2592 .halt_reg = 0x17028, 2593 .clkr = { 2594 .enable_reg = 0x17028, 2595 .enable_mask = BIT(0), 2596 .hw.init = &(const struct clk_init_data) { 2597 .name = "gcc_nssnoc_snoc_clk", 2598 .parent_hws = (const struct clk_hw *[]) { 2599 &system_noc_bfdcd_clk_src.clkr.hw 2600 }, 2601 .num_parents = 1, 2602 .flags = CLK_SET_RATE_PARENT, 2603 .ops = &clk_branch2_ops, 2604 }, 2605 }, 2606 }; 2607 2608 static struct clk_branch gcc_nssnoc_snoc_1_clk = { 2609 .halt_reg = 0x1707c, 2610 .clkr = { 2611 .enable_reg = 0x1707c, 2612 .enable_mask = BIT(0), 2613 .hw.init = &(const struct clk_init_data) { 2614 .name = "gcc_nssnoc_snoc_1_clk", 2615 .parent_hws = (const struct clk_hw *[]) { 2616 &system_noc_bfdcd_clk_src.clkr.hw 2617 }, 2618 .num_parents = 1, 2619 .flags = CLK_SET_RATE_PARENT, 2620 .ops = &clk_branch2_ops, 2621 }, 2622 }, 2623 }; 2624 2625 static struct clk_branch gcc_qdss_etr_usb_clk = { 2626 .halt_reg = 0x2d060, 2627 .clkr = { 2628 .enable_reg = 0x2d060, 2629 .enable_mask = BIT(0), 2630 .hw.init = &(const struct clk_init_data) { 2631 .name = "gcc_qdss_etr_usb_clk", 2632 .parent_hws = (const struct clk_hw *[]) { 2633 &system_noc_bfdcd_clk_src.clkr.hw 2634 }, 2635 .num_parents = 1, 2636 .flags = CLK_SET_RATE_PARENT, 2637 .ops = &clk_branch2_ops, 2638 }, 2639 }, 2640 }; 2641 2642 static const struct freq_tbl ftbl_wcss_ahb_clk_src[] = { 2643 F(24000000, P_XO, 1, 0, 0), 2644 F(133333333, P_GPLL0, 6, 0, 0), 2645 { } 2646 }; 2647 2648 static struct clk_rcg2 wcss_ahb_clk_src = { 2649 .cmd_rcgr = 0x25030, 2650 .freq_tbl = ftbl_wcss_ahb_clk_src, 2651 .hid_width = 5, 2652 .parent_map = gcc_xo_gpll0_map, 2653 .clkr.hw.init = &(const struct clk_init_data) { 2654 .name = "wcss_ahb_clk_src", 2655 .parent_data = gcc_xo_gpll0, 2656 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 2657 .ops = &clk_rcg2_ops, 2658 }, 2659 }; 2660 2661 static struct clk_branch gcc_q6_ahb_clk = { 2662 .halt_reg = 0x25014, 2663 .clkr = { 2664 .enable_reg = 0x25014, 2665 .enable_mask = BIT(0), 2666 .hw.init = &(const struct clk_init_data) { 2667 .name = "gcc_q6_ahb_clk", 2668 .parent_hws = (const struct clk_hw *[]) { 2669 &wcss_ahb_clk_src.clkr.hw 2670 }, 2671 .num_parents = 1, 2672 .flags = CLK_SET_RATE_PARENT, 2673 .ops = &clk_branch2_ops, 2674 }, 2675 }, 2676 }; 2677 2678 static struct clk_branch gcc_q6_ahb_s_clk = { 2679 .halt_reg = 0x25018, 2680 .clkr = { 2681 .enable_reg = 0x25018, 2682 .enable_mask = BIT(0), 2683 .hw.init = &(const struct clk_init_data) { 2684 .name = "gcc_q6_ahb_s_clk", 2685 .parent_hws = (const struct clk_hw *[]) { 2686 &wcss_ahb_clk_src.clkr.hw 2687 }, 2688 .num_parents = 1, 2689 .flags = CLK_SET_RATE_PARENT, 2690 .ops = &clk_branch2_ops, 2691 }, 2692 }, 2693 }; 2694 2695 static struct clk_branch gcc_wcss_ecahb_clk = { 2696 .halt_reg = 0x25058, 2697 .clkr = { 2698 .enable_reg = 0x25058, 2699 .enable_mask = BIT(0), 2700 .hw.init = &(const struct clk_init_data) { 2701 .name = "gcc_wcss_ecahb_clk", 2702 .parent_hws = (const struct clk_hw *[]) { 2703 &wcss_ahb_clk_src.clkr.hw 2704 }, 2705 .num_parents = 1, 2706 .flags = CLK_SET_RATE_PARENT, 2707 .ops = &clk_branch2_ops, 2708 }, 2709 }, 2710 }; 2711 2712 static struct clk_branch gcc_wcss_acmt_clk = { 2713 .halt_reg = 0x2505c, 2714 .clkr = { 2715 .enable_reg = 0x2505c, 2716 .enable_mask = BIT(0), 2717 .hw.init = &(const struct clk_init_data) { 2718 .name = "gcc_wcss_acmt_clk", 2719 .parent_hws = (const struct clk_hw *[]) { 2720 &wcss_ahb_clk_src.clkr.hw 2721 }, 2722 .num_parents = 1, 2723 .flags = CLK_SET_RATE_PARENT, 2724 .ops = &clk_branch2_ops, 2725 }, 2726 }, 2727 }; 2728 2729 static struct clk_branch gcc_sys_noc_wcss_ahb_clk = { 2730 .halt_reg = 0x2e030, 2731 .clkr = { 2732 .enable_reg = 0x2e030, 2733 .enable_mask = BIT(0), 2734 .hw.init = &(const struct clk_init_data) { 2735 .name = "gcc_sys_noc_wcss_ahb_clk", 2736 .parent_hws = (const struct clk_hw *[]) { 2737 &wcss_ahb_clk_src.clkr.hw 2738 }, 2739 .num_parents = 1, 2740 .flags = CLK_SET_RATE_PARENT, 2741 .ops = &clk_branch2_ops, 2742 }, 2743 }, 2744 }; 2745 2746 static const struct freq_tbl ftbl_wcss_axi_m_clk_src[] = { 2747 F(24000000, P_XO, 1, 0, 0), 2748 F(133333333, P_GPLL0, 6, 0, 0), 2749 F(266666667, P_GPLL0, 3, 0, 0), 2750 { } 2751 }; 2752 2753 static struct clk_rcg2 wcss_axi_m_clk_src = { 2754 .cmd_rcgr = 0x25078, 2755 .freq_tbl = ftbl_wcss_axi_m_clk_src, 2756 .hid_width = 5, 2757 .parent_map = gcc_xo_gpll0_map, 2758 .clkr.hw.init = &(const struct clk_init_data) { 2759 .name = "wcss_axi_m_clk_src", 2760 .parent_data = gcc_xo_gpll0, 2761 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 2762 .ops = &clk_rcg2_ops, 2763 }, 2764 }; 2765 2766 static struct clk_branch gcc_anoc_wcss_axi_m_clk = { 2767 .halt_reg = 0x2e0a8, 2768 .clkr = { 2769 .enable_reg = 0x2e0a8, 2770 .enable_mask = BIT(0), 2771 .hw.init = &(const struct clk_init_data) { 2772 .name = "gcc_anoc_wcss_axi_m_clk", 2773 .parent_hws = (const struct clk_hw *[]) { 2774 &wcss_axi_m_clk_src.clkr.hw 2775 }, 2776 .num_parents = 1, 2777 .flags = CLK_SET_RATE_PARENT, 2778 .ops = &clk_branch2_ops, 2779 }, 2780 }, 2781 }; 2782 2783 static const struct freq_tbl ftbl_qdss_at_clk_src[] = { 2784 F(240000000, P_GPLL4, 5, 0, 0), 2785 { } 2786 }; 2787 2788 static struct clk_rcg2 qdss_at_clk_src = { 2789 .cmd_rcgr = 0x2d004, 2790 .freq_tbl = ftbl_qdss_at_clk_src, 2791 .hid_width = 5, 2792 .parent_map = gcc_xo_gpll4_gpll0_gpll0_div2_map, 2793 .clkr.hw.init = &(const struct clk_init_data) { 2794 .name = "qdss_at_clk_src", 2795 .parent_data = gcc_xo_gpll4_gpll0_gpll0_div2, 2796 .num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_div2), 2797 .ops = &clk_rcg2_ops, 2798 }, 2799 }; 2800 2801 static struct clk_branch gcc_q6ss_atbm_clk = { 2802 .halt_reg = 0x2501c, 2803 .clkr = { 2804 .enable_reg = 0x2501c, 2805 .enable_mask = BIT(0), 2806 .hw.init = &(const struct clk_init_data) { 2807 .name = "gcc_q6ss_atbm_clk", 2808 .parent_hws = (const struct clk_hw *[]) { 2809 &qdss_at_clk_src.clkr.hw 2810 }, 2811 .num_parents = 1, 2812 .flags = CLK_SET_RATE_PARENT, 2813 .ops = &clk_branch2_ops, 2814 }, 2815 }, 2816 }; 2817 2818 static struct clk_branch gcc_wcss_dbg_ifc_atb_clk = { 2819 .halt_reg = 0x2503c, 2820 .clkr = { 2821 .enable_reg = 0x2503c, 2822 .enable_mask = BIT(0), 2823 .hw.init = &(const struct clk_init_data) { 2824 .name = "gcc_wcss_dbg_ifc_atb_clk", 2825 .parent_hws = (const struct clk_hw *[]) { 2826 &qdss_at_clk_src.clkr.hw 2827 }, 2828 .num_parents = 1, 2829 .flags = CLK_SET_RATE_PARENT, 2830 .ops = &clk_branch2_ops, 2831 }, 2832 }, 2833 }; 2834 2835 static struct clk_branch gcc_nssnoc_atb_clk = { 2836 .halt_reg = 0x17014, 2837 .clkr = { 2838 .enable_reg = 0x17014, 2839 .enable_mask = BIT(0), 2840 .hw.init = &(const struct clk_init_data) { 2841 .name = "gcc_nssnoc_atb_clk", 2842 .parent_hws = (const struct clk_hw *[]) { 2843 &qdss_at_clk_src.clkr.hw 2844 }, 2845 .num_parents = 1, 2846 .flags = CLK_SET_RATE_PARENT, 2847 .ops = &clk_branch2_ops, 2848 }, 2849 }, 2850 }; 2851 2852 static struct clk_branch gcc_qdss_at_clk = { 2853 .halt_reg = 0x2d038, 2854 .clkr = { 2855 .enable_reg = 0x2d038, 2856 .enable_mask = BIT(0), 2857 .hw.init = &(const struct clk_init_data) { 2858 .name = "gcc_qdss_at_clk", 2859 .parent_hws = (const struct clk_hw *[]) { 2860 &qdss_at_clk_src.clkr.hw 2861 }, 2862 .num_parents = 1, 2863 .flags = CLK_SET_RATE_PARENT, 2864 .ops = &clk_branch2_ops, 2865 }, 2866 }, 2867 }; 2868 2869 static struct clk_branch gcc_sys_noc_at_clk = { 2870 .halt_reg = 0x2e038, 2871 .clkr = { 2872 .enable_reg = 0x2e038, 2873 .enable_mask = BIT(0), 2874 .hw.init = &(const struct clk_init_data) { 2875 .name = "gcc_sys_noc_at_clk", 2876 .parent_hws = (const struct clk_hw *[]) { 2877 &qdss_at_clk_src.clkr.hw 2878 }, 2879 .num_parents = 1, 2880 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 2881 .ops = &clk_branch2_ops, 2882 }, 2883 }, 2884 }; 2885 2886 static struct clk_branch gcc_pcnoc_at_clk = { 2887 .halt_reg = 0x31024, 2888 .clkr = { 2889 .enable_reg = 0x31024, 2890 .enable_mask = BIT(0), 2891 .hw.init = &(const struct clk_init_data) { 2892 .name = "gcc_pcnoc_at_clk", 2893 .parent_hws = (const struct clk_hw *[]) { 2894 &qdss_at_clk_src.clkr.hw 2895 }, 2896 .num_parents = 1, 2897 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 2898 .ops = &clk_branch2_ops, 2899 }, 2900 }, 2901 }; 2902 2903 static struct clk_fixed_factor gcc_eud_at_div_clk_src = { 2904 .mult = 1, 2905 .div = 6, 2906 .hw.init = &(const struct clk_init_data) { 2907 .name = "gcc_eud_at_div_clk_src", 2908 .parent_hws = (const struct clk_hw *[]) { 2909 &qdss_at_clk_src.clkr.hw 2910 }, 2911 .num_parents = 1, 2912 .flags = CLK_SET_RATE_PARENT, 2913 .ops = &clk_fixed_factor_ops, 2914 }, 2915 }; 2916 2917 static struct clk_branch gcc_usb0_eud_at_clk = { 2918 .halt_reg = 0x30004, 2919 .clkr = { 2920 .enable_reg = 0x30004, 2921 .enable_mask = BIT(0), 2922 .hw.init = &(const struct clk_init_data) { 2923 .name = "gcc_usb0_eud_at_clk", 2924 .parent_hws = (const struct clk_hw *[]) { 2925 &gcc_eud_at_div_clk_src.hw 2926 }, 2927 .num_parents = 1, 2928 .flags = CLK_SET_RATE_PARENT, 2929 .ops = &clk_branch2_ops, 2930 }, 2931 }, 2932 }; 2933 2934 static struct clk_branch gcc_qdss_eud_at_clk = { 2935 .halt_reg = 0x2d06c, 2936 .clkr = { 2937 .enable_reg = 0x2d06c, 2938 .enable_mask = BIT(0), 2939 .hw.init = &(const struct clk_init_data) { 2940 .name = "gcc_qdss_eud_at_clk", 2941 .parent_hws = (const struct clk_hw *[]) { 2942 &gcc_eud_at_div_clk_src.hw 2943 }, 2944 .num_parents = 1, 2945 .flags = CLK_SET_RATE_PARENT, 2946 .ops = &clk_branch2_ops, 2947 }, 2948 }, 2949 }; 2950 2951 static const struct freq_tbl ftbl_qdss_stm_clk_src[] = { 2952 F(24000000, P_XO, 1, 0, 0), 2953 F(200000000, P_GPLL0, 4, 0, 0), 2954 { } 2955 }; 2956 2957 static struct clk_rcg2 qdss_stm_clk_src = { 2958 .cmd_rcgr = 0x2d00c, 2959 .freq_tbl = ftbl_qdss_stm_clk_src, 2960 .hid_width = 5, 2961 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 2962 .clkr.hw.init = &(const struct clk_init_data) { 2963 .name = "qdss_stm_clk_src", 2964 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, 2965 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), 2966 .ops = &clk_rcg2_ops, 2967 }, 2968 }; 2969 2970 static struct clk_branch gcc_qdss_stm_clk = { 2971 .halt_reg = 0x2d03c, 2972 .clkr = { 2973 .enable_reg = 0x2d03c, 2974 .enable_mask = BIT(0), 2975 .hw.init = &(const struct clk_init_data) { 2976 .name = "gcc_qdss_stm_clk", 2977 .parent_hws = (const struct clk_hw *[]) { 2978 &qdss_stm_clk_src.clkr.hw 2979 }, 2980 .num_parents = 1, 2981 .flags = CLK_SET_RATE_PARENT, 2982 .ops = &clk_branch2_ops, 2983 }, 2984 }, 2985 }; 2986 2987 static struct clk_branch gcc_sys_noc_qdss_stm_axi_clk = { 2988 .halt_reg = 0x2e034, 2989 .clkr = { 2990 .enable_reg = 0x2e034, 2991 .enable_mask = BIT(0), 2992 .hw.init = &(const struct clk_init_data) { 2993 .name = "gcc_sys_noc_qdss_stm_axi_clk", 2994 .parent_hws = (const struct clk_hw *[]) { 2995 &qdss_stm_clk_src.clkr.hw 2996 }, 2997 .num_parents = 1, 2998 .flags = CLK_SET_RATE_PARENT, 2999 .ops = &clk_branch2_ops, 3000 }, 3001 }, 3002 }; 3003 3004 static const struct freq_tbl ftbl_qdss_traceclkin_clk_src[] = { 3005 F(300000000, P_GPLL4, 4, 0, 0), 3006 { } 3007 }; 3008 3009 static struct clk_rcg2 qdss_traceclkin_clk_src = { 3010 .cmd_rcgr = 0x2d014, 3011 .freq_tbl = ftbl_qdss_traceclkin_clk_src, 3012 .hid_width = 5, 3013 .parent_map = gcc_xo_gpll4_gpll0_gpll0_div2_map, 3014 .clkr.hw.init = &(const struct clk_init_data) { 3015 .name = "qdss_traceclkin_clk_src", 3016 .parent_data = gcc_xo_gpll4_gpll0_gpll0_div2, 3017 .num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_div2), 3018 .ops = &clk_rcg2_ops, 3019 }, 3020 }; 3021 3022 static struct clk_branch gcc_qdss_traceclkin_clk = { 3023 .halt_reg = 0x2d040, 3024 .clkr = { 3025 .enable_reg = 0x2d040, 3026 .enable_mask = BIT(0), 3027 .hw.init = &(const struct clk_init_data) { 3028 .name = "gcc_qdss_traceclkin_clk", 3029 .parent_hws = (const struct clk_hw *[]) { 3030 &qdss_traceclkin_clk_src.clkr.hw 3031 }, 3032 .num_parents = 1, 3033 .flags = CLK_SET_RATE_PARENT, 3034 .ops = &clk_branch2_ops, 3035 }, 3036 }, 3037 }; 3038 3039 static const struct freq_tbl ftbl_qdss_tsctr_clk_src[] = { 3040 F(600000000, P_GPLL4, 2, 0, 0), 3041 { } 3042 }; 3043 3044 static struct clk_rcg2 qdss_tsctr_clk_src = { 3045 .cmd_rcgr = 0x2d01c, 3046 .freq_tbl = ftbl_qdss_tsctr_clk_src, 3047 .hid_width = 5, 3048 .parent_map = gcc_xo_gpll4_gpll0_gpll0_div2_map, 3049 .clkr.hw.init = &(const struct clk_init_data) { 3050 .name = "qdss_tsctr_clk_src", 3051 .parent_data = gcc_xo_gpll4_gpll0_gpll0_div2, 3052 .num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_div2), 3053 .ops = &clk_rcg2_ops, 3054 }, 3055 }; 3056 3057 static struct clk_fixed_factor qdss_tsctr_div2_clk_src = { 3058 .mult = 1, 3059 .div = 2, 3060 .hw.init = &(const struct clk_init_data) { 3061 .name = "qdss_tsctr_div2_clk_src", 3062 .parent_hws = (const struct clk_hw *[]) { 3063 &qdss_tsctr_clk_src.clkr.hw 3064 }, 3065 .num_parents = 1, 3066 .flags = CLK_SET_RATE_PARENT, 3067 .ops = &clk_fixed_factor_ops, 3068 }, 3069 }; 3070 3071 static struct clk_branch gcc_q6_tsctr_1to2_clk = { 3072 .halt_reg = 0x25020, 3073 .clkr = { 3074 .enable_reg = 0x25020, 3075 .enable_mask = BIT(0), 3076 .hw.init = &(const struct clk_init_data) { 3077 .name = "gcc_q6_tsctr_1to2_clk", 3078 .parent_hws = (const struct clk_hw *[]) { 3079 &qdss_tsctr_div2_clk_src.hw 3080 }, 3081 .num_parents = 1, 3082 .flags = CLK_SET_RATE_PARENT, 3083 .ops = &clk_branch2_ops, 3084 }, 3085 }, 3086 }; 3087 3088 static struct clk_branch gcc_wcss_dbg_ifc_nts_clk = { 3089 .halt_reg = 0x25040, 3090 .clkr = { 3091 .enable_reg = 0x25040, 3092 .enable_mask = BIT(0), 3093 .hw.init = &(const struct clk_init_data) { 3094 .name = "gcc_wcss_dbg_ifc_nts_clk", 3095 .parent_hws = (const struct clk_hw *[]) { 3096 &qdss_tsctr_div2_clk_src.hw 3097 }, 3098 .num_parents = 1, 3099 .flags = CLK_SET_RATE_PARENT, 3100 .ops = &clk_branch2_ops, 3101 }, 3102 }, 3103 }; 3104 3105 static struct clk_branch gcc_qdss_tsctr_div2_clk = { 3106 .halt_reg = 0x2d044, 3107 .clkr = { 3108 .enable_reg = 0x2d044, 3109 .enable_mask = BIT(0), 3110 .hw.init = &(const struct clk_init_data) { 3111 .name = "gcc_qdss_tsctr_div2_clk", 3112 .parent_hws = (const struct clk_hw *[]) { 3113 &qdss_tsctr_div2_clk_src.hw 3114 }, 3115 .num_parents = 1, 3116 .flags = CLK_SET_RATE_PARENT, 3117 .ops = &clk_branch2_ops, 3118 }, 3119 }, 3120 }; 3121 3122 static const struct freq_tbl ftbl_uniphy_sys_clk_src[] = { 3123 F(24000000, P_XO, 1, 0, 0), 3124 { } 3125 }; 3126 3127 static struct clk_rcg2 uniphy_sys_clk_src = { 3128 .cmd_rcgr = 0x17090, 3129 .freq_tbl = ftbl_uniphy_sys_clk_src, 3130 .mnd_width = 8, 3131 .hid_width = 5, 3132 .parent_map = gcc_xo_map, 3133 .clkr.hw.init = &(const struct clk_init_data) { 3134 .name = "uniphy_sys_clk_src", 3135 .parent_data = gcc_xo_data, 3136 .num_parents = ARRAY_SIZE(gcc_xo_data), 3137 .ops = &clk_rcg2_ops, 3138 }, 3139 }; 3140 3141 static struct clk_rcg2 nss_ts_clk_src = { 3142 .cmd_rcgr = 0x17088, 3143 .freq_tbl = ftbl_uniphy_sys_clk_src, 3144 .mnd_width = 8, 3145 .hid_width = 5, 3146 .parent_map = gcc_xo_map, 3147 .clkr.hw.init = &(const struct clk_init_data) { 3148 .name = "nss_ts_clk_src", 3149 .parent_data = gcc_xo_data, 3150 .num_parents = ARRAY_SIZE(gcc_xo_data), 3151 .ops = &clk_rcg2_ops, 3152 }, 3153 }; 3154 3155 static struct clk_branch gcc_qdss_ts_clk = { 3156 .halt_reg = 0x2d078, 3157 .clkr = { 3158 .enable_reg = 0x2d078, 3159 .enable_mask = BIT(0), 3160 .hw.init = &(const struct clk_init_data) { 3161 .name = "gcc_qdss_ts_clk", 3162 .parent_hws = (const struct clk_hw *[]) { 3163 &nss_ts_clk_src.clkr.hw 3164 }, 3165 .num_parents = 1, 3166 .flags = CLK_SET_RATE_PARENT, 3167 .ops = &clk_branch2_ops, 3168 }, 3169 }, 3170 }; 3171 3172 static struct clk_fixed_factor qdss_dap_sync_clk_src = { 3173 .mult = 1, 3174 .div = 4, 3175 .hw.init = &(const struct clk_init_data) { 3176 .name = "qdss_dap_sync_clk_src", 3177 .parent_hws = (const struct clk_hw *[]) { 3178 &qdss_tsctr_clk_src.clkr.hw 3179 }, 3180 .num_parents = 1, 3181 .ops = &clk_fixed_factor_ops, 3182 }, 3183 }; 3184 3185 static struct clk_branch gcc_qdss_tsctr_div4_clk = { 3186 .halt_reg = 0x2d04c, 3187 .clkr = { 3188 .enable_reg = 0x2d04c, 3189 .enable_mask = BIT(0), 3190 .hw.init = &(const struct clk_init_data) { 3191 .name = "gcc_qdss_tsctr_div4_clk", 3192 .parent_hws = (const struct clk_hw *[]) { 3193 &qdss_dap_sync_clk_src.hw 3194 }, 3195 .num_parents = 1, 3196 .flags = CLK_SET_RATE_PARENT, 3197 .ops = &clk_branch2_ops, 3198 }, 3199 }, 3200 }; 3201 3202 static struct clk_fixed_factor qdss_tsctr_div8_clk_src = { 3203 .mult = 1, 3204 .div = 8, 3205 .hw.init = &(const struct clk_init_data) { 3206 .name = "qdss_tsctr_div8_clk_src", 3207 .parent_hws = (const struct clk_hw *[]) { 3208 &qdss_tsctr_clk_src.clkr.hw 3209 }, 3210 .num_parents = 1, 3211 .ops = &clk_fixed_factor_ops, 3212 }, 3213 }; 3214 3215 static struct clk_branch gcc_nss_ts_clk = { 3216 .halt_reg = 0x17018, 3217 .clkr = { 3218 .enable_reg = 0x17018, 3219 .enable_mask = BIT(0), 3220 .hw.init = &(const struct clk_init_data) { 3221 .name = "gcc_nss_ts_clk", 3222 .parent_hws = (const struct clk_hw *[]) { 3223 &nss_ts_clk_src.clkr.hw 3224 }, 3225 .num_parents = 1, 3226 .flags = CLK_SET_RATE_PARENT, 3227 .ops = &clk_branch2_ops, 3228 }, 3229 }, 3230 }; 3231 3232 static struct clk_branch gcc_qdss_tsctr_div8_clk = { 3233 .halt_reg = 0x2d050, 3234 .clkr = { 3235 .enable_reg = 0x2d050, 3236 .enable_mask = BIT(0), 3237 .hw.init = &(const struct clk_init_data) { 3238 .name = "gcc_qdss_tsctr_div8_clk", 3239 .parent_hws = (const struct clk_hw *[]) { 3240 &qdss_tsctr_div8_clk_src.hw 3241 }, 3242 .num_parents = 1, 3243 .flags = CLK_SET_RATE_PARENT, 3244 .ops = &clk_branch2_ops, 3245 }, 3246 }, 3247 }; 3248 3249 static struct clk_fixed_factor qdss_tsctr_div16_clk_src = { 3250 .mult = 1, 3251 .div = 16, 3252 .hw.init = &(const struct clk_init_data) { 3253 .name = "qdss_tsctr_div16_clk_src", 3254 .parent_hws = (const struct clk_hw *[]) { 3255 &qdss_tsctr_clk_src.clkr.hw 3256 }, 3257 .num_parents = 1, 3258 .ops = &clk_fixed_factor_ops, 3259 }, 3260 }; 3261 3262 static struct clk_branch gcc_qdss_tsctr_div16_clk = { 3263 .halt_reg = 0x2d054, 3264 .clkr = { 3265 .enable_reg = 0x2d054, 3266 .enable_mask = BIT(0), 3267 .hw.init = &(const struct clk_init_data) { 3268 .name = "gcc_qdss_tsctr_div16_clk", 3269 .parent_hws = (const struct clk_hw *[]) { 3270 &qdss_tsctr_div16_clk_src.hw 3271 }, 3272 .num_parents = 1, 3273 .flags = CLK_SET_RATE_PARENT, 3274 .ops = &clk_branch2_ops, 3275 }, 3276 }, 3277 }; 3278 3279 static struct clk_branch gcc_q6ss_pclkdbg_clk = { 3280 .halt_reg = 0x25024, 3281 .clkr = { 3282 .enable_reg = 0x25024, 3283 .enable_mask = BIT(0), 3284 .hw.init = &(const struct clk_init_data) { 3285 .name = "gcc_q6ss_pclkdbg_clk", 3286 .parent_hws = (const struct clk_hw *[]) { 3287 &qdss_dap_sync_clk_src.hw 3288 }, 3289 .num_parents = 1, 3290 .flags = CLK_SET_RATE_PARENT, 3291 .ops = &clk_branch2_ops, 3292 }, 3293 }, 3294 }; 3295 3296 static struct clk_branch gcc_q6ss_trig_clk = { 3297 .halt_reg = 0x25068, 3298 .clkr = { 3299 .enable_reg = 0x25068, 3300 .enable_mask = BIT(0), 3301 .hw.init = &(const struct clk_init_data) { 3302 .name = "gcc_q6ss_trig_clk", 3303 .parent_hws = (const struct clk_hw *[]) { 3304 &qdss_dap_sync_clk_src.hw 3305 }, 3306 .num_parents = 1, 3307 .flags = CLK_SET_RATE_PARENT, 3308 .ops = &clk_branch2_ops, 3309 }, 3310 }, 3311 }; 3312 3313 static struct clk_branch gcc_wcss_dbg_ifc_apb_clk = { 3314 .halt_reg = 0x25038, 3315 .clkr = { 3316 .enable_reg = 0x25038, 3317 .enable_mask = BIT(0), 3318 .hw.init = &(const struct clk_init_data) { 3319 .name = "gcc_wcss_dbg_ifc_apb_clk", 3320 .parent_hws = (const struct clk_hw *[]) { 3321 &qdss_dap_sync_clk_src.hw 3322 }, 3323 .num_parents = 1, 3324 .flags = CLK_SET_RATE_PARENT, 3325 .ops = &clk_branch2_ops, 3326 }, 3327 }, 3328 }; 3329 3330 static struct clk_branch gcc_wcss_dbg_ifc_dapbus_clk = { 3331 .halt_reg = 0x25044, 3332 .clkr = { 3333 .enable_reg = 0x25044, 3334 .enable_mask = BIT(0), 3335 .hw.init = &(const struct clk_init_data) { 3336 .name = "gcc_wcss_dbg_ifc_dapbus_clk", 3337 .parent_hws = (const struct clk_hw *[]) { 3338 &qdss_dap_sync_clk_src.hw 3339 }, 3340 .num_parents = 1, 3341 .flags = CLK_SET_RATE_PARENT, 3342 .ops = &clk_branch2_ops, 3343 }, 3344 }, 3345 }; 3346 3347 static struct clk_branch gcc_qdss_dap_clk = { 3348 .halt_reg = 0x2d058, 3349 .clkr = { 3350 .enable_reg = 0x2d058, 3351 .enable_mask = BIT(0), 3352 .hw.init = &(const struct clk_init_data) { 3353 .name = "gcc_qdss_dap_clk", 3354 .parent_hws = (const struct clk_hw *[]) { 3355 &qdss_dap_sync_clk_src.hw 3356 }, 3357 .num_parents = 1, 3358 .flags = CLK_SET_RATE_PARENT, 3359 .ops = &clk_branch2_ops, 3360 }, 3361 }, 3362 }; 3363 3364 static struct clk_branch gcc_qdss_apb2jtag_clk = { 3365 .halt_reg = 0x2d05c, 3366 .clkr = { 3367 .enable_reg = 0x2d05c, 3368 .enable_mask = BIT(0), 3369 .hw.init = &(const struct clk_init_data) { 3370 .name = "gcc_qdss_apb2jtag_clk", 3371 .parent_hws = (const struct clk_hw *[]) { 3372 &qdss_dap_sync_clk_src.hw 3373 }, 3374 .num_parents = 1, 3375 .flags = CLK_SET_RATE_PARENT, 3376 .ops = &clk_branch2_ops, 3377 }, 3378 }, 3379 }; 3380 3381 static struct clk_fixed_factor qdss_tsctr_div3_clk_src = { 3382 .mult = 1, 3383 .div = 3, 3384 .hw.init = &(const struct clk_init_data) { 3385 .name = "qdss_tsctr_div3_clk_src", 3386 .parent_hws = (const struct clk_hw *[]) { 3387 &qdss_tsctr_clk_src.clkr.hw 3388 }, 3389 .num_parents = 1, 3390 .ops = &clk_fixed_factor_ops, 3391 }, 3392 }; 3393 3394 static struct clk_branch gcc_qdss_tsctr_div3_clk = { 3395 .halt_reg = 0x2d048, 3396 .clkr = { 3397 .enable_reg = 0x2d048, 3398 .enable_mask = BIT(0), 3399 .hw.init = &(const struct clk_init_data) { 3400 .name = "gcc_qdss_tsctr_div3_clk", 3401 .parent_hws = (const struct clk_hw *[]) { 3402 &qdss_tsctr_div3_clk_src.hw 3403 }, 3404 .num_parents = 1, 3405 .flags = CLK_SET_RATE_PARENT, 3406 .ops = &clk_branch2_ops, 3407 }, 3408 }, 3409 }; 3410 3411 static const struct freq_tbl ftbl_qpic_io_macro_clk_src[] = { 3412 F(24000000, P_XO, 1, 0, 0), 3413 F(100000000, P_GPLL0, 8, 0, 0), 3414 F(200000000, P_GPLL0, 4, 0, 0), 3415 F(320000000, P_GPLL0, 2.5, 0, 0), 3416 F(400000000, P_GPLL0, 2, 0, 0), 3417 { } 3418 }; 3419 3420 static struct clk_rcg2 qpic_io_macro_clk_src = { 3421 .cmd_rcgr = 0x32004, 3422 .freq_tbl = ftbl_qpic_io_macro_clk_src, 3423 .hid_width = 5, 3424 .parent_map = gcc_xo_gpll0_gpll2_map, 3425 .clkr.hw.init = &(const struct clk_init_data) { 3426 .name = "qpic_io_macro_clk_src", 3427 .parent_data = gcc_xo_gpll0_gpll2, 3428 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2), 3429 .ops = &clk_rcg2_ops, 3430 }, 3431 }; 3432 3433 static struct clk_branch gcc_qpic_io_macro_clk = { 3434 .halt_reg = 0x3200c, 3435 .clkr = { 3436 .enable_reg = 0x3200c, 3437 .enable_mask = BIT(0), 3438 .hw.init = &(const struct clk_init_data){ 3439 .name = "gcc_qpic_io_macro_clk", 3440 .parent_hws = (const struct clk_hw *[]){ 3441 &qpic_io_macro_clk_src.clkr.hw 3442 }, 3443 .num_parents = 1, 3444 .flags = CLK_SET_RATE_PARENT, 3445 .ops = &clk_branch2_ops, 3446 }, 3447 }, 3448 }; 3449 3450 static const struct freq_tbl ftbl_q6_axi_clk_src[] = { 3451 F(533333333, P_GPLL0, 1.5, 0, 0), 3452 { } 3453 }; 3454 3455 static struct clk_rcg2 q6_axi_clk_src = { 3456 .cmd_rcgr = 0x25004, 3457 .freq_tbl = ftbl_q6_axi_clk_src, 3458 .hid_width = 5, 3459 .parent_map = gcc_xo_gpll0_gpll2_gpll4_pi_sleep_map, 3460 .clkr.hw.init = &(const struct clk_init_data) { 3461 .name = "q6_axi_clk_src", 3462 .parent_data = gcc_xo_gpll0_gpll2_gpll4_pi_sleep, 3463 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll4_pi_sleep), 3464 .ops = &clk_rcg2_ops, 3465 }, 3466 }; 3467 3468 static struct clk_branch gcc_q6_axim_clk = { 3469 .halt_reg = 0x2500c, 3470 .clkr = { 3471 .enable_reg = 0x2500c, 3472 .enable_mask = BIT(0), 3473 .hw.init = &(const struct clk_init_data) { 3474 .name = "gcc_q6_axim_clk", 3475 .parent_hws = (const struct clk_hw *[]) { 3476 &q6_axi_clk_src.clkr.hw 3477 }, 3478 .num_parents = 1, 3479 .flags = CLK_SET_RATE_PARENT, 3480 .ops = &clk_branch2_ops, 3481 }, 3482 }, 3483 }; 3484 3485 static struct clk_branch gcc_wcss_q6_tbu_clk = { 3486 .halt_reg = 0x12050, 3487 .halt_check = BRANCH_HALT_DELAY, 3488 .clkr = { 3489 .enable_reg = 0xb00c, 3490 .enable_mask = BIT(6), 3491 .hw.init = &(const struct clk_init_data) { 3492 .name = "gcc_wcss_q6_tbu_clk", 3493 .parent_hws = (const struct clk_hw *[]) { 3494 &q6_axi_clk_src.clkr.hw 3495 }, 3496 .num_parents = 1, 3497 .flags = CLK_SET_RATE_PARENT, 3498 .ops = &clk_branch2_ops, 3499 }, 3500 }, 3501 }; 3502 3503 static struct clk_branch gcc_mem_noc_q6_axi_clk = { 3504 .halt_reg = 0x19010, 3505 .clkr = { 3506 .enable_reg = 0x19010, 3507 .enable_mask = BIT(0), 3508 .hw.init = &(const struct clk_init_data) { 3509 .name = "gcc_mem_noc_q6_axi_clk", 3510 .parent_hws = (const struct clk_hw *[]) { 3511 &q6_axi_clk_src.clkr.hw 3512 }, 3513 .num_parents = 1, 3514 .flags = CLK_SET_RATE_PARENT, 3515 .ops = &clk_branch2_ops, 3516 }, 3517 }, 3518 }; 3519 3520 static const struct freq_tbl ftbl_q6_axim2_clk_src[] = { 3521 F(342857143, P_GPLL4, 3.5, 0, 0), 3522 { } 3523 }; 3524 3525 static const struct parent_map gcc_xo_gpll0_gpll4_bias_pll_ubinc_clk_map[] = { 3526 { P_XO, 0 }, 3527 { P_GPLL0, 1 }, 3528 { P_GPLL4, 2 }, 3529 { P_BIAS_PLL_UBI_NC_CLK, 4 }, 3530 }; 3531 3532 static struct clk_rcg2 q6_axim2_clk_src = { 3533 .cmd_rcgr = 0x25028, 3534 .freq_tbl = ftbl_q6_axim2_clk_src, 3535 .hid_width = 5, 3536 .parent_map = gcc_xo_gpll0_gpll4_bias_pll_ubinc_clk_map, 3537 .clkr.hw.init = &(const struct clk_init_data) { 3538 .name = "q6_axim2_clk_src", 3539 .parent_data = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk, 3540 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk), 3541 .ops = &clk_rcg2_ops, 3542 }, 3543 }; 3544 3545 static const struct freq_tbl ftbl_nssnoc_memnoc_bfdcd_clk_src[] = { 3546 F(533333333, P_GPLL0, 1.5, 0, 0), 3547 { } 3548 }; 3549 3550 static struct clk_rcg2 nssnoc_memnoc_bfdcd_clk_src = { 3551 .cmd_rcgr = 0x17004, 3552 .freq_tbl = ftbl_nssnoc_memnoc_bfdcd_clk_src, 3553 .hid_width = 5, 3554 .parent_map = gcc_xo_gpll0_gpll0_aux_gpll2_map, 3555 .clkr.hw.init = &(const struct clk_init_data) { 3556 .name = "nssnoc_memnoc_bfdcd_clk_src", 3557 .parent_data = gcc_xo_gpll0_gpll0_aux_gpll2, 3558 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_aux_gpll2), 3559 .ops = &clk_rcg2_ops, 3560 }, 3561 }; 3562 3563 static struct clk_branch gcc_nssnoc_memnoc_clk = { 3564 .halt_reg = 0x17024, 3565 .clkr = { 3566 .enable_reg = 0x17024, 3567 .enable_mask = BIT(0), 3568 .hw.init = &(const struct clk_init_data) { 3569 .name = "gcc_nssnoc_memnoc_clk", 3570 .parent_hws = (const struct clk_hw *[]) { 3571 &nssnoc_memnoc_bfdcd_clk_src.clkr.hw 3572 }, 3573 .num_parents = 1, 3574 .flags = CLK_SET_RATE_PARENT, 3575 .ops = &clk_branch2_ops, 3576 }, 3577 }, 3578 }; 3579 3580 static struct clk_branch gcc_nssnoc_mem_noc_1_clk = { 3581 .halt_reg = 0x17084, 3582 .clkr = { 3583 .enable_reg = 0x17084, 3584 .enable_mask = BIT(0), 3585 .hw.init = &(const struct clk_init_data) { 3586 .name = "gcc_nssnoc_mem_noc_1_clk", 3587 .parent_hws = (const struct clk_hw *[]) { 3588 &nssnoc_memnoc_bfdcd_clk_src.clkr.hw 3589 }, 3590 .num_parents = 1, 3591 .flags = CLK_SET_RATE_PARENT, 3592 .ops = &clk_branch2_ops, 3593 }, 3594 }, 3595 }; 3596 3597 static struct clk_branch gcc_nss_tbu_clk = { 3598 .halt_reg = 0x12040, 3599 .clkr = { 3600 .enable_reg = 0xb00c, 3601 .enable_mask = BIT(4), 3602 .hw.init = &(const struct clk_init_data) { 3603 .name = "gcc_nss_tbu_clk", 3604 .parent_hws = (const struct clk_hw *[]) { 3605 &nssnoc_memnoc_bfdcd_clk_src.clkr.hw 3606 }, 3607 .num_parents = 1, 3608 .flags = CLK_SET_RATE_PARENT, 3609 .ops = &clk_branch2_ops, 3610 }, 3611 }, 3612 }; 3613 3614 static struct clk_branch gcc_mem_noc_nssnoc_clk = { 3615 .halt_reg = 0x19014, 3616 .clkr = { 3617 .enable_reg = 0x19014, 3618 .enable_mask = BIT(0), 3619 .hw.init = &(const struct clk_init_data) { 3620 .name = "gcc_mem_noc_nssnoc_clk", 3621 .parent_hws = (const struct clk_hw *[]) { 3622 &nssnoc_memnoc_bfdcd_clk_src.clkr.hw 3623 }, 3624 .num_parents = 1, 3625 .flags = CLK_SET_RATE_PARENT, 3626 .ops = &clk_branch2_ops, 3627 }, 3628 }, 3629 }; 3630 3631 static const struct freq_tbl ftbl_lpass_axim_clk_src[] = { 3632 F(133333333, P_GPLL0, 6, 0, 0), 3633 { } 3634 }; 3635 3636 static struct clk_rcg2 lpass_axim_clk_src = { 3637 .cmd_rcgr = 0x2700c, 3638 .freq_tbl = ftbl_lpass_axim_clk_src, 3639 .hid_width = 5, 3640 .parent_map = gcc_xo_gpll0_map, 3641 .clkr.hw.init = &(const struct clk_init_data) { 3642 .name = "lpass_axim_clk_src", 3643 .parent_data = gcc_xo_gpll0, 3644 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 3645 .ops = &clk_rcg2_ops, 3646 }, 3647 }; 3648 3649 static struct clk_rcg2 lpass_sway_clk_src = { 3650 .cmd_rcgr = 0x27004, 3651 .freq_tbl = ftbl_lpass_axim_clk_src, 3652 .hid_width = 5, 3653 .parent_map = gcc_xo_gpll0_map, 3654 .clkr.hw.init = &(const struct clk_init_data) { 3655 .name = "lpass_sway_clk_src", 3656 .parent_data = gcc_xo_gpll0, 3657 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 3658 .ops = &clk_rcg2_ops, 3659 }, 3660 }; 3661 3662 static const struct freq_tbl ftbl_adss_pwm_clk_src[] = { 3663 F(24000000, P_XO, 1, 0, 0), 3664 F(100000000, P_GPLL0, 8, 0, 0), 3665 { } 3666 }; 3667 3668 static struct clk_rcg2 adss_pwm_clk_src = { 3669 .cmd_rcgr = 0x1c004, 3670 .freq_tbl = ftbl_adss_pwm_clk_src, 3671 .hid_width = 5, 3672 .parent_map = gcc_xo_gpll0_map, 3673 .clkr.hw.init = &(const struct clk_init_data) { 3674 .name = "adss_pwm_clk_src", 3675 .parent_data = gcc_xo_gpll0, 3676 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 3677 .ops = &clk_rcg2_ops, 3678 }, 3679 }; 3680 3681 static struct clk_branch gcc_adss_pwm_clk = { 3682 .halt_reg = 0x1c00c, 3683 .clkr = { 3684 .enable_reg = 0x1c00c, 3685 .enable_mask = BIT(0), 3686 .hw.init = &(const struct clk_init_data) { 3687 .name = "gcc_adss_pwm_clk", 3688 .parent_hws = (const struct clk_hw *[]) { 3689 &adss_pwm_clk_src.clkr.hw 3690 }, 3691 .num_parents = 1, 3692 .flags = CLK_SET_RATE_PARENT, 3693 .ops = &clk_branch2_ops, 3694 }, 3695 }, 3696 }; 3697 3698 static const struct freq_tbl ftbl_gp1_clk_src[] = { 3699 F(24000000, P_XO, 1, 0, 0), 3700 F(200000000, P_GPLL0, 4, 0, 0), 3701 { } 3702 }; 3703 3704 static struct clk_rcg2 gp1_clk_src = { 3705 .cmd_rcgr = 0x8004, 3706 .freq_tbl = ftbl_gp1_clk_src, 3707 .hid_width = 5, 3708 .parent_map = gcc_xo_gpll0_gpll0_sleep_clk_map, 3709 .clkr.hw.init = &(const struct clk_init_data) { 3710 .name = "gp1_clk_src", 3711 .parent_data = gcc_xo_gpll0_gpll0_sleep_clk, 3712 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_sleep_clk), 3713 .ops = &clk_rcg2_ops, 3714 }, 3715 }; 3716 3717 static struct clk_rcg2 gp2_clk_src = { 3718 .cmd_rcgr = 0x9004, 3719 .freq_tbl = ftbl_gp1_clk_src, 3720 .hid_width = 5, 3721 .parent_map = gcc_xo_gpll0_gpll0_sleep_clk_map, 3722 .clkr.hw.init = &(const struct clk_init_data) { 3723 .name = "gp2_clk_src", 3724 .parent_data = gcc_xo_gpll0_gpll0_sleep_clk, 3725 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_sleep_clk), 3726 .ops = &clk_rcg2_ops, 3727 }, 3728 }; 3729 3730 static struct clk_rcg2 gp3_clk_src = { 3731 .cmd_rcgr = 0xa004, 3732 .freq_tbl = ftbl_gp1_clk_src, 3733 .hid_width = 5, 3734 .parent_map = gcc_xo_gpll0_gpll0_sleep_clk_map, 3735 .clkr.hw.init = &(const struct clk_init_data) { 3736 .name = "gp3_clk_src", 3737 .parent_data = gcc_xo_gpll0_gpll0_sleep_clk, 3738 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_sleep_clk), 3739 .ops = &clk_rcg2_ops, 3740 }, 3741 }; 3742 3743 static struct clk_branch gcc_xo_clk_src = { 3744 .halt_reg = 0x34004, 3745 .clkr = { 3746 .enable_reg = 0x34004, 3747 .enable_mask = BIT(1), 3748 .hw.init = &(const struct clk_init_data) { 3749 .name = "gcc_xo_clk_src", 3750 .parent_data = gcc_xo_data, 3751 .num_parents = ARRAY_SIZE(gcc_xo_data), 3752 .flags = CLK_SET_RATE_PARENT, 3753 .ops = &clk_branch2_ops, 3754 }, 3755 }, 3756 }; 3757 3758 static struct clk_branch gcc_nssnoc_xo_dcd_clk = { 3759 .halt_reg = 0x17074, 3760 .clkr = { 3761 .enable_reg = 0x17074, 3762 .enable_mask = BIT(0), 3763 .hw.init = &(const struct clk_init_data) { 3764 .name = "gcc_nssnoc_xo_dcd_clk", 3765 .parent_hws = (const struct clk_hw *[]) { 3766 &gcc_xo_clk_src.clkr.hw 3767 }, 3768 .num_parents = 1, 3769 .flags = CLK_SET_RATE_PARENT, 3770 .ops = &clk_branch2_ops, 3771 }, 3772 }, 3773 }; 3774 3775 static struct clk_branch gcc_xo_clk = { 3776 .halt_reg = 0x34018, 3777 .clkr = { 3778 .enable_reg = 0x34018, 3779 .enable_mask = BIT(0), 3780 .hw.init = &(const struct clk_init_data) { 3781 .name = "gcc_xo_clk", 3782 .parent_hws = (const struct clk_hw *[]) { 3783 &gcc_xo_clk_src.clkr.hw 3784 }, 3785 .num_parents = 1, 3786 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 3787 .ops = &clk_branch2_ops, 3788 }, 3789 }, 3790 }; 3791 3792 static struct clk_branch gcc_uniphy0_sys_clk = { 3793 .halt_reg = 0x17048, 3794 .clkr = { 3795 .enable_reg = 0x17048, 3796 .enable_mask = BIT(0), 3797 .hw.init = &(const struct clk_init_data) { 3798 .name = "gcc_uniphy0_sys_clk", 3799 .parent_hws = (const struct clk_hw *[]) { 3800 &uniphy_sys_clk_src.clkr.hw 3801 }, 3802 .num_parents = 1, 3803 .flags = CLK_SET_RATE_PARENT, 3804 .ops = &clk_branch2_ops, 3805 }, 3806 }, 3807 }; 3808 3809 static struct clk_branch gcc_uniphy1_sys_clk = { 3810 .halt_reg = 0x17058, 3811 .clkr = { 3812 .enable_reg = 0x17058, 3813 .enable_mask = BIT(0), 3814 .hw.init = &(const struct clk_init_data) { 3815 .name = "gcc_uniphy1_sys_clk", 3816 .parent_hws = (const struct clk_hw *[]) { 3817 &uniphy_sys_clk_src.clkr.hw 3818 }, 3819 .num_parents = 1, 3820 .flags = CLK_SET_RATE_PARENT, 3821 .ops = &clk_branch2_ops, 3822 }, 3823 }, 3824 }; 3825 3826 static struct clk_branch gcc_uniphy2_sys_clk = { 3827 .halt_reg = 0x17068, 3828 .clkr = { 3829 .enable_reg = 0x17068, 3830 .enable_mask = BIT(0), 3831 .hw.init = &(const struct clk_init_data) { 3832 .name = "gcc_uniphy2_sys_clk", 3833 .parent_hws = (const struct clk_hw *[]) { 3834 &uniphy_sys_clk_src.clkr.hw 3835 }, 3836 .num_parents = 1, 3837 .flags = CLK_SET_RATE_PARENT, 3838 .ops = &clk_branch2_ops, 3839 }, 3840 }, 3841 }; 3842 3843 static struct clk_branch gcc_cmn_12gpll_sys_clk = { 3844 .halt_reg = 0x3a008, 3845 .clkr = { 3846 .enable_reg = 0x3a008, 3847 .enable_mask = BIT(0), 3848 .hw.init = &(const struct clk_init_data) { 3849 .name = "gcc_cmn_12gpll_sys_clk", 3850 .parent_hws = (const struct clk_hw *[]) { 3851 &uniphy_sys_clk_src.clkr.hw 3852 }, 3853 .num_parents = 1, 3854 .flags = CLK_SET_RATE_PARENT, 3855 .ops = &clk_branch2_ops, 3856 }, 3857 }, 3858 }; 3859 3860 static struct clk_fixed_factor gcc_xo_div4_clk_src = { 3861 .mult = 1, 3862 .div = 4, 3863 .hw.init = &(const struct clk_init_data) { 3864 .name = "gcc_xo_div4_clk_src", 3865 .parent_hws = (const struct clk_hw *[]) { 3866 &gcc_xo_clk_src.clkr.hw 3867 }, 3868 .num_parents = 1, 3869 .flags = CLK_SET_RATE_PARENT, 3870 .ops = &clk_fixed_factor_ops, 3871 }, 3872 }; 3873 3874 static struct clk_branch gcc_nssnoc_qosgen_ref_clk = { 3875 .halt_reg = 0x1701c, 3876 .clkr = { 3877 .enable_reg = 0x1701c, 3878 .enable_mask = BIT(0), 3879 .hw.init = &(const struct clk_init_data) { 3880 .name = "gcc_nssnoc_qosgen_ref_clk", 3881 .parent_hws = (const struct clk_hw *[]) { 3882 &gcc_xo_div4_clk_src.hw 3883 }, 3884 .num_parents = 1, 3885 .flags = CLK_SET_RATE_PARENT, 3886 .ops = &clk_branch2_ops, 3887 }, 3888 }, 3889 }; 3890 3891 static struct clk_branch gcc_nssnoc_timeout_ref_clk = { 3892 .halt_reg = 0x17020, 3893 .clkr = { 3894 .enable_reg = 0x17020, 3895 .enable_mask = BIT(0), 3896 .hw.init = &(const struct clk_init_data) { 3897 .name = "gcc_nssnoc_timeout_ref_clk", 3898 .parent_hws = (const struct clk_hw *[]) { 3899 &gcc_xo_div4_clk_src.hw 3900 }, 3901 .num_parents = 1, 3902 .flags = CLK_SET_RATE_PARENT, 3903 .ops = &clk_branch2_ops, 3904 }, 3905 }, 3906 }; 3907 3908 static struct clk_branch gcc_xo_div4_clk = { 3909 .halt_reg = 0x3401c, 3910 .clkr = { 3911 .enable_reg = 0x3401c, 3912 .enable_mask = BIT(0), 3913 .hw.init = &(const struct clk_init_data) { 3914 .name = "gcc_xo_div4_clk", 3915 .parent_hws = (const struct clk_hw *[]) { 3916 &gcc_xo_div4_clk_src.hw 3917 }, 3918 .num_parents = 1, 3919 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 3920 .ops = &clk_branch2_ops, 3921 }, 3922 }, 3923 }; 3924 3925 static struct clk_hw *gcc_ipq9574_hws[] = { 3926 &gpll0_out_main_div2.hw, 3927 &gcc_xo_div4_clk_src.hw, 3928 &qdss_dap_sync_clk_src.hw, 3929 &qdss_tsctr_div2_clk_src.hw, 3930 &qdss_tsctr_div8_clk_src.hw, 3931 &qdss_tsctr_div16_clk_src.hw, 3932 &qdss_tsctr_div3_clk_src.hw, 3933 &gcc_eud_at_div_clk_src.hw, 3934 }; 3935 3936 static struct clk_regmap *gcc_ipq9574_clks[] = { 3937 [GPLL0_MAIN] = &gpll0_main.clkr, 3938 [GPLL0] = &gpll0.clkr, 3939 [GPLL4_MAIN] = &gpll4_main.clkr, 3940 [GPLL4] = &gpll4.clkr, 3941 [GPLL2_MAIN] = &gpll2_main.clkr, 3942 [GPLL2] = &gpll2.clkr, 3943 [GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr, 3944 [APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr, 3945 [APSS_AXI_CLK_SRC] = &apss_axi_clk_src.clkr, 3946 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr, 3947 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr, 3948 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr, 3949 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr, 3950 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr, 3951 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr, 3952 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr, 3953 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr, 3954 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr, 3955 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr, 3956 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr, 3957 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr, 3958 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr, 3959 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr, 3960 [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr, 3961 [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr, 3962 [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr, 3963 [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr, 3964 [GCC_APSS_AHB_CLK] = &gcc_apss_ahb_clk.clkr, 3965 [GCC_APSS_AXI_CLK] = &gcc_apss_axi_clk.clkr, 3966 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr, 3967 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr, 3968 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr, 3969 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr, 3970 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr, 3971 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr, 3972 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr, 3973 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr, 3974 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr, 3975 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr, 3976 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr, 3977 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr, 3978 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, 3979 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr, 3980 [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr, 3981 [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr, 3982 [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr, 3983 [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr, 3984 [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr, 3985 [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr, 3986 [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr, 3987 [GCC_CRYPTO_CLK_SRC] = &gcc_crypto_clk_src.clkr, 3988 [PCIE0_AXI_M_CLK_SRC] = &pcie0_axi_m_clk_src.clkr, 3989 [GCC_PCIE0_AXI_M_CLK] = &gcc_pcie0_axi_m_clk.clkr, 3990 [PCIE1_AXI_M_CLK_SRC] = &pcie1_axi_m_clk_src.clkr, 3991 [GCC_PCIE1_AXI_M_CLK] = &gcc_pcie1_axi_m_clk.clkr, 3992 [PCIE2_AXI_M_CLK_SRC] = &pcie2_axi_m_clk_src.clkr, 3993 [GCC_PCIE2_AXI_M_CLK] = &gcc_pcie2_axi_m_clk.clkr, 3994 [PCIE3_AXI_M_CLK_SRC] = &pcie3_axi_m_clk_src.clkr, 3995 [GCC_PCIE3_AXI_M_CLK] = &gcc_pcie3_axi_m_clk.clkr, 3996 [PCIE0_AXI_S_CLK_SRC] = &pcie0_axi_s_clk_src.clkr, 3997 [GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr, 3998 [GCC_PCIE0_AXI_S_CLK] = &gcc_pcie0_axi_s_clk.clkr, 3999 [PCIE1_AXI_S_CLK_SRC] = &pcie1_axi_s_clk_src.clkr, 4000 [GCC_PCIE1_AXI_S_BRIDGE_CLK] = &gcc_pcie1_axi_s_bridge_clk.clkr, 4001 [GCC_PCIE1_AXI_S_CLK] = &gcc_pcie1_axi_s_clk.clkr, 4002 [PCIE2_AXI_S_CLK_SRC] = &pcie2_axi_s_clk_src.clkr, 4003 [GCC_PCIE2_AXI_S_BRIDGE_CLK] = &gcc_pcie2_axi_s_bridge_clk.clkr, 4004 [GCC_PCIE2_AXI_S_CLK] = &gcc_pcie2_axi_s_clk.clkr, 4005 [PCIE3_AXI_S_CLK_SRC] = &pcie3_axi_s_clk_src.clkr, 4006 [GCC_PCIE3_AXI_S_BRIDGE_CLK] = &gcc_pcie3_axi_s_bridge_clk.clkr, 4007 [GCC_PCIE3_AXI_S_CLK] = &gcc_pcie3_axi_s_clk.clkr, 4008 [PCIE0_PIPE_CLK_SRC] = &pcie0_pipe_clk_src.clkr, 4009 [PCIE1_PIPE_CLK_SRC] = &pcie1_pipe_clk_src.clkr, 4010 [PCIE2_PIPE_CLK_SRC] = &pcie2_pipe_clk_src.clkr, 4011 [PCIE3_PIPE_CLK_SRC] = &pcie3_pipe_clk_src.clkr, 4012 [PCIE_AUX_CLK_SRC] = &pcie_aux_clk_src.clkr, 4013 [GCC_PCIE0_AUX_CLK] = &gcc_pcie0_aux_clk.clkr, 4014 [GCC_PCIE1_AUX_CLK] = &gcc_pcie1_aux_clk.clkr, 4015 [GCC_PCIE2_AUX_CLK] = &gcc_pcie2_aux_clk.clkr, 4016 [GCC_PCIE3_AUX_CLK] = &gcc_pcie3_aux_clk.clkr, 4017 [PCIE0_RCHNG_CLK_SRC] = &pcie0_rchng_clk_src.clkr, 4018 [GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr, 4019 [PCIE1_RCHNG_CLK_SRC] = &pcie1_rchng_clk_src.clkr, 4020 [GCC_PCIE1_RCHNG_CLK] = &gcc_pcie1_rchng_clk.clkr, 4021 [PCIE2_RCHNG_CLK_SRC] = &pcie2_rchng_clk_src.clkr, 4022 [GCC_PCIE2_RCHNG_CLK] = &gcc_pcie2_rchng_clk.clkr, 4023 [PCIE3_RCHNG_CLK_SRC] = &pcie3_rchng_clk_src.clkr, 4024 [GCC_PCIE3_RCHNG_CLK] = &gcc_pcie3_rchng_clk.clkr, 4025 [GCC_PCIE0_AHB_CLK] = &gcc_pcie0_ahb_clk.clkr, 4026 [GCC_PCIE1_AHB_CLK] = &gcc_pcie1_ahb_clk.clkr, 4027 [GCC_PCIE2_AHB_CLK] = &gcc_pcie2_ahb_clk.clkr, 4028 [GCC_PCIE3_AHB_CLK] = &gcc_pcie3_ahb_clk.clkr, 4029 [USB0_AUX_CLK_SRC] = &usb0_aux_clk_src.clkr, 4030 [GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr, 4031 [USB0_MASTER_CLK_SRC] = &usb0_master_clk_src.clkr, 4032 [GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr, 4033 [GCC_SNOC_USB_CLK] = &gcc_snoc_usb_clk.clkr, 4034 [GCC_ANOC_USB_AXI_CLK] = &gcc_anoc_usb_axi_clk.clkr, 4035 [USB0_MOCK_UTMI_CLK_SRC] = &usb0_mock_utmi_clk_src.clkr, 4036 [USB0_MOCK_UTMI_DIV_CLK_SRC] = &usb0_mock_utmi_div_clk_src.clkr, 4037 [GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr, 4038 [USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr, 4039 [GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr, 4040 [GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr, 4041 [GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr, 4042 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr, 4043 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, 4044 [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr, 4045 [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr, 4046 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, 4047 [PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr, 4048 [GCC_NSSCFG_CLK] = &gcc_nsscfg_clk.clkr, 4049 [GCC_NSSNOC_NSSCC_CLK] = &gcc_nssnoc_nsscc_clk.clkr, 4050 [GCC_NSSCC_CLK] = &gcc_nsscc_clk.clkr, 4051 [GCC_NSSNOC_PCNOC_1_CLK] = &gcc_nssnoc_pcnoc_1_clk.clkr, 4052 [GCC_QDSS_DAP_AHB_CLK] = &gcc_qdss_dap_ahb_clk.clkr, 4053 [GCC_QDSS_CFG_AHB_CLK] = &gcc_qdss_cfg_ahb_clk.clkr, 4054 [GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr, 4055 [GCC_QPIC_CLK] = &gcc_qpic_clk.clkr, 4056 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr, 4057 [GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr, 4058 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, 4059 [GCC_UNIPHY0_AHB_CLK] = &gcc_uniphy0_ahb_clk.clkr, 4060 [GCC_UNIPHY1_AHB_CLK] = &gcc_uniphy1_ahb_clk.clkr, 4061 [GCC_UNIPHY2_AHB_CLK] = &gcc_uniphy2_ahb_clk.clkr, 4062 [GCC_CMN_12GPLL_AHB_CLK] = &gcc_cmn_12gpll_ahb_clk.clkr, 4063 [GCC_CMN_12GPLL_APU_CLK] = &gcc_cmn_12gpll_apu_clk.clkr, 4064 [SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr, 4065 [GCC_NSSNOC_SNOC_CLK] = &gcc_nssnoc_snoc_clk.clkr, 4066 [GCC_NSSNOC_SNOC_1_CLK] = &gcc_nssnoc_snoc_1_clk.clkr, 4067 [GCC_QDSS_ETR_USB_CLK] = &gcc_qdss_etr_usb_clk.clkr, 4068 [WCSS_AHB_CLK_SRC] = &wcss_ahb_clk_src.clkr, 4069 [GCC_Q6_AHB_CLK] = &gcc_q6_ahb_clk.clkr, 4070 [GCC_Q6_AHB_S_CLK] = &gcc_q6_ahb_s_clk.clkr, 4071 [GCC_WCSS_ECAHB_CLK] = &gcc_wcss_ecahb_clk.clkr, 4072 [GCC_WCSS_ACMT_CLK] = &gcc_wcss_acmt_clk.clkr, 4073 [GCC_SYS_NOC_WCSS_AHB_CLK] = &gcc_sys_noc_wcss_ahb_clk.clkr, 4074 [WCSS_AXI_M_CLK_SRC] = &wcss_axi_m_clk_src.clkr, 4075 [GCC_ANOC_WCSS_AXI_M_CLK] = &gcc_anoc_wcss_axi_m_clk.clkr, 4076 [QDSS_AT_CLK_SRC] = &qdss_at_clk_src.clkr, 4077 [GCC_Q6SS_ATBM_CLK] = &gcc_q6ss_atbm_clk.clkr, 4078 [GCC_WCSS_DBG_IFC_ATB_CLK] = &gcc_wcss_dbg_ifc_atb_clk.clkr, 4079 [GCC_NSSNOC_ATB_CLK] = &gcc_nssnoc_atb_clk.clkr, 4080 [GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr, 4081 [GCC_SYS_NOC_AT_CLK] = &gcc_sys_noc_at_clk.clkr, 4082 [GCC_PCNOC_AT_CLK] = &gcc_pcnoc_at_clk.clkr, 4083 [GCC_USB0_EUD_AT_CLK] = &gcc_usb0_eud_at_clk.clkr, 4084 [GCC_QDSS_EUD_AT_CLK] = &gcc_qdss_eud_at_clk.clkr, 4085 [QDSS_STM_CLK_SRC] = &qdss_stm_clk_src.clkr, 4086 [GCC_QDSS_STM_CLK] = &gcc_qdss_stm_clk.clkr, 4087 [GCC_SYS_NOC_QDSS_STM_AXI_CLK] = &gcc_sys_noc_qdss_stm_axi_clk.clkr, 4088 [QDSS_TRACECLKIN_CLK_SRC] = &qdss_traceclkin_clk_src.clkr, 4089 [GCC_QDSS_TRACECLKIN_CLK] = &gcc_qdss_traceclkin_clk.clkr, 4090 [QDSS_TSCTR_CLK_SRC] = &qdss_tsctr_clk_src.clkr, 4091 [GCC_Q6_TSCTR_1TO2_CLK] = &gcc_q6_tsctr_1to2_clk.clkr, 4092 [GCC_WCSS_DBG_IFC_NTS_CLK] = &gcc_wcss_dbg_ifc_nts_clk.clkr, 4093 [GCC_QDSS_TSCTR_DIV2_CLK] = &gcc_qdss_tsctr_div2_clk.clkr, 4094 [GCC_QDSS_TS_CLK] = &gcc_qdss_ts_clk.clkr, 4095 [GCC_QDSS_TSCTR_DIV4_CLK] = &gcc_qdss_tsctr_div4_clk.clkr, 4096 [GCC_NSS_TS_CLK] = &gcc_nss_ts_clk.clkr, 4097 [GCC_QDSS_TSCTR_DIV8_CLK] = &gcc_qdss_tsctr_div8_clk.clkr, 4098 [GCC_QDSS_TSCTR_DIV16_CLK] = &gcc_qdss_tsctr_div16_clk.clkr, 4099 [GCC_Q6SS_PCLKDBG_CLK] = &gcc_q6ss_pclkdbg_clk.clkr, 4100 [GCC_Q6SS_TRIG_CLK] = &gcc_q6ss_trig_clk.clkr, 4101 [GCC_WCSS_DBG_IFC_APB_CLK] = &gcc_wcss_dbg_ifc_apb_clk.clkr, 4102 [GCC_WCSS_DBG_IFC_DAPBUS_CLK] = &gcc_wcss_dbg_ifc_dapbus_clk.clkr, 4103 [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr, 4104 [GCC_QDSS_APB2JTAG_CLK] = &gcc_qdss_apb2jtag_clk.clkr, 4105 [GCC_QDSS_TSCTR_DIV3_CLK] = &gcc_qdss_tsctr_div3_clk.clkr, 4106 [QPIC_IO_MACRO_CLK_SRC] = &qpic_io_macro_clk_src.clkr, 4107 [GCC_QPIC_IO_MACRO_CLK] = &gcc_qpic_io_macro_clk.clkr, 4108 [Q6_AXI_CLK_SRC] = &q6_axi_clk_src.clkr, 4109 [GCC_Q6_AXIM_CLK] = &gcc_q6_axim_clk.clkr, 4110 [GCC_WCSS_Q6_TBU_CLK] = &gcc_wcss_q6_tbu_clk.clkr, 4111 [GCC_MEM_NOC_Q6_AXI_CLK] = &gcc_mem_noc_q6_axi_clk.clkr, 4112 [Q6_AXIM2_CLK_SRC] = &q6_axim2_clk_src.clkr, 4113 [NSSNOC_MEMNOC_BFDCD_CLK_SRC] = &nssnoc_memnoc_bfdcd_clk_src.clkr, 4114 [GCC_NSSNOC_MEMNOC_CLK] = &gcc_nssnoc_memnoc_clk.clkr, 4115 [GCC_NSSNOC_MEM_NOC_1_CLK] = &gcc_nssnoc_mem_noc_1_clk.clkr, 4116 [GCC_NSS_TBU_CLK] = &gcc_nss_tbu_clk.clkr, 4117 [GCC_MEM_NOC_NSSNOC_CLK] = &gcc_mem_noc_nssnoc_clk.clkr, 4118 [LPASS_AXIM_CLK_SRC] = &lpass_axim_clk_src.clkr, 4119 [LPASS_SWAY_CLK_SRC] = &lpass_sway_clk_src.clkr, 4120 [ADSS_PWM_CLK_SRC] = &adss_pwm_clk_src.clkr, 4121 [GCC_ADSS_PWM_CLK] = &gcc_adss_pwm_clk.clkr, 4122 [GP1_CLK_SRC] = &gp1_clk_src.clkr, 4123 [GP2_CLK_SRC] = &gp2_clk_src.clkr, 4124 [GP3_CLK_SRC] = &gp3_clk_src.clkr, 4125 [GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr, 4126 [GCC_NSSNOC_XO_DCD_CLK] = &gcc_nssnoc_xo_dcd_clk.clkr, 4127 [GCC_XO_CLK] = &gcc_xo_clk.clkr, 4128 [GCC_NSSNOC_QOSGEN_REF_CLK] = &gcc_nssnoc_qosgen_ref_clk.clkr, 4129 [GCC_NSSNOC_TIMEOUT_REF_CLK] = &gcc_nssnoc_timeout_ref_clk.clkr, 4130 [GCC_XO_DIV4_CLK] = &gcc_xo_div4_clk.clkr, 4131 [GCC_UNIPHY0_SYS_CLK] = &gcc_uniphy0_sys_clk.clkr, 4132 [GCC_UNIPHY1_SYS_CLK] = &gcc_uniphy1_sys_clk.clkr, 4133 [GCC_UNIPHY2_SYS_CLK] = &gcc_uniphy2_sys_clk.clkr, 4134 [GCC_CMN_12GPLL_SYS_CLK] = &gcc_cmn_12gpll_sys_clk.clkr, 4135 [GCC_Q6SS_BOOT_CLK] = &gcc_q6ss_boot_clk.clkr, 4136 [UNIPHY_SYS_CLK_SRC] = &uniphy_sys_clk_src.clkr, 4137 [NSS_TS_CLK_SRC] = &nss_ts_clk_src.clkr, 4138 [GCC_ANOC_PCIE0_1LANE_M_CLK] = &gcc_anoc_pcie0_1lane_m_clk.clkr, 4139 [GCC_ANOC_PCIE1_1LANE_M_CLK] = &gcc_anoc_pcie1_1lane_m_clk.clkr, 4140 [GCC_ANOC_PCIE2_2LANE_M_CLK] = &gcc_anoc_pcie2_2lane_m_clk.clkr, 4141 [GCC_ANOC_PCIE3_2LANE_M_CLK] = &gcc_anoc_pcie3_2lane_m_clk.clkr, 4142 [GCC_SNOC_PCIE0_1LANE_S_CLK] = &gcc_snoc_pcie0_1lane_s_clk.clkr, 4143 [GCC_SNOC_PCIE1_1LANE_S_CLK] = &gcc_snoc_pcie1_1lane_s_clk.clkr, 4144 [GCC_SNOC_PCIE2_2LANE_S_CLK] = &gcc_snoc_pcie2_2lane_s_clk.clkr, 4145 [GCC_SNOC_PCIE3_2LANE_S_CLK] = &gcc_snoc_pcie3_2lane_s_clk.clkr, 4146 }; 4147 4148 static const struct qcom_reset_map gcc_ipq9574_resets[] = { 4149 [GCC_ADSS_BCR] = { 0x1c000, 0 }, 4150 [GCC_ANOC0_TBU_BCR] = { 0x1203c, 0 }, 4151 [GCC_ANOC1_TBU_BCR] = { 0x1204c, 0 }, 4152 [GCC_ANOC_BCR] = { 0x2e074, 0 }, 4153 [GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x38000, 0 }, 4154 [GCC_APSS_TCU_BCR] = { 0x12014, 0 }, 4155 [GCC_BLSP1_BCR] = { 0x01000, 0 }, 4156 [GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 }, 4157 [GCC_BLSP1_QUP2_BCR] = { 0x03000, 0 }, 4158 [GCC_BLSP1_QUP3_BCR] = { 0x04000, 0 }, 4159 [GCC_BLSP1_QUP4_BCR] = { 0x05000, 0 }, 4160 [GCC_BLSP1_QUP5_BCR] = { 0x06000, 0 }, 4161 [GCC_BLSP1_QUP6_BCR] = { 0x07000, 0 }, 4162 [GCC_BLSP1_UART1_BCR] = { 0x02028, 0 }, 4163 [GCC_BLSP1_UART2_BCR] = { 0x03028, 0 }, 4164 [GCC_BLSP1_UART3_BCR] = { 0x04028, 0 }, 4165 [GCC_BLSP1_UART4_BCR] = { 0x05028, 0 }, 4166 [GCC_BLSP1_UART5_BCR] = { 0x06028, 0 }, 4167 [GCC_BLSP1_UART6_BCR] = { 0x07028, 0 }, 4168 [GCC_BOOT_ROM_BCR] = { 0x13028, 0 }, 4169 [GCC_CMN_BLK_BCR] = { 0x3a000, 0 }, 4170 [GCC_CMN_BLK_AHB_ARES] = { 0x3a010, 0 }, 4171 [GCC_CMN_BLK_SYS_ARES] = { 0x3a010, 1 }, 4172 [GCC_CMN_BLK_APU_ARES] = { 0x3a010, 2 }, 4173 [GCC_CRYPTO_BCR] = { 0x16000, 0 }, 4174 [GCC_DCC_BCR] = { 0x35000, 0 }, 4175 [GCC_DDRSS_BCR] = { 0x11000, 0 }, 4176 [GCC_IMEM_BCR] = { 0x0e000, 0 }, 4177 [GCC_LPASS_BCR] = { 0x27000, 0 }, 4178 [GCC_MDIO_BCR] = { 0x1703c, 0 }, 4179 [GCC_MPM_BCR] = { 0x37000, 0 }, 4180 [GCC_MSG_RAM_BCR] = { 0x26000, 0 }, 4181 [GCC_NSS_BCR] = { 0x17000, 0 }, 4182 [GCC_NSS_TBU_BCR] = { 0x12044, 0 }, 4183 [GCC_NSSNOC_MEMNOC_1_ARES] = { 0x17038, 13 }, 4184 [GCC_NSSNOC_PCNOC_1_ARES] = { 0x17038, 12 }, 4185 [GCC_NSSNOC_SNOC_1_ARES] = { 0x17038, 11 }, 4186 [GCC_NSSNOC_XO_DCD_ARES] = { 0x17038, 10 }, 4187 [GCC_NSSNOC_TS_ARES] = { 0x17038, 9 }, 4188 [GCC_NSSCC_ARES] = { 0x17038, 8 }, 4189 [GCC_NSSNOC_NSSCC_ARES] = { 0x17038, 7 }, 4190 [GCC_NSSNOC_ATB_ARES] = { 0x17038, 6 }, 4191 [GCC_NSSNOC_MEMNOC_ARES] = { 0x17038, 5 }, 4192 [GCC_NSSNOC_QOSGEN_REF_ARES] = { 0x17038, 4 }, 4193 [GCC_NSSNOC_SNOC_ARES] = { 0x17038, 3 }, 4194 [GCC_NSSNOC_TIMEOUT_REF_ARES] = { 0x17038, 2 }, 4195 [GCC_NSS_CFG_ARES] = { 0x17038, 1 }, 4196 [GCC_UBI0_DBG_ARES] = { 0x17038, 0 }, 4197 [GCC_PCIE0PHY_PHY_BCR] = { 0x2805c, 0 }, 4198 [GCC_PCIE0_AHB_ARES] = { 0x28058, 7 }, 4199 [GCC_PCIE0_AUX_ARES] = { 0x28058, 6 }, 4200 [GCC_PCIE0_AXI_M_ARES] = { 0x28058, 5 }, 4201 [GCC_PCIE0_AXI_M_STICKY_ARES] = { 0x28058, 4 }, 4202 [GCC_PCIE0_AXI_S_ARES] = { 0x28058, 3 }, 4203 [GCC_PCIE0_AXI_S_STICKY_ARES] = { 0x28058, 2 }, 4204 [GCC_PCIE0_CORE_STICKY_ARES] = { 0x28058, 1 }, 4205 [GCC_PCIE0_PIPE_ARES] = { 0x28058, 0 }, 4206 [GCC_PCIE1_AHB_ARES] = { 0x29058, 7 }, 4207 [GCC_PCIE1_AUX_ARES] = { 0x29058, 6 }, 4208 [GCC_PCIE1_AXI_M_ARES] = { 0x29058, 5 }, 4209 [GCC_PCIE1_AXI_M_STICKY_ARES] = { 0x29058, 4 }, 4210 [GCC_PCIE1_AXI_S_ARES] = { 0x29058, 3 }, 4211 [GCC_PCIE1_AXI_S_STICKY_ARES] = { 0x29058, 2 }, 4212 [GCC_PCIE1_CORE_STICKY_ARES] = { 0x29058, 1 }, 4213 [GCC_PCIE1_PIPE_ARES] = { 0x29058, 0 }, 4214 [GCC_PCIE2_AHB_ARES] = { 0x2a058, 7 }, 4215 [GCC_PCIE2_AUX_ARES] = { 0x2a058, 6 }, 4216 [GCC_PCIE2_AXI_M_ARES] = { 0x2a058, 5 }, 4217 [GCC_PCIE2_AXI_M_STICKY_ARES] = { 0x2a058, 4 }, 4218 [GCC_PCIE2_AXI_S_ARES] = { 0x2a058, 3 }, 4219 [GCC_PCIE2_AXI_S_STICKY_ARES] = { 0x2a058, 2 }, 4220 [GCC_PCIE2_CORE_STICKY_ARES] = { 0x2a058, 1 }, 4221 [GCC_PCIE2_PIPE_ARES] = { 0x2a058, 0 }, 4222 [GCC_PCIE3_AHB_ARES] = { 0x2b058, 7 }, 4223 [GCC_PCIE3_AUX_ARES] = { 0x2b058, 6 }, 4224 [GCC_PCIE3_AXI_M_ARES] = { 0x2b058, 5 }, 4225 [GCC_PCIE3_AXI_M_STICKY_ARES] = { 0x2b058, 4 }, 4226 [GCC_PCIE3_AXI_S_ARES] = { 0x2b058, 3 }, 4227 [GCC_PCIE3_AXI_S_STICKY_ARES] = { 0x2b058, 2 }, 4228 [GCC_PCIE3_CORE_STICKY_ARES] = { 0x2b058, 1 }, 4229 [GCC_PCIE3_PIPE_ARES] = { 0x2b058, 0 }, 4230 [GCC_PCIE0_BCR] = { 0x28000, 0 }, 4231 [GCC_PCIE0_LINK_DOWN_BCR] = { 0x28054, 0 }, 4232 [GCC_PCIE0_PHY_BCR] = { 0x28060, 0 }, 4233 [GCC_PCIE1_BCR] = { 0x29000, 0 }, 4234 [GCC_PCIE1_LINK_DOWN_BCR] = { 0x29054, 0 }, 4235 [GCC_PCIE1_PHY_BCR] = { 0x29060, 0 }, 4236 [GCC_PCIE1PHY_PHY_BCR] = { 0x2905c, 0 }, 4237 [GCC_PCIE2_BCR] = { 0x2a000, 0 }, 4238 [GCC_PCIE2_LINK_DOWN_BCR] = { 0x2a054, 0 }, 4239 [GCC_PCIE2_PHY_BCR] = { 0x2a060, 0 }, 4240 [GCC_PCIE2PHY_PHY_BCR] = { 0x2a05c, 0 }, 4241 [GCC_PCIE3_BCR] = { 0x2b000, 0 }, 4242 [GCC_PCIE3_LINK_DOWN_BCR] = { 0x2b054, 0 }, 4243 [GCC_PCIE3PHY_PHY_BCR] = { 0x2b05c, 0 }, 4244 [GCC_PCIE3_PHY_BCR] = { 0x2b060, 0 }, 4245 [GCC_PCNOC_BCR] = { 0x31000, 0 }, 4246 [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x31030, 0 }, 4247 [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x31038, 0 }, 4248 [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x31040, 0 }, 4249 [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x31048, 0 }, 4250 [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x31050, 0 }, 4251 [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x31058, 0 }, 4252 [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x31060, 0 }, 4253 [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x31068, 0 }, 4254 [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x31070, 0 }, 4255 [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x31078, 0 }, 4256 [GCC_PCNOC_TBU_BCR] = { 0x12034, 0 }, 4257 [GCC_PRNG_BCR] = { 0x13020, 0 }, 4258 [GCC_Q6SS_DBG_ARES] = { 0x2506c, 4 }, 4259 [GCC_Q6_AHB_ARES] = { 0x2506c, 3 }, 4260 [GCC_Q6_AHB_S_ARES] = { 0x2506c, 2 }, 4261 [GCC_Q6_AXIM2_ARES] = { 0x2506c, 1 }, 4262 [GCC_Q6_AXIM_ARES] = { 0x2506c, 0 }, 4263 [GCC_QDSS_BCR] = { 0x2d000, 0 }, 4264 [GCC_QPIC_BCR] = { 0x32000, 0 }, 4265 [GCC_QPIC_AHB_ARES] = { 0x3201c, 1 }, 4266 [GCC_QPIC_ARES] = { 0x3201c, 0 }, 4267 [GCC_QUSB2_0_PHY_BCR] = { 0x2c068, 0 }, 4268 [GCC_RBCPR_BCR] = { 0x39000, 0 }, 4269 [GCC_RBCPR_MX_BCR] = { 0x39014, 0 }, 4270 [GCC_SDCC_BCR] = { 0x33000, 0 }, 4271 [GCC_SEC_CTRL_BCR] = { 0x1a000, 0 }, 4272 [GCC_SMMU_CFG_BCR] = { 0x1202c, 0 }, 4273 [GCC_SNOC_BCR] = { 0x2e000, 0 }, 4274 [GCC_SPDM_BCR] = { 0x36000, 0 }, 4275 [GCC_TCSR_BCR] = { 0x3d000, 0 }, 4276 [GCC_TLMM_BCR] = { 0x3e000, 0 }, 4277 [GCC_TME_BCR] = { 0x10000, 0 }, 4278 [GCC_UNIPHY0_BCR] = { 0x17044, 0 }, 4279 [GCC_UNIPHY0_SYS_RESET] = { 0x17050, 0 }, 4280 [GCC_UNIPHY0_AHB_RESET] = { 0x17050, 1 }, 4281 [GCC_UNIPHY0_XPCS_RESET] = { 0x17050, 2 }, 4282 [GCC_UNIPHY1_SYS_RESET] = { 0x17060, 0 }, 4283 [GCC_UNIPHY1_AHB_RESET] = { 0x17060, 1 }, 4284 [GCC_UNIPHY1_XPCS_RESET] = { 0x17060, 2 }, 4285 [GCC_UNIPHY2_SYS_RESET] = { 0x17070, 0 }, 4286 [GCC_UNIPHY2_AHB_RESET] = { 0x17070, 1 }, 4287 [GCC_UNIPHY2_XPCS_RESET] = { 0x17070, 2 }, 4288 [GCC_UNIPHY1_BCR] = { 0x17054, 0 }, 4289 [GCC_UNIPHY2_BCR] = { 0x17064, 0 }, 4290 [GCC_USB0_PHY_BCR] = { 0x2c06c, 0 }, 4291 [GCC_USB3PHY_0_PHY_BCR] = { 0x2c070, 0 }, 4292 [GCC_USB_BCR] = { 0x2c000, 0 }, 4293 [GCC_USB_MISC_RESET] = { 0x2c064, 0 }, 4294 [GCC_WCSSAON_RESET] = { 0x25074, 0 }, 4295 [GCC_WCSS_ACMT_ARES] = { 0x25070, 5 }, 4296 [GCC_WCSS_AHB_S_ARES] = { 0x25070, 4 }, 4297 [GCC_WCSS_AXI_M_ARES] = { 0x25070, 3 }, 4298 [GCC_WCSS_BCR] = { 0x18004, 0 }, 4299 [GCC_WCSS_DBG_ARES] = { 0x25070, 2 }, 4300 [GCC_WCSS_DBG_BDG_ARES] = { 0x25070, 1 }, 4301 [GCC_WCSS_ECAHB_ARES] = { 0x25070, 0 }, 4302 [GCC_WCSS_Q6_BCR] = { 0x18000, 0 }, 4303 [GCC_WCSS_Q6_TBU_BCR] = { 0x12054, 0 }, 4304 }; 4305 4306 static const struct of_device_id gcc_ipq9574_match_table[] = { 4307 { .compatible = "qcom,ipq9574-gcc" }, 4308 { } 4309 }; 4310 MODULE_DEVICE_TABLE(of, gcc_ipq9574_match_table); 4311 4312 static const struct regmap_config gcc_ipq9574_regmap_config = { 4313 .reg_bits = 32, 4314 .reg_stride = 4, 4315 .val_bits = 32, 4316 .max_register = 0x7fffc, 4317 .fast_io = true, 4318 }; 4319 4320 static const struct qcom_cc_desc gcc_ipq9574_desc = { 4321 .config = &gcc_ipq9574_regmap_config, 4322 .clks = gcc_ipq9574_clks, 4323 .num_clks = ARRAY_SIZE(gcc_ipq9574_clks), 4324 .resets = gcc_ipq9574_resets, 4325 .num_resets = ARRAY_SIZE(gcc_ipq9574_resets), 4326 .clk_hws = gcc_ipq9574_hws, 4327 .num_clk_hws = ARRAY_SIZE(gcc_ipq9574_hws), 4328 }; 4329 4330 static int gcc_ipq9574_probe(struct platform_device *pdev) 4331 { 4332 return qcom_cc_probe(pdev, &gcc_ipq9574_desc); 4333 } 4334 4335 static struct platform_driver gcc_ipq9574_driver = { 4336 .probe = gcc_ipq9574_probe, 4337 .driver = { 4338 .name = "qcom,gcc-ipq9574", 4339 .of_match_table = gcc_ipq9574_match_table, 4340 }, 4341 }; 4342 4343 static int __init gcc_ipq9574_init(void) 4344 { 4345 return platform_driver_register(&gcc_ipq9574_driver); 4346 } 4347 core_initcall(gcc_ipq9574_init); 4348 4349 static void __exit gcc_ipq9574_exit(void) 4350 { 4351 platform_driver_unregister(&gcc_ipq9574_driver); 4352 } 4353 module_exit(gcc_ipq9574_exit); 4354 4355 MODULE_DESCRIPTION("Qualcomm Technologies, Inc. GCC IPQ9574 Driver"); 4356 MODULE_LICENSE("GPL"); 4357