1 /* 2 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include <linux/kernel.h> 15 #include <linux/err.h> 16 #include <linux/platform_device.h> 17 #include <linux/module.h> 18 #include <linux/of.h> 19 #include <linux/of_device.h> 20 #include <linux/clk-provider.h> 21 #include <linux/regmap.h> 22 23 #include <dt-bindings/clock/qcom,gcc-ipq8074.h> 24 25 #include "common.h" 26 #include "clk-regmap.h" 27 #include "clk-pll.h" 28 #include "clk-rcg.h" 29 #include "clk-branch.h" 30 #include "clk-alpha-pll.h" 31 #include "reset.h" 32 33 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } 34 35 enum { 36 P_XO, 37 P_GPLL0, 38 P_GPLL0_DIV2, 39 }; 40 41 static const char * const gcc_xo_gpll0_gpll0_out_main_div2[] = { 42 "xo", 43 "gpll0", 44 "gpll0_out_main_div2", 45 }; 46 47 static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = { 48 { P_XO, 0 }, 49 { P_GPLL0, 1 }, 50 { P_GPLL0_DIV2, 4 }, 51 }; 52 53 static struct clk_alpha_pll gpll0_main = { 54 .offset = 0x21000, 55 .clkr = { 56 .enable_reg = 0x0b000, 57 .enable_mask = BIT(0), 58 .hw.init = &(struct clk_init_data){ 59 .name = "gpll0_main", 60 .parent_names = (const char *[]){ 61 "xo" 62 }, 63 .num_parents = 1, 64 .ops = &clk_alpha_pll_ops, 65 }, 66 }, 67 }; 68 69 static struct clk_fixed_factor gpll0_out_main_div2 = { 70 .mult = 1, 71 .div = 2, 72 .hw.init = &(struct clk_init_data){ 73 .name = "gpll0_out_main_div2", 74 .parent_names = (const char *[]){ 75 "gpll0_main" 76 }, 77 .num_parents = 1, 78 .ops = &clk_fixed_factor_ops, 79 .flags = CLK_SET_RATE_PARENT, 80 }, 81 }; 82 83 static struct clk_alpha_pll_postdiv gpll0 = { 84 .offset = 0x21000, 85 .clkr.hw.init = &(struct clk_init_data){ 86 .name = "gpll0", 87 .parent_names = (const char *[]){ 88 "gpll0_main" 89 }, 90 .num_parents = 1, 91 .ops = &clk_alpha_pll_postdiv_ops, 92 }, 93 }; 94 95 static const struct freq_tbl ftbl_pcnoc_bfdcd_clk_src[] = { 96 F(19200000, P_XO, 1, 0, 0), 97 F(50000000, P_GPLL0, 16, 0, 0), 98 F(100000000, P_GPLL0, 8, 0, 0), 99 { } 100 }; 101 102 static struct clk_rcg2 pcnoc_bfdcd_clk_src = { 103 .cmd_rcgr = 0x27000, 104 .freq_tbl = ftbl_pcnoc_bfdcd_clk_src, 105 .hid_width = 5, 106 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 107 .clkr.hw.init = &(struct clk_init_data){ 108 .name = "pcnoc_bfdcd_clk_src", 109 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, 110 .num_parents = 3, 111 .ops = &clk_rcg2_ops, 112 .flags = CLK_IS_CRITICAL, 113 }, 114 }; 115 116 static struct clk_fixed_factor pcnoc_clk_src = { 117 .mult = 1, 118 .div = 1, 119 .hw.init = &(struct clk_init_data){ 120 .name = "pcnoc_clk_src", 121 .parent_names = (const char *[]){ 122 "pcnoc_bfdcd_clk_src" 123 }, 124 .num_parents = 1, 125 .ops = &clk_fixed_factor_ops, 126 .flags = CLK_SET_RATE_PARENT, 127 }, 128 }; 129 130 static struct clk_branch gcc_sleep_clk_src = { 131 .halt_reg = 0x30000, 132 .clkr = { 133 .enable_reg = 0x30000, 134 .enable_mask = BIT(1), 135 .hw.init = &(struct clk_init_data){ 136 .name = "gcc_sleep_clk_src", 137 .parent_names = (const char *[]){ 138 "sleep_clk" 139 }, 140 .num_parents = 1, 141 .ops = &clk_branch2_ops, 142 }, 143 }, 144 }; 145 146 static const struct freq_tbl ftbl_blsp1_qup_i2c_apps_clk_src[] = { 147 F(19200000, P_XO, 1, 0, 0), 148 F(25000000, P_GPLL0_DIV2, 16, 0, 0), 149 F(50000000, P_GPLL0, 16, 0, 0), 150 { } 151 }; 152 153 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { 154 .cmd_rcgr = 0x0200c, 155 .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src, 156 .hid_width = 5, 157 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 158 .clkr.hw.init = &(struct clk_init_data){ 159 .name = "blsp1_qup1_i2c_apps_clk_src", 160 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, 161 .num_parents = 3, 162 .ops = &clk_rcg2_ops, 163 }, 164 }; 165 166 static const struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src[] = { 167 F(960000, P_XO, 10, 1, 2), 168 F(4800000, P_XO, 4, 0, 0), 169 F(9600000, P_XO, 2, 0, 0), 170 F(12500000, P_GPLL0_DIV2, 16, 1, 2), 171 F(16000000, P_GPLL0, 10, 1, 5), 172 F(19200000, P_XO, 1, 0, 0), 173 F(25000000, P_GPLL0, 16, 1, 2), 174 F(50000000, P_GPLL0, 16, 0, 0), 175 { } 176 }; 177 178 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { 179 .cmd_rcgr = 0x02024, 180 .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src, 181 .mnd_width = 8, 182 .hid_width = 5, 183 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 184 .clkr.hw.init = &(struct clk_init_data){ 185 .name = "blsp1_qup1_spi_apps_clk_src", 186 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, 187 .num_parents = 3, 188 .ops = &clk_rcg2_ops, 189 }, 190 }; 191 192 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { 193 .cmd_rcgr = 0x03000, 194 .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src, 195 .hid_width = 5, 196 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 197 .clkr.hw.init = &(struct clk_init_data){ 198 .name = "blsp1_qup2_i2c_apps_clk_src", 199 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, 200 .num_parents = 3, 201 .ops = &clk_rcg2_ops, 202 }, 203 }; 204 205 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { 206 .cmd_rcgr = 0x03014, 207 .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src, 208 .mnd_width = 8, 209 .hid_width = 5, 210 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 211 .clkr.hw.init = &(struct clk_init_data){ 212 .name = "blsp1_qup2_spi_apps_clk_src", 213 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, 214 .num_parents = 3, 215 .ops = &clk_rcg2_ops, 216 }, 217 }; 218 219 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { 220 .cmd_rcgr = 0x04000, 221 .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src, 222 .hid_width = 5, 223 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 224 .clkr.hw.init = &(struct clk_init_data){ 225 .name = "blsp1_qup3_i2c_apps_clk_src", 226 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, 227 .num_parents = 3, 228 .ops = &clk_rcg2_ops, 229 }, 230 }; 231 232 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { 233 .cmd_rcgr = 0x04014, 234 .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src, 235 .mnd_width = 8, 236 .hid_width = 5, 237 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 238 .clkr.hw.init = &(struct clk_init_data){ 239 .name = "blsp1_qup3_spi_apps_clk_src", 240 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, 241 .num_parents = 3, 242 .ops = &clk_rcg2_ops, 243 }, 244 }; 245 246 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { 247 .cmd_rcgr = 0x05000, 248 .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src, 249 .hid_width = 5, 250 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 251 .clkr.hw.init = &(struct clk_init_data){ 252 .name = "blsp1_qup4_i2c_apps_clk_src", 253 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, 254 .num_parents = 3, 255 .ops = &clk_rcg2_ops, 256 }, 257 }; 258 259 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { 260 .cmd_rcgr = 0x05014, 261 .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src, 262 .mnd_width = 8, 263 .hid_width = 5, 264 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 265 .clkr.hw.init = &(struct clk_init_data){ 266 .name = "blsp1_qup4_spi_apps_clk_src", 267 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, 268 .num_parents = 3, 269 .ops = &clk_rcg2_ops, 270 }, 271 }; 272 273 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = { 274 .cmd_rcgr = 0x06000, 275 .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src, 276 .hid_width = 5, 277 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 278 .clkr.hw.init = &(struct clk_init_data){ 279 .name = "blsp1_qup5_i2c_apps_clk_src", 280 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, 281 .num_parents = 3, 282 .ops = &clk_rcg2_ops, 283 }, 284 }; 285 286 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = { 287 .cmd_rcgr = 0x06014, 288 .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src, 289 .mnd_width = 8, 290 .hid_width = 5, 291 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 292 .clkr.hw.init = &(struct clk_init_data){ 293 .name = "blsp1_qup5_spi_apps_clk_src", 294 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, 295 .num_parents = 3, 296 .ops = &clk_rcg2_ops, 297 }, 298 }; 299 300 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = { 301 .cmd_rcgr = 0x07000, 302 .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src, 303 .hid_width = 5, 304 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 305 .clkr.hw.init = &(struct clk_init_data){ 306 .name = "blsp1_qup6_i2c_apps_clk_src", 307 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, 308 .num_parents = 3, 309 .ops = &clk_rcg2_ops, 310 }, 311 }; 312 313 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = { 314 .cmd_rcgr = 0x07014, 315 .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src, 316 .mnd_width = 8, 317 .hid_width = 5, 318 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 319 .clkr.hw.init = &(struct clk_init_data){ 320 .name = "blsp1_qup6_spi_apps_clk_src", 321 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, 322 .num_parents = 3, 323 .ops = &clk_rcg2_ops, 324 }, 325 }; 326 327 static const struct freq_tbl ftbl_blsp1_uart_apps_clk_src[] = { 328 F(3686400, P_GPLL0_DIV2, 1, 144, 15625), 329 F(7372800, P_GPLL0_DIV2, 1, 288, 15625), 330 F(14745600, P_GPLL0_DIV2, 1, 576, 15625), 331 F(16000000, P_GPLL0_DIV2, 5, 1, 5), 332 F(19200000, P_XO, 1, 0, 0), 333 F(24000000, P_GPLL0, 1, 3, 100), 334 F(25000000, P_GPLL0, 16, 1, 2), 335 F(32000000, P_GPLL0, 1, 1, 25), 336 F(40000000, P_GPLL0, 1, 1, 20), 337 F(46400000, P_GPLL0, 1, 29, 500), 338 F(48000000, P_GPLL0, 1, 3, 50), 339 F(51200000, P_GPLL0, 1, 8, 125), 340 F(56000000, P_GPLL0, 1, 7, 100), 341 F(58982400, P_GPLL0, 1, 1152, 15625), 342 F(60000000, P_GPLL0, 1, 3, 40), 343 F(64000000, P_GPLL0, 12.5, 1, 1), 344 { } 345 }; 346 347 static struct clk_rcg2 blsp1_uart1_apps_clk_src = { 348 .cmd_rcgr = 0x02044, 349 .freq_tbl = ftbl_blsp1_uart_apps_clk_src, 350 .mnd_width = 16, 351 .hid_width = 5, 352 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 353 .clkr.hw.init = &(struct clk_init_data){ 354 .name = "blsp1_uart1_apps_clk_src", 355 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, 356 .num_parents = 3, 357 .ops = &clk_rcg2_ops, 358 }, 359 }; 360 361 static struct clk_rcg2 blsp1_uart2_apps_clk_src = { 362 .cmd_rcgr = 0x03034, 363 .freq_tbl = ftbl_blsp1_uart_apps_clk_src, 364 .mnd_width = 16, 365 .hid_width = 5, 366 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 367 .clkr.hw.init = &(struct clk_init_data){ 368 .name = "blsp1_uart2_apps_clk_src", 369 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, 370 .num_parents = 3, 371 .ops = &clk_rcg2_ops, 372 }, 373 }; 374 375 static struct clk_rcg2 blsp1_uart3_apps_clk_src = { 376 .cmd_rcgr = 0x04034, 377 .freq_tbl = ftbl_blsp1_uart_apps_clk_src, 378 .mnd_width = 16, 379 .hid_width = 5, 380 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 381 .clkr.hw.init = &(struct clk_init_data){ 382 .name = "blsp1_uart3_apps_clk_src", 383 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, 384 .num_parents = 3, 385 .ops = &clk_rcg2_ops, 386 }, 387 }; 388 389 static struct clk_rcg2 blsp1_uart4_apps_clk_src = { 390 .cmd_rcgr = 0x05034, 391 .freq_tbl = ftbl_blsp1_uart_apps_clk_src, 392 .mnd_width = 16, 393 .hid_width = 5, 394 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 395 .clkr.hw.init = &(struct clk_init_data){ 396 .name = "blsp1_uart4_apps_clk_src", 397 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, 398 .num_parents = 3, 399 .ops = &clk_rcg2_ops, 400 }, 401 }; 402 403 static struct clk_rcg2 blsp1_uart5_apps_clk_src = { 404 .cmd_rcgr = 0x06034, 405 .freq_tbl = ftbl_blsp1_uart_apps_clk_src, 406 .mnd_width = 16, 407 .hid_width = 5, 408 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 409 .clkr.hw.init = &(struct clk_init_data){ 410 .name = "blsp1_uart5_apps_clk_src", 411 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, 412 .num_parents = 3, 413 .ops = &clk_rcg2_ops, 414 }, 415 }; 416 417 static struct clk_rcg2 blsp1_uart6_apps_clk_src = { 418 .cmd_rcgr = 0x07034, 419 .freq_tbl = ftbl_blsp1_uart_apps_clk_src, 420 .mnd_width = 16, 421 .hid_width = 5, 422 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 423 .clkr.hw.init = &(struct clk_init_data){ 424 .name = "blsp1_uart6_apps_clk_src", 425 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, 426 .num_parents = 3, 427 .ops = &clk_rcg2_ops, 428 }, 429 }; 430 431 static struct clk_branch gcc_blsp1_ahb_clk = { 432 .halt_reg = 0x01008, 433 .clkr = { 434 .enable_reg = 0x01008, 435 .enable_mask = BIT(0), 436 .hw.init = &(struct clk_init_data){ 437 .name = "gcc_blsp1_ahb_clk", 438 .parent_names = (const char *[]){ 439 "pcnoc_clk_src" 440 }, 441 .num_parents = 1, 442 .flags = CLK_SET_RATE_PARENT, 443 .ops = &clk_branch2_ops, 444 }, 445 }, 446 }; 447 448 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { 449 .halt_reg = 0x02008, 450 .clkr = { 451 .enable_reg = 0x02008, 452 .enable_mask = BIT(0), 453 .hw.init = &(struct clk_init_data){ 454 .name = "gcc_blsp1_qup1_i2c_apps_clk", 455 .parent_names = (const char *[]){ 456 "blsp1_qup1_i2c_apps_clk_src" 457 }, 458 .num_parents = 1, 459 .flags = CLK_SET_RATE_PARENT, 460 .ops = &clk_branch2_ops, 461 }, 462 }, 463 }; 464 465 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { 466 .halt_reg = 0x02004, 467 .clkr = { 468 .enable_reg = 0x02004, 469 .enable_mask = BIT(0), 470 .hw.init = &(struct clk_init_data){ 471 .name = "gcc_blsp1_qup1_spi_apps_clk", 472 .parent_names = (const char *[]){ 473 "blsp1_qup1_spi_apps_clk_src" 474 }, 475 .num_parents = 1, 476 .flags = CLK_SET_RATE_PARENT, 477 .ops = &clk_branch2_ops, 478 }, 479 }, 480 }; 481 482 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { 483 .halt_reg = 0x03010, 484 .clkr = { 485 .enable_reg = 0x03010, 486 .enable_mask = BIT(0), 487 .hw.init = &(struct clk_init_data){ 488 .name = "gcc_blsp1_qup2_i2c_apps_clk", 489 .parent_names = (const char *[]){ 490 "blsp1_qup2_i2c_apps_clk_src" 491 }, 492 .num_parents = 1, 493 .flags = CLK_SET_RATE_PARENT, 494 .ops = &clk_branch2_ops, 495 }, 496 }, 497 }; 498 499 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { 500 .halt_reg = 0x0300c, 501 .clkr = { 502 .enable_reg = 0x0300c, 503 .enable_mask = BIT(0), 504 .hw.init = &(struct clk_init_data){ 505 .name = "gcc_blsp1_qup2_spi_apps_clk", 506 .parent_names = (const char *[]){ 507 "blsp1_qup2_spi_apps_clk_src" 508 }, 509 .num_parents = 1, 510 .flags = CLK_SET_RATE_PARENT, 511 .ops = &clk_branch2_ops, 512 }, 513 }, 514 }; 515 516 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = { 517 .halt_reg = 0x04010, 518 .clkr = { 519 .enable_reg = 0x04010, 520 .enable_mask = BIT(0), 521 .hw.init = &(struct clk_init_data){ 522 .name = "gcc_blsp1_qup3_i2c_apps_clk", 523 .parent_names = (const char *[]){ 524 "blsp1_qup3_i2c_apps_clk_src" 525 }, 526 .num_parents = 1, 527 .flags = CLK_SET_RATE_PARENT, 528 .ops = &clk_branch2_ops, 529 }, 530 }, 531 }; 532 533 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = { 534 .halt_reg = 0x0400c, 535 .clkr = { 536 .enable_reg = 0x0400c, 537 .enable_mask = BIT(0), 538 .hw.init = &(struct clk_init_data){ 539 .name = "gcc_blsp1_qup3_spi_apps_clk", 540 .parent_names = (const char *[]){ 541 "blsp1_qup3_spi_apps_clk_src" 542 }, 543 .num_parents = 1, 544 .flags = CLK_SET_RATE_PARENT, 545 .ops = &clk_branch2_ops, 546 }, 547 }, 548 }; 549 550 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = { 551 .halt_reg = 0x05010, 552 .clkr = { 553 .enable_reg = 0x05010, 554 .enable_mask = BIT(0), 555 .hw.init = &(struct clk_init_data){ 556 .name = "gcc_blsp1_qup4_i2c_apps_clk", 557 .parent_names = (const char *[]){ 558 "blsp1_qup4_i2c_apps_clk_src" 559 }, 560 .num_parents = 1, 561 .flags = CLK_SET_RATE_PARENT, 562 .ops = &clk_branch2_ops, 563 }, 564 }, 565 }; 566 567 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = { 568 .halt_reg = 0x0500c, 569 .clkr = { 570 .enable_reg = 0x0500c, 571 .enable_mask = BIT(0), 572 .hw.init = &(struct clk_init_data){ 573 .name = "gcc_blsp1_qup4_spi_apps_clk", 574 .parent_names = (const char *[]){ 575 "blsp1_qup4_spi_apps_clk_src" 576 }, 577 .num_parents = 1, 578 .flags = CLK_SET_RATE_PARENT, 579 .ops = &clk_branch2_ops, 580 }, 581 }, 582 }; 583 584 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = { 585 .halt_reg = 0x06010, 586 .clkr = { 587 .enable_reg = 0x06010, 588 .enable_mask = BIT(0), 589 .hw.init = &(struct clk_init_data){ 590 .name = "gcc_blsp1_qup5_i2c_apps_clk", 591 .parent_names = (const char *[]){ 592 "blsp1_qup5_i2c_apps_clk_src" 593 }, 594 .num_parents = 1, 595 .flags = CLK_SET_RATE_PARENT, 596 .ops = &clk_branch2_ops, 597 }, 598 }, 599 }; 600 601 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = { 602 .halt_reg = 0x0600c, 603 .clkr = { 604 .enable_reg = 0x0600c, 605 .enable_mask = BIT(0), 606 .hw.init = &(struct clk_init_data){ 607 .name = "gcc_blsp1_qup5_spi_apps_clk", 608 .parent_names = (const char *[]){ 609 "blsp1_qup5_spi_apps_clk_src" 610 }, 611 .num_parents = 1, 612 .flags = CLK_SET_RATE_PARENT, 613 .ops = &clk_branch2_ops, 614 }, 615 }, 616 }; 617 618 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = { 619 .halt_reg = 0x07010, 620 .clkr = { 621 .enable_reg = 0x07010, 622 .enable_mask = BIT(0), 623 .hw.init = &(struct clk_init_data){ 624 .name = "gcc_blsp1_qup6_i2c_apps_clk", 625 .parent_names = (const char *[]){ 626 "blsp1_qup6_i2c_apps_clk_src" 627 }, 628 .num_parents = 1, 629 .flags = CLK_SET_RATE_PARENT, 630 .ops = &clk_branch2_ops, 631 }, 632 }, 633 }; 634 635 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = { 636 .halt_reg = 0x0700c, 637 .clkr = { 638 .enable_reg = 0x0700c, 639 .enable_mask = BIT(0), 640 .hw.init = &(struct clk_init_data){ 641 .name = "gcc_blsp1_qup6_spi_apps_clk", 642 .parent_names = (const char *[]){ 643 "blsp1_qup6_spi_apps_clk_src" 644 }, 645 .num_parents = 1, 646 .flags = CLK_SET_RATE_PARENT, 647 .ops = &clk_branch2_ops, 648 }, 649 }, 650 }; 651 652 static struct clk_branch gcc_blsp1_uart1_apps_clk = { 653 .halt_reg = 0x0203c, 654 .clkr = { 655 .enable_reg = 0x0203c, 656 .enable_mask = BIT(0), 657 .hw.init = &(struct clk_init_data){ 658 .name = "gcc_blsp1_uart1_apps_clk", 659 .parent_names = (const char *[]){ 660 "blsp1_uart1_apps_clk_src" 661 }, 662 .num_parents = 1, 663 .flags = CLK_SET_RATE_PARENT, 664 .ops = &clk_branch2_ops, 665 }, 666 }, 667 }; 668 669 static struct clk_branch gcc_blsp1_uart2_apps_clk = { 670 .halt_reg = 0x0302c, 671 .clkr = { 672 .enable_reg = 0x0302c, 673 .enable_mask = BIT(0), 674 .hw.init = &(struct clk_init_data){ 675 .name = "gcc_blsp1_uart2_apps_clk", 676 .parent_names = (const char *[]){ 677 "blsp1_uart2_apps_clk_src" 678 }, 679 .num_parents = 1, 680 .flags = CLK_SET_RATE_PARENT, 681 .ops = &clk_branch2_ops, 682 }, 683 }, 684 }; 685 686 static struct clk_branch gcc_blsp1_uart3_apps_clk = { 687 .halt_reg = 0x0402c, 688 .clkr = { 689 .enable_reg = 0x0402c, 690 .enable_mask = BIT(0), 691 .hw.init = &(struct clk_init_data){ 692 .name = "gcc_blsp1_uart3_apps_clk", 693 .parent_names = (const char *[]){ 694 "blsp1_uart3_apps_clk_src" 695 }, 696 .num_parents = 1, 697 .flags = CLK_SET_RATE_PARENT, 698 .ops = &clk_branch2_ops, 699 }, 700 }, 701 }; 702 703 static struct clk_branch gcc_blsp1_uart4_apps_clk = { 704 .halt_reg = 0x0502c, 705 .clkr = { 706 .enable_reg = 0x0502c, 707 .enable_mask = BIT(0), 708 .hw.init = &(struct clk_init_data){ 709 .name = "gcc_blsp1_uart4_apps_clk", 710 .parent_names = (const char *[]){ 711 "blsp1_uart4_apps_clk_src" 712 }, 713 .num_parents = 1, 714 .flags = CLK_SET_RATE_PARENT, 715 .ops = &clk_branch2_ops, 716 }, 717 }, 718 }; 719 720 static struct clk_branch gcc_blsp1_uart5_apps_clk = { 721 .halt_reg = 0x0602c, 722 .clkr = { 723 .enable_reg = 0x0602c, 724 .enable_mask = BIT(0), 725 .hw.init = &(struct clk_init_data){ 726 .name = "gcc_blsp1_uart5_apps_clk", 727 .parent_names = (const char *[]){ 728 "blsp1_uart5_apps_clk_src" 729 }, 730 .num_parents = 1, 731 .flags = CLK_SET_RATE_PARENT, 732 .ops = &clk_branch2_ops, 733 }, 734 }, 735 }; 736 737 static struct clk_branch gcc_blsp1_uart6_apps_clk = { 738 .halt_reg = 0x0702c, 739 .clkr = { 740 .enable_reg = 0x0702c, 741 .enable_mask = BIT(0), 742 .hw.init = &(struct clk_init_data){ 743 .name = "gcc_blsp1_uart6_apps_clk", 744 .parent_names = (const char *[]){ 745 "blsp1_uart6_apps_clk_src" 746 }, 747 .num_parents = 1, 748 .flags = CLK_SET_RATE_PARENT, 749 .ops = &clk_branch2_ops, 750 }, 751 }, 752 }; 753 754 static struct clk_branch gcc_prng_ahb_clk = { 755 .halt_reg = 0x13004, 756 .halt_check = BRANCH_HALT_VOTED, 757 .clkr = { 758 .enable_reg = 0x0b004, 759 .enable_mask = BIT(8), 760 .hw.init = &(struct clk_init_data){ 761 .name = "gcc_prng_ahb_clk", 762 .parent_names = (const char *[]){ 763 "pcnoc_clk_src" 764 }, 765 .num_parents = 1, 766 .flags = CLK_SET_RATE_PARENT, 767 .ops = &clk_branch2_ops, 768 }, 769 }, 770 }; 771 772 static struct clk_branch gcc_qpic_ahb_clk = { 773 .halt_reg = 0x57024, 774 .clkr = { 775 .enable_reg = 0x57024, 776 .enable_mask = BIT(0), 777 .hw.init = &(struct clk_init_data){ 778 .name = "gcc_qpic_ahb_clk", 779 .parent_names = (const char *[]){ 780 "pcnoc_clk_src" 781 }, 782 .num_parents = 1, 783 .flags = CLK_SET_RATE_PARENT, 784 .ops = &clk_branch2_ops, 785 }, 786 }, 787 }; 788 789 static struct clk_branch gcc_qpic_clk = { 790 .halt_reg = 0x57020, 791 .clkr = { 792 .enable_reg = 0x57020, 793 .enable_mask = BIT(0), 794 .hw.init = &(struct clk_init_data){ 795 .name = "gcc_qpic_clk", 796 .parent_names = (const char *[]){ 797 "pcnoc_clk_src" 798 }, 799 .num_parents = 1, 800 .flags = CLK_SET_RATE_PARENT, 801 .ops = &clk_branch2_ops, 802 }, 803 }, 804 }; 805 806 static struct clk_hw *gcc_ipq8074_hws[] = { 807 &gpll0_out_main_div2.hw, 808 &pcnoc_clk_src.hw, 809 }; 810 811 static struct clk_regmap *gcc_ipq8074_clks[] = { 812 [GPLL0_MAIN] = &gpll0_main.clkr, 813 [GPLL0] = &gpll0.clkr, 814 [PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr, 815 [GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr, 816 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr, 817 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr, 818 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr, 819 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr, 820 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr, 821 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr, 822 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr, 823 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr, 824 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr, 825 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr, 826 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr, 827 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr, 828 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr, 829 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr, 830 [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr, 831 [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr, 832 [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr, 833 [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr, 834 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr, 835 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr, 836 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr, 837 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr, 838 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr, 839 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr, 840 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr, 841 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr, 842 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr, 843 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr, 844 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr, 845 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr, 846 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr, 847 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, 848 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr, 849 [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr, 850 [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr, 851 [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr, 852 [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr, 853 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, 854 [GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr, 855 [GCC_QPIC_CLK] = &gcc_qpic_clk.clkr, 856 }; 857 858 static const struct qcom_reset_map gcc_ipq8074_resets[] = { 859 [GCC_BLSP1_BCR] = { 0x01000, 0 }, 860 [GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 }, 861 [GCC_BLSP1_UART1_BCR] = { 0x02038, 0 }, 862 [GCC_BLSP1_QUP2_BCR] = { 0x03008, 0 }, 863 [GCC_BLSP1_UART2_BCR] = { 0x03028, 0 }, 864 [GCC_BLSP1_QUP3_BCR] = { 0x04008, 0 }, 865 [GCC_BLSP1_UART3_BCR] = { 0x04028, 0 }, 866 [GCC_BLSP1_QUP4_BCR] = { 0x05008, 0 }, 867 [GCC_BLSP1_UART4_BCR] = { 0x05028, 0 }, 868 [GCC_BLSP1_QUP5_BCR] = { 0x06008, 0 }, 869 [GCC_BLSP1_UART5_BCR] = { 0x06028, 0 }, 870 [GCC_BLSP1_QUP6_BCR] = { 0x07008, 0 }, 871 [GCC_BLSP1_UART6_BCR] = { 0x07028, 0 }, 872 [GCC_IMEM_BCR] = { 0x0e000, 0 }, 873 [GCC_SMMU_BCR] = { 0x12000, 0 }, 874 [GCC_APSS_TCU_BCR] = { 0x12050, 0 }, 875 [GCC_SMMU_XPU_BCR] = { 0x12054, 0 }, 876 [GCC_PCNOC_TBU_BCR] = { 0x12058, 0 }, 877 [GCC_SMMU_CFG_BCR] = { 0x1208c, 0 }, 878 [GCC_PRNG_BCR] = { 0x13000, 0 }, 879 [GCC_BOOT_ROM_BCR] = { 0x13008, 0 }, 880 [GCC_CRYPTO_BCR] = { 0x16000, 0 }, 881 [GCC_WCSS_BCR] = { 0x18000, 0 }, 882 [GCC_WCSS_Q6_BCR] = { 0x18100, 0 }, 883 [GCC_NSS_BCR] = { 0x19000, 0 }, 884 [GCC_SEC_CTRL_BCR] = { 0x1a000, 0 }, 885 [GCC_ADSS_BCR] = { 0x1c000, 0 }, 886 [GCC_DDRSS_BCR] = { 0x1e000, 0 }, 887 [GCC_SYSTEM_NOC_BCR] = { 0x26000, 0 }, 888 [GCC_PCNOC_BCR] = { 0x27018, 0 }, 889 [GCC_TCSR_BCR] = { 0x28000, 0 }, 890 [GCC_QDSS_BCR] = { 0x29000, 0 }, 891 [GCC_DCD_BCR] = { 0x2a000, 0 }, 892 [GCC_MSG_RAM_BCR] = { 0x2b000, 0 }, 893 [GCC_MPM_BCR] = { 0x2c000, 0 }, 894 [GCC_SPMI_BCR] = { 0x2e000, 0 }, 895 [GCC_SPDM_BCR] = { 0x2f000, 0 }, 896 [GCC_RBCPR_BCR] = { 0x33000, 0 }, 897 [GCC_RBCPR_MX_BCR] = { 0x33014, 0 }, 898 [GCC_TLMM_BCR] = { 0x34000, 0 }, 899 [GCC_RBCPR_WCSS_BCR] = { 0x3a000, 0 }, 900 [GCC_USB0_PHY_BCR] = { 0x3e034, 0 }, 901 [GCC_USB3PHY_0_PHY_BCR] = { 0x3e03c, 0 }, 902 [GCC_USB0_BCR] = { 0x3e070, 0 }, 903 [GCC_USB1_PHY_BCR] = { 0x3f034, 0 }, 904 [GCC_USB3PHY_1_PHY_BCR] = { 0x3f03c, 0 }, 905 [GCC_USB1_BCR] = { 0x3f070, 0 }, 906 [GCC_QUSB2_0_PHY_BCR] = { 0x4103c, 0 }, 907 [GCC_QUSB2_1_PHY_BCR] = { 0x41040, 0 }, 908 [GCC_SDCC1_BCR] = { 0x42000, 0 }, 909 [GCC_SDCC2_BCR] = { 0x43000, 0 }, 910 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000, 0 }, 911 [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x47008, 0 }, 912 [GCC_SNOC_BUS_TIMEOUT3_BCR] = { 0x47010, 0 }, 913 [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000, 0 }, 914 [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008, 0 }, 915 [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010, 0 }, 916 [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018, 0 }, 917 [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020, 0 }, 918 [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028, 0 }, 919 [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030, 0 }, 920 [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038, 0 }, 921 [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040, 0 }, 922 [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048, 0 }, 923 [GCC_UNIPHY0_BCR] = { 0x56000, 0 }, 924 [GCC_UNIPHY1_BCR] = { 0x56100, 0 }, 925 [GCC_UNIPHY2_BCR] = { 0x56200, 0 }, 926 [GCC_CMN_12GPLL_BCR] = { 0x56300, 0 }, 927 [GCC_QPIC_BCR] = { 0x57018, 0 }, 928 [GCC_MDIO_BCR] = { 0x58000, 0 }, 929 [GCC_PCIE1_TBU_BCR] = { 0x65000, 0 }, 930 [GCC_WCSS_CORE_TBU_BCR] = { 0x66000, 0 }, 931 [GCC_WCSS_Q6_TBU_BCR] = { 0x67000, 0 }, 932 [GCC_USB0_TBU_BCR] = { 0x6a000, 0 }, 933 [GCC_USB1_TBU_BCR] = { 0x6a004, 0 }, 934 [GCC_PCIE0_TBU_BCR] = { 0x6b000, 0 }, 935 [GCC_NSS_NOC_TBU_BCR] = { 0x6e000, 0 }, 936 [GCC_PCIE0_BCR] = { 0x75004, 0 }, 937 [GCC_PCIE0_PHY_BCR] = { 0x75038, 0 }, 938 [GCC_PCIE0PHY_PHY_BCR] = { 0x7503c, 0 }, 939 [GCC_PCIE0_LINK_DOWN_BCR] = { 0x75044, 0 }, 940 [GCC_PCIE1_BCR] = { 0x76004, 0 }, 941 [GCC_PCIE1_PHY_BCR] = { 0x76038, 0 }, 942 [GCC_PCIE1PHY_PHY_BCR] = { 0x7603c, 0 }, 943 [GCC_PCIE1_LINK_DOWN_BCR] = { 0x76044, 0 }, 944 [GCC_DCC_BCR] = { 0x77000, 0 }, 945 [GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x78000, 0 }, 946 [GCC_APC1_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x79000, 0 }, 947 [GCC_SMMU_CATS_BCR] = { 0x7c000, 0 }, 948 }; 949 950 static const struct of_device_id gcc_ipq8074_match_table[] = { 951 { .compatible = "qcom,gcc-ipq8074" }, 952 { } 953 }; 954 MODULE_DEVICE_TABLE(of, gcc_ipq8074_match_table); 955 956 static const struct regmap_config gcc_ipq8074_regmap_config = { 957 .reg_bits = 32, 958 .reg_stride = 4, 959 .val_bits = 32, 960 .max_register = 0x7fffc, 961 .fast_io = true, 962 }; 963 964 static const struct qcom_cc_desc gcc_ipq8074_desc = { 965 .config = &gcc_ipq8074_regmap_config, 966 .clks = gcc_ipq8074_clks, 967 .num_clks = ARRAY_SIZE(gcc_ipq8074_clks), 968 .resets = gcc_ipq8074_resets, 969 .num_resets = ARRAY_SIZE(gcc_ipq8074_resets), 970 }; 971 972 static int gcc_ipq8074_probe(struct platform_device *pdev) 973 { 974 int ret, i; 975 976 for (i = 0; i < ARRAY_SIZE(gcc_ipq8074_hws); i++) { 977 ret = devm_clk_hw_register(&pdev->dev, gcc_ipq8074_hws[i]); 978 if (ret) 979 return ret; 980 } 981 982 return qcom_cc_probe(pdev, &gcc_ipq8074_desc); 983 } 984 985 static struct platform_driver gcc_ipq8074_driver = { 986 .probe = gcc_ipq8074_probe, 987 .driver = { 988 .name = "qcom,gcc-ipq8074", 989 .of_match_table = gcc_ipq8074_match_table, 990 }, 991 }; 992 993 static int __init gcc_ipq8074_init(void) 994 { 995 return platform_driver_register(&gcc_ipq8074_driver); 996 } 997 core_initcall(gcc_ipq8074_init); 998 999 static void __exit gcc_ipq8074_exit(void) 1000 { 1001 platform_driver_unregister(&gcc_ipq8074_driver); 1002 } 1003 module_exit(gcc_ipq8074_exit); 1004 1005 MODULE_DESCRIPTION("QCOM GCC IPQ8074 Driver"); 1006 MODULE_LICENSE("GPL v2"); 1007 MODULE_ALIAS("platform:gcc-ipq8074"); 1008