1 /* 2 * Copyright (c) 2014, The Linux Foundation. All rights reserved. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include <linux/kernel.h> 15 #include <linux/bitops.h> 16 #include <linux/err.h> 17 #include <linux/platform_device.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/of_device.h> 21 #include <linux/clk-provider.h> 22 #include <linux/regmap.h> 23 #include <linux/reset-controller.h> 24 25 #include <dt-bindings/clock/qcom,gcc-ipq806x.h> 26 #include <dt-bindings/reset/qcom,gcc-ipq806x.h> 27 28 #include "common.h" 29 #include "clk-regmap.h" 30 #include "clk-pll.h" 31 #include "clk-rcg.h" 32 #include "clk-branch.h" 33 #include "reset.h" 34 35 static struct clk_pll pll0 = { 36 .l_reg = 0x30c4, 37 .m_reg = 0x30c8, 38 .n_reg = 0x30cc, 39 .config_reg = 0x30d4, 40 .mode_reg = 0x30c0, 41 .status_reg = 0x30d8, 42 .status_bit = 16, 43 .clkr.hw.init = &(struct clk_init_data){ 44 .name = "pll0", 45 .parent_names = (const char *[]){ "pxo" }, 46 .num_parents = 1, 47 .ops = &clk_pll_ops, 48 }, 49 }; 50 51 static struct clk_regmap pll0_vote = { 52 .enable_reg = 0x34c0, 53 .enable_mask = BIT(0), 54 .hw.init = &(struct clk_init_data){ 55 .name = "pll0_vote", 56 .parent_names = (const char *[]){ "pll0" }, 57 .num_parents = 1, 58 .ops = &clk_pll_vote_ops, 59 }, 60 }; 61 62 static struct clk_pll pll3 = { 63 .l_reg = 0x3164, 64 .m_reg = 0x3168, 65 .n_reg = 0x316c, 66 .config_reg = 0x3174, 67 .mode_reg = 0x3160, 68 .status_reg = 0x3178, 69 .status_bit = 16, 70 .clkr.hw.init = &(struct clk_init_data){ 71 .name = "pll3", 72 .parent_names = (const char *[]){ "pxo" }, 73 .num_parents = 1, 74 .ops = &clk_pll_ops, 75 }, 76 }; 77 78 static struct clk_pll pll8 = { 79 .l_reg = 0x3144, 80 .m_reg = 0x3148, 81 .n_reg = 0x314c, 82 .config_reg = 0x3154, 83 .mode_reg = 0x3140, 84 .status_reg = 0x3158, 85 .status_bit = 16, 86 .clkr.hw.init = &(struct clk_init_data){ 87 .name = "pll8", 88 .parent_names = (const char *[]){ "pxo" }, 89 .num_parents = 1, 90 .ops = &clk_pll_ops, 91 }, 92 }; 93 94 static struct clk_regmap pll8_vote = { 95 .enable_reg = 0x34c0, 96 .enable_mask = BIT(8), 97 .hw.init = &(struct clk_init_data){ 98 .name = "pll8_vote", 99 .parent_names = (const char *[]){ "pll8" }, 100 .num_parents = 1, 101 .ops = &clk_pll_vote_ops, 102 }, 103 }; 104 105 static struct clk_pll pll14 = { 106 .l_reg = 0x31c4, 107 .m_reg = 0x31c8, 108 .n_reg = 0x31cc, 109 .config_reg = 0x31d4, 110 .mode_reg = 0x31c0, 111 .status_reg = 0x31d8, 112 .status_bit = 16, 113 .clkr.hw.init = &(struct clk_init_data){ 114 .name = "pll14", 115 .parent_names = (const char *[]){ "pxo" }, 116 .num_parents = 1, 117 .ops = &clk_pll_ops, 118 }, 119 }; 120 121 static struct clk_regmap pll14_vote = { 122 .enable_reg = 0x34c0, 123 .enable_mask = BIT(14), 124 .hw.init = &(struct clk_init_data){ 125 .name = "pll14_vote", 126 .parent_names = (const char *[]){ "pll14" }, 127 .num_parents = 1, 128 .ops = &clk_pll_vote_ops, 129 }, 130 }; 131 132 #define P_PXO 0 133 #define P_PLL8 1 134 #define P_PLL3 1 135 #define P_PLL0 2 136 #define P_CXO 2 137 138 static const u8 gcc_pxo_pll8_map[] = { 139 [P_PXO] = 0, 140 [P_PLL8] = 3, 141 }; 142 143 static const char *gcc_pxo_pll8[] = { 144 "pxo", 145 "pll8_vote", 146 }; 147 148 static const u8 gcc_pxo_pll8_cxo_map[] = { 149 [P_PXO] = 0, 150 [P_PLL8] = 3, 151 [P_CXO] = 5, 152 }; 153 154 static const char *gcc_pxo_pll8_cxo[] = { 155 "pxo", 156 "pll8_vote", 157 "cxo", 158 }; 159 160 static const u8 gcc_pxo_pll3_map[] = { 161 [P_PXO] = 0, 162 [P_PLL3] = 1, 163 }; 164 165 static const u8 gcc_pxo_pll3_sata_map[] = { 166 [P_PXO] = 0, 167 [P_PLL3] = 6, 168 }; 169 170 static const char *gcc_pxo_pll3[] = { 171 "pxo", 172 "pll3", 173 }; 174 175 static const u8 gcc_pxo_pll8_pll0[] = { 176 [P_PXO] = 0, 177 [P_PLL8] = 3, 178 [P_PLL0] = 2, 179 }; 180 181 static const char *gcc_pxo_pll8_pll0_map[] = { 182 "pxo", 183 "pll8_vote", 184 "pll0_vote", 185 }; 186 187 static struct freq_tbl clk_tbl_gsbi_uart[] = { 188 { 1843200, P_PLL8, 2, 6, 625 }, 189 { 3686400, P_PLL8, 2, 12, 625 }, 190 { 7372800, P_PLL8, 2, 24, 625 }, 191 { 14745600, P_PLL8, 2, 48, 625 }, 192 { 16000000, P_PLL8, 4, 1, 6 }, 193 { 24000000, P_PLL8, 4, 1, 4 }, 194 { 32000000, P_PLL8, 4, 1, 3 }, 195 { 40000000, P_PLL8, 1, 5, 48 }, 196 { 46400000, P_PLL8, 1, 29, 240 }, 197 { 48000000, P_PLL8, 4, 1, 2 }, 198 { 51200000, P_PLL8, 1, 2, 15 }, 199 { 56000000, P_PLL8, 1, 7, 48 }, 200 { 58982400, P_PLL8, 1, 96, 625 }, 201 { 64000000, P_PLL8, 2, 1, 3 }, 202 { } 203 }; 204 205 static struct clk_rcg gsbi1_uart_src = { 206 .ns_reg = 0x29d4, 207 .md_reg = 0x29d0, 208 .mn = { 209 .mnctr_en_bit = 8, 210 .mnctr_reset_bit = 7, 211 .mnctr_mode_shift = 5, 212 .n_val_shift = 16, 213 .m_val_shift = 16, 214 .width = 16, 215 }, 216 .p = { 217 .pre_div_shift = 3, 218 .pre_div_width = 2, 219 }, 220 .s = { 221 .src_sel_shift = 0, 222 .parent_map = gcc_pxo_pll8_map, 223 }, 224 .freq_tbl = clk_tbl_gsbi_uart, 225 .clkr = { 226 .enable_reg = 0x29d4, 227 .enable_mask = BIT(11), 228 .hw.init = &(struct clk_init_data){ 229 .name = "gsbi1_uart_src", 230 .parent_names = gcc_pxo_pll8, 231 .num_parents = 2, 232 .ops = &clk_rcg_ops, 233 .flags = CLK_SET_PARENT_GATE, 234 }, 235 }, 236 }; 237 238 static struct clk_branch gsbi1_uart_clk = { 239 .halt_reg = 0x2fcc, 240 .halt_bit = 12, 241 .clkr = { 242 .enable_reg = 0x29d4, 243 .enable_mask = BIT(9), 244 .hw.init = &(struct clk_init_data){ 245 .name = "gsbi1_uart_clk", 246 .parent_names = (const char *[]){ 247 "gsbi1_uart_src", 248 }, 249 .num_parents = 1, 250 .ops = &clk_branch_ops, 251 .flags = CLK_SET_RATE_PARENT, 252 }, 253 }, 254 }; 255 256 static struct clk_rcg gsbi2_uart_src = { 257 .ns_reg = 0x29f4, 258 .md_reg = 0x29f0, 259 .mn = { 260 .mnctr_en_bit = 8, 261 .mnctr_reset_bit = 7, 262 .mnctr_mode_shift = 5, 263 .n_val_shift = 16, 264 .m_val_shift = 16, 265 .width = 16, 266 }, 267 .p = { 268 .pre_div_shift = 3, 269 .pre_div_width = 2, 270 }, 271 .s = { 272 .src_sel_shift = 0, 273 .parent_map = gcc_pxo_pll8_map, 274 }, 275 .freq_tbl = clk_tbl_gsbi_uart, 276 .clkr = { 277 .enable_reg = 0x29f4, 278 .enable_mask = BIT(11), 279 .hw.init = &(struct clk_init_data){ 280 .name = "gsbi2_uart_src", 281 .parent_names = gcc_pxo_pll8, 282 .num_parents = 2, 283 .ops = &clk_rcg_ops, 284 .flags = CLK_SET_PARENT_GATE, 285 }, 286 }, 287 }; 288 289 static struct clk_branch gsbi2_uart_clk = { 290 .halt_reg = 0x2fcc, 291 .halt_bit = 8, 292 .clkr = { 293 .enable_reg = 0x29f4, 294 .enable_mask = BIT(9), 295 .hw.init = &(struct clk_init_data){ 296 .name = "gsbi2_uart_clk", 297 .parent_names = (const char *[]){ 298 "gsbi2_uart_src", 299 }, 300 .num_parents = 1, 301 .ops = &clk_branch_ops, 302 .flags = CLK_SET_RATE_PARENT, 303 }, 304 }, 305 }; 306 307 static struct clk_rcg gsbi4_uart_src = { 308 .ns_reg = 0x2a34, 309 .md_reg = 0x2a30, 310 .mn = { 311 .mnctr_en_bit = 8, 312 .mnctr_reset_bit = 7, 313 .mnctr_mode_shift = 5, 314 .n_val_shift = 16, 315 .m_val_shift = 16, 316 .width = 16, 317 }, 318 .p = { 319 .pre_div_shift = 3, 320 .pre_div_width = 2, 321 }, 322 .s = { 323 .src_sel_shift = 0, 324 .parent_map = gcc_pxo_pll8_map, 325 }, 326 .freq_tbl = clk_tbl_gsbi_uart, 327 .clkr = { 328 .enable_reg = 0x2a34, 329 .enable_mask = BIT(11), 330 .hw.init = &(struct clk_init_data){ 331 .name = "gsbi4_uart_src", 332 .parent_names = gcc_pxo_pll8, 333 .num_parents = 2, 334 .ops = &clk_rcg_ops, 335 .flags = CLK_SET_PARENT_GATE, 336 }, 337 }, 338 }; 339 340 static struct clk_branch gsbi4_uart_clk = { 341 .halt_reg = 0x2fd0, 342 .halt_bit = 26, 343 .clkr = { 344 .enable_reg = 0x2a34, 345 .enable_mask = BIT(9), 346 .hw.init = &(struct clk_init_data){ 347 .name = "gsbi4_uart_clk", 348 .parent_names = (const char *[]){ 349 "gsbi4_uart_src", 350 }, 351 .num_parents = 1, 352 .ops = &clk_branch_ops, 353 .flags = CLK_SET_RATE_PARENT, 354 }, 355 }, 356 }; 357 358 static struct clk_rcg gsbi5_uart_src = { 359 .ns_reg = 0x2a54, 360 .md_reg = 0x2a50, 361 .mn = { 362 .mnctr_en_bit = 8, 363 .mnctr_reset_bit = 7, 364 .mnctr_mode_shift = 5, 365 .n_val_shift = 16, 366 .m_val_shift = 16, 367 .width = 16, 368 }, 369 .p = { 370 .pre_div_shift = 3, 371 .pre_div_width = 2, 372 }, 373 .s = { 374 .src_sel_shift = 0, 375 .parent_map = gcc_pxo_pll8_map, 376 }, 377 .freq_tbl = clk_tbl_gsbi_uart, 378 .clkr = { 379 .enable_reg = 0x2a54, 380 .enable_mask = BIT(11), 381 .hw.init = &(struct clk_init_data){ 382 .name = "gsbi5_uart_src", 383 .parent_names = gcc_pxo_pll8, 384 .num_parents = 2, 385 .ops = &clk_rcg_ops, 386 .flags = CLK_SET_PARENT_GATE, 387 }, 388 }, 389 }; 390 391 static struct clk_branch gsbi5_uart_clk = { 392 .halt_reg = 0x2fd0, 393 .halt_bit = 22, 394 .clkr = { 395 .enable_reg = 0x2a54, 396 .enable_mask = BIT(9), 397 .hw.init = &(struct clk_init_data){ 398 .name = "gsbi5_uart_clk", 399 .parent_names = (const char *[]){ 400 "gsbi5_uart_src", 401 }, 402 .num_parents = 1, 403 .ops = &clk_branch_ops, 404 .flags = CLK_SET_RATE_PARENT, 405 }, 406 }, 407 }; 408 409 static struct clk_rcg gsbi6_uart_src = { 410 .ns_reg = 0x2a74, 411 .md_reg = 0x2a70, 412 .mn = { 413 .mnctr_en_bit = 8, 414 .mnctr_reset_bit = 7, 415 .mnctr_mode_shift = 5, 416 .n_val_shift = 16, 417 .m_val_shift = 16, 418 .width = 16, 419 }, 420 .p = { 421 .pre_div_shift = 3, 422 .pre_div_width = 2, 423 }, 424 .s = { 425 .src_sel_shift = 0, 426 .parent_map = gcc_pxo_pll8_map, 427 }, 428 .freq_tbl = clk_tbl_gsbi_uart, 429 .clkr = { 430 .enable_reg = 0x2a74, 431 .enable_mask = BIT(11), 432 .hw.init = &(struct clk_init_data){ 433 .name = "gsbi6_uart_src", 434 .parent_names = gcc_pxo_pll8, 435 .num_parents = 2, 436 .ops = &clk_rcg_ops, 437 .flags = CLK_SET_PARENT_GATE, 438 }, 439 }, 440 }; 441 442 static struct clk_branch gsbi6_uart_clk = { 443 .halt_reg = 0x2fd0, 444 .halt_bit = 18, 445 .clkr = { 446 .enable_reg = 0x2a74, 447 .enable_mask = BIT(9), 448 .hw.init = &(struct clk_init_data){ 449 .name = "gsbi6_uart_clk", 450 .parent_names = (const char *[]){ 451 "gsbi6_uart_src", 452 }, 453 .num_parents = 1, 454 .ops = &clk_branch_ops, 455 .flags = CLK_SET_RATE_PARENT, 456 }, 457 }, 458 }; 459 460 static struct clk_rcg gsbi7_uart_src = { 461 .ns_reg = 0x2a94, 462 .md_reg = 0x2a90, 463 .mn = { 464 .mnctr_en_bit = 8, 465 .mnctr_reset_bit = 7, 466 .mnctr_mode_shift = 5, 467 .n_val_shift = 16, 468 .m_val_shift = 16, 469 .width = 16, 470 }, 471 .p = { 472 .pre_div_shift = 3, 473 .pre_div_width = 2, 474 }, 475 .s = { 476 .src_sel_shift = 0, 477 .parent_map = gcc_pxo_pll8_map, 478 }, 479 .freq_tbl = clk_tbl_gsbi_uart, 480 .clkr = { 481 .enable_reg = 0x2a94, 482 .enable_mask = BIT(11), 483 .hw.init = &(struct clk_init_data){ 484 .name = "gsbi7_uart_src", 485 .parent_names = gcc_pxo_pll8, 486 .num_parents = 2, 487 .ops = &clk_rcg_ops, 488 .flags = CLK_SET_PARENT_GATE, 489 }, 490 }, 491 }; 492 493 static struct clk_branch gsbi7_uart_clk = { 494 .halt_reg = 0x2fd0, 495 .halt_bit = 14, 496 .clkr = { 497 .enable_reg = 0x2a94, 498 .enable_mask = BIT(9), 499 .hw.init = &(struct clk_init_data){ 500 .name = "gsbi7_uart_clk", 501 .parent_names = (const char *[]){ 502 "gsbi7_uart_src", 503 }, 504 .num_parents = 1, 505 .ops = &clk_branch_ops, 506 .flags = CLK_SET_RATE_PARENT, 507 }, 508 }, 509 }; 510 511 static struct freq_tbl clk_tbl_gsbi_qup[] = { 512 { 1100000, P_PXO, 1, 2, 49 }, 513 { 5400000, P_PXO, 1, 1, 5 }, 514 { 10800000, P_PXO, 1, 2, 5 }, 515 { 15060000, P_PLL8, 1, 2, 51 }, 516 { 24000000, P_PLL8, 4, 1, 4 }, 517 { 25600000, P_PLL8, 1, 1, 15 }, 518 { 27000000, P_PXO, 1, 0, 0 }, 519 { 48000000, P_PLL8, 4, 1, 2 }, 520 { 51200000, P_PLL8, 1, 2, 15 }, 521 { } 522 }; 523 524 static struct clk_rcg gsbi1_qup_src = { 525 .ns_reg = 0x29cc, 526 .md_reg = 0x29c8, 527 .mn = { 528 .mnctr_en_bit = 8, 529 .mnctr_reset_bit = 7, 530 .mnctr_mode_shift = 5, 531 .n_val_shift = 16, 532 .m_val_shift = 16, 533 .width = 8, 534 }, 535 .p = { 536 .pre_div_shift = 3, 537 .pre_div_width = 2, 538 }, 539 .s = { 540 .src_sel_shift = 0, 541 .parent_map = gcc_pxo_pll8_map, 542 }, 543 .freq_tbl = clk_tbl_gsbi_qup, 544 .clkr = { 545 .enable_reg = 0x29cc, 546 .enable_mask = BIT(11), 547 .hw.init = &(struct clk_init_data){ 548 .name = "gsbi1_qup_src", 549 .parent_names = gcc_pxo_pll8, 550 .num_parents = 2, 551 .ops = &clk_rcg_ops, 552 .flags = CLK_SET_PARENT_GATE, 553 }, 554 }, 555 }; 556 557 static struct clk_branch gsbi1_qup_clk = { 558 .halt_reg = 0x2fcc, 559 .halt_bit = 11, 560 .clkr = { 561 .enable_reg = 0x29cc, 562 .enable_mask = BIT(9), 563 .hw.init = &(struct clk_init_data){ 564 .name = "gsbi1_qup_clk", 565 .parent_names = (const char *[]){ "gsbi1_qup_src" }, 566 .num_parents = 1, 567 .ops = &clk_branch_ops, 568 .flags = CLK_SET_RATE_PARENT, 569 }, 570 }, 571 }; 572 573 static struct clk_rcg gsbi2_qup_src = { 574 .ns_reg = 0x29ec, 575 .md_reg = 0x29e8, 576 .mn = { 577 .mnctr_en_bit = 8, 578 .mnctr_reset_bit = 7, 579 .mnctr_mode_shift = 5, 580 .n_val_shift = 16, 581 .m_val_shift = 16, 582 .width = 8, 583 }, 584 .p = { 585 .pre_div_shift = 3, 586 .pre_div_width = 2, 587 }, 588 .s = { 589 .src_sel_shift = 0, 590 .parent_map = gcc_pxo_pll8_map, 591 }, 592 .freq_tbl = clk_tbl_gsbi_qup, 593 .clkr = { 594 .enable_reg = 0x29ec, 595 .enable_mask = BIT(11), 596 .hw.init = &(struct clk_init_data){ 597 .name = "gsbi2_qup_src", 598 .parent_names = gcc_pxo_pll8, 599 .num_parents = 2, 600 .ops = &clk_rcg_ops, 601 .flags = CLK_SET_PARENT_GATE, 602 }, 603 }, 604 }; 605 606 static struct clk_branch gsbi2_qup_clk = { 607 .halt_reg = 0x2fcc, 608 .halt_bit = 6, 609 .clkr = { 610 .enable_reg = 0x29ec, 611 .enable_mask = BIT(9), 612 .hw.init = &(struct clk_init_data){ 613 .name = "gsbi2_qup_clk", 614 .parent_names = (const char *[]){ "gsbi2_qup_src" }, 615 .num_parents = 1, 616 .ops = &clk_branch_ops, 617 .flags = CLK_SET_RATE_PARENT, 618 }, 619 }, 620 }; 621 622 static struct clk_rcg gsbi4_qup_src = { 623 .ns_reg = 0x2a2c, 624 .md_reg = 0x2a28, 625 .mn = { 626 .mnctr_en_bit = 8, 627 .mnctr_reset_bit = 7, 628 .mnctr_mode_shift = 5, 629 .n_val_shift = 16, 630 .m_val_shift = 16, 631 .width = 8, 632 }, 633 .p = { 634 .pre_div_shift = 3, 635 .pre_div_width = 2, 636 }, 637 .s = { 638 .src_sel_shift = 0, 639 .parent_map = gcc_pxo_pll8_map, 640 }, 641 .freq_tbl = clk_tbl_gsbi_qup, 642 .clkr = { 643 .enable_reg = 0x2a2c, 644 .enable_mask = BIT(11), 645 .hw.init = &(struct clk_init_data){ 646 .name = "gsbi4_qup_src", 647 .parent_names = gcc_pxo_pll8, 648 .num_parents = 2, 649 .ops = &clk_rcg_ops, 650 .flags = CLK_SET_PARENT_GATE, 651 }, 652 }, 653 }; 654 655 static struct clk_branch gsbi4_qup_clk = { 656 .halt_reg = 0x2fd0, 657 .halt_bit = 24, 658 .clkr = { 659 .enable_reg = 0x2a2c, 660 .enable_mask = BIT(9), 661 .hw.init = &(struct clk_init_data){ 662 .name = "gsbi4_qup_clk", 663 .parent_names = (const char *[]){ "gsbi4_qup_src" }, 664 .num_parents = 1, 665 .ops = &clk_branch_ops, 666 .flags = CLK_SET_RATE_PARENT, 667 }, 668 }, 669 }; 670 671 static struct clk_rcg gsbi5_qup_src = { 672 .ns_reg = 0x2a4c, 673 .md_reg = 0x2a48, 674 .mn = { 675 .mnctr_en_bit = 8, 676 .mnctr_reset_bit = 7, 677 .mnctr_mode_shift = 5, 678 .n_val_shift = 16, 679 .m_val_shift = 16, 680 .width = 8, 681 }, 682 .p = { 683 .pre_div_shift = 3, 684 .pre_div_width = 2, 685 }, 686 .s = { 687 .src_sel_shift = 0, 688 .parent_map = gcc_pxo_pll8_map, 689 }, 690 .freq_tbl = clk_tbl_gsbi_qup, 691 .clkr = { 692 .enable_reg = 0x2a4c, 693 .enable_mask = BIT(11), 694 .hw.init = &(struct clk_init_data){ 695 .name = "gsbi5_qup_src", 696 .parent_names = gcc_pxo_pll8, 697 .num_parents = 2, 698 .ops = &clk_rcg_ops, 699 .flags = CLK_SET_PARENT_GATE, 700 }, 701 }, 702 }; 703 704 static struct clk_branch gsbi5_qup_clk = { 705 .halt_reg = 0x2fd0, 706 .halt_bit = 20, 707 .clkr = { 708 .enable_reg = 0x2a4c, 709 .enable_mask = BIT(9), 710 .hw.init = &(struct clk_init_data){ 711 .name = "gsbi5_qup_clk", 712 .parent_names = (const char *[]){ "gsbi5_qup_src" }, 713 .num_parents = 1, 714 .ops = &clk_branch_ops, 715 .flags = CLK_SET_RATE_PARENT, 716 }, 717 }, 718 }; 719 720 static struct clk_rcg gsbi6_qup_src = { 721 .ns_reg = 0x2a6c, 722 .md_reg = 0x2a68, 723 .mn = { 724 .mnctr_en_bit = 8, 725 .mnctr_reset_bit = 7, 726 .mnctr_mode_shift = 5, 727 .n_val_shift = 16, 728 .m_val_shift = 16, 729 .width = 8, 730 }, 731 .p = { 732 .pre_div_shift = 3, 733 .pre_div_width = 2, 734 }, 735 .s = { 736 .src_sel_shift = 0, 737 .parent_map = gcc_pxo_pll8_map, 738 }, 739 .freq_tbl = clk_tbl_gsbi_qup, 740 .clkr = { 741 .enable_reg = 0x2a6c, 742 .enable_mask = BIT(11), 743 .hw.init = &(struct clk_init_data){ 744 .name = "gsbi6_qup_src", 745 .parent_names = gcc_pxo_pll8, 746 .num_parents = 2, 747 .ops = &clk_rcg_ops, 748 .flags = CLK_SET_PARENT_GATE, 749 }, 750 }, 751 }; 752 753 static struct clk_branch gsbi6_qup_clk = { 754 .halt_reg = 0x2fd0, 755 .halt_bit = 16, 756 .clkr = { 757 .enable_reg = 0x2a6c, 758 .enable_mask = BIT(9), 759 .hw.init = &(struct clk_init_data){ 760 .name = "gsbi6_qup_clk", 761 .parent_names = (const char *[]){ "gsbi6_qup_src" }, 762 .num_parents = 1, 763 .ops = &clk_branch_ops, 764 .flags = CLK_SET_RATE_PARENT, 765 }, 766 }, 767 }; 768 769 static struct clk_rcg gsbi7_qup_src = { 770 .ns_reg = 0x2a8c, 771 .md_reg = 0x2a88, 772 .mn = { 773 .mnctr_en_bit = 8, 774 .mnctr_reset_bit = 7, 775 .mnctr_mode_shift = 5, 776 .n_val_shift = 16, 777 .m_val_shift = 16, 778 .width = 8, 779 }, 780 .p = { 781 .pre_div_shift = 3, 782 .pre_div_width = 2, 783 }, 784 .s = { 785 .src_sel_shift = 0, 786 .parent_map = gcc_pxo_pll8_map, 787 }, 788 .freq_tbl = clk_tbl_gsbi_qup, 789 .clkr = { 790 .enable_reg = 0x2a8c, 791 .enable_mask = BIT(11), 792 .hw.init = &(struct clk_init_data){ 793 .name = "gsbi7_qup_src", 794 .parent_names = gcc_pxo_pll8, 795 .num_parents = 2, 796 .ops = &clk_rcg_ops, 797 .flags = CLK_SET_PARENT_GATE, 798 }, 799 }, 800 }; 801 802 static struct clk_branch gsbi7_qup_clk = { 803 .halt_reg = 0x2fd0, 804 .halt_bit = 12, 805 .clkr = { 806 .enable_reg = 0x2a8c, 807 .enable_mask = BIT(9), 808 .hw.init = &(struct clk_init_data){ 809 .name = "gsbi7_qup_clk", 810 .parent_names = (const char *[]){ "gsbi7_qup_src" }, 811 .num_parents = 1, 812 .ops = &clk_branch_ops, 813 .flags = CLK_SET_RATE_PARENT, 814 }, 815 }, 816 }; 817 818 static struct clk_branch gsbi1_h_clk = { 819 .hwcg_reg = 0x29c0, 820 .hwcg_bit = 6, 821 .halt_reg = 0x2fcc, 822 .halt_bit = 13, 823 .clkr = { 824 .enable_reg = 0x29c0, 825 .enable_mask = BIT(4), 826 .hw.init = &(struct clk_init_data){ 827 .name = "gsbi1_h_clk", 828 .ops = &clk_branch_ops, 829 .flags = CLK_IS_ROOT, 830 }, 831 }, 832 }; 833 834 static struct clk_branch gsbi2_h_clk = { 835 .hwcg_reg = 0x29e0, 836 .hwcg_bit = 6, 837 .halt_reg = 0x2fcc, 838 .halt_bit = 9, 839 .clkr = { 840 .enable_reg = 0x29e0, 841 .enable_mask = BIT(4), 842 .hw.init = &(struct clk_init_data){ 843 .name = "gsbi2_h_clk", 844 .ops = &clk_branch_ops, 845 .flags = CLK_IS_ROOT, 846 }, 847 }, 848 }; 849 850 static struct clk_branch gsbi4_h_clk = { 851 .hwcg_reg = 0x2a20, 852 .hwcg_bit = 6, 853 .halt_reg = 0x2fd0, 854 .halt_bit = 27, 855 .clkr = { 856 .enable_reg = 0x2a20, 857 .enable_mask = BIT(4), 858 .hw.init = &(struct clk_init_data){ 859 .name = "gsbi4_h_clk", 860 .ops = &clk_branch_ops, 861 .flags = CLK_IS_ROOT, 862 }, 863 }, 864 }; 865 866 static struct clk_branch gsbi5_h_clk = { 867 .hwcg_reg = 0x2a40, 868 .hwcg_bit = 6, 869 .halt_reg = 0x2fd0, 870 .halt_bit = 23, 871 .clkr = { 872 .enable_reg = 0x2a40, 873 .enable_mask = BIT(4), 874 .hw.init = &(struct clk_init_data){ 875 .name = "gsbi5_h_clk", 876 .ops = &clk_branch_ops, 877 .flags = CLK_IS_ROOT, 878 }, 879 }, 880 }; 881 882 static struct clk_branch gsbi6_h_clk = { 883 .hwcg_reg = 0x2a60, 884 .hwcg_bit = 6, 885 .halt_reg = 0x2fd0, 886 .halt_bit = 19, 887 .clkr = { 888 .enable_reg = 0x2a60, 889 .enable_mask = BIT(4), 890 .hw.init = &(struct clk_init_data){ 891 .name = "gsbi6_h_clk", 892 .ops = &clk_branch_ops, 893 .flags = CLK_IS_ROOT, 894 }, 895 }, 896 }; 897 898 static struct clk_branch gsbi7_h_clk = { 899 .hwcg_reg = 0x2a80, 900 .hwcg_bit = 6, 901 .halt_reg = 0x2fd0, 902 .halt_bit = 15, 903 .clkr = { 904 .enable_reg = 0x2a80, 905 .enable_mask = BIT(4), 906 .hw.init = &(struct clk_init_data){ 907 .name = "gsbi7_h_clk", 908 .ops = &clk_branch_ops, 909 .flags = CLK_IS_ROOT, 910 }, 911 }, 912 }; 913 914 static const struct freq_tbl clk_tbl_gp[] = { 915 { 12500000, P_PXO, 2, 0, 0 }, 916 { 25000000, P_PXO, 1, 0, 0 }, 917 { 64000000, P_PLL8, 2, 1, 3 }, 918 { 76800000, P_PLL8, 1, 1, 5 }, 919 { 96000000, P_PLL8, 4, 0, 0 }, 920 { 128000000, P_PLL8, 3, 0, 0 }, 921 { 192000000, P_PLL8, 2, 0, 0 }, 922 { } 923 }; 924 925 static struct clk_rcg gp0_src = { 926 .ns_reg = 0x2d24, 927 .md_reg = 0x2d00, 928 .mn = { 929 .mnctr_en_bit = 8, 930 .mnctr_reset_bit = 7, 931 .mnctr_mode_shift = 5, 932 .n_val_shift = 16, 933 .m_val_shift = 16, 934 .width = 8, 935 }, 936 .p = { 937 .pre_div_shift = 3, 938 .pre_div_width = 2, 939 }, 940 .s = { 941 .src_sel_shift = 0, 942 .parent_map = gcc_pxo_pll8_cxo_map, 943 }, 944 .freq_tbl = clk_tbl_gp, 945 .clkr = { 946 .enable_reg = 0x2d24, 947 .enable_mask = BIT(11), 948 .hw.init = &(struct clk_init_data){ 949 .name = "gp0_src", 950 .parent_names = gcc_pxo_pll8_cxo, 951 .num_parents = 3, 952 .ops = &clk_rcg_ops, 953 .flags = CLK_SET_PARENT_GATE, 954 }, 955 } 956 }; 957 958 static struct clk_branch gp0_clk = { 959 .halt_reg = 0x2fd8, 960 .halt_bit = 7, 961 .clkr = { 962 .enable_reg = 0x2d24, 963 .enable_mask = BIT(9), 964 .hw.init = &(struct clk_init_data){ 965 .name = "gp0_clk", 966 .parent_names = (const char *[]){ "gp0_src" }, 967 .num_parents = 1, 968 .ops = &clk_branch_ops, 969 .flags = CLK_SET_RATE_PARENT, 970 }, 971 }, 972 }; 973 974 static struct clk_rcg gp1_src = { 975 .ns_reg = 0x2d44, 976 .md_reg = 0x2d40, 977 .mn = { 978 .mnctr_en_bit = 8, 979 .mnctr_reset_bit = 7, 980 .mnctr_mode_shift = 5, 981 .n_val_shift = 16, 982 .m_val_shift = 16, 983 .width = 8, 984 }, 985 .p = { 986 .pre_div_shift = 3, 987 .pre_div_width = 2, 988 }, 989 .s = { 990 .src_sel_shift = 0, 991 .parent_map = gcc_pxo_pll8_cxo_map, 992 }, 993 .freq_tbl = clk_tbl_gp, 994 .clkr = { 995 .enable_reg = 0x2d44, 996 .enable_mask = BIT(11), 997 .hw.init = &(struct clk_init_data){ 998 .name = "gp1_src", 999 .parent_names = gcc_pxo_pll8_cxo, 1000 .num_parents = 3, 1001 .ops = &clk_rcg_ops, 1002 .flags = CLK_SET_RATE_GATE, 1003 }, 1004 } 1005 }; 1006 1007 static struct clk_branch gp1_clk = { 1008 .halt_reg = 0x2fd8, 1009 .halt_bit = 6, 1010 .clkr = { 1011 .enable_reg = 0x2d44, 1012 .enable_mask = BIT(9), 1013 .hw.init = &(struct clk_init_data){ 1014 .name = "gp1_clk", 1015 .parent_names = (const char *[]){ "gp1_src" }, 1016 .num_parents = 1, 1017 .ops = &clk_branch_ops, 1018 .flags = CLK_SET_RATE_PARENT, 1019 }, 1020 }, 1021 }; 1022 1023 static struct clk_rcg gp2_src = { 1024 .ns_reg = 0x2d64, 1025 .md_reg = 0x2d60, 1026 .mn = { 1027 .mnctr_en_bit = 8, 1028 .mnctr_reset_bit = 7, 1029 .mnctr_mode_shift = 5, 1030 .n_val_shift = 16, 1031 .m_val_shift = 16, 1032 .width = 8, 1033 }, 1034 .p = { 1035 .pre_div_shift = 3, 1036 .pre_div_width = 2, 1037 }, 1038 .s = { 1039 .src_sel_shift = 0, 1040 .parent_map = gcc_pxo_pll8_cxo_map, 1041 }, 1042 .freq_tbl = clk_tbl_gp, 1043 .clkr = { 1044 .enable_reg = 0x2d64, 1045 .enable_mask = BIT(11), 1046 .hw.init = &(struct clk_init_data){ 1047 .name = "gp2_src", 1048 .parent_names = gcc_pxo_pll8_cxo, 1049 .num_parents = 3, 1050 .ops = &clk_rcg_ops, 1051 .flags = CLK_SET_RATE_GATE, 1052 }, 1053 } 1054 }; 1055 1056 static struct clk_branch gp2_clk = { 1057 .halt_reg = 0x2fd8, 1058 .halt_bit = 5, 1059 .clkr = { 1060 .enable_reg = 0x2d64, 1061 .enable_mask = BIT(9), 1062 .hw.init = &(struct clk_init_data){ 1063 .name = "gp2_clk", 1064 .parent_names = (const char *[]){ "gp2_src" }, 1065 .num_parents = 1, 1066 .ops = &clk_branch_ops, 1067 .flags = CLK_SET_RATE_PARENT, 1068 }, 1069 }, 1070 }; 1071 1072 static struct clk_branch pmem_clk = { 1073 .hwcg_reg = 0x25a0, 1074 .hwcg_bit = 6, 1075 .halt_reg = 0x2fc8, 1076 .halt_bit = 20, 1077 .clkr = { 1078 .enable_reg = 0x25a0, 1079 .enable_mask = BIT(4), 1080 .hw.init = &(struct clk_init_data){ 1081 .name = "pmem_clk", 1082 .ops = &clk_branch_ops, 1083 .flags = CLK_IS_ROOT, 1084 }, 1085 }, 1086 }; 1087 1088 static struct clk_rcg prng_src = { 1089 .ns_reg = 0x2e80, 1090 .p = { 1091 .pre_div_shift = 3, 1092 .pre_div_width = 4, 1093 }, 1094 .s = { 1095 .src_sel_shift = 0, 1096 .parent_map = gcc_pxo_pll8_map, 1097 }, 1098 .clkr = { 1099 .hw.init = &(struct clk_init_data){ 1100 .name = "prng_src", 1101 .parent_names = gcc_pxo_pll8, 1102 .num_parents = 2, 1103 .ops = &clk_rcg_ops, 1104 }, 1105 }, 1106 }; 1107 1108 static struct clk_branch prng_clk = { 1109 .halt_reg = 0x2fd8, 1110 .halt_check = BRANCH_HALT_VOTED, 1111 .halt_bit = 10, 1112 .clkr = { 1113 .enable_reg = 0x3080, 1114 .enable_mask = BIT(10), 1115 .hw.init = &(struct clk_init_data){ 1116 .name = "prng_clk", 1117 .parent_names = (const char *[]){ "prng_src" }, 1118 .num_parents = 1, 1119 .ops = &clk_branch_ops, 1120 }, 1121 }, 1122 }; 1123 1124 static const struct freq_tbl clk_tbl_sdc[] = { 1125 { 200000, P_PXO, 2, 2, 125 }, 1126 { 400000, P_PLL8, 4, 1, 240 }, 1127 { 16000000, P_PLL8, 4, 1, 6 }, 1128 { 17070000, P_PLL8, 1, 2, 45 }, 1129 { 20210000, P_PLL8, 1, 1, 19 }, 1130 { 24000000, P_PLL8, 4, 1, 4 }, 1131 { 48000000, P_PLL8, 4, 1, 2 }, 1132 { 64000000, P_PLL8, 3, 1, 2 }, 1133 { 96000000, P_PLL8, 4, 0, 0 }, 1134 { 192000000, P_PLL8, 2, 0, 0 }, 1135 { } 1136 }; 1137 1138 static struct clk_rcg sdc1_src = { 1139 .ns_reg = 0x282c, 1140 .md_reg = 0x2828, 1141 .mn = { 1142 .mnctr_en_bit = 8, 1143 .mnctr_reset_bit = 7, 1144 .mnctr_mode_shift = 5, 1145 .n_val_shift = 16, 1146 .m_val_shift = 16, 1147 .width = 8, 1148 }, 1149 .p = { 1150 .pre_div_shift = 3, 1151 .pre_div_width = 2, 1152 }, 1153 .s = { 1154 .src_sel_shift = 0, 1155 .parent_map = gcc_pxo_pll8_map, 1156 }, 1157 .freq_tbl = clk_tbl_sdc, 1158 .clkr = { 1159 .enable_reg = 0x282c, 1160 .enable_mask = BIT(11), 1161 .hw.init = &(struct clk_init_data){ 1162 .name = "sdc1_src", 1163 .parent_names = gcc_pxo_pll8, 1164 .num_parents = 2, 1165 .ops = &clk_rcg_ops, 1166 .flags = CLK_SET_RATE_GATE, 1167 }, 1168 } 1169 }; 1170 1171 static struct clk_branch sdc1_clk = { 1172 .halt_reg = 0x2fc8, 1173 .halt_bit = 6, 1174 .clkr = { 1175 .enable_reg = 0x282c, 1176 .enable_mask = BIT(9), 1177 .hw.init = &(struct clk_init_data){ 1178 .name = "sdc1_clk", 1179 .parent_names = (const char *[]){ "sdc1_src" }, 1180 .num_parents = 1, 1181 .ops = &clk_branch_ops, 1182 .flags = CLK_SET_RATE_PARENT, 1183 }, 1184 }, 1185 }; 1186 1187 static struct clk_rcg sdc3_src = { 1188 .ns_reg = 0x286c, 1189 .md_reg = 0x2868, 1190 .mn = { 1191 .mnctr_en_bit = 8, 1192 .mnctr_reset_bit = 7, 1193 .mnctr_mode_shift = 5, 1194 .n_val_shift = 16, 1195 .m_val_shift = 16, 1196 .width = 8, 1197 }, 1198 .p = { 1199 .pre_div_shift = 3, 1200 .pre_div_width = 2, 1201 }, 1202 .s = { 1203 .src_sel_shift = 0, 1204 .parent_map = gcc_pxo_pll8_map, 1205 }, 1206 .freq_tbl = clk_tbl_sdc, 1207 .clkr = { 1208 .enable_reg = 0x286c, 1209 .enable_mask = BIT(11), 1210 .hw.init = &(struct clk_init_data){ 1211 .name = "sdc3_src", 1212 .parent_names = gcc_pxo_pll8, 1213 .num_parents = 2, 1214 .ops = &clk_rcg_ops, 1215 .flags = CLK_SET_RATE_GATE, 1216 }, 1217 } 1218 }; 1219 1220 static struct clk_branch sdc3_clk = { 1221 .halt_reg = 0x2fc8, 1222 .halt_bit = 4, 1223 .clkr = { 1224 .enable_reg = 0x286c, 1225 .enable_mask = BIT(9), 1226 .hw.init = &(struct clk_init_data){ 1227 .name = "sdc3_clk", 1228 .parent_names = (const char *[]){ "sdc3_src" }, 1229 .num_parents = 1, 1230 .ops = &clk_branch_ops, 1231 .flags = CLK_SET_RATE_PARENT, 1232 }, 1233 }, 1234 }; 1235 1236 static struct clk_branch sdc1_h_clk = { 1237 .hwcg_reg = 0x2820, 1238 .hwcg_bit = 6, 1239 .halt_reg = 0x2fc8, 1240 .halt_bit = 11, 1241 .clkr = { 1242 .enable_reg = 0x2820, 1243 .enable_mask = BIT(4), 1244 .hw.init = &(struct clk_init_data){ 1245 .name = "sdc1_h_clk", 1246 .ops = &clk_branch_ops, 1247 .flags = CLK_IS_ROOT, 1248 }, 1249 }, 1250 }; 1251 1252 static struct clk_branch sdc3_h_clk = { 1253 .hwcg_reg = 0x2860, 1254 .hwcg_bit = 6, 1255 .halt_reg = 0x2fc8, 1256 .halt_bit = 9, 1257 .clkr = { 1258 .enable_reg = 0x2860, 1259 .enable_mask = BIT(4), 1260 .hw.init = &(struct clk_init_data){ 1261 .name = "sdc3_h_clk", 1262 .ops = &clk_branch_ops, 1263 .flags = CLK_IS_ROOT, 1264 }, 1265 }, 1266 }; 1267 1268 static const struct freq_tbl clk_tbl_tsif_ref[] = { 1269 { 105000, P_PXO, 1, 1, 256 }, 1270 { } 1271 }; 1272 1273 static struct clk_rcg tsif_ref_src = { 1274 .ns_reg = 0x2710, 1275 .md_reg = 0x270c, 1276 .mn = { 1277 .mnctr_en_bit = 8, 1278 .mnctr_reset_bit = 7, 1279 .mnctr_mode_shift = 5, 1280 .n_val_shift = 16, 1281 .m_val_shift = 16, 1282 .width = 16, 1283 }, 1284 .p = { 1285 .pre_div_shift = 3, 1286 .pre_div_width = 2, 1287 }, 1288 .s = { 1289 .src_sel_shift = 0, 1290 .parent_map = gcc_pxo_pll8_map, 1291 }, 1292 .freq_tbl = clk_tbl_tsif_ref, 1293 .clkr = { 1294 .enable_reg = 0x2710, 1295 .enable_mask = BIT(11), 1296 .hw.init = &(struct clk_init_data){ 1297 .name = "tsif_ref_src", 1298 .parent_names = gcc_pxo_pll8, 1299 .num_parents = 2, 1300 .ops = &clk_rcg_ops, 1301 .flags = CLK_SET_RATE_GATE, 1302 }, 1303 } 1304 }; 1305 1306 static struct clk_branch tsif_ref_clk = { 1307 .halt_reg = 0x2fd4, 1308 .halt_bit = 5, 1309 .clkr = { 1310 .enable_reg = 0x2710, 1311 .enable_mask = BIT(9), 1312 .hw.init = &(struct clk_init_data){ 1313 .name = "tsif_ref_clk", 1314 .parent_names = (const char *[]){ "tsif_ref_src" }, 1315 .num_parents = 1, 1316 .ops = &clk_branch_ops, 1317 .flags = CLK_SET_RATE_PARENT, 1318 }, 1319 }, 1320 }; 1321 1322 static struct clk_branch tsif_h_clk = { 1323 .hwcg_reg = 0x2700, 1324 .hwcg_bit = 6, 1325 .halt_reg = 0x2fd4, 1326 .halt_bit = 7, 1327 .clkr = { 1328 .enable_reg = 0x2700, 1329 .enable_mask = BIT(4), 1330 .hw.init = &(struct clk_init_data){ 1331 .name = "tsif_h_clk", 1332 .ops = &clk_branch_ops, 1333 .flags = CLK_IS_ROOT, 1334 }, 1335 }, 1336 }; 1337 1338 static struct clk_branch dma_bam_h_clk = { 1339 .hwcg_reg = 0x25c0, 1340 .hwcg_bit = 6, 1341 .halt_reg = 0x2fc8, 1342 .halt_bit = 12, 1343 .clkr = { 1344 .enable_reg = 0x25c0, 1345 .enable_mask = BIT(4), 1346 .hw.init = &(struct clk_init_data){ 1347 .name = "dma_bam_h_clk", 1348 .ops = &clk_branch_ops, 1349 .flags = CLK_IS_ROOT, 1350 }, 1351 }, 1352 }; 1353 1354 static struct clk_branch adm0_clk = { 1355 .halt_reg = 0x2fdc, 1356 .halt_check = BRANCH_HALT_VOTED, 1357 .halt_bit = 12, 1358 .clkr = { 1359 .enable_reg = 0x3080, 1360 .enable_mask = BIT(2), 1361 .hw.init = &(struct clk_init_data){ 1362 .name = "adm0_clk", 1363 .ops = &clk_branch_ops, 1364 .flags = CLK_IS_ROOT, 1365 }, 1366 }, 1367 }; 1368 1369 static struct clk_branch adm0_pbus_clk = { 1370 .hwcg_reg = 0x2208, 1371 .hwcg_bit = 6, 1372 .halt_reg = 0x2fdc, 1373 .halt_check = BRANCH_HALT_VOTED, 1374 .halt_bit = 11, 1375 .clkr = { 1376 .enable_reg = 0x3080, 1377 .enable_mask = BIT(3), 1378 .hw.init = &(struct clk_init_data){ 1379 .name = "adm0_pbus_clk", 1380 .ops = &clk_branch_ops, 1381 .flags = CLK_IS_ROOT, 1382 }, 1383 }, 1384 }; 1385 1386 static struct clk_branch pmic_arb0_h_clk = { 1387 .halt_reg = 0x2fd8, 1388 .halt_check = BRANCH_HALT_VOTED, 1389 .halt_bit = 22, 1390 .clkr = { 1391 .enable_reg = 0x3080, 1392 .enable_mask = BIT(8), 1393 .hw.init = &(struct clk_init_data){ 1394 .name = "pmic_arb0_h_clk", 1395 .ops = &clk_branch_ops, 1396 .flags = CLK_IS_ROOT, 1397 }, 1398 }, 1399 }; 1400 1401 static struct clk_branch pmic_arb1_h_clk = { 1402 .halt_reg = 0x2fd8, 1403 .halt_check = BRANCH_HALT_VOTED, 1404 .halt_bit = 21, 1405 .clkr = { 1406 .enable_reg = 0x3080, 1407 .enable_mask = BIT(9), 1408 .hw.init = &(struct clk_init_data){ 1409 .name = "pmic_arb1_h_clk", 1410 .ops = &clk_branch_ops, 1411 .flags = CLK_IS_ROOT, 1412 }, 1413 }, 1414 }; 1415 1416 static struct clk_branch pmic_ssbi2_clk = { 1417 .halt_reg = 0x2fd8, 1418 .halt_check = BRANCH_HALT_VOTED, 1419 .halt_bit = 23, 1420 .clkr = { 1421 .enable_reg = 0x3080, 1422 .enable_mask = BIT(7), 1423 .hw.init = &(struct clk_init_data){ 1424 .name = "pmic_ssbi2_clk", 1425 .ops = &clk_branch_ops, 1426 .flags = CLK_IS_ROOT, 1427 }, 1428 }, 1429 }; 1430 1431 static struct clk_branch rpm_msg_ram_h_clk = { 1432 .hwcg_reg = 0x27e0, 1433 .hwcg_bit = 6, 1434 .halt_reg = 0x2fd8, 1435 .halt_check = BRANCH_HALT_VOTED, 1436 .halt_bit = 12, 1437 .clkr = { 1438 .enable_reg = 0x3080, 1439 .enable_mask = BIT(6), 1440 .hw.init = &(struct clk_init_data){ 1441 .name = "rpm_msg_ram_h_clk", 1442 .ops = &clk_branch_ops, 1443 .flags = CLK_IS_ROOT, 1444 }, 1445 }, 1446 }; 1447 1448 static const struct freq_tbl clk_tbl_pcie_ref[] = { 1449 { 100000000, P_PLL3, 12, 0, 0 }, 1450 { } 1451 }; 1452 1453 static struct clk_rcg pcie_ref_src = { 1454 .ns_reg = 0x3860, 1455 .p = { 1456 .pre_div_shift = 3, 1457 .pre_div_width = 4, 1458 }, 1459 .s = { 1460 .src_sel_shift = 0, 1461 .parent_map = gcc_pxo_pll3_map, 1462 }, 1463 .freq_tbl = clk_tbl_pcie_ref, 1464 .clkr = { 1465 .enable_reg = 0x3860, 1466 .enable_mask = BIT(11), 1467 .hw.init = &(struct clk_init_data){ 1468 .name = "pcie_ref_src", 1469 .parent_names = gcc_pxo_pll3, 1470 .num_parents = 2, 1471 .ops = &clk_rcg_ops, 1472 .flags = CLK_SET_RATE_GATE, 1473 }, 1474 }, 1475 }; 1476 1477 static struct clk_branch pcie_ref_src_clk = { 1478 .halt_reg = 0x2fdc, 1479 .halt_bit = 30, 1480 .clkr = { 1481 .enable_reg = 0x3860, 1482 .enable_mask = BIT(9), 1483 .hw.init = &(struct clk_init_data){ 1484 .name = "pcie_ref_src_clk", 1485 .parent_names = (const char *[]){ "pcie_ref_src" }, 1486 .num_parents = 1, 1487 .ops = &clk_branch_ops, 1488 .flags = CLK_SET_RATE_PARENT, 1489 }, 1490 }, 1491 }; 1492 1493 static struct clk_branch pcie_a_clk = { 1494 .halt_reg = 0x2fc0, 1495 .halt_bit = 13, 1496 .clkr = { 1497 .enable_reg = 0x22c0, 1498 .enable_mask = BIT(4), 1499 .hw.init = &(struct clk_init_data){ 1500 .name = "pcie_a_clk", 1501 .ops = &clk_branch_ops, 1502 .flags = CLK_IS_ROOT, 1503 }, 1504 }, 1505 }; 1506 1507 static struct clk_branch pcie_aux_clk = { 1508 .halt_reg = 0x2fdc, 1509 .halt_bit = 31, 1510 .clkr = { 1511 .enable_reg = 0x22c8, 1512 .enable_mask = BIT(4), 1513 .hw.init = &(struct clk_init_data){ 1514 .name = "pcie_aux_clk", 1515 .ops = &clk_branch_ops, 1516 .flags = CLK_IS_ROOT, 1517 }, 1518 }, 1519 }; 1520 1521 static struct clk_branch pcie_h_clk = { 1522 .halt_reg = 0x2fd4, 1523 .halt_bit = 8, 1524 .clkr = { 1525 .enable_reg = 0x22cc, 1526 .enable_mask = BIT(4), 1527 .hw.init = &(struct clk_init_data){ 1528 .name = "pcie_h_clk", 1529 .ops = &clk_branch_ops, 1530 .flags = CLK_IS_ROOT, 1531 }, 1532 }, 1533 }; 1534 1535 static struct clk_branch pcie_phy_clk = { 1536 .halt_reg = 0x2fdc, 1537 .halt_bit = 29, 1538 .clkr = { 1539 .enable_reg = 0x22d0, 1540 .enable_mask = BIT(4), 1541 .hw.init = &(struct clk_init_data){ 1542 .name = "pcie_phy_clk", 1543 .ops = &clk_branch_ops, 1544 .flags = CLK_IS_ROOT, 1545 }, 1546 }, 1547 }; 1548 1549 static struct clk_rcg pcie1_ref_src = { 1550 .ns_reg = 0x3aa0, 1551 .p = { 1552 .pre_div_shift = 3, 1553 .pre_div_width = 4, 1554 }, 1555 .s = { 1556 .src_sel_shift = 0, 1557 .parent_map = gcc_pxo_pll3_map, 1558 }, 1559 .freq_tbl = clk_tbl_pcie_ref, 1560 .clkr = { 1561 .enable_reg = 0x3aa0, 1562 .enable_mask = BIT(11), 1563 .hw.init = &(struct clk_init_data){ 1564 .name = "pcie1_ref_src", 1565 .parent_names = gcc_pxo_pll3, 1566 .num_parents = 2, 1567 .ops = &clk_rcg_ops, 1568 .flags = CLK_SET_RATE_GATE, 1569 }, 1570 }, 1571 }; 1572 1573 static struct clk_branch pcie1_ref_src_clk = { 1574 .halt_reg = 0x2fdc, 1575 .halt_bit = 27, 1576 .clkr = { 1577 .enable_reg = 0x3aa0, 1578 .enable_mask = BIT(9), 1579 .hw.init = &(struct clk_init_data){ 1580 .name = "pcie1_ref_src_clk", 1581 .parent_names = (const char *[]){ "pcie1_ref_src" }, 1582 .num_parents = 1, 1583 .ops = &clk_branch_ops, 1584 .flags = CLK_SET_RATE_PARENT, 1585 }, 1586 }, 1587 }; 1588 1589 static struct clk_branch pcie1_a_clk = { 1590 .halt_reg = 0x2fc0, 1591 .halt_bit = 10, 1592 .clkr = { 1593 .enable_reg = 0x3a80, 1594 .enable_mask = BIT(4), 1595 .hw.init = &(struct clk_init_data){ 1596 .name = "pcie1_a_clk", 1597 .ops = &clk_branch_ops, 1598 .flags = CLK_IS_ROOT, 1599 }, 1600 }, 1601 }; 1602 1603 static struct clk_branch pcie1_aux_clk = { 1604 .halt_reg = 0x2fdc, 1605 .halt_bit = 28, 1606 .clkr = { 1607 .enable_reg = 0x3a88, 1608 .enable_mask = BIT(4), 1609 .hw.init = &(struct clk_init_data){ 1610 .name = "pcie1_aux_clk", 1611 .ops = &clk_branch_ops, 1612 .flags = CLK_IS_ROOT, 1613 }, 1614 }, 1615 }; 1616 1617 static struct clk_branch pcie1_h_clk = { 1618 .halt_reg = 0x2fd4, 1619 .halt_bit = 9, 1620 .clkr = { 1621 .enable_reg = 0x3a8c, 1622 .enable_mask = BIT(4), 1623 .hw.init = &(struct clk_init_data){ 1624 .name = "pcie1_h_clk", 1625 .ops = &clk_branch_ops, 1626 .flags = CLK_IS_ROOT, 1627 }, 1628 }, 1629 }; 1630 1631 static struct clk_branch pcie1_phy_clk = { 1632 .halt_reg = 0x2fdc, 1633 .halt_bit = 26, 1634 .clkr = { 1635 .enable_reg = 0x3a90, 1636 .enable_mask = BIT(4), 1637 .hw.init = &(struct clk_init_data){ 1638 .name = "pcie1_phy_clk", 1639 .ops = &clk_branch_ops, 1640 .flags = CLK_IS_ROOT, 1641 }, 1642 }, 1643 }; 1644 1645 static struct clk_rcg pcie2_ref_src = { 1646 .ns_reg = 0x3ae0, 1647 .p = { 1648 .pre_div_shift = 3, 1649 .pre_div_width = 4, 1650 }, 1651 .s = { 1652 .src_sel_shift = 0, 1653 .parent_map = gcc_pxo_pll3_map, 1654 }, 1655 .freq_tbl = clk_tbl_pcie_ref, 1656 .clkr = { 1657 .enable_reg = 0x3ae0, 1658 .enable_mask = BIT(11), 1659 .hw.init = &(struct clk_init_data){ 1660 .name = "pcie2_ref_src", 1661 .parent_names = gcc_pxo_pll3, 1662 .num_parents = 2, 1663 .ops = &clk_rcg_ops, 1664 .flags = CLK_SET_RATE_GATE, 1665 }, 1666 }, 1667 }; 1668 1669 static struct clk_branch pcie2_ref_src_clk = { 1670 .halt_reg = 0x2fdc, 1671 .halt_bit = 24, 1672 .clkr = { 1673 .enable_reg = 0x3ae0, 1674 .enable_mask = BIT(9), 1675 .hw.init = &(struct clk_init_data){ 1676 .name = "pcie2_ref_src_clk", 1677 .parent_names = (const char *[]){ "pcie2_ref_src" }, 1678 .num_parents = 1, 1679 .ops = &clk_branch_ops, 1680 .flags = CLK_SET_RATE_PARENT, 1681 }, 1682 }, 1683 }; 1684 1685 static struct clk_branch pcie2_a_clk = { 1686 .halt_reg = 0x2fc0, 1687 .halt_bit = 9, 1688 .clkr = { 1689 .enable_reg = 0x3ac0, 1690 .enable_mask = BIT(4), 1691 .hw.init = &(struct clk_init_data){ 1692 .name = "pcie2_a_clk", 1693 .ops = &clk_branch_ops, 1694 .flags = CLK_IS_ROOT, 1695 }, 1696 }, 1697 }; 1698 1699 static struct clk_branch pcie2_aux_clk = { 1700 .halt_reg = 0x2fdc, 1701 .halt_bit = 25, 1702 .clkr = { 1703 .enable_reg = 0x3ac8, 1704 .enable_mask = BIT(4), 1705 .hw.init = &(struct clk_init_data){ 1706 .name = "pcie2_aux_clk", 1707 .ops = &clk_branch_ops, 1708 .flags = CLK_IS_ROOT, 1709 }, 1710 }, 1711 }; 1712 1713 static struct clk_branch pcie2_h_clk = { 1714 .halt_reg = 0x2fd4, 1715 .halt_bit = 10, 1716 .clkr = { 1717 .enable_reg = 0x3acc, 1718 .enable_mask = BIT(4), 1719 .hw.init = &(struct clk_init_data){ 1720 .name = "pcie2_h_clk", 1721 .ops = &clk_branch_ops, 1722 .flags = CLK_IS_ROOT, 1723 }, 1724 }, 1725 }; 1726 1727 static struct clk_branch pcie2_phy_clk = { 1728 .halt_reg = 0x2fdc, 1729 .halt_bit = 23, 1730 .clkr = { 1731 .enable_reg = 0x3ad0, 1732 .enable_mask = BIT(4), 1733 .hw.init = &(struct clk_init_data){ 1734 .name = "pcie2_phy_clk", 1735 .ops = &clk_branch_ops, 1736 .flags = CLK_IS_ROOT, 1737 }, 1738 }, 1739 }; 1740 1741 static const struct freq_tbl clk_tbl_sata_ref[] = { 1742 { 100000000, P_PLL3, 12, 0, 0 }, 1743 { } 1744 }; 1745 1746 static struct clk_rcg sata_ref_src = { 1747 .ns_reg = 0x2c08, 1748 .p = { 1749 .pre_div_shift = 3, 1750 .pre_div_width = 4, 1751 }, 1752 .s = { 1753 .src_sel_shift = 0, 1754 .parent_map = gcc_pxo_pll3_sata_map, 1755 }, 1756 .freq_tbl = clk_tbl_sata_ref, 1757 .clkr = { 1758 .enable_reg = 0x2c08, 1759 .enable_mask = BIT(7), 1760 .hw.init = &(struct clk_init_data){ 1761 .name = "sata_ref_src", 1762 .parent_names = gcc_pxo_pll3, 1763 .num_parents = 2, 1764 .ops = &clk_rcg_ops, 1765 .flags = CLK_SET_RATE_GATE, 1766 }, 1767 }, 1768 }; 1769 1770 static struct clk_branch sata_rxoob_clk = { 1771 .halt_reg = 0x2fdc, 1772 .halt_bit = 20, 1773 .clkr = { 1774 .enable_reg = 0x2c0c, 1775 .enable_mask = BIT(4), 1776 .hw.init = &(struct clk_init_data){ 1777 .name = "sata_rxoob_clk", 1778 .parent_names = (const char *[]){ "sata_ref_src" }, 1779 .num_parents = 1, 1780 .ops = &clk_branch_ops, 1781 .flags = CLK_SET_RATE_PARENT, 1782 }, 1783 }, 1784 }; 1785 1786 static struct clk_branch sata_pmalive_clk = { 1787 .halt_reg = 0x2fdc, 1788 .halt_bit = 19, 1789 .clkr = { 1790 .enable_reg = 0x2c10, 1791 .enable_mask = BIT(4), 1792 .hw.init = &(struct clk_init_data){ 1793 .name = "sata_pmalive_clk", 1794 .parent_names = (const char *[]){ "sata_ref_src" }, 1795 .num_parents = 1, 1796 .ops = &clk_branch_ops, 1797 .flags = CLK_SET_RATE_PARENT, 1798 }, 1799 }, 1800 }; 1801 1802 static struct clk_branch sata_phy_ref_clk = { 1803 .halt_reg = 0x2fdc, 1804 .halt_bit = 18, 1805 .clkr = { 1806 .enable_reg = 0x2c14, 1807 .enable_mask = BIT(4), 1808 .hw.init = &(struct clk_init_data){ 1809 .name = "sata_phy_ref_clk", 1810 .parent_names = (const char *[]){ "pxo" }, 1811 .num_parents = 1, 1812 .ops = &clk_branch_ops, 1813 }, 1814 }, 1815 }; 1816 1817 static struct clk_branch sata_a_clk = { 1818 .halt_reg = 0x2fc0, 1819 .halt_bit = 12, 1820 .clkr = { 1821 .enable_reg = 0x2c20, 1822 .enable_mask = BIT(4), 1823 .hw.init = &(struct clk_init_data){ 1824 .name = "sata_a_clk", 1825 .ops = &clk_branch_ops, 1826 .flags = CLK_IS_ROOT, 1827 }, 1828 }, 1829 }; 1830 1831 static struct clk_branch sata_h_clk = { 1832 .halt_reg = 0x2fdc, 1833 .halt_bit = 21, 1834 .clkr = { 1835 .enable_reg = 0x2c00, 1836 .enable_mask = BIT(4), 1837 .hw.init = &(struct clk_init_data){ 1838 .name = "sata_h_clk", 1839 .ops = &clk_branch_ops, 1840 .flags = CLK_IS_ROOT, 1841 }, 1842 }, 1843 }; 1844 1845 static struct clk_branch sfab_sata_s_h_clk = { 1846 .halt_reg = 0x2fc4, 1847 .halt_bit = 14, 1848 .clkr = { 1849 .enable_reg = 0x2480, 1850 .enable_mask = BIT(4), 1851 .hw.init = &(struct clk_init_data){ 1852 .name = "sfab_sata_s_h_clk", 1853 .ops = &clk_branch_ops, 1854 .flags = CLK_IS_ROOT, 1855 }, 1856 }, 1857 }; 1858 1859 static struct clk_branch sata_phy_cfg_clk = { 1860 .halt_reg = 0x2fcc, 1861 .halt_bit = 14, 1862 .clkr = { 1863 .enable_reg = 0x2c40, 1864 .enable_mask = BIT(4), 1865 .hw.init = &(struct clk_init_data){ 1866 .name = "sata_phy_cfg_clk", 1867 .ops = &clk_branch_ops, 1868 .flags = CLK_IS_ROOT, 1869 }, 1870 }, 1871 }; 1872 1873 static const struct freq_tbl clk_tbl_usb30_master[] = { 1874 { 125000000, P_PLL0, 1, 5, 32 }, 1875 { } 1876 }; 1877 1878 static struct clk_rcg usb30_master_clk_src = { 1879 .ns_reg = 0x3b2c, 1880 .md_reg = 0x3b28, 1881 .mn = { 1882 .mnctr_en_bit = 8, 1883 .mnctr_reset_bit = 7, 1884 .mnctr_mode_shift = 5, 1885 .n_val_shift = 16, 1886 .m_val_shift = 16, 1887 .width = 8, 1888 }, 1889 .p = { 1890 .pre_div_shift = 3, 1891 .pre_div_width = 2, 1892 }, 1893 .s = { 1894 .src_sel_shift = 0, 1895 .parent_map = gcc_pxo_pll8_pll0, 1896 }, 1897 .freq_tbl = clk_tbl_usb30_master, 1898 .clkr = { 1899 .enable_reg = 0x3b2c, 1900 .enable_mask = BIT(11), 1901 .hw.init = &(struct clk_init_data){ 1902 .name = "usb30_master_ref_src", 1903 .parent_names = gcc_pxo_pll8_pll0_map, 1904 .num_parents = 3, 1905 .ops = &clk_rcg_ops, 1906 .flags = CLK_SET_RATE_GATE, 1907 }, 1908 }, 1909 }; 1910 1911 static struct clk_branch usb30_0_branch_clk = { 1912 .halt_reg = 0x2fc4, 1913 .halt_bit = 22, 1914 .clkr = { 1915 .enable_reg = 0x3b24, 1916 .enable_mask = BIT(4), 1917 .hw.init = &(struct clk_init_data){ 1918 .name = "usb30_0_branch_clk", 1919 .parent_names = (const char *[]){ "usb30_master_ref_src", }, 1920 .num_parents = 1, 1921 .ops = &clk_branch_ops, 1922 .flags = CLK_SET_RATE_PARENT, 1923 }, 1924 }, 1925 }; 1926 1927 static struct clk_branch usb30_1_branch_clk = { 1928 .halt_reg = 0x2fc4, 1929 .halt_bit = 17, 1930 .clkr = { 1931 .enable_reg = 0x3b34, 1932 .enable_mask = BIT(4), 1933 .hw.init = &(struct clk_init_data){ 1934 .name = "usb30_1_branch_clk", 1935 .parent_names = (const char *[]){ "usb30_master_ref_src", }, 1936 .num_parents = 1, 1937 .ops = &clk_branch_ops, 1938 .flags = CLK_SET_RATE_PARENT, 1939 }, 1940 }, 1941 }; 1942 1943 static const struct freq_tbl clk_tbl_usb30_utmi[] = { 1944 { 60000000, P_PLL8, 1, 5, 32 }, 1945 { } 1946 }; 1947 1948 static struct clk_rcg usb30_utmi_clk = { 1949 .ns_reg = 0x3b44, 1950 .md_reg = 0x3b40, 1951 .mn = { 1952 .mnctr_en_bit = 8, 1953 .mnctr_reset_bit = 7, 1954 .mnctr_mode_shift = 5, 1955 .n_val_shift = 16, 1956 .m_val_shift = 16, 1957 .width = 8, 1958 }, 1959 .p = { 1960 .pre_div_shift = 3, 1961 .pre_div_width = 2, 1962 }, 1963 .s = { 1964 .src_sel_shift = 0, 1965 .parent_map = gcc_pxo_pll8_pll0, 1966 }, 1967 .freq_tbl = clk_tbl_usb30_utmi, 1968 .clkr = { 1969 .enable_reg = 0x3b44, 1970 .enable_mask = BIT(11), 1971 .hw.init = &(struct clk_init_data){ 1972 .name = "usb30_utmi_clk", 1973 .parent_names = gcc_pxo_pll8_pll0_map, 1974 .num_parents = 3, 1975 .ops = &clk_rcg_ops, 1976 .flags = CLK_SET_RATE_GATE, 1977 }, 1978 }, 1979 }; 1980 1981 static struct clk_branch usb30_0_utmi_clk_ctl = { 1982 .halt_reg = 0x2fc4, 1983 .halt_bit = 21, 1984 .clkr = { 1985 .enable_reg = 0x3b48, 1986 .enable_mask = BIT(4), 1987 .hw.init = &(struct clk_init_data){ 1988 .name = "usb30_0_utmi_clk_ctl", 1989 .parent_names = (const char *[]){ "usb30_utmi_clk", }, 1990 .num_parents = 1, 1991 .ops = &clk_branch_ops, 1992 .flags = CLK_SET_RATE_PARENT, 1993 }, 1994 }, 1995 }; 1996 1997 static struct clk_branch usb30_1_utmi_clk_ctl = { 1998 .halt_reg = 0x2fc4, 1999 .halt_bit = 15, 2000 .clkr = { 2001 .enable_reg = 0x3b4c, 2002 .enable_mask = BIT(4), 2003 .hw.init = &(struct clk_init_data){ 2004 .name = "usb30_1_utmi_clk_ctl", 2005 .parent_names = (const char *[]){ "usb30_utmi_clk", }, 2006 .num_parents = 1, 2007 .ops = &clk_branch_ops, 2008 .flags = CLK_SET_RATE_PARENT, 2009 }, 2010 }, 2011 }; 2012 2013 static const struct freq_tbl clk_tbl_usb[] = { 2014 { 60000000, P_PLL8, 1, 5, 32 }, 2015 { } 2016 }; 2017 2018 static struct clk_rcg usb_hs1_xcvr_clk_src = { 2019 .ns_reg = 0x290C, 2020 .md_reg = 0x2908, 2021 .mn = { 2022 .mnctr_en_bit = 8, 2023 .mnctr_reset_bit = 7, 2024 .mnctr_mode_shift = 5, 2025 .n_val_shift = 16, 2026 .m_val_shift = 16, 2027 .width = 8, 2028 }, 2029 .p = { 2030 .pre_div_shift = 3, 2031 .pre_div_width = 2, 2032 }, 2033 .s = { 2034 .src_sel_shift = 0, 2035 .parent_map = gcc_pxo_pll8_pll0, 2036 }, 2037 .freq_tbl = clk_tbl_usb, 2038 .clkr = { 2039 .enable_reg = 0x2968, 2040 .enable_mask = BIT(11), 2041 .hw.init = &(struct clk_init_data){ 2042 .name = "usb_hs1_xcvr_src", 2043 .parent_names = gcc_pxo_pll8_pll0_map, 2044 .num_parents = 3, 2045 .ops = &clk_rcg_ops, 2046 .flags = CLK_SET_RATE_GATE, 2047 }, 2048 }, 2049 }; 2050 2051 static struct clk_branch usb_hs1_xcvr_clk = { 2052 .halt_reg = 0x2fcc, 2053 .halt_bit = 17, 2054 .clkr = { 2055 .enable_reg = 0x290c, 2056 .enable_mask = BIT(9), 2057 .hw.init = &(struct clk_init_data){ 2058 .name = "usb_hs1_xcvr_clk", 2059 .parent_names = (const char *[]){ "usb_hs1_xcvr_src" }, 2060 .num_parents = 1, 2061 .ops = &clk_branch_ops, 2062 .flags = CLK_SET_RATE_PARENT, 2063 }, 2064 }, 2065 }; 2066 2067 static struct clk_branch usb_hs1_h_clk = { 2068 .hwcg_reg = 0x2900, 2069 .hwcg_bit = 6, 2070 .halt_reg = 0x2fc8, 2071 .halt_bit = 1, 2072 .clkr = { 2073 .enable_reg = 0x2900, 2074 .enable_mask = BIT(4), 2075 .hw.init = &(struct clk_init_data){ 2076 .name = "usb_hs1_h_clk", 2077 .ops = &clk_branch_ops, 2078 .flags = CLK_IS_ROOT, 2079 }, 2080 }, 2081 }; 2082 2083 static struct clk_rcg usb_fs1_xcvr_clk_src = { 2084 .ns_reg = 0x2968, 2085 .md_reg = 0x2964, 2086 .mn = { 2087 .mnctr_en_bit = 8, 2088 .mnctr_reset_bit = 7, 2089 .mnctr_mode_shift = 5, 2090 .n_val_shift = 16, 2091 .m_val_shift = 16, 2092 .width = 8, 2093 }, 2094 .p = { 2095 .pre_div_shift = 3, 2096 .pre_div_width = 2, 2097 }, 2098 .s = { 2099 .src_sel_shift = 0, 2100 .parent_map = gcc_pxo_pll8_pll0, 2101 }, 2102 .freq_tbl = clk_tbl_usb, 2103 .clkr = { 2104 .enable_reg = 0x2968, 2105 .enable_mask = BIT(11), 2106 .hw.init = &(struct clk_init_data){ 2107 .name = "usb_fs1_xcvr_src", 2108 .parent_names = gcc_pxo_pll8_pll0_map, 2109 .num_parents = 3, 2110 .ops = &clk_rcg_ops, 2111 .flags = CLK_SET_RATE_GATE, 2112 }, 2113 }, 2114 }; 2115 2116 static struct clk_branch usb_fs1_xcvr_clk = { 2117 .halt_reg = 0x2fcc, 2118 .halt_bit = 17, 2119 .clkr = { 2120 .enable_reg = 0x2968, 2121 .enable_mask = BIT(9), 2122 .hw.init = &(struct clk_init_data){ 2123 .name = "usb_fs1_xcvr_clk", 2124 .parent_names = (const char *[]){ "usb_fs1_xcvr_src", }, 2125 .num_parents = 1, 2126 .ops = &clk_branch_ops, 2127 .flags = CLK_SET_RATE_PARENT, 2128 }, 2129 }, 2130 }; 2131 2132 static struct clk_branch usb_fs1_sys_clk = { 2133 .halt_reg = 0x2fcc, 2134 .halt_bit = 18, 2135 .clkr = { 2136 .enable_reg = 0x296c, 2137 .enable_mask = BIT(4), 2138 .hw.init = &(struct clk_init_data){ 2139 .name = "usb_fs1_sys_clk", 2140 .parent_names = (const char *[]){ "usb_fs1_xcvr_src", }, 2141 .num_parents = 1, 2142 .ops = &clk_branch_ops, 2143 .flags = CLK_SET_RATE_PARENT, 2144 }, 2145 }, 2146 }; 2147 2148 static struct clk_branch usb_fs1_h_clk = { 2149 .halt_reg = 0x2fcc, 2150 .halt_bit = 19, 2151 .clkr = { 2152 .enable_reg = 0x2960, 2153 .enable_mask = BIT(4), 2154 .hw.init = &(struct clk_init_data){ 2155 .name = "usb_fs1_h_clk", 2156 .ops = &clk_branch_ops, 2157 .flags = CLK_IS_ROOT, 2158 }, 2159 }, 2160 }; 2161 2162 static struct clk_regmap *gcc_ipq806x_clks[] = { 2163 [PLL0] = &pll0.clkr, 2164 [PLL0_VOTE] = &pll0_vote, 2165 [PLL3] = &pll3.clkr, 2166 [PLL8] = &pll8.clkr, 2167 [PLL8_VOTE] = &pll8_vote, 2168 [PLL14] = &pll14.clkr, 2169 [PLL14_VOTE] = &pll14_vote, 2170 [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr, 2171 [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr, 2172 [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr, 2173 [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr, 2174 [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr, 2175 [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr, 2176 [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr, 2177 [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr, 2178 [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr, 2179 [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr, 2180 [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr, 2181 [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr, 2182 [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr, 2183 [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr, 2184 [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr, 2185 [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr, 2186 [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr, 2187 [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr, 2188 [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr, 2189 [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr, 2190 [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr, 2191 [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr, 2192 [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr, 2193 [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr, 2194 [GP0_SRC] = &gp0_src.clkr, 2195 [GP0_CLK] = &gp0_clk.clkr, 2196 [GP1_SRC] = &gp1_src.clkr, 2197 [GP1_CLK] = &gp1_clk.clkr, 2198 [GP2_SRC] = &gp2_src.clkr, 2199 [GP2_CLK] = &gp2_clk.clkr, 2200 [PMEM_A_CLK] = &pmem_clk.clkr, 2201 [PRNG_SRC] = &prng_src.clkr, 2202 [PRNG_CLK] = &prng_clk.clkr, 2203 [SDC1_SRC] = &sdc1_src.clkr, 2204 [SDC1_CLK] = &sdc1_clk.clkr, 2205 [SDC3_SRC] = &sdc3_src.clkr, 2206 [SDC3_CLK] = &sdc3_clk.clkr, 2207 [TSIF_REF_SRC] = &tsif_ref_src.clkr, 2208 [TSIF_REF_CLK] = &tsif_ref_clk.clkr, 2209 [DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr, 2210 [GSBI1_H_CLK] = &gsbi1_h_clk.clkr, 2211 [GSBI2_H_CLK] = &gsbi2_h_clk.clkr, 2212 [GSBI4_H_CLK] = &gsbi4_h_clk.clkr, 2213 [GSBI5_H_CLK] = &gsbi5_h_clk.clkr, 2214 [GSBI6_H_CLK] = &gsbi6_h_clk.clkr, 2215 [GSBI7_H_CLK] = &gsbi7_h_clk.clkr, 2216 [TSIF_H_CLK] = &tsif_h_clk.clkr, 2217 [SDC1_H_CLK] = &sdc1_h_clk.clkr, 2218 [SDC3_H_CLK] = &sdc3_h_clk.clkr, 2219 [ADM0_CLK] = &adm0_clk.clkr, 2220 [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr, 2221 [PCIE_A_CLK] = &pcie_a_clk.clkr, 2222 [PCIE_AUX_CLK] = &pcie_aux_clk.clkr, 2223 [PCIE_H_CLK] = &pcie_h_clk.clkr, 2224 [PCIE_PHY_CLK] = &pcie_phy_clk.clkr, 2225 [SFAB_SATA_S_H_CLK] = &sfab_sata_s_h_clk.clkr, 2226 [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr, 2227 [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr, 2228 [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr, 2229 [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr, 2230 [SATA_H_CLK] = &sata_h_clk.clkr, 2231 [SATA_CLK_SRC] = &sata_ref_src.clkr, 2232 [SATA_RXOOB_CLK] = &sata_rxoob_clk.clkr, 2233 [SATA_PMALIVE_CLK] = &sata_pmalive_clk.clkr, 2234 [SATA_PHY_REF_CLK] = &sata_phy_ref_clk.clkr, 2235 [SATA_A_CLK] = &sata_a_clk.clkr, 2236 [SATA_PHY_CFG_CLK] = &sata_phy_cfg_clk.clkr, 2237 [PCIE_ALT_REF_SRC] = &pcie_ref_src.clkr, 2238 [PCIE_ALT_REF_CLK] = &pcie_ref_src_clk.clkr, 2239 [PCIE_1_A_CLK] = &pcie1_a_clk.clkr, 2240 [PCIE_1_AUX_CLK] = &pcie1_aux_clk.clkr, 2241 [PCIE_1_H_CLK] = &pcie1_h_clk.clkr, 2242 [PCIE_1_PHY_CLK] = &pcie1_phy_clk.clkr, 2243 [PCIE_1_ALT_REF_SRC] = &pcie1_ref_src.clkr, 2244 [PCIE_1_ALT_REF_CLK] = &pcie1_ref_src_clk.clkr, 2245 [PCIE_2_A_CLK] = &pcie2_a_clk.clkr, 2246 [PCIE_2_AUX_CLK] = &pcie2_aux_clk.clkr, 2247 [PCIE_2_H_CLK] = &pcie2_h_clk.clkr, 2248 [PCIE_2_PHY_CLK] = &pcie2_phy_clk.clkr, 2249 [PCIE_2_ALT_REF_SRC] = &pcie2_ref_src.clkr, 2250 [PCIE_2_ALT_REF_CLK] = &pcie2_ref_src_clk.clkr, 2251 [USB30_MASTER_SRC] = &usb30_master_clk_src.clkr, 2252 [USB30_0_MASTER_CLK] = &usb30_0_branch_clk.clkr, 2253 [USB30_1_MASTER_CLK] = &usb30_1_branch_clk.clkr, 2254 [USB30_UTMI_SRC] = &usb30_utmi_clk.clkr, 2255 [USB30_0_UTMI_CLK] = &usb30_0_utmi_clk_ctl.clkr, 2256 [USB30_1_UTMI_CLK] = &usb30_1_utmi_clk_ctl.clkr, 2257 [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr, 2258 [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_clk_src.clkr, 2259 [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr, 2260 [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr, 2261 [USB_FS1_XCVR_SRC] = &usb_fs1_xcvr_clk_src.clkr, 2262 [USB_FS1_XCVR_CLK] = &usb_fs1_xcvr_clk.clkr, 2263 [USB_FS1_SYSTEM_CLK] = &usb_fs1_sys_clk.clkr, 2264 }; 2265 2266 static const struct qcom_reset_map gcc_ipq806x_resets[] = { 2267 [QDSS_STM_RESET] = { 0x2060, 6 }, 2268 [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 }, 2269 [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 }, 2270 [AFAB_SMPSS_M0_RESET] = { 0x20b8, 0 }, 2271 [AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 }, 2272 [AFAB_EBI1_CH1_RESET] = { 0x20c4, 7 }, 2273 [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 }, 2274 [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 }, 2275 [SFAB_ADM0_M2_RESET] = { 0x21e8, 7 }, 2276 [ADM0_C2_RESET] = { 0x220c, 4 }, 2277 [ADM0_C1_RESET] = { 0x220c, 3 }, 2278 [ADM0_C0_RESET] = { 0x220c, 2 }, 2279 [ADM0_PBUS_RESET] = { 0x220c, 1 }, 2280 [ADM0_RESET] = { 0x220c, 0 }, 2281 [QDSS_CLKS_SW_RESET] = { 0x2260, 5 }, 2282 [QDSS_POR_RESET] = { 0x2260, 4 }, 2283 [QDSS_TSCTR_RESET] = { 0x2260, 3 }, 2284 [QDSS_HRESET_RESET] = { 0x2260, 2 }, 2285 [QDSS_AXI_RESET] = { 0x2260, 1 }, 2286 [QDSS_DBG_RESET] = { 0x2260, 0 }, 2287 [SFAB_PCIE_M_RESET] = { 0x22d8, 1 }, 2288 [SFAB_PCIE_S_RESET] = { 0x22d8, 0 }, 2289 [PCIE_EXT_RESET] = { 0x22dc, 6 }, 2290 [PCIE_PHY_RESET] = { 0x22dc, 5 }, 2291 [PCIE_PCI_RESET] = { 0x22dc, 4 }, 2292 [PCIE_POR_RESET] = { 0x22dc, 3 }, 2293 [PCIE_HCLK_RESET] = { 0x22dc, 2 }, 2294 [PCIE_ACLK_RESET] = { 0x22dc, 0 }, 2295 [SFAB_LPASS_RESET] = { 0x23a0, 7 }, 2296 [SFAB_AFAB_M_RESET] = { 0x23e0, 7 }, 2297 [AFAB_SFAB_M0_RESET] = { 0x2420, 7 }, 2298 [AFAB_SFAB_M1_RESET] = { 0x2424, 7 }, 2299 [SFAB_SATA_S_RESET] = { 0x2480, 7 }, 2300 [SFAB_DFAB_M_RESET] = { 0x2500, 7 }, 2301 [DFAB_SFAB_M_RESET] = { 0x2520, 7 }, 2302 [DFAB_SWAY0_RESET] = { 0x2540, 7 }, 2303 [DFAB_SWAY1_RESET] = { 0x2544, 7 }, 2304 [DFAB_ARB0_RESET] = { 0x2560, 7 }, 2305 [DFAB_ARB1_RESET] = { 0x2564, 7 }, 2306 [PPSS_PROC_RESET] = { 0x2594, 1 }, 2307 [PPSS_RESET] = { 0x2594, 0 }, 2308 [DMA_BAM_RESET] = { 0x25c0, 7 }, 2309 [SPS_TIC_H_RESET] = { 0x2600, 7 }, 2310 [SFAB_CFPB_M_RESET] = { 0x2680, 7 }, 2311 [SFAB_CFPB_S_RESET] = { 0x26c0, 7 }, 2312 [TSIF_H_RESET] = { 0x2700, 7 }, 2313 [CE1_H_RESET] = { 0x2720, 7 }, 2314 [CE1_CORE_RESET] = { 0x2724, 7 }, 2315 [CE1_SLEEP_RESET] = { 0x2728, 7 }, 2316 [CE2_H_RESET] = { 0x2740, 7 }, 2317 [CE2_CORE_RESET] = { 0x2744, 7 }, 2318 [SFAB_SFPB_M_RESET] = { 0x2780, 7 }, 2319 [SFAB_SFPB_S_RESET] = { 0x27a0, 7 }, 2320 [RPM_PROC_RESET] = { 0x27c0, 7 }, 2321 [PMIC_SSBI2_RESET] = { 0x280c, 12 }, 2322 [SDC1_RESET] = { 0x2830, 0 }, 2323 [SDC2_RESET] = { 0x2850, 0 }, 2324 [SDC3_RESET] = { 0x2870, 0 }, 2325 [SDC4_RESET] = { 0x2890, 0 }, 2326 [USB_HS1_RESET] = { 0x2910, 0 }, 2327 [USB_HSIC_RESET] = { 0x2934, 0 }, 2328 [USB_FS1_XCVR_RESET] = { 0x2974, 1 }, 2329 [USB_FS1_RESET] = { 0x2974, 0 }, 2330 [GSBI1_RESET] = { 0x29dc, 0 }, 2331 [GSBI2_RESET] = { 0x29fc, 0 }, 2332 [GSBI3_RESET] = { 0x2a1c, 0 }, 2333 [GSBI4_RESET] = { 0x2a3c, 0 }, 2334 [GSBI5_RESET] = { 0x2a5c, 0 }, 2335 [GSBI6_RESET] = { 0x2a7c, 0 }, 2336 [GSBI7_RESET] = { 0x2a9c, 0 }, 2337 [SPDM_RESET] = { 0x2b6c, 0 }, 2338 [SEC_CTRL_RESET] = { 0x2b80, 7 }, 2339 [TLMM_H_RESET] = { 0x2ba0, 7 }, 2340 [SFAB_SATA_M_RESET] = { 0x2c18, 0 }, 2341 [SATA_RESET] = { 0x2c1c, 0 }, 2342 [TSSC_RESET] = { 0x2ca0, 7 }, 2343 [PDM_RESET] = { 0x2cc0, 12 }, 2344 [MPM_H_RESET] = { 0x2da0, 7 }, 2345 [MPM_RESET] = { 0x2da4, 0 }, 2346 [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 }, 2347 [PRNG_RESET] = { 0x2e80, 12 }, 2348 [SFAB_CE3_M_RESET] = { 0x36c8, 1 }, 2349 [SFAB_CE3_S_RESET] = { 0x36c8, 0 }, 2350 [CE3_SLEEP_RESET] = { 0x36d0, 7 }, 2351 [PCIE_1_M_RESET] = { 0x3a98, 1 }, 2352 [PCIE_1_S_RESET] = { 0x3a98, 0 }, 2353 [PCIE_1_EXT_RESET] = { 0x3a9c, 6 }, 2354 [PCIE_1_PHY_RESET] = { 0x3a9c, 5 }, 2355 [PCIE_1_PCI_RESET] = { 0x3a9c, 4 }, 2356 [PCIE_1_POR_RESET] = { 0x3a9c, 3 }, 2357 [PCIE_1_HCLK_RESET] = { 0x3a9c, 2 }, 2358 [PCIE_1_ACLK_RESET] = { 0x3a9c, 0 }, 2359 [PCIE_2_M_RESET] = { 0x3ad8, 1 }, 2360 [PCIE_2_S_RESET] = { 0x3ad8, 0 }, 2361 [PCIE_2_EXT_RESET] = { 0x3adc, 6 }, 2362 [PCIE_2_PHY_RESET] = { 0x3adc, 5 }, 2363 [PCIE_2_PCI_RESET] = { 0x3adc, 4 }, 2364 [PCIE_2_POR_RESET] = { 0x3adc, 3 }, 2365 [PCIE_2_HCLK_RESET] = { 0x3adc, 2 }, 2366 [PCIE_2_ACLK_RESET] = { 0x3adc, 0 }, 2367 [SFAB_USB30_S_RESET] = { 0x3b54, 1 }, 2368 [SFAB_USB30_M_RESET] = { 0x3b54, 0 }, 2369 [USB30_0_PORT2_HS_PHY_RESET] = { 0x3b50, 5 }, 2370 [USB30_0_MASTER_RESET] = { 0x3b50, 4 }, 2371 [USB30_0_SLEEP_RESET] = { 0x3b50, 3 }, 2372 [USB30_0_UTMI_PHY_RESET] = { 0x3b50, 2 }, 2373 [USB30_0_POWERON_RESET] = { 0x3b50, 1 }, 2374 [USB30_0_PHY_RESET] = { 0x3b50, 0 }, 2375 [USB30_1_MASTER_RESET] = { 0x3b58, 4 }, 2376 [USB30_1_SLEEP_RESET] = { 0x3b58, 3 }, 2377 [USB30_1_UTMI_PHY_RESET] = { 0x3b58, 2 }, 2378 [USB30_1_POWERON_RESET] = { 0x3b58, 1 }, 2379 [USB30_1_PHY_RESET] = { 0x3b58, 0 }, 2380 [NSSFB0_RESET] = { 0x3b60, 6 }, 2381 [NSSFB1_RESET] = { 0x3b60, 7 }, 2382 }; 2383 2384 static const struct regmap_config gcc_ipq806x_regmap_config = { 2385 .reg_bits = 32, 2386 .reg_stride = 4, 2387 .val_bits = 32, 2388 .max_register = 0x3e40, 2389 .fast_io = true, 2390 }; 2391 2392 static const struct qcom_cc_desc gcc_ipq806x_desc = { 2393 .config = &gcc_ipq806x_regmap_config, 2394 .clks = gcc_ipq806x_clks, 2395 .num_clks = ARRAY_SIZE(gcc_ipq806x_clks), 2396 .resets = gcc_ipq806x_resets, 2397 .num_resets = ARRAY_SIZE(gcc_ipq806x_resets), 2398 }; 2399 2400 static const struct of_device_id gcc_ipq806x_match_table[] = { 2401 { .compatible = "qcom,gcc-ipq8064" }, 2402 { } 2403 }; 2404 MODULE_DEVICE_TABLE(of, gcc_ipq806x_match_table); 2405 2406 static int gcc_ipq806x_probe(struct platform_device *pdev) 2407 { 2408 struct clk *clk; 2409 struct device *dev = &pdev->dev; 2410 2411 /* Temporary until RPM clocks supported */ 2412 clk = clk_register_fixed_rate(dev, "cxo", NULL, CLK_IS_ROOT, 25000000); 2413 if (IS_ERR(clk)) 2414 return PTR_ERR(clk); 2415 2416 clk = clk_register_fixed_rate(dev, "pxo", NULL, CLK_IS_ROOT, 25000000); 2417 if (IS_ERR(clk)) 2418 return PTR_ERR(clk); 2419 2420 return qcom_cc_probe(pdev, &gcc_ipq806x_desc); 2421 } 2422 2423 static int gcc_ipq806x_remove(struct platform_device *pdev) 2424 { 2425 qcom_cc_remove(pdev); 2426 return 0; 2427 } 2428 2429 static struct platform_driver gcc_ipq806x_driver = { 2430 .probe = gcc_ipq806x_probe, 2431 .remove = gcc_ipq806x_remove, 2432 .driver = { 2433 .name = "gcc-ipq806x", 2434 .of_match_table = gcc_ipq806x_match_table, 2435 }, 2436 }; 2437 2438 static int __init gcc_ipq806x_init(void) 2439 { 2440 return platform_driver_register(&gcc_ipq806x_driver); 2441 } 2442 core_initcall(gcc_ipq806x_init); 2443 2444 static void __exit gcc_ipq806x_exit(void) 2445 { 2446 platform_driver_unregister(&gcc_ipq806x_driver); 2447 } 2448 module_exit(gcc_ipq806x_exit); 2449 2450 MODULE_DESCRIPTION("QCOM GCC IPQ806x Driver"); 2451 MODULE_LICENSE("GPL v2"); 2452 MODULE_ALIAS("platform:gcc-ipq806x"); 2453