1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/bitops.h> 8 #include <linux/err.h> 9 #include <linux/platform_device.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/of_device.h> 13 #include <linux/clk-provider.h> 14 #include <linux/regmap.h> 15 #include <linux/reset-controller.h> 16 17 #include <dt-bindings/clock/qcom,gcc-ipq806x.h> 18 #include <dt-bindings/reset/qcom,gcc-ipq806x.h> 19 20 #include "common.h" 21 #include "clk-regmap.h" 22 #include "clk-pll.h" 23 #include "clk-rcg.h" 24 #include "clk-branch.h" 25 #include "clk-hfpll.h" 26 #include "reset.h" 27 28 static const struct clk_parent_data gcc_pxo[] = { 29 { .fw_name = "pxo", .name = "pxo" }, 30 }; 31 32 static struct clk_pll pll0 = { 33 .l_reg = 0x30c4, 34 .m_reg = 0x30c8, 35 .n_reg = 0x30cc, 36 .config_reg = 0x30d4, 37 .mode_reg = 0x30c0, 38 .status_reg = 0x30d8, 39 .status_bit = 16, 40 .clkr.hw.init = &(struct clk_init_data){ 41 .name = "pll0", 42 .parent_data = gcc_pxo, 43 .num_parents = 1, 44 .ops = &clk_pll_ops, 45 }, 46 }; 47 48 static struct clk_regmap pll0_vote = { 49 .enable_reg = 0x34c0, 50 .enable_mask = BIT(0), 51 .hw.init = &(struct clk_init_data){ 52 .name = "pll0_vote", 53 .parent_hws = (const struct clk_hw*[]){ 54 &pll0.clkr.hw, 55 }, 56 .num_parents = 1, 57 .ops = &clk_pll_vote_ops, 58 }, 59 }; 60 61 static struct clk_pll pll3 = { 62 .l_reg = 0x3164, 63 .m_reg = 0x3168, 64 .n_reg = 0x316c, 65 .config_reg = 0x3174, 66 .mode_reg = 0x3160, 67 .status_reg = 0x3178, 68 .status_bit = 16, 69 .clkr.hw.init = &(struct clk_init_data){ 70 .name = "pll3", 71 .parent_data = gcc_pxo, 72 .num_parents = 1, 73 .ops = &clk_pll_ops, 74 }, 75 }; 76 77 static struct clk_regmap pll4_vote = { 78 .enable_reg = 0x34c0, 79 .enable_mask = BIT(4), 80 .hw.init = &(struct clk_init_data){ 81 .name = "pll4_vote", 82 .parent_names = (const char *[]){ "pll4" }, 83 .num_parents = 1, 84 .ops = &clk_pll_vote_ops, 85 }, 86 }; 87 88 static struct clk_pll pll8 = { 89 .l_reg = 0x3144, 90 .m_reg = 0x3148, 91 .n_reg = 0x314c, 92 .config_reg = 0x3154, 93 .mode_reg = 0x3140, 94 .status_reg = 0x3158, 95 .status_bit = 16, 96 .clkr.hw.init = &(struct clk_init_data){ 97 .name = "pll8", 98 .parent_data = gcc_pxo, 99 .num_parents = 1, 100 .ops = &clk_pll_ops, 101 }, 102 }; 103 104 static struct clk_regmap pll8_vote = { 105 .enable_reg = 0x34c0, 106 .enable_mask = BIT(8), 107 .hw.init = &(struct clk_init_data){ 108 .name = "pll8_vote", 109 .parent_hws = (const struct clk_hw*[]){ 110 &pll8.clkr.hw, 111 }, 112 .num_parents = 1, 113 .ops = &clk_pll_vote_ops, 114 }, 115 }; 116 117 static struct hfpll_data hfpll0_data = { 118 .mode_reg = 0x3200, 119 .l_reg = 0x3208, 120 .m_reg = 0x320c, 121 .n_reg = 0x3210, 122 .config_reg = 0x3204, 123 .status_reg = 0x321c, 124 .config_val = 0x7845c665, 125 .droop_reg = 0x3214, 126 .droop_val = 0x0108c000, 127 .min_rate = 600000000UL, 128 .max_rate = 1800000000UL, 129 }; 130 131 static struct clk_hfpll hfpll0 = { 132 .d = &hfpll0_data, 133 .clkr.hw.init = &(struct clk_init_data){ 134 .parent_data = gcc_pxo, 135 .num_parents = 1, 136 .name = "hfpll0", 137 .ops = &clk_ops_hfpll, 138 .flags = CLK_IGNORE_UNUSED, 139 }, 140 .lock = __SPIN_LOCK_UNLOCKED(hfpll0.lock), 141 }; 142 143 static struct hfpll_data hfpll1_data = { 144 .mode_reg = 0x3240, 145 .l_reg = 0x3248, 146 .m_reg = 0x324c, 147 .n_reg = 0x3250, 148 .config_reg = 0x3244, 149 .status_reg = 0x325c, 150 .config_val = 0x7845c665, 151 .droop_reg = 0x3314, 152 .droop_val = 0x0108c000, 153 .min_rate = 600000000UL, 154 .max_rate = 1800000000UL, 155 }; 156 157 static struct clk_hfpll hfpll1 = { 158 .d = &hfpll1_data, 159 .clkr.hw.init = &(struct clk_init_data){ 160 .parent_data = gcc_pxo, 161 .num_parents = 1, 162 .name = "hfpll1", 163 .ops = &clk_ops_hfpll, 164 .flags = CLK_IGNORE_UNUSED, 165 }, 166 .lock = __SPIN_LOCK_UNLOCKED(hfpll1.lock), 167 }; 168 169 static struct hfpll_data hfpll_l2_data = { 170 .mode_reg = 0x3300, 171 .l_reg = 0x3308, 172 .m_reg = 0x330c, 173 .n_reg = 0x3310, 174 .config_reg = 0x3304, 175 .status_reg = 0x331c, 176 .config_val = 0x7845c665, 177 .droop_reg = 0x3314, 178 .droop_val = 0x0108c000, 179 .min_rate = 600000000UL, 180 .max_rate = 1800000000UL, 181 }; 182 183 static struct clk_hfpll hfpll_l2 = { 184 .d = &hfpll_l2_data, 185 .clkr.hw.init = &(struct clk_init_data){ 186 .parent_data = gcc_pxo, 187 .num_parents = 1, 188 .name = "hfpll_l2", 189 .ops = &clk_ops_hfpll, 190 .flags = CLK_IGNORE_UNUSED, 191 }, 192 .lock = __SPIN_LOCK_UNLOCKED(hfpll_l2.lock), 193 }; 194 195 static struct clk_pll pll14 = { 196 .l_reg = 0x31c4, 197 .m_reg = 0x31c8, 198 .n_reg = 0x31cc, 199 .config_reg = 0x31d4, 200 .mode_reg = 0x31c0, 201 .status_reg = 0x31d8, 202 .status_bit = 16, 203 .clkr.hw.init = &(struct clk_init_data){ 204 .name = "pll14", 205 .parent_data = gcc_pxo, 206 .num_parents = 1, 207 .ops = &clk_pll_ops, 208 }, 209 }; 210 211 static struct clk_regmap pll14_vote = { 212 .enable_reg = 0x34c0, 213 .enable_mask = BIT(14), 214 .hw.init = &(struct clk_init_data){ 215 .name = "pll14_vote", 216 .parent_hws = (const struct clk_hw*[]){ 217 &pll14.clkr.hw, 218 }, 219 .num_parents = 1, 220 .ops = &clk_pll_vote_ops, 221 }, 222 }; 223 224 #define NSS_PLL_RATE(f, _l, _m, _n, i) \ 225 { \ 226 .freq = f, \ 227 .l = _l, \ 228 .m = _m, \ 229 .n = _n, \ 230 .ibits = i, \ 231 } 232 233 static struct pll_freq_tbl pll18_freq_tbl[] = { 234 NSS_PLL_RATE(550000000, 44, 0, 1, 0x01495625), 235 NSS_PLL_RATE(733000000, 58, 16, 25, 0x014b5625), 236 }; 237 238 static struct clk_pll pll18 = { 239 .l_reg = 0x31a4, 240 .m_reg = 0x31a8, 241 .n_reg = 0x31ac, 242 .config_reg = 0x31b4, 243 .mode_reg = 0x31a0, 244 .status_reg = 0x31b8, 245 .status_bit = 16, 246 .post_div_shift = 16, 247 .post_div_width = 1, 248 .freq_tbl = pll18_freq_tbl, 249 .clkr.hw.init = &(struct clk_init_data){ 250 .name = "pll18", 251 .parent_data = gcc_pxo, 252 .num_parents = 1, 253 .ops = &clk_pll_ops, 254 }, 255 }; 256 257 enum { 258 P_PXO, 259 P_PLL8, 260 P_PLL3, 261 P_PLL0, 262 P_CXO, 263 P_PLL14, 264 P_PLL18, 265 }; 266 267 static const struct parent_map gcc_pxo_pll8_map[] = { 268 { P_PXO, 0 }, 269 { P_PLL8, 3 } 270 }; 271 272 static const struct clk_parent_data gcc_pxo_pll8[] = { 273 { .fw_name = "pxo", .name = "pxo" }, 274 { .hw = &pll8_vote.hw }, 275 }; 276 277 static const struct parent_map gcc_pxo_pll8_cxo_map[] = { 278 { P_PXO, 0 }, 279 { P_PLL8, 3 }, 280 { P_CXO, 5 } 281 }; 282 283 static const struct clk_parent_data gcc_pxo_pll8_cxo[] = { 284 { .fw_name = "pxo", .name = "pxo" }, 285 { .hw = &pll8_vote.hw }, 286 { .fw_name = "cxo", .name = "cxo" }, 287 }; 288 289 static const struct parent_map gcc_pxo_pll3_map[] = { 290 { P_PXO, 0 }, 291 { P_PLL3, 1 } 292 }; 293 294 static const struct parent_map gcc_pxo_pll3_sata_map[] = { 295 { P_PXO, 0 }, 296 { P_PLL3, 6 } 297 }; 298 299 static const struct clk_parent_data gcc_pxo_pll3[] = { 300 { .fw_name = "pxo", .name = "pxo" }, 301 { .hw = &pll3.clkr.hw }, 302 }; 303 304 static const struct parent_map gcc_pxo_pll8_pll0_map[] = { 305 { P_PXO, 0 }, 306 { P_PLL8, 3 }, 307 { P_PLL0, 2 } 308 }; 309 310 static const struct clk_parent_data gcc_pxo_pll8_pll0[] = { 311 { .fw_name = "pxo", .name = "pxo" }, 312 { .hw = &pll8_vote.hw }, 313 { .hw = &pll0_vote.hw }, 314 }; 315 316 static const struct parent_map gcc_pxo_pll8_pll14_pll18_pll0_map[] = { 317 { P_PXO, 0 }, 318 { P_PLL8, 4 }, 319 { P_PLL0, 2 }, 320 { P_PLL14, 5 }, 321 { P_PLL18, 1 } 322 }; 323 324 static const struct clk_parent_data gcc_pxo_pll8_pll14_pll18_pll0[] = { 325 { .fw_name = "pxo", .name = "pxo" }, 326 { .hw = &pll8_vote.hw }, 327 { .hw = &pll0_vote.hw }, 328 { .hw = &pll14.clkr.hw }, 329 { .hw = &pll18.clkr.hw }, 330 }; 331 332 static struct freq_tbl clk_tbl_gsbi_uart[] = { 333 { 1843200, P_PLL8, 2, 6, 625 }, 334 { 3686400, P_PLL8, 2, 12, 625 }, 335 { 7372800, P_PLL8, 2, 24, 625 }, 336 { 14745600, P_PLL8, 2, 48, 625 }, 337 { 16000000, P_PLL8, 4, 1, 6 }, 338 { 24000000, P_PLL8, 4, 1, 4 }, 339 { 32000000, P_PLL8, 4, 1, 3 }, 340 { 40000000, P_PLL8, 1, 5, 48 }, 341 { 46400000, P_PLL8, 1, 29, 240 }, 342 { 48000000, P_PLL8, 4, 1, 2 }, 343 { 51200000, P_PLL8, 1, 2, 15 }, 344 { 56000000, P_PLL8, 1, 7, 48 }, 345 { 58982400, P_PLL8, 1, 96, 625 }, 346 { 64000000, P_PLL8, 2, 1, 3 }, 347 { } 348 }; 349 350 static struct clk_rcg gsbi1_uart_src = { 351 .ns_reg = 0x29d4, 352 .md_reg = 0x29d0, 353 .mn = { 354 .mnctr_en_bit = 8, 355 .mnctr_reset_bit = 7, 356 .mnctr_mode_shift = 5, 357 .n_val_shift = 16, 358 .m_val_shift = 16, 359 .width = 16, 360 }, 361 .p = { 362 .pre_div_shift = 3, 363 .pre_div_width = 2, 364 }, 365 .s = { 366 .src_sel_shift = 0, 367 .parent_map = gcc_pxo_pll8_map, 368 }, 369 .freq_tbl = clk_tbl_gsbi_uart, 370 .clkr = { 371 .enable_reg = 0x29d4, 372 .enable_mask = BIT(11), 373 .hw.init = &(struct clk_init_data){ 374 .name = "gsbi1_uart_src", 375 .parent_data = gcc_pxo_pll8, 376 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 377 .ops = &clk_rcg_ops, 378 .flags = CLK_SET_PARENT_GATE, 379 }, 380 }, 381 }; 382 383 static struct clk_branch gsbi1_uart_clk = { 384 .halt_reg = 0x2fcc, 385 .halt_bit = 12, 386 .clkr = { 387 .enable_reg = 0x29d4, 388 .enable_mask = BIT(9), 389 .hw.init = &(struct clk_init_data){ 390 .name = "gsbi1_uart_clk", 391 .parent_hws = (const struct clk_hw*[]){ 392 &gsbi1_uart_src.clkr.hw, 393 }, 394 .num_parents = 1, 395 .ops = &clk_branch_ops, 396 .flags = CLK_SET_RATE_PARENT, 397 }, 398 }, 399 }; 400 401 static struct clk_rcg gsbi2_uart_src = { 402 .ns_reg = 0x29f4, 403 .md_reg = 0x29f0, 404 .mn = { 405 .mnctr_en_bit = 8, 406 .mnctr_reset_bit = 7, 407 .mnctr_mode_shift = 5, 408 .n_val_shift = 16, 409 .m_val_shift = 16, 410 .width = 16, 411 }, 412 .p = { 413 .pre_div_shift = 3, 414 .pre_div_width = 2, 415 }, 416 .s = { 417 .src_sel_shift = 0, 418 .parent_map = gcc_pxo_pll8_map, 419 }, 420 .freq_tbl = clk_tbl_gsbi_uart, 421 .clkr = { 422 .enable_reg = 0x29f4, 423 .enable_mask = BIT(11), 424 .hw.init = &(struct clk_init_data){ 425 .name = "gsbi2_uart_src", 426 .parent_data = gcc_pxo_pll8, 427 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 428 .ops = &clk_rcg_ops, 429 .flags = CLK_SET_PARENT_GATE, 430 }, 431 }, 432 }; 433 434 static struct clk_branch gsbi2_uart_clk = { 435 .halt_reg = 0x2fcc, 436 .halt_bit = 8, 437 .clkr = { 438 .enable_reg = 0x29f4, 439 .enable_mask = BIT(9), 440 .hw.init = &(struct clk_init_data){ 441 .name = "gsbi2_uart_clk", 442 .parent_hws = (const struct clk_hw*[]){ 443 &gsbi2_uart_src.clkr.hw, 444 }, 445 .num_parents = 1, 446 .ops = &clk_branch_ops, 447 .flags = CLK_SET_RATE_PARENT, 448 }, 449 }, 450 }; 451 452 static struct clk_rcg gsbi4_uart_src = { 453 .ns_reg = 0x2a34, 454 .md_reg = 0x2a30, 455 .mn = { 456 .mnctr_en_bit = 8, 457 .mnctr_reset_bit = 7, 458 .mnctr_mode_shift = 5, 459 .n_val_shift = 16, 460 .m_val_shift = 16, 461 .width = 16, 462 }, 463 .p = { 464 .pre_div_shift = 3, 465 .pre_div_width = 2, 466 }, 467 .s = { 468 .src_sel_shift = 0, 469 .parent_map = gcc_pxo_pll8_map, 470 }, 471 .freq_tbl = clk_tbl_gsbi_uart, 472 .clkr = { 473 .enable_reg = 0x2a34, 474 .enable_mask = BIT(11), 475 .hw.init = &(struct clk_init_data){ 476 .name = "gsbi4_uart_src", 477 .parent_data = gcc_pxo_pll8, 478 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 479 .ops = &clk_rcg_ops, 480 .flags = CLK_SET_PARENT_GATE, 481 }, 482 }, 483 }; 484 485 static struct clk_branch gsbi4_uart_clk = { 486 .halt_reg = 0x2fd0, 487 .halt_bit = 26, 488 .clkr = { 489 .enable_reg = 0x2a34, 490 .enable_mask = BIT(9), 491 .hw.init = &(struct clk_init_data){ 492 .name = "gsbi4_uart_clk", 493 .parent_hws = (const struct clk_hw*[]){ 494 &gsbi4_uart_src.clkr.hw, 495 }, 496 .num_parents = 1, 497 .ops = &clk_branch_ops, 498 .flags = CLK_SET_RATE_PARENT, 499 }, 500 }, 501 }; 502 503 static struct clk_rcg gsbi5_uart_src = { 504 .ns_reg = 0x2a54, 505 .md_reg = 0x2a50, 506 .mn = { 507 .mnctr_en_bit = 8, 508 .mnctr_reset_bit = 7, 509 .mnctr_mode_shift = 5, 510 .n_val_shift = 16, 511 .m_val_shift = 16, 512 .width = 16, 513 }, 514 .p = { 515 .pre_div_shift = 3, 516 .pre_div_width = 2, 517 }, 518 .s = { 519 .src_sel_shift = 0, 520 .parent_map = gcc_pxo_pll8_map, 521 }, 522 .freq_tbl = clk_tbl_gsbi_uart, 523 .clkr = { 524 .enable_reg = 0x2a54, 525 .enable_mask = BIT(11), 526 .hw.init = &(struct clk_init_data){ 527 .name = "gsbi5_uart_src", 528 .parent_data = gcc_pxo_pll8, 529 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 530 .ops = &clk_rcg_ops, 531 .flags = CLK_SET_PARENT_GATE, 532 }, 533 }, 534 }; 535 536 static struct clk_branch gsbi5_uart_clk = { 537 .halt_reg = 0x2fd0, 538 .halt_bit = 22, 539 .clkr = { 540 .enable_reg = 0x2a54, 541 .enable_mask = BIT(9), 542 .hw.init = &(struct clk_init_data){ 543 .name = "gsbi5_uart_clk", 544 .parent_hws = (const struct clk_hw*[]){ 545 &gsbi5_uart_src.clkr.hw, 546 }, 547 .num_parents = 1, 548 .ops = &clk_branch_ops, 549 .flags = CLK_SET_RATE_PARENT, 550 }, 551 }, 552 }; 553 554 static struct clk_rcg gsbi6_uart_src = { 555 .ns_reg = 0x2a74, 556 .md_reg = 0x2a70, 557 .mn = { 558 .mnctr_en_bit = 8, 559 .mnctr_reset_bit = 7, 560 .mnctr_mode_shift = 5, 561 .n_val_shift = 16, 562 .m_val_shift = 16, 563 .width = 16, 564 }, 565 .p = { 566 .pre_div_shift = 3, 567 .pre_div_width = 2, 568 }, 569 .s = { 570 .src_sel_shift = 0, 571 .parent_map = gcc_pxo_pll8_map, 572 }, 573 .freq_tbl = clk_tbl_gsbi_uart, 574 .clkr = { 575 .enable_reg = 0x2a74, 576 .enable_mask = BIT(11), 577 .hw.init = &(struct clk_init_data){ 578 .name = "gsbi6_uart_src", 579 .parent_data = gcc_pxo_pll8, 580 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 581 .ops = &clk_rcg_ops, 582 .flags = CLK_SET_PARENT_GATE, 583 }, 584 }, 585 }; 586 587 static struct clk_branch gsbi6_uart_clk = { 588 .halt_reg = 0x2fd0, 589 .halt_bit = 18, 590 .clkr = { 591 .enable_reg = 0x2a74, 592 .enable_mask = BIT(9), 593 .hw.init = &(struct clk_init_data){ 594 .name = "gsbi6_uart_clk", 595 .parent_hws = (const struct clk_hw*[]){ 596 &gsbi6_uart_src.clkr.hw, 597 }, 598 .num_parents = 1, 599 .ops = &clk_branch_ops, 600 .flags = CLK_SET_RATE_PARENT, 601 }, 602 }, 603 }; 604 605 static struct clk_rcg gsbi7_uart_src = { 606 .ns_reg = 0x2a94, 607 .md_reg = 0x2a90, 608 .mn = { 609 .mnctr_en_bit = 8, 610 .mnctr_reset_bit = 7, 611 .mnctr_mode_shift = 5, 612 .n_val_shift = 16, 613 .m_val_shift = 16, 614 .width = 16, 615 }, 616 .p = { 617 .pre_div_shift = 3, 618 .pre_div_width = 2, 619 }, 620 .s = { 621 .src_sel_shift = 0, 622 .parent_map = gcc_pxo_pll8_map, 623 }, 624 .freq_tbl = clk_tbl_gsbi_uart, 625 .clkr = { 626 .enable_reg = 0x2a94, 627 .enable_mask = BIT(11), 628 .hw.init = &(struct clk_init_data){ 629 .name = "gsbi7_uart_src", 630 .parent_data = gcc_pxo_pll8, 631 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 632 .ops = &clk_rcg_ops, 633 .flags = CLK_SET_PARENT_GATE, 634 }, 635 }, 636 }; 637 638 static struct clk_branch gsbi7_uart_clk = { 639 .halt_reg = 0x2fd0, 640 .halt_bit = 14, 641 .clkr = { 642 .enable_reg = 0x2a94, 643 .enable_mask = BIT(9), 644 .hw.init = &(struct clk_init_data){ 645 .name = "gsbi7_uart_clk", 646 .parent_hws = (const struct clk_hw*[]){ 647 &gsbi7_uart_src.clkr.hw, 648 }, 649 .num_parents = 1, 650 .ops = &clk_branch_ops, 651 .flags = CLK_SET_RATE_PARENT, 652 }, 653 }, 654 }; 655 656 static struct freq_tbl clk_tbl_gsbi_qup[] = { 657 { 1100000, P_PXO, 1, 2, 49 }, 658 { 5400000, P_PXO, 1, 1, 5 }, 659 { 10800000, P_PXO, 1, 2, 5 }, 660 { 15060000, P_PLL8, 1, 2, 51 }, 661 { 24000000, P_PLL8, 4, 1, 4 }, 662 { 25000000, P_PXO, 1, 0, 0 }, 663 { 25600000, P_PLL8, 1, 1, 15 }, 664 { 48000000, P_PLL8, 4, 1, 2 }, 665 { 51200000, P_PLL8, 1, 2, 15 }, 666 { } 667 }; 668 669 static struct clk_rcg gsbi1_qup_src = { 670 .ns_reg = 0x29cc, 671 .md_reg = 0x29c8, 672 .mn = { 673 .mnctr_en_bit = 8, 674 .mnctr_reset_bit = 7, 675 .mnctr_mode_shift = 5, 676 .n_val_shift = 16, 677 .m_val_shift = 16, 678 .width = 8, 679 }, 680 .p = { 681 .pre_div_shift = 3, 682 .pre_div_width = 2, 683 }, 684 .s = { 685 .src_sel_shift = 0, 686 .parent_map = gcc_pxo_pll8_map, 687 }, 688 .freq_tbl = clk_tbl_gsbi_qup, 689 .clkr = { 690 .enable_reg = 0x29cc, 691 .enable_mask = BIT(11), 692 .hw.init = &(struct clk_init_data){ 693 .name = "gsbi1_qup_src", 694 .parent_data = gcc_pxo_pll8, 695 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 696 .ops = &clk_rcg_ops, 697 .flags = CLK_SET_PARENT_GATE, 698 }, 699 }, 700 }; 701 702 static struct clk_branch gsbi1_qup_clk = { 703 .halt_reg = 0x2fcc, 704 .halt_bit = 11, 705 .clkr = { 706 .enable_reg = 0x29cc, 707 .enable_mask = BIT(9), 708 .hw.init = &(struct clk_init_data){ 709 .name = "gsbi1_qup_clk", 710 .parent_hws = (const struct clk_hw*[]){ 711 &gsbi1_qup_src.clkr.hw, 712 }, 713 .num_parents = 1, 714 .ops = &clk_branch_ops, 715 .flags = CLK_SET_RATE_PARENT, 716 }, 717 }, 718 }; 719 720 static struct clk_rcg gsbi2_qup_src = { 721 .ns_reg = 0x29ec, 722 .md_reg = 0x29e8, 723 .mn = { 724 .mnctr_en_bit = 8, 725 .mnctr_reset_bit = 7, 726 .mnctr_mode_shift = 5, 727 .n_val_shift = 16, 728 .m_val_shift = 16, 729 .width = 8, 730 }, 731 .p = { 732 .pre_div_shift = 3, 733 .pre_div_width = 2, 734 }, 735 .s = { 736 .src_sel_shift = 0, 737 .parent_map = gcc_pxo_pll8_map, 738 }, 739 .freq_tbl = clk_tbl_gsbi_qup, 740 .clkr = { 741 .enable_reg = 0x29ec, 742 .enable_mask = BIT(11), 743 .hw.init = &(struct clk_init_data){ 744 .name = "gsbi2_qup_src", 745 .parent_data = gcc_pxo_pll8, 746 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 747 .ops = &clk_rcg_ops, 748 .flags = CLK_SET_PARENT_GATE, 749 }, 750 }, 751 }; 752 753 static struct clk_branch gsbi2_qup_clk = { 754 .halt_reg = 0x2fcc, 755 .halt_bit = 6, 756 .clkr = { 757 .enable_reg = 0x29ec, 758 .enable_mask = BIT(9), 759 .hw.init = &(struct clk_init_data){ 760 .name = "gsbi2_qup_clk", 761 .parent_hws = (const struct clk_hw*[]){ 762 &gsbi2_qup_src.clkr.hw, 763 }, 764 .num_parents = 1, 765 .ops = &clk_branch_ops, 766 .flags = CLK_SET_RATE_PARENT, 767 }, 768 }, 769 }; 770 771 static struct clk_rcg gsbi4_qup_src = { 772 .ns_reg = 0x2a2c, 773 .md_reg = 0x2a28, 774 .mn = { 775 .mnctr_en_bit = 8, 776 .mnctr_reset_bit = 7, 777 .mnctr_mode_shift = 5, 778 .n_val_shift = 16, 779 .m_val_shift = 16, 780 .width = 8, 781 }, 782 .p = { 783 .pre_div_shift = 3, 784 .pre_div_width = 2, 785 }, 786 .s = { 787 .src_sel_shift = 0, 788 .parent_map = gcc_pxo_pll8_map, 789 }, 790 .freq_tbl = clk_tbl_gsbi_qup, 791 .clkr = { 792 .enable_reg = 0x2a2c, 793 .enable_mask = BIT(11), 794 .hw.init = &(struct clk_init_data){ 795 .name = "gsbi4_qup_src", 796 .parent_data = gcc_pxo_pll8, 797 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 798 .ops = &clk_rcg_ops, 799 .flags = CLK_SET_PARENT_GATE, 800 }, 801 }, 802 }; 803 804 static struct clk_branch gsbi4_qup_clk = { 805 .halt_reg = 0x2fd0, 806 .halt_bit = 24, 807 .clkr = { 808 .enable_reg = 0x2a2c, 809 .enable_mask = BIT(9), 810 .hw.init = &(struct clk_init_data){ 811 .name = "gsbi4_qup_clk", 812 .parent_hws = (const struct clk_hw*[]){ 813 &gsbi4_qup_src.clkr.hw, 814 }, 815 .num_parents = 1, 816 .ops = &clk_branch_ops, 817 .flags = CLK_SET_RATE_PARENT, 818 }, 819 }, 820 }; 821 822 static struct clk_rcg gsbi5_qup_src = { 823 .ns_reg = 0x2a4c, 824 .md_reg = 0x2a48, 825 .mn = { 826 .mnctr_en_bit = 8, 827 .mnctr_reset_bit = 7, 828 .mnctr_mode_shift = 5, 829 .n_val_shift = 16, 830 .m_val_shift = 16, 831 .width = 8, 832 }, 833 .p = { 834 .pre_div_shift = 3, 835 .pre_div_width = 2, 836 }, 837 .s = { 838 .src_sel_shift = 0, 839 .parent_map = gcc_pxo_pll8_map, 840 }, 841 .freq_tbl = clk_tbl_gsbi_qup, 842 .clkr = { 843 .enable_reg = 0x2a4c, 844 .enable_mask = BIT(11), 845 .hw.init = &(struct clk_init_data){ 846 .name = "gsbi5_qup_src", 847 .parent_data = gcc_pxo_pll8, 848 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 849 .ops = &clk_rcg_ops, 850 .flags = CLK_SET_PARENT_GATE, 851 }, 852 }, 853 }; 854 855 static struct clk_branch gsbi5_qup_clk = { 856 .halt_reg = 0x2fd0, 857 .halt_bit = 20, 858 .clkr = { 859 .enable_reg = 0x2a4c, 860 .enable_mask = BIT(9), 861 .hw.init = &(struct clk_init_data){ 862 .name = "gsbi5_qup_clk", 863 .parent_hws = (const struct clk_hw*[]){ 864 &gsbi5_qup_src.clkr.hw, 865 }, 866 .num_parents = 1, 867 .ops = &clk_branch_ops, 868 .flags = CLK_SET_RATE_PARENT, 869 }, 870 }, 871 }; 872 873 static struct clk_rcg gsbi6_qup_src = { 874 .ns_reg = 0x2a6c, 875 .md_reg = 0x2a68, 876 .mn = { 877 .mnctr_en_bit = 8, 878 .mnctr_reset_bit = 7, 879 .mnctr_mode_shift = 5, 880 .n_val_shift = 16, 881 .m_val_shift = 16, 882 .width = 8, 883 }, 884 .p = { 885 .pre_div_shift = 3, 886 .pre_div_width = 2, 887 }, 888 .s = { 889 .src_sel_shift = 0, 890 .parent_map = gcc_pxo_pll8_map, 891 }, 892 .freq_tbl = clk_tbl_gsbi_qup, 893 .clkr = { 894 .enable_reg = 0x2a6c, 895 .enable_mask = BIT(11), 896 .hw.init = &(struct clk_init_data){ 897 .name = "gsbi6_qup_src", 898 .parent_data = gcc_pxo_pll8, 899 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 900 .ops = &clk_rcg_ops, 901 .flags = CLK_SET_PARENT_GATE, 902 }, 903 }, 904 }; 905 906 static struct clk_branch gsbi6_qup_clk = { 907 .halt_reg = 0x2fd0, 908 .halt_bit = 16, 909 .clkr = { 910 .enable_reg = 0x2a6c, 911 .enable_mask = BIT(9), 912 .hw.init = &(struct clk_init_data){ 913 .name = "gsbi6_qup_clk", 914 .parent_hws = (const struct clk_hw*[]){ 915 &gsbi6_qup_src.clkr.hw, 916 }, 917 .num_parents = 1, 918 .ops = &clk_branch_ops, 919 .flags = CLK_SET_RATE_PARENT, 920 }, 921 }, 922 }; 923 924 static struct clk_rcg gsbi7_qup_src = { 925 .ns_reg = 0x2a8c, 926 .md_reg = 0x2a88, 927 .mn = { 928 .mnctr_en_bit = 8, 929 .mnctr_reset_bit = 7, 930 .mnctr_mode_shift = 5, 931 .n_val_shift = 16, 932 .m_val_shift = 16, 933 .width = 8, 934 }, 935 .p = { 936 .pre_div_shift = 3, 937 .pre_div_width = 2, 938 }, 939 .s = { 940 .src_sel_shift = 0, 941 .parent_map = gcc_pxo_pll8_map, 942 }, 943 .freq_tbl = clk_tbl_gsbi_qup, 944 .clkr = { 945 .enable_reg = 0x2a8c, 946 .enable_mask = BIT(11), 947 .hw.init = &(struct clk_init_data){ 948 .name = "gsbi7_qup_src", 949 .parent_data = gcc_pxo_pll8, 950 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 951 .ops = &clk_rcg_ops, 952 .flags = CLK_SET_PARENT_GATE, 953 }, 954 }, 955 }; 956 957 static struct clk_branch gsbi7_qup_clk = { 958 .halt_reg = 0x2fd0, 959 .halt_bit = 12, 960 .clkr = { 961 .enable_reg = 0x2a8c, 962 .enable_mask = BIT(9), 963 .hw.init = &(struct clk_init_data){ 964 .name = "gsbi7_qup_clk", 965 .parent_hws = (const struct clk_hw*[]){ 966 &gsbi7_qup_src.clkr.hw, 967 }, 968 .num_parents = 1, 969 .ops = &clk_branch_ops, 970 .flags = CLK_SET_RATE_PARENT, 971 }, 972 }, 973 }; 974 975 static struct clk_branch gsbi1_h_clk = { 976 .hwcg_reg = 0x29c0, 977 .hwcg_bit = 6, 978 .halt_reg = 0x2fcc, 979 .halt_bit = 13, 980 .clkr = { 981 .enable_reg = 0x29c0, 982 .enable_mask = BIT(4), 983 .hw.init = &(struct clk_init_data){ 984 .name = "gsbi1_h_clk", 985 .ops = &clk_branch_ops, 986 }, 987 }, 988 }; 989 990 static struct clk_branch gsbi2_h_clk = { 991 .hwcg_reg = 0x29e0, 992 .hwcg_bit = 6, 993 .halt_reg = 0x2fcc, 994 .halt_bit = 9, 995 .clkr = { 996 .enable_reg = 0x29e0, 997 .enable_mask = BIT(4), 998 .hw.init = &(struct clk_init_data){ 999 .name = "gsbi2_h_clk", 1000 .ops = &clk_branch_ops, 1001 }, 1002 }, 1003 }; 1004 1005 static struct clk_branch gsbi4_h_clk = { 1006 .hwcg_reg = 0x2a20, 1007 .hwcg_bit = 6, 1008 .halt_reg = 0x2fd0, 1009 .halt_bit = 27, 1010 .clkr = { 1011 .enable_reg = 0x2a20, 1012 .enable_mask = BIT(4), 1013 .hw.init = &(struct clk_init_data){ 1014 .name = "gsbi4_h_clk", 1015 .ops = &clk_branch_ops, 1016 }, 1017 }, 1018 }; 1019 1020 static struct clk_branch gsbi5_h_clk = { 1021 .hwcg_reg = 0x2a40, 1022 .hwcg_bit = 6, 1023 .halt_reg = 0x2fd0, 1024 .halt_bit = 23, 1025 .clkr = { 1026 .enable_reg = 0x2a40, 1027 .enable_mask = BIT(4), 1028 .hw.init = &(struct clk_init_data){ 1029 .name = "gsbi5_h_clk", 1030 .ops = &clk_branch_ops, 1031 }, 1032 }, 1033 }; 1034 1035 static struct clk_branch gsbi6_h_clk = { 1036 .hwcg_reg = 0x2a60, 1037 .hwcg_bit = 6, 1038 .halt_reg = 0x2fd0, 1039 .halt_bit = 19, 1040 .clkr = { 1041 .enable_reg = 0x2a60, 1042 .enable_mask = BIT(4), 1043 .hw.init = &(struct clk_init_data){ 1044 .name = "gsbi6_h_clk", 1045 .ops = &clk_branch_ops, 1046 }, 1047 }, 1048 }; 1049 1050 static struct clk_branch gsbi7_h_clk = { 1051 .hwcg_reg = 0x2a80, 1052 .hwcg_bit = 6, 1053 .halt_reg = 0x2fd0, 1054 .halt_bit = 15, 1055 .clkr = { 1056 .enable_reg = 0x2a80, 1057 .enable_mask = BIT(4), 1058 .hw.init = &(struct clk_init_data){ 1059 .name = "gsbi7_h_clk", 1060 .ops = &clk_branch_ops, 1061 }, 1062 }, 1063 }; 1064 1065 static const struct freq_tbl clk_tbl_gp[] = { 1066 { 12500000, P_PXO, 2, 0, 0 }, 1067 { 25000000, P_PXO, 1, 0, 0 }, 1068 { 64000000, P_PLL8, 2, 1, 3 }, 1069 { 76800000, P_PLL8, 1, 1, 5 }, 1070 { 96000000, P_PLL8, 4, 0, 0 }, 1071 { 128000000, P_PLL8, 3, 0, 0 }, 1072 { 192000000, P_PLL8, 2, 0, 0 }, 1073 { } 1074 }; 1075 1076 static struct clk_rcg gp0_src = { 1077 .ns_reg = 0x2d24, 1078 .md_reg = 0x2d00, 1079 .mn = { 1080 .mnctr_en_bit = 8, 1081 .mnctr_reset_bit = 7, 1082 .mnctr_mode_shift = 5, 1083 .n_val_shift = 16, 1084 .m_val_shift = 16, 1085 .width = 8, 1086 }, 1087 .p = { 1088 .pre_div_shift = 3, 1089 .pre_div_width = 2, 1090 }, 1091 .s = { 1092 .src_sel_shift = 0, 1093 .parent_map = gcc_pxo_pll8_cxo_map, 1094 }, 1095 .freq_tbl = clk_tbl_gp, 1096 .clkr = { 1097 .enable_reg = 0x2d24, 1098 .enable_mask = BIT(11), 1099 .hw.init = &(struct clk_init_data){ 1100 .name = "gp0_src", 1101 .parent_data = gcc_pxo_pll8_cxo, 1102 .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo), 1103 .ops = &clk_rcg_ops, 1104 .flags = CLK_SET_PARENT_GATE, 1105 }, 1106 } 1107 }; 1108 1109 static struct clk_branch gp0_clk = { 1110 .halt_reg = 0x2fd8, 1111 .halt_bit = 7, 1112 .clkr = { 1113 .enable_reg = 0x2d24, 1114 .enable_mask = BIT(9), 1115 .hw.init = &(struct clk_init_data){ 1116 .name = "gp0_clk", 1117 .parent_hws = (const struct clk_hw*[]){ 1118 &gp0_src.clkr.hw, 1119 }, 1120 .num_parents = 1, 1121 .ops = &clk_branch_ops, 1122 .flags = CLK_SET_RATE_PARENT, 1123 }, 1124 }, 1125 }; 1126 1127 static struct clk_rcg gp1_src = { 1128 .ns_reg = 0x2d44, 1129 .md_reg = 0x2d40, 1130 .mn = { 1131 .mnctr_en_bit = 8, 1132 .mnctr_reset_bit = 7, 1133 .mnctr_mode_shift = 5, 1134 .n_val_shift = 16, 1135 .m_val_shift = 16, 1136 .width = 8, 1137 }, 1138 .p = { 1139 .pre_div_shift = 3, 1140 .pre_div_width = 2, 1141 }, 1142 .s = { 1143 .src_sel_shift = 0, 1144 .parent_map = gcc_pxo_pll8_cxo_map, 1145 }, 1146 .freq_tbl = clk_tbl_gp, 1147 .clkr = { 1148 .enable_reg = 0x2d44, 1149 .enable_mask = BIT(11), 1150 .hw.init = &(struct clk_init_data){ 1151 .name = "gp1_src", 1152 .parent_data = gcc_pxo_pll8_cxo, 1153 .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo), 1154 .ops = &clk_rcg_ops, 1155 .flags = CLK_SET_RATE_GATE, 1156 }, 1157 } 1158 }; 1159 1160 static struct clk_branch gp1_clk = { 1161 .halt_reg = 0x2fd8, 1162 .halt_bit = 6, 1163 .clkr = { 1164 .enable_reg = 0x2d44, 1165 .enable_mask = BIT(9), 1166 .hw.init = &(struct clk_init_data){ 1167 .name = "gp1_clk", 1168 .parent_hws = (const struct clk_hw*[]){ 1169 &gp1_src.clkr.hw, 1170 }, 1171 .num_parents = 1, 1172 .ops = &clk_branch_ops, 1173 .flags = CLK_SET_RATE_PARENT, 1174 }, 1175 }, 1176 }; 1177 1178 static struct clk_rcg gp2_src = { 1179 .ns_reg = 0x2d64, 1180 .md_reg = 0x2d60, 1181 .mn = { 1182 .mnctr_en_bit = 8, 1183 .mnctr_reset_bit = 7, 1184 .mnctr_mode_shift = 5, 1185 .n_val_shift = 16, 1186 .m_val_shift = 16, 1187 .width = 8, 1188 }, 1189 .p = { 1190 .pre_div_shift = 3, 1191 .pre_div_width = 2, 1192 }, 1193 .s = { 1194 .src_sel_shift = 0, 1195 .parent_map = gcc_pxo_pll8_cxo_map, 1196 }, 1197 .freq_tbl = clk_tbl_gp, 1198 .clkr = { 1199 .enable_reg = 0x2d64, 1200 .enable_mask = BIT(11), 1201 .hw.init = &(struct clk_init_data){ 1202 .name = "gp2_src", 1203 .parent_data = gcc_pxo_pll8_cxo, 1204 .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo), 1205 .ops = &clk_rcg_ops, 1206 .flags = CLK_SET_RATE_GATE, 1207 }, 1208 } 1209 }; 1210 1211 static struct clk_branch gp2_clk = { 1212 .halt_reg = 0x2fd8, 1213 .halt_bit = 5, 1214 .clkr = { 1215 .enable_reg = 0x2d64, 1216 .enable_mask = BIT(9), 1217 .hw.init = &(struct clk_init_data){ 1218 .name = "gp2_clk", 1219 .parent_hws = (const struct clk_hw*[]){ 1220 &gp2_src.clkr.hw, 1221 }, 1222 .num_parents = 1, 1223 .ops = &clk_branch_ops, 1224 .flags = CLK_SET_RATE_PARENT, 1225 }, 1226 }, 1227 }; 1228 1229 static struct clk_branch pmem_clk = { 1230 .hwcg_reg = 0x25a0, 1231 .hwcg_bit = 6, 1232 .halt_reg = 0x2fc8, 1233 .halt_bit = 20, 1234 .clkr = { 1235 .enable_reg = 0x25a0, 1236 .enable_mask = BIT(4), 1237 .hw.init = &(struct clk_init_data){ 1238 .name = "pmem_clk", 1239 .ops = &clk_branch_ops, 1240 }, 1241 }, 1242 }; 1243 1244 static struct clk_rcg prng_src = { 1245 .ns_reg = 0x2e80, 1246 .p = { 1247 .pre_div_shift = 3, 1248 .pre_div_width = 4, 1249 }, 1250 .s = { 1251 .src_sel_shift = 0, 1252 .parent_map = gcc_pxo_pll8_map, 1253 }, 1254 .clkr = { 1255 .enable_reg = 0x2e80, 1256 .enable_mask = BIT(11), 1257 .hw.init = &(struct clk_init_data){ 1258 .name = "prng_src", 1259 .parent_data = gcc_pxo_pll8, 1260 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1261 .ops = &clk_rcg_ops, 1262 }, 1263 }, 1264 }; 1265 1266 static struct clk_branch prng_clk = { 1267 .halt_reg = 0x2fd8, 1268 .halt_check = BRANCH_HALT_VOTED, 1269 .halt_bit = 10, 1270 .clkr = { 1271 .enable_reg = 0x3080, 1272 .enable_mask = BIT(10), 1273 .hw.init = &(struct clk_init_data){ 1274 .name = "prng_clk", 1275 .parent_hws = (const struct clk_hw*[]){ 1276 &prng_src.clkr.hw, 1277 }, 1278 .num_parents = 1, 1279 .ops = &clk_branch_ops, 1280 }, 1281 }, 1282 }; 1283 1284 static const struct freq_tbl clk_tbl_sdc[] = { 1285 { 200000, P_PXO, 2, 2, 125 }, 1286 { 400000, P_PLL8, 4, 1, 240 }, 1287 { 16000000, P_PLL8, 4, 1, 6 }, 1288 { 17070000, P_PLL8, 1, 2, 45 }, 1289 { 20210000, P_PLL8, 1, 1, 19 }, 1290 { 24000000, P_PLL8, 4, 1, 4 }, 1291 { 48000000, P_PLL8, 4, 1, 2 }, 1292 { 64000000, P_PLL8, 3, 1, 2 }, 1293 { 96000000, P_PLL8, 4, 0, 0 }, 1294 { 192000000, P_PLL8, 2, 0, 0 }, 1295 { } 1296 }; 1297 1298 static struct clk_rcg sdc1_src = { 1299 .ns_reg = 0x282c, 1300 .md_reg = 0x2828, 1301 .mn = { 1302 .mnctr_en_bit = 8, 1303 .mnctr_reset_bit = 7, 1304 .mnctr_mode_shift = 5, 1305 .n_val_shift = 16, 1306 .m_val_shift = 16, 1307 .width = 8, 1308 }, 1309 .p = { 1310 .pre_div_shift = 3, 1311 .pre_div_width = 2, 1312 }, 1313 .s = { 1314 .src_sel_shift = 0, 1315 .parent_map = gcc_pxo_pll8_map, 1316 }, 1317 .freq_tbl = clk_tbl_sdc, 1318 .clkr = { 1319 .enable_reg = 0x282c, 1320 .enable_mask = BIT(11), 1321 .hw.init = &(struct clk_init_data){ 1322 .name = "sdc1_src", 1323 .parent_data = gcc_pxo_pll8, 1324 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1325 .ops = &clk_rcg_ops, 1326 }, 1327 } 1328 }; 1329 1330 static struct clk_branch sdc1_clk = { 1331 .halt_reg = 0x2fc8, 1332 .halt_bit = 6, 1333 .clkr = { 1334 .enable_reg = 0x282c, 1335 .enable_mask = BIT(9), 1336 .hw.init = &(struct clk_init_data){ 1337 .name = "sdc1_clk", 1338 .parent_hws = (const struct clk_hw*[]){ 1339 &sdc1_src.clkr.hw, 1340 }, 1341 .num_parents = 1, 1342 .ops = &clk_branch_ops, 1343 .flags = CLK_SET_RATE_PARENT, 1344 }, 1345 }, 1346 }; 1347 1348 static struct clk_rcg sdc3_src = { 1349 .ns_reg = 0x286c, 1350 .md_reg = 0x2868, 1351 .mn = { 1352 .mnctr_en_bit = 8, 1353 .mnctr_reset_bit = 7, 1354 .mnctr_mode_shift = 5, 1355 .n_val_shift = 16, 1356 .m_val_shift = 16, 1357 .width = 8, 1358 }, 1359 .p = { 1360 .pre_div_shift = 3, 1361 .pre_div_width = 2, 1362 }, 1363 .s = { 1364 .src_sel_shift = 0, 1365 .parent_map = gcc_pxo_pll8_map, 1366 }, 1367 .freq_tbl = clk_tbl_sdc, 1368 .clkr = { 1369 .enable_reg = 0x286c, 1370 .enable_mask = BIT(11), 1371 .hw.init = &(struct clk_init_data){ 1372 .name = "sdc3_src", 1373 .parent_data = gcc_pxo_pll8, 1374 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1375 .ops = &clk_rcg_ops, 1376 }, 1377 } 1378 }; 1379 1380 static struct clk_branch sdc3_clk = { 1381 .halt_reg = 0x2fc8, 1382 .halt_bit = 4, 1383 .clkr = { 1384 .enable_reg = 0x286c, 1385 .enable_mask = BIT(9), 1386 .hw.init = &(struct clk_init_data){ 1387 .name = "sdc3_clk", 1388 .parent_hws = (const struct clk_hw*[]){ 1389 &sdc3_src.clkr.hw, 1390 }, 1391 .num_parents = 1, 1392 .ops = &clk_branch_ops, 1393 .flags = CLK_SET_RATE_PARENT, 1394 }, 1395 }, 1396 }; 1397 1398 static struct clk_branch sdc1_h_clk = { 1399 .hwcg_reg = 0x2820, 1400 .hwcg_bit = 6, 1401 .halt_reg = 0x2fc8, 1402 .halt_bit = 11, 1403 .clkr = { 1404 .enable_reg = 0x2820, 1405 .enable_mask = BIT(4), 1406 .hw.init = &(struct clk_init_data){ 1407 .name = "sdc1_h_clk", 1408 .ops = &clk_branch_ops, 1409 }, 1410 }, 1411 }; 1412 1413 static struct clk_branch sdc3_h_clk = { 1414 .hwcg_reg = 0x2860, 1415 .hwcg_bit = 6, 1416 .halt_reg = 0x2fc8, 1417 .halt_bit = 9, 1418 .clkr = { 1419 .enable_reg = 0x2860, 1420 .enable_mask = BIT(4), 1421 .hw.init = &(struct clk_init_data){ 1422 .name = "sdc3_h_clk", 1423 .ops = &clk_branch_ops, 1424 }, 1425 }, 1426 }; 1427 1428 static const struct freq_tbl clk_tbl_tsif_ref[] = { 1429 { 105000, P_PXO, 1, 1, 256 }, 1430 { } 1431 }; 1432 1433 static struct clk_rcg tsif_ref_src = { 1434 .ns_reg = 0x2710, 1435 .md_reg = 0x270c, 1436 .mn = { 1437 .mnctr_en_bit = 8, 1438 .mnctr_reset_bit = 7, 1439 .mnctr_mode_shift = 5, 1440 .n_val_shift = 16, 1441 .m_val_shift = 16, 1442 .width = 16, 1443 }, 1444 .p = { 1445 .pre_div_shift = 3, 1446 .pre_div_width = 2, 1447 }, 1448 .s = { 1449 .src_sel_shift = 0, 1450 .parent_map = gcc_pxo_pll8_map, 1451 }, 1452 .freq_tbl = clk_tbl_tsif_ref, 1453 .clkr = { 1454 .enable_reg = 0x2710, 1455 .enable_mask = BIT(11), 1456 .hw.init = &(struct clk_init_data){ 1457 .name = "tsif_ref_src", 1458 .parent_data = gcc_pxo_pll8, 1459 .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1460 .ops = &clk_rcg_ops, 1461 }, 1462 } 1463 }; 1464 1465 static struct clk_branch tsif_ref_clk = { 1466 .halt_reg = 0x2fd4, 1467 .halt_bit = 5, 1468 .clkr = { 1469 .enable_reg = 0x2710, 1470 .enable_mask = BIT(9), 1471 .hw.init = &(struct clk_init_data){ 1472 .name = "tsif_ref_clk", 1473 .parent_hws = (const struct clk_hw*[]){ 1474 &tsif_ref_src.clkr.hw, 1475 }, 1476 .num_parents = 1, 1477 .ops = &clk_branch_ops, 1478 .flags = CLK_SET_RATE_PARENT, 1479 }, 1480 }, 1481 }; 1482 1483 static struct clk_branch tsif_h_clk = { 1484 .hwcg_reg = 0x2700, 1485 .hwcg_bit = 6, 1486 .halt_reg = 0x2fd4, 1487 .halt_bit = 7, 1488 .clkr = { 1489 .enable_reg = 0x2700, 1490 .enable_mask = BIT(4), 1491 .hw.init = &(struct clk_init_data){ 1492 .name = "tsif_h_clk", 1493 .ops = &clk_branch_ops, 1494 }, 1495 }, 1496 }; 1497 1498 static struct clk_branch dma_bam_h_clk = { 1499 .hwcg_reg = 0x25c0, 1500 .hwcg_bit = 6, 1501 .halt_reg = 0x2fc8, 1502 .halt_bit = 12, 1503 .clkr = { 1504 .enable_reg = 0x25c0, 1505 .enable_mask = BIT(4), 1506 .hw.init = &(struct clk_init_data){ 1507 .name = "dma_bam_h_clk", 1508 .ops = &clk_branch_ops, 1509 }, 1510 }, 1511 }; 1512 1513 static struct clk_branch adm0_clk = { 1514 .halt_reg = 0x2fdc, 1515 .halt_check = BRANCH_HALT_VOTED, 1516 .halt_bit = 12, 1517 .clkr = { 1518 .enable_reg = 0x3080, 1519 .enable_mask = BIT(2), 1520 .hw.init = &(struct clk_init_data){ 1521 .name = "adm0_clk", 1522 .ops = &clk_branch_ops, 1523 }, 1524 }, 1525 }; 1526 1527 static struct clk_branch adm0_pbus_clk = { 1528 .hwcg_reg = 0x2208, 1529 .hwcg_bit = 6, 1530 .halt_reg = 0x2fdc, 1531 .halt_check = BRANCH_HALT_VOTED, 1532 .halt_bit = 11, 1533 .clkr = { 1534 .enable_reg = 0x3080, 1535 .enable_mask = BIT(3), 1536 .hw.init = &(struct clk_init_data){ 1537 .name = "adm0_pbus_clk", 1538 .ops = &clk_branch_ops, 1539 }, 1540 }, 1541 }; 1542 1543 static struct clk_branch pmic_arb0_h_clk = { 1544 .halt_reg = 0x2fd8, 1545 .halt_check = BRANCH_HALT_VOTED, 1546 .halt_bit = 22, 1547 .clkr = { 1548 .enable_reg = 0x3080, 1549 .enable_mask = BIT(8), 1550 .hw.init = &(struct clk_init_data){ 1551 .name = "pmic_arb0_h_clk", 1552 .ops = &clk_branch_ops, 1553 }, 1554 }, 1555 }; 1556 1557 static struct clk_branch pmic_arb1_h_clk = { 1558 .halt_reg = 0x2fd8, 1559 .halt_check = BRANCH_HALT_VOTED, 1560 .halt_bit = 21, 1561 .clkr = { 1562 .enable_reg = 0x3080, 1563 .enable_mask = BIT(9), 1564 .hw.init = &(struct clk_init_data){ 1565 .name = "pmic_arb1_h_clk", 1566 .ops = &clk_branch_ops, 1567 }, 1568 }, 1569 }; 1570 1571 static struct clk_branch pmic_ssbi2_clk = { 1572 .halt_reg = 0x2fd8, 1573 .halt_check = BRANCH_HALT_VOTED, 1574 .halt_bit = 23, 1575 .clkr = { 1576 .enable_reg = 0x3080, 1577 .enable_mask = BIT(7), 1578 .hw.init = &(struct clk_init_data){ 1579 .name = "pmic_ssbi2_clk", 1580 .ops = &clk_branch_ops, 1581 }, 1582 }, 1583 }; 1584 1585 static struct clk_branch rpm_msg_ram_h_clk = { 1586 .hwcg_reg = 0x27e0, 1587 .hwcg_bit = 6, 1588 .halt_reg = 0x2fd8, 1589 .halt_check = BRANCH_HALT_VOTED, 1590 .halt_bit = 12, 1591 .clkr = { 1592 .enable_reg = 0x3080, 1593 .enable_mask = BIT(6), 1594 .hw.init = &(struct clk_init_data){ 1595 .name = "rpm_msg_ram_h_clk", 1596 .ops = &clk_branch_ops, 1597 }, 1598 }, 1599 }; 1600 1601 static const struct freq_tbl clk_tbl_pcie_ref[] = { 1602 { 100000000, P_PLL3, 12, 0, 0 }, 1603 { } 1604 }; 1605 1606 static struct clk_rcg pcie_ref_src = { 1607 .ns_reg = 0x3860, 1608 .p = { 1609 .pre_div_shift = 3, 1610 .pre_div_width = 4, 1611 }, 1612 .s = { 1613 .src_sel_shift = 0, 1614 .parent_map = gcc_pxo_pll3_map, 1615 }, 1616 .freq_tbl = clk_tbl_pcie_ref, 1617 .clkr = { 1618 .enable_reg = 0x3860, 1619 .enable_mask = BIT(11), 1620 .hw.init = &(struct clk_init_data){ 1621 .name = "pcie_ref_src", 1622 .parent_data = gcc_pxo_pll3, 1623 .num_parents = ARRAY_SIZE(gcc_pxo_pll3), 1624 .ops = &clk_rcg_ops, 1625 .flags = CLK_SET_RATE_GATE, 1626 }, 1627 }, 1628 }; 1629 1630 static struct clk_branch pcie_ref_src_clk = { 1631 .halt_reg = 0x2fdc, 1632 .halt_bit = 30, 1633 .clkr = { 1634 .enable_reg = 0x3860, 1635 .enable_mask = BIT(9), 1636 .hw.init = &(struct clk_init_data){ 1637 .name = "pcie_ref_src_clk", 1638 .parent_hws = (const struct clk_hw*[]){ 1639 &pcie_ref_src.clkr.hw, 1640 }, 1641 .num_parents = 1, 1642 .ops = &clk_branch_ops, 1643 .flags = CLK_SET_RATE_PARENT, 1644 }, 1645 }, 1646 }; 1647 1648 static struct clk_branch pcie_a_clk = { 1649 .halt_reg = 0x2fc0, 1650 .halt_bit = 13, 1651 .clkr = { 1652 .enable_reg = 0x22c0, 1653 .enable_mask = BIT(4), 1654 .hw.init = &(struct clk_init_data){ 1655 .name = "pcie_a_clk", 1656 .ops = &clk_branch_ops, 1657 }, 1658 }, 1659 }; 1660 1661 static struct clk_branch pcie_aux_clk = { 1662 .halt_reg = 0x2fdc, 1663 .halt_bit = 31, 1664 .clkr = { 1665 .enable_reg = 0x22c8, 1666 .enable_mask = BIT(4), 1667 .hw.init = &(struct clk_init_data){ 1668 .name = "pcie_aux_clk", 1669 .ops = &clk_branch_ops, 1670 }, 1671 }, 1672 }; 1673 1674 static struct clk_branch pcie_h_clk = { 1675 .halt_reg = 0x2fd4, 1676 .halt_bit = 8, 1677 .clkr = { 1678 .enable_reg = 0x22cc, 1679 .enable_mask = BIT(4), 1680 .hw.init = &(struct clk_init_data){ 1681 .name = "pcie_h_clk", 1682 .ops = &clk_branch_ops, 1683 }, 1684 }, 1685 }; 1686 1687 static struct clk_branch pcie_phy_clk = { 1688 .halt_reg = 0x2fdc, 1689 .halt_bit = 29, 1690 .clkr = { 1691 .enable_reg = 0x22d0, 1692 .enable_mask = BIT(4), 1693 .hw.init = &(struct clk_init_data){ 1694 .name = "pcie_phy_clk", 1695 .ops = &clk_branch_ops, 1696 }, 1697 }, 1698 }; 1699 1700 static struct clk_rcg pcie1_ref_src = { 1701 .ns_reg = 0x3aa0, 1702 .p = { 1703 .pre_div_shift = 3, 1704 .pre_div_width = 4, 1705 }, 1706 .s = { 1707 .src_sel_shift = 0, 1708 .parent_map = gcc_pxo_pll3_map, 1709 }, 1710 .freq_tbl = clk_tbl_pcie_ref, 1711 .clkr = { 1712 .enable_reg = 0x3aa0, 1713 .enable_mask = BIT(11), 1714 .hw.init = &(struct clk_init_data){ 1715 .name = "pcie1_ref_src", 1716 .parent_data = gcc_pxo_pll3, 1717 .num_parents = ARRAY_SIZE(gcc_pxo_pll3), 1718 .ops = &clk_rcg_ops, 1719 .flags = CLK_SET_RATE_GATE, 1720 }, 1721 }, 1722 }; 1723 1724 static struct clk_branch pcie1_ref_src_clk = { 1725 .halt_reg = 0x2fdc, 1726 .halt_bit = 27, 1727 .clkr = { 1728 .enable_reg = 0x3aa0, 1729 .enable_mask = BIT(9), 1730 .hw.init = &(struct clk_init_data){ 1731 .name = "pcie1_ref_src_clk", 1732 .parent_hws = (const struct clk_hw*[]){ 1733 &pcie1_ref_src.clkr.hw, 1734 }, 1735 .num_parents = 1, 1736 .ops = &clk_branch_ops, 1737 .flags = CLK_SET_RATE_PARENT, 1738 }, 1739 }, 1740 }; 1741 1742 static struct clk_branch pcie1_a_clk = { 1743 .halt_reg = 0x2fc0, 1744 .halt_bit = 10, 1745 .clkr = { 1746 .enable_reg = 0x3a80, 1747 .enable_mask = BIT(4), 1748 .hw.init = &(struct clk_init_data){ 1749 .name = "pcie1_a_clk", 1750 .ops = &clk_branch_ops, 1751 }, 1752 }, 1753 }; 1754 1755 static struct clk_branch pcie1_aux_clk = { 1756 .halt_reg = 0x2fdc, 1757 .halt_bit = 28, 1758 .clkr = { 1759 .enable_reg = 0x3a88, 1760 .enable_mask = BIT(4), 1761 .hw.init = &(struct clk_init_data){ 1762 .name = "pcie1_aux_clk", 1763 .ops = &clk_branch_ops, 1764 }, 1765 }, 1766 }; 1767 1768 static struct clk_branch pcie1_h_clk = { 1769 .halt_reg = 0x2fd4, 1770 .halt_bit = 9, 1771 .clkr = { 1772 .enable_reg = 0x3a8c, 1773 .enable_mask = BIT(4), 1774 .hw.init = &(struct clk_init_data){ 1775 .name = "pcie1_h_clk", 1776 .ops = &clk_branch_ops, 1777 }, 1778 }, 1779 }; 1780 1781 static struct clk_branch pcie1_phy_clk = { 1782 .halt_reg = 0x2fdc, 1783 .halt_bit = 26, 1784 .clkr = { 1785 .enable_reg = 0x3a90, 1786 .enable_mask = BIT(4), 1787 .hw.init = &(struct clk_init_data){ 1788 .name = "pcie1_phy_clk", 1789 .ops = &clk_branch_ops, 1790 }, 1791 }, 1792 }; 1793 1794 static struct clk_rcg pcie2_ref_src = { 1795 .ns_reg = 0x3ae0, 1796 .p = { 1797 .pre_div_shift = 3, 1798 .pre_div_width = 4, 1799 }, 1800 .s = { 1801 .src_sel_shift = 0, 1802 .parent_map = gcc_pxo_pll3_map, 1803 }, 1804 .freq_tbl = clk_tbl_pcie_ref, 1805 .clkr = { 1806 .enable_reg = 0x3ae0, 1807 .enable_mask = BIT(11), 1808 .hw.init = &(struct clk_init_data){ 1809 .name = "pcie2_ref_src", 1810 .parent_data = gcc_pxo_pll3, 1811 .num_parents = ARRAY_SIZE(gcc_pxo_pll3), 1812 .ops = &clk_rcg_ops, 1813 .flags = CLK_SET_RATE_GATE, 1814 }, 1815 }, 1816 }; 1817 1818 static struct clk_branch pcie2_ref_src_clk = { 1819 .halt_reg = 0x2fdc, 1820 .halt_bit = 24, 1821 .clkr = { 1822 .enable_reg = 0x3ae0, 1823 .enable_mask = BIT(9), 1824 .hw.init = &(struct clk_init_data){ 1825 .name = "pcie2_ref_src_clk", 1826 .parent_hws = (const struct clk_hw*[]){ 1827 &pcie2_ref_src.clkr.hw, 1828 }, 1829 .num_parents = 1, 1830 .ops = &clk_branch_ops, 1831 .flags = CLK_SET_RATE_PARENT, 1832 }, 1833 }, 1834 }; 1835 1836 static struct clk_branch pcie2_a_clk = { 1837 .halt_reg = 0x2fc0, 1838 .halt_bit = 9, 1839 .clkr = { 1840 .enable_reg = 0x3ac0, 1841 .enable_mask = BIT(4), 1842 .hw.init = &(struct clk_init_data){ 1843 .name = "pcie2_a_clk", 1844 .ops = &clk_branch_ops, 1845 }, 1846 }, 1847 }; 1848 1849 static struct clk_branch pcie2_aux_clk = { 1850 .halt_reg = 0x2fdc, 1851 .halt_bit = 25, 1852 .clkr = { 1853 .enable_reg = 0x3ac8, 1854 .enable_mask = BIT(4), 1855 .hw.init = &(struct clk_init_data){ 1856 .name = "pcie2_aux_clk", 1857 .ops = &clk_branch_ops, 1858 }, 1859 }, 1860 }; 1861 1862 static struct clk_branch pcie2_h_clk = { 1863 .halt_reg = 0x2fd4, 1864 .halt_bit = 10, 1865 .clkr = { 1866 .enable_reg = 0x3acc, 1867 .enable_mask = BIT(4), 1868 .hw.init = &(struct clk_init_data){ 1869 .name = "pcie2_h_clk", 1870 .ops = &clk_branch_ops, 1871 }, 1872 }, 1873 }; 1874 1875 static struct clk_branch pcie2_phy_clk = { 1876 .halt_reg = 0x2fdc, 1877 .halt_bit = 23, 1878 .clkr = { 1879 .enable_reg = 0x3ad0, 1880 .enable_mask = BIT(4), 1881 .hw.init = &(struct clk_init_data){ 1882 .name = "pcie2_phy_clk", 1883 .ops = &clk_branch_ops, 1884 }, 1885 }, 1886 }; 1887 1888 static const struct freq_tbl clk_tbl_sata_ref[] = { 1889 { 100000000, P_PLL3, 12, 0, 0 }, 1890 { } 1891 }; 1892 1893 static struct clk_rcg sata_ref_src = { 1894 .ns_reg = 0x2c08, 1895 .p = { 1896 .pre_div_shift = 3, 1897 .pre_div_width = 4, 1898 }, 1899 .s = { 1900 .src_sel_shift = 0, 1901 .parent_map = gcc_pxo_pll3_sata_map, 1902 }, 1903 .freq_tbl = clk_tbl_sata_ref, 1904 .clkr = { 1905 .enable_reg = 0x2c08, 1906 .enable_mask = BIT(7), 1907 .hw.init = &(struct clk_init_data){ 1908 .name = "sata_ref_src", 1909 .parent_data = gcc_pxo_pll3, 1910 .num_parents = ARRAY_SIZE(gcc_pxo_pll3), 1911 .ops = &clk_rcg_ops, 1912 .flags = CLK_SET_RATE_GATE, 1913 }, 1914 }, 1915 }; 1916 1917 static struct clk_branch sata_rxoob_clk = { 1918 .halt_reg = 0x2fdc, 1919 .halt_bit = 20, 1920 .clkr = { 1921 .enable_reg = 0x2c0c, 1922 .enable_mask = BIT(4), 1923 .hw.init = &(struct clk_init_data){ 1924 .name = "sata_rxoob_clk", 1925 .parent_hws = (const struct clk_hw*[]){ 1926 &sata_ref_src.clkr.hw, 1927 }, 1928 .num_parents = 1, 1929 .ops = &clk_branch_ops, 1930 .flags = CLK_SET_RATE_PARENT, 1931 }, 1932 }, 1933 }; 1934 1935 static struct clk_branch sata_pmalive_clk = { 1936 .halt_reg = 0x2fdc, 1937 .halt_bit = 19, 1938 .clkr = { 1939 .enable_reg = 0x2c10, 1940 .enable_mask = BIT(4), 1941 .hw.init = &(struct clk_init_data){ 1942 .name = "sata_pmalive_clk", 1943 .parent_hws = (const struct clk_hw*[]){ 1944 &sata_ref_src.clkr.hw, 1945 }, 1946 .num_parents = 1, 1947 .ops = &clk_branch_ops, 1948 .flags = CLK_SET_RATE_PARENT, 1949 }, 1950 }, 1951 }; 1952 1953 static struct clk_branch sata_phy_ref_clk = { 1954 .halt_reg = 0x2fdc, 1955 .halt_bit = 18, 1956 .clkr = { 1957 .enable_reg = 0x2c14, 1958 .enable_mask = BIT(4), 1959 .hw.init = &(struct clk_init_data){ 1960 .name = "sata_phy_ref_clk", 1961 .parent_data = gcc_pxo, 1962 .num_parents = 1, 1963 .ops = &clk_branch_ops, 1964 }, 1965 }, 1966 }; 1967 1968 static struct clk_branch sata_a_clk = { 1969 .halt_reg = 0x2fc0, 1970 .halt_bit = 12, 1971 .clkr = { 1972 .enable_reg = 0x2c20, 1973 .enable_mask = BIT(4), 1974 .hw.init = &(struct clk_init_data){ 1975 .name = "sata_a_clk", 1976 .ops = &clk_branch_ops, 1977 }, 1978 }, 1979 }; 1980 1981 static struct clk_branch sata_h_clk = { 1982 .halt_reg = 0x2fdc, 1983 .halt_bit = 21, 1984 .clkr = { 1985 .enable_reg = 0x2c00, 1986 .enable_mask = BIT(4), 1987 .hw.init = &(struct clk_init_data){ 1988 .name = "sata_h_clk", 1989 .ops = &clk_branch_ops, 1990 }, 1991 }, 1992 }; 1993 1994 static struct clk_branch sfab_sata_s_h_clk = { 1995 .halt_reg = 0x2fc4, 1996 .halt_bit = 14, 1997 .clkr = { 1998 .enable_reg = 0x2480, 1999 .enable_mask = BIT(4), 2000 .hw.init = &(struct clk_init_data){ 2001 .name = "sfab_sata_s_h_clk", 2002 .ops = &clk_branch_ops, 2003 }, 2004 }, 2005 }; 2006 2007 static struct clk_branch sata_phy_cfg_clk = { 2008 .halt_reg = 0x2fcc, 2009 .halt_bit = 14, 2010 .clkr = { 2011 .enable_reg = 0x2c40, 2012 .enable_mask = BIT(4), 2013 .hw.init = &(struct clk_init_data){ 2014 .name = "sata_phy_cfg_clk", 2015 .ops = &clk_branch_ops, 2016 }, 2017 }, 2018 }; 2019 2020 static const struct freq_tbl clk_tbl_usb30_master[] = { 2021 { 125000000, P_PLL0, 1, 5, 32 }, 2022 { } 2023 }; 2024 2025 static struct clk_rcg usb30_master_clk_src = { 2026 .ns_reg = 0x3b2c, 2027 .md_reg = 0x3b28, 2028 .mn = { 2029 .mnctr_en_bit = 8, 2030 .mnctr_reset_bit = 7, 2031 .mnctr_mode_shift = 5, 2032 .n_val_shift = 16, 2033 .m_val_shift = 16, 2034 .width = 8, 2035 }, 2036 .p = { 2037 .pre_div_shift = 3, 2038 .pre_div_width = 2, 2039 }, 2040 .s = { 2041 .src_sel_shift = 0, 2042 .parent_map = gcc_pxo_pll8_pll0_map, 2043 }, 2044 .freq_tbl = clk_tbl_usb30_master, 2045 .clkr = { 2046 .enable_reg = 0x3b2c, 2047 .enable_mask = BIT(11), 2048 .hw.init = &(struct clk_init_data){ 2049 .name = "usb30_master_ref_src", 2050 .parent_data = gcc_pxo_pll8_pll0, 2051 .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0), 2052 .ops = &clk_rcg_ops, 2053 .flags = CLK_SET_RATE_GATE, 2054 }, 2055 }, 2056 }; 2057 2058 static struct clk_branch usb30_0_branch_clk = { 2059 .halt_reg = 0x2fc4, 2060 .halt_bit = 22, 2061 .clkr = { 2062 .enable_reg = 0x3b24, 2063 .enable_mask = BIT(4), 2064 .hw.init = &(struct clk_init_data){ 2065 .name = "usb30_0_branch_clk", 2066 .parent_hws = (const struct clk_hw*[]){ 2067 &usb30_master_clk_src.clkr.hw, 2068 }, 2069 .num_parents = 1, 2070 .ops = &clk_branch_ops, 2071 .flags = CLK_SET_RATE_PARENT, 2072 }, 2073 }, 2074 }; 2075 2076 static struct clk_branch usb30_1_branch_clk = { 2077 .halt_reg = 0x2fc4, 2078 .halt_bit = 17, 2079 .clkr = { 2080 .enable_reg = 0x3b34, 2081 .enable_mask = BIT(4), 2082 .hw.init = &(struct clk_init_data){ 2083 .name = "usb30_1_branch_clk", 2084 .parent_hws = (const struct clk_hw*[]){ 2085 &usb30_master_clk_src.clkr.hw, 2086 }, 2087 .num_parents = 1, 2088 .ops = &clk_branch_ops, 2089 .flags = CLK_SET_RATE_PARENT, 2090 }, 2091 }, 2092 }; 2093 2094 static const struct freq_tbl clk_tbl_usb30_utmi[] = { 2095 { 60000000, P_PLL8, 1, 5, 32 }, 2096 { } 2097 }; 2098 2099 static struct clk_rcg usb30_utmi_clk = { 2100 .ns_reg = 0x3b44, 2101 .md_reg = 0x3b40, 2102 .mn = { 2103 .mnctr_en_bit = 8, 2104 .mnctr_reset_bit = 7, 2105 .mnctr_mode_shift = 5, 2106 .n_val_shift = 16, 2107 .m_val_shift = 16, 2108 .width = 8, 2109 }, 2110 .p = { 2111 .pre_div_shift = 3, 2112 .pre_div_width = 2, 2113 }, 2114 .s = { 2115 .src_sel_shift = 0, 2116 .parent_map = gcc_pxo_pll8_pll0_map, 2117 }, 2118 .freq_tbl = clk_tbl_usb30_utmi, 2119 .clkr = { 2120 .enable_reg = 0x3b44, 2121 .enable_mask = BIT(11), 2122 .hw.init = &(struct clk_init_data){ 2123 .name = "usb30_utmi_clk", 2124 .parent_data = gcc_pxo_pll8_pll0, 2125 .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0), 2126 .ops = &clk_rcg_ops, 2127 .flags = CLK_SET_RATE_GATE, 2128 }, 2129 }, 2130 }; 2131 2132 static struct clk_branch usb30_0_utmi_clk_ctl = { 2133 .halt_reg = 0x2fc4, 2134 .halt_bit = 21, 2135 .clkr = { 2136 .enable_reg = 0x3b48, 2137 .enable_mask = BIT(4), 2138 .hw.init = &(struct clk_init_data){ 2139 .name = "usb30_0_utmi_clk_ctl", 2140 .parent_hws = (const struct clk_hw*[]){ 2141 &usb30_utmi_clk.clkr.hw, 2142 }, 2143 .num_parents = 1, 2144 .ops = &clk_branch_ops, 2145 .flags = CLK_SET_RATE_PARENT, 2146 }, 2147 }, 2148 }; 2149 2150 static struct clk_branch usb30_1_utmi_clk_ctl = { 2151 .halt_reg = 0x2fc4, 2152 .halt_bit = 15, 2153 .clkr = { 2154 .enable_reg = 0x3b4c, 2155 .enable_mask = BIT(4), 2156 .hw.init = &(struct clk_init_data){ 2157 .name = "usb30_1_utmi_clk_ctl", 2158 .parent_hws = (const struct clk_hw*[]){ 2159 &usb30_utmi_clk.clkr.hw, 2160 }, 2161 .num_parents = 1, 2162 .ops = &clk_branch_ops, 2163 .flags = CLK_SET_RATE_PARENT, 2164 }, 2165 }, 2166 }; 2167 2168 static const struct freq_tbl clk_tbl_usb[] = { 2169 { 60000000, P_PLL8, 1, 5, 32 }, 2170 { } 2171 }; 2172 2173 static struct clk_rcg usb_hs1_xcvr_clk_src = { 2174 .ns_reg = 0x290C, 2175 .md_reg = 0x2908, 2176 .mn = { 2177 .mnctr_en_bit = 8, 2178 .mnctr_reset_bit = 7, 2179 .mnctr_mode_shift = 5, 2180 .n_val_shift = 16, 2181 .m_val_shift = 16, 2182 .width = 8, 2183 }, 2184 .p = { 2185 .pre_div_shift = 3, 2186 .pre_div_width = 2, 2187 }, 2188 .s = { 2189 .src_sel_shift = 0, 2190 .parent_map = gcc_pxo_pll8_pll0_map, 2191 }, 2192 .freq_tbl = clk_tbl_usb, 2193 .clkr = { 2194 .enable_reg = 0x2968, 2195 .enable_mask = BIT(11), 2196 .hw.init = &(struct clk_init_data){ 2197 .name = "usb_hs1_xcvr_src", 2198 .parent_data = gcc_pxo_pll8_pll0, 2199 .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0), 2200 .ops = &clk_rcg_ops, 2201 .flags = CLK_SET_RATE_GATE, 2202 }, 2203 }, 2204 }; 2205 2206 static struct clk_branch usb_hs1_xcvr_clk = { 2207 .halt_reg = 0x2fcc, 2208 .halt_bit = 17, 2209 .clkr = { 2210 .enable_reg = 0x290c, 2211 .enable_mask = BIT(9), 2212 .hw.init = &(struct clk_init_data){ 2213 .name = "usb_hs1_xcvr_clk", 2214 .parent_hws = (const struct clk_hw*[]){ 2215 &usb_hs1_xcvr_clk_src.clkr.hw, 2216 }, 2217 .num_parents = 1, 2218 .ops = &clk_branch_ops, 2219 .flags = CLK_SET_RATE_PARENT, 2220 }, 2221 }, 2222 }; 2223 2224 static struct clk_branch usb_hs1_h_clk = { 2225 .hwcg_reg = 0x2900, 2226 .hwcg_bit = 6, 2227 .halt_reg = 0x2fc8, 2228 .halt_bit = 1, 2229 .clkr = { 2230 .enable_reg = 0x2900, 2231 .enable_mask = BIT(4), 2232 .hw.init = &(struct clk_init_data){ 2233 .name = "usb_hs1_h_clk", 2234 .ops = &clk_branch_ops, 2235 }, 2236 }, 2237 }; 2238 2239 static struct clk_rcg usb_fs1_xcvr_clk_src = { 2240 .ns_reg = 0x2968, 2241 .md_reg = 0x2964, 2242 .mn = { 2243 .mnctr_en_bit = 8, 2244 .mnctr_reset_bit = 7, 2245 .mnctr_mode_shift = 5, 2246 .n_val_shift = 16, 2247 .m_val_shift = 16, 2248 .width = 8, 2249 }, 2250 .p = { 2251 .pre_div_shift = 3, 2252 .pre_div_width = 2, 2253 }, 2254 .s = { 2255 .src_sel_shift = 0, 2256 .parent_map = gcc_pxo_pll8_pll0_map, 2257 }, 2258 .freq_tbl = clk_tbl_usb, 2259 .clkr = { 2260 .enable_reg = 0x2968, 2261 .enable_mask = BIT(11), 2262 .hw.init = &(struct clk_init_data){ 2263 .name = "usb_fs1_xcvr_src", 2264 .parent_data = gcc_pxo_pll8_pll0, 2265 .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0), 2266 .ops = &clk_rcg_ops, 2267 .flags = CLK_SET_RATE_GATE, 2268 }, 2269 }, 2270 }; 2271 2272 static struct clk_branch usb_fs1_xcvr_clk = { 2273 .halt_reg = 0x2fcc, 2274 .halt_bit = 17, 2275 .clkr = { 2276 .enable_reg = 0x2968, 2277 .enable_mask = BIT(9), 2278 .hw.init = &(struct clk_init_data){ 2279 .name = "usb_fs1_xcvr_clk", 2280 .parent_hws = (const struct clk_hw*[]){ 2281 &usb_fs1_xcvr_clk_src.clkr.hw, 2282 }, 2283 .num_parents = 1, 2284 .ops = &clk_branch_ops, 2285 .flags = CLK_SET_RATE_PARENT, 2286 }, 2287 }, 2288 }; 2289 2290 static struct clk_branch usb_fs1_sys_clk = { 2291 .halt_reg = 0x2fcc, 2292 .halt_bit = 18, 2293 .clkr = { 2294 .enable_reg = 0x296c, 2295 .enable_mask = BIT(4), 2296 .hw.init = &(struct clk_init_data){ 2297 .name = "usb_fs1_sys_clk", 2298 .parent_hws = (const struct clk_hw*[]){ 2299 &usb_fs1_xcvr_clk_src.clkr.hw, 2300 }, 2301 .num_parents = 1, 2302 .ops = &clk_branch_ops, 2303 .flags = CLK_SET_RATE_PARENT, 2304 }, 2305 }, 2306 }; 2307 2308 static struct clk_branch usb_fs1_h_clk = { 2309 .halt_reg = 0x2fcc, 2310 .halt_bit = 19, 2311 .clkr = { 2312 .enable_reg = 0x2960, 2313 .enable_mask = BIT(4), 2314 .hw.init = &(struct clk_init_data){ 2315 .name = "usb_fs1_h_clk", 2316 .ops = &clk_branch_ops, 2317 }, 2318 }, 2319 }; 2320 2321 static struct clk_branch ebi2_clk = { 2322 .hwcg_reg = 0x3b00, 2323 .hwcg_bit = 6, 2324 .halt_reg = 0x2fcc, 2325 .halt_bit = 1, 2326 .clkr = { 2327 .enable_reg = 0x3b00, 2328 .enable_mask = BIT(4), 2329 .hw.init = &(struct clk_init_data){ 2330 .name = "ebi2_clk", 2331 .ops = &clk_branch_ops, 2332 }, 2333 }, 2334 }; 2335 2336 static struct clk_branch ebi2_aon_clk = { 2337 .halt_reg = 0x2fcc, 2338 .halt_bit = 0, 2339 .clkr = { 2340 .enable_reg = 0x3b00, 2341 .enable_mask = BIT(8), 2342 .hw.init = &(struct clk_init_data){ 2343 .name = "ebi2_always_on_clk", 2344 .ops = &clk_branch_ops, 2345 }, 2346 }, 2347 }; 2348 2349 static const struct freq_tbl clk_tbl_gmac[] = { 2350 { 133000000, P_PLL0, 1, 50, 301 }, 2351 { 266000000, P_PLL0, 1, 127, 382 }, 2352 { } 2353 }; 2354 2355 static struct clk_dyn_rcg gmac_core1_src = { 2356 .ns_reg[0] = 0x3cac, 2357 .ns_reg[1] = 0x3cb0, 2358 .md_reg[0] = 0x3ca4, 2359 .md_reg[1] = 0x3ca8, 2360 .bank_reg = 0x3ca0, 2361 .mn[0] = { 2362 .mnctr_en_bit = 8, 2363 .mnctr_reset_bit = 7, 2364 .mnctr_mode_shift = 5, 2365 .n_val_shift = 16, 2366 .m_val_shift = 16, 2367 .width = 8, 2368 }, 2369 .mn[1] = { 2370 .mnctr_en_bit = 8, 2371 .mnctr_reset_bit = 7, 2372 .mnctr_mode_shift = 5, 2373 .n_val_shift = 16, 2374 .m_val_shift = 16, 2375 .width = 8, 2376 }, 2377 .s[0] = { 2378 .src_sel_shift = 0, 2379 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, 2380 }, 2381 .s[1] = { 2382 .src_sel_shift = 0, 2383 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, 2384 }, 2385 .p[0] = { 2386 .pre_div_shift = 3, 2387 .pre_div_width = 2, 2388 }, 2389 .p[1] = { 2390 .pre_div_shift = 3, 2391 .pre_div_width = 2, 2392 }, 2393 .mux_sel_bit = 0, 2394 .freq_tbl = clk_tbl_gmac, 2395 .clkr = { 2396 .enable_reg = 0x3ca0, 2397 .enable_mask = BIT(1), 2398 .hw.init = &(struct clk_init_data){ 2399 .name = "gmac_core1_src", 2400 .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, 2401 .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), 2402 .ops = &clk_dyn_rcg_ops, 2403 }, 2404 }, 2405 }; 2406 2407 static struct clk_branch gmac_core1_clk = { 2408 .halt_reg = 0x3c20, 2409 .halt_bit = 4, 2410 .hwcg_reg = 0x3cb4, 2411 .hwcg_bit = 6, 2412 .clkr = { 2413 .enable_reg = 0x3cb4, 2414 .enable_mask = BIT(4), 2415 .hw.init = &(struct clk_init_data){ 2416 .name = "gmac_core1_clk", 2417 .parent_hws = (const struct clk_hw*[]){ 2418 &gmac_core1_src.clkr.hw, 2419 }, 2420 .num_parents = 1, 2421 .ops = &clk_branch_ops, 2422 .flags = CLK_SET_RATE_PARENT, 2423 }, 2424 }, 2425 }; 2426 2427 static struct clk_dyn_rcg gmac_core2_src = { 2428 .ns_reg[0] = 0x3ccc, 2429 .ns_reg[1] = 0x3cd0, 2430 .md_reg[0] = 0x3cc4, 2431 .md_reg[1] = 0x3cc8, 2432 .bank_reg = 0x3ca0, 2433 .mn[0] = { 2434 .mnctr_en_bit = 8, 2435 .mnctr_reset_bit = 7, 2436 .mnctr_mode_shift = 5, 2437 .n_val_shift = 16, 2438 .m_val_shift = 16, 2439 .width = 8, 2440 }, 2441 .mn[1] = { 2442 .mnctr_en_bit = 8, 2443 .mnctr_reset_bit = 7, 2444 .mnctr_mode_shift = 5, 2445 .n_val_shift = 16, 2446 .m_val_shift = 16, 2447 .width = 8, 2448 }, 2449 .s[0] = { 2450 .src_sel_shift = 0, 2451 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, 2452 }, 2453 .s[1] = { 2454 .src_sel_shift = 0, 2455 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, 2456 }, 2457 .p[0] = { 2458 .pre_div_shift = 3, 2459 .pre_div_width = 2, 2460 }, 2461 .p[1] = { 2462 .pre_div_shift = 3, 2463 .pre_div_width = 2, 2464 }, 2465 .mux_sel_bit = 0, 2466 .freq_tbl = clk_tbl_gmac, 2467 .clkr = { 2468 .enable_reg = 0x3cc0, 2469 .enable_mask = BIT(1), 2470 .hw.init = &(struct clk_init_data){ 2471 .name = "gmac_core2_src", 2472 .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, 2473 .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), 2474 .ops = &clk_dyn_rcg_ops, 2475 }, 2476 }, 2477 }; 2478 2479 static struct clk_branch gmac_core2_clk = { 2480 .halt_reg = 0x3c20, 2481 .halt_bit = 5, 2482 .hwcg_reg = 0x3cd4, 2483 .hwcg_bit = 6, 2484 .clkr = { 2485 .enable_reg = 0x3cd4, 2486 .enable_mask = BIT(4), 2487 .hw.init = &(struct clk_init_data){ 2488 .name = "gmac_core2_clk", 2489 .parent_hws = (const struct clk_hw*[]){ 2490 &gmac_core2_src.clkr.hw, 2491 }, 2492 .num_parents = 1, 2493 .ops = &clk_branch_ops, 2494 .flags = CLK_SET_RATE_PARENT, 2495 }, 2496 }, 2497 }; 2498 2499 static struct clk_dyn_rcg gmac_core3_src = { 2500 .ns_reg[0] = 0x3cec, 2501 .ns_reg[1] = 0x3cf0, 2502 .md_reg[0] = 0x3ce4, 2503 .md_reg[1] = 0x3ce8, 2504 .bank_reg = 0x3ce0, 2505 .mn[0] = { 2506 .mnctr_en_bit = 8, 2507 .mnctr_reset_bit = 7, 2508 .mnctr_mode_shift = 5, 2509 .n_val_shift = 16, 2510 .m_val_shift = 16, 2511 .width = 8, 2512 }, 2513 .mn[1] = { 2514 .mnctr_en_bit = 8, 2515 .mnctr_reset_bit = 7, 2516 .mnctr_mode_shift = 5, 2517 .n_val_shift = 16, 2518 .m_val_shift = 16, 2519 .width = 8, 2520 }, 2521 .s[0] = { 2522 .src_sel_shift = 0, 2523 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, 2524 }, 2525 .s[1] = { 2526 .src_sel_shift = 0, 2527 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, 2528 }, 2529 .p[0] = { 2530 .pre_div_shift = 3, 2531 .pre_div_width = 2, 2532 }, 2533 .p[1] = { 2534 .pre_div_shift = 3, 2535 .pre_div_width = 2, 2536 }, 2537 .mux_sel_bit = 0, 2538 .freq_tbl = clk_tbl_gmac, 2539 .clkr = { 2540 .enable_reg = 0x3ce0, 2541 .enable_mask = BIT(1), 2542 .hw.init = &(struct clk_init_data){ 2543 .name = "gmac_core3_src", 2544 .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, 2545 .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), 2546 .ops = &clk_dyn_rcg_ops, 2547 }, 2548 }, 2549 }; 2550 2551 static struct clk_branch gmac_core3_clk = { 2552 .halt_reg = 0x3c20, 2553 .halt_bit = 6, 2554 .hwcg_reg = 0x3cf4, 2555 .hwcg_bit = 6, 2556 .clkr = { 2557 .enable_reg = 0x3cf4, 2558 .enable_mask = BIT(4), 2559 .hw.init = &(struct clk_init_data){ 2560 .name = "gmac_core3_clk", 2561 .parent_hws = (const struct clk_hw*[]){ 2562 &gmac_core3_src.clkr.hw, 2563 }, 2564 .num_parents = 1, 2565 .ops = &clk_branch_ops, 2566 .flags = CLK_SET_RATE_PARENT, 2567 }, 2568 }, 2569 }; 2570 2571 static struct clk_dyn_rcg gmac_core4_src = { 2572 .ns_reg[0] = 0x3d0c, 2573 .ns_reg[1] = 0x3d10, 2574 .md_reg[0] = 0x3d04, 2575 .md_reg[1] = 0x3d08, 2576 .bank_reg = 0x3d00, 2577 .mn[0] = { 2578 .mnctr_en_bit = 8, 2579 .mnctr_reset_bit = 7, 2580 .mnctr_mode_shift = 5, 2581 .n_val_shift = 16, 2582 .m_val_shift = 16, 2583 .width = 8, 2584 }, 2585 .mn[1] = { 2586 .mnctr_en_bit = 8, 2587 .mnctr_reset_bit = 7, 2588 .mnctr_mode_shift = 5, 2589 .n_val_shift = 16, 2590 .m_val_shift = 16, 2591 .width = 8, 2592 }, 2593 .s[0] = { 2594 .src_sel_shift = 0, 2595 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, 2596 }, 2597 .s[1] = { 2598 .src_sel_shift = 0, 2599 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, 2600 }, 2601 .p[0] = { 2602 .pre_div_shift = 3, 2603 .pre_div_width = 2, 2604 }, 2605 .p[1] = { 2606 .pre_div_shift = 3, 2607 .pre_div_width = 2, 2608 }, 2609 .mux_sel_bit = 0, 2610 .freq_tbl = clk_tbl_gmac, 2611 .clkr = { 2612 .enable_reg = 0x3d00, 2613 .enable_mask = BIT(1), 2614 .hw.init = &(struct clk_init_data){ 2615 .name = "gmac_core4_src", 2616 .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, 2617 .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), 2618 .ops = &clk_dyn_rcg_ops, 2619 }, 2620 }, 2621 }; 2622 2623 static struct clk_branch gmac_core4_clk = { 2624 .halt_reg = 0x3c20, 2625 .halt_bit = 7, 2626 .hwcg_reg = 0x3d14, 2627 .hwcg_bit = 6, 2628 .clkr = { 2629 .enable_reg = 0x3d14, 2630 .enable_mask = BIT(4), 2631 .hw.init = &(struct clk_init_data){ 2632 .name = "gmac_core4_clk", 2633 .parent_hws = (const struct clk_hw*[]){ 2634 &gmac_core4_src.clkr.hw, 2635 }, 2636 .num_parents = 1, 2637 .ops = &clk_branch_ops, 2638 .flags = CLK_SET_RATE_PARENT, 2639 }, 2640 }, 2641 }; 2642 2643 static const struct freq_tbl clk_tbl_nss_tcm[] = { 2644 { 266000000, P_PLL0, 3, 0, 0 }, 2645 { 400000000, P_PLL0, 2, 0, 0 }, 2646 { } 2647 }; 2648 2649 static struct clk_dyn_rcg nss_tcm_src = { 2650 .ns_reg[0] = 0x3dc4, 2651 .ns_reg[1] = 0x3dc8, 2652 .bank_reg = 0x3dc0, 2653 .s[0] = { 2654 .src_sel_shift = 0, 2655 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, 2656 }, 2657 .s[1] = { 2658 .src_sel_shift = 0, 2659 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, 2660 }, 2661 .p[0] = { 2662 .pre_div_shift = 3, 2663 .pre_div_width = 4, 2664 }, 2665 .p[1] = { 2666 .pre_div_shift = 3, 2667 .pre_div_width = 4, 2668 }, 2669 .mux_sel_bit = 0, 2670 .freq_tbl = clk_tbl_nss_tcm, 2671 .clkr = { 2672 .enable_reg = 0x3dc0, 2673 .enable_mask = BIT(1), 2674 .hw.init = &(struct clk_init_data){ 2675 .name = "nss_tcm_src", 2676 .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, 2677 .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), 2678 .ops = &clk_dyn_rcg_ops, 2679 }, 2680 }, 2681 }; 2682 2683 static struct clk_branch nss_tcm_clk = { 2684 .halt_reg = 0x3c20, 2685 .halt_bit = 14, 2686 .clkr = { 2687 .enable_reg = 0x3dd0, 2688 .enable_mask = BIT(6) | BIT(4), 2689 .hw.init = &(struct clk_init_data){ 2690 .name = "nss_tcm_clk", 2691 .parent_hws = (const struct clk_hw*[]){ 2692 &nss_tcm_src.clkr.hw, 2693 }, 2694 .num_parents = 1, 2695 .ops = &clk_branch_ops, 2696 .flags = CLK_SET_RATE_PARENT, 2697 }, 2698 }, 2699 }; 2700 2701 static const struct freq_tbl clk_tbl_nss[] = { 2702 { 110000000, P_PLL18, 1, 1, 5 }, 2703 { 275000000, P_PLL18, 2, 0, 0 }, 2704 { 550000000, P_PLL18, 1, 0, 0 }, 2705 { 733000000, P_PLL18, 1, 0, 0 }, 2706 { } 2707 }; 2708 2709 static struct clk_dyn_rcg ubi32_core1_src_clk = { 2710 .ns_reg[0] = 0x3d2c, 2711 .ns_reg[1] = 0x3d30, 2712 .md_reg[0] = 0x3d24, 2713 .md_reg[1] = 0x3d28, 2714 .bank_reg = 0x3d20, 2715 .mn[0] = { 2716 .mnctr_en_bit = 8, 2717 .mnctr_reset_bit = 7, 2718 .mnctr_mode_shift = 5, 2719 .n_val_shift = 16, 2720 .m_val_shift = 16, 2721 .width = 8, 2722 }, 2723 .mn[1] = { 2724 .mnctr_en_bit = 8, 2725 .mnctr_reset_bit = 7, 2726 .mnctr_mode_shift = 5, 2727 .n_val_shift = 16, 2728 .m_val_shift = 16, 2729 .width = 8, 2730 }, 2731 .s[0] = { 2732 .src_sel_shift = 0, 2733 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, 2734 }, 2735 .s[1] = { 2736 .src_sel_shift = 0, 2737 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, 2738 }, 2739 .p[0] = { 2740 .pre_div_shift = 3, 2741 .pre_div_width = 2, 2742 }, 2743 .p[1] = { 2744 .pre_div_shift = 3, 2745 .pre_div_width = 2, 2746 }, 2747 .mux_sel_bit = 0, 2748 .freq_tbl = clk_tbl_nss, 2749 .clkr = { 2750 .enable_reg = 0x3d20, 2751 .enable_mask = BIT(1), 2752 .hw.init = &(struct clk_init_data){ 2753 .name = "ubi32_core1_src_clk", 2754 .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, 2755 .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), 2756 .ops = &clk_dyn_rcg_ops, 2757 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, 2758 }, 2759 }, 2760 }; 2761 2762 static struct clk_dyn_rcg ubi32_core2_src_clk = { 2763 .ns_reg[0] = 0x3d4c, 2764 .ns_reg[1] = 0x3d50, 2765 .md_reg[0] = 0x3d44, 2766 .md_reg[1] = 0x3d48, 2767 .bank_reg = 0x3d40, 2768 .mn[0] = { 2769 .mnctr_en_bit = 8, 2770 .mnctr_reset_bit = 7, 2771 .mnctr_mode_shift = 5, 2772 .n_val_shift = 16, 2773 .m_val_shift = 16, 2774 .width = 8, 2775 }, 2776 .mn[1] = { 2777 .mnctr_en_bit = 8, 2778 .mnctr_reset_bit = 7, 2779 .mnctr_mode_shift = 5, 2780 .n_val_shift = 16, 2781 .m_val_shift = 16, 2782 .width = 8, 2783 }, 2784 .s[0] = { 2785 .src_sel_shift = 0, 2786 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, 2787 }, 2788 .s[1] = { 2789 .src_sel_shift = 0, 2790 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, 2791 }, 2792 .p[0] = { 2793 .pre_div_shift = 3, 2794 .pre_div_width = 2, 2795 }, 2796 .p[1] = { 2797 .pre_div_shift = 3, 2798 .pre_div_width = 2, 2799 }, 2800 .mux_sel_bit = 0, 2801 .freq_tbl = clk_tbl_nss, 2802 .clkr = { 2803 .enable_reg = 0x3d40, 2804 .enable_mask = BIT(1), 2805 .hw.init = &(struct clk_init_data){ 2806 .name = "ubi32_core2_src_clk", 2807 .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, 2808 .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), 2809 .ops = &clk_dyn_rcg_ops, 2810 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, 2811 }, 2812 }, 2813 }; 2814 2815 static struct clk_regmap *gcc_ipq806x_clks[] = { 2816 [PLL0] = &pll0.clkr, 2817 [PLL0_VOTE] = &pll0_vote, 2818 [PLL3] = &pll3.clkr, 2819 [PLL4_VOTE] = &pll4_vote, 2820 [PLL8] = &pll8.clkr, 2821 [PLL8_VOTE] = &pll8_vote, 2822 [PLL14] = &pll14.clkr, 2823 [PLL14_VOTE] = &pll14_vote, 2824 [PLL18] = &pll18.clkr, 2825 [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr, 2826 [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr, 2827 [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr, 2828 [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr, 2829 [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr, 2830 [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr, 2831 [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr, 2832 [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr, 2833 [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr, 2834 [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr, 2835 [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr, 2836 [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr, 2837 [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr, 2838 [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr, 2839 [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr, 2840 [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr, 2841 [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr, 2842 [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr, 2843 [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr, 2844 [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr, 2845 [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr, 2846 [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr, 2847 [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr, 2848 [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr, 2849 [GP0_SRC] = &gp0_src.clkr, 2850 [GP0_CLK] = &gp0_clk.clkr, 2851 [GP1_SRC] = &gp1_src.clkr, 2852 [GP1_CLK] = &gp1_clk.clkr, 2853 [GP2_SRC] = &gp2_src.clkr, 2854 [GP2_CLK] = &gp2_clk.clkr, 2855 [PMEM_A_CLK] = &pmem_clk.clkr, 2856 [PRNG_SRC] = &prng_src.clkr, 2857 [PRNG_CLK] = &prng_clk.clkr, 2858 [SDC1_SRC] = &sdc1_src.clkr, 2859 [SDC1_CLK] = &sdc1_clk.clkr, 2860 [SDC3_SRC] = &sdc3_src.clkr, 2861 [SDC3_CLK] = &sdc3_clk.clkr, 2862 [TSIF_REF_SRC] = &tsif_ref_src.clkr, 2863 [TSIF_REF_CLK] = &tsif_ref_clk.clkr, 2864 [DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr, 2865 [GSBI1_H_CLK] = &gsbi1_h_clk.clkr, 2866 [GSBI2_H_CLK] = &gsbi2_h_clk.clkr, 2867 [GSBI4_H_CLK] = &gsbi4_h_clk.clkr, 2868 [GSBI5_H_CLK] = &gsbi5_h_clk.clkr, 2869 [GSBI6_H_CLK] = &gsbi6_h_clk.clkr, 2870 [GSBI7_H_CLK] = &gsbi7_h_clk.clkr, 2871 [TSIF_H_CLK] = &tsif_h_clk.clkr, 2872 [SDC1_H_CLK] = &sdc1_h_clk.clkr, 2873 [SDC3_H_CLK] = &sdc3_h_clk.clkr, 2874 [ADM0_CLK] = &adm0_clk.clkr, 2875 [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr, 2876 [PCIE_A_CLK] = &pcie_a_clk.clkr, 2877 [PCIE_AUX_CLK] = &pcie_aux_clk.clkr, 2878 [PCIE_H_CLK] = &pcie_h_clk.clkr, 2879 [PCIE_PHY_CLK] = &pcie_phy_clk.clkr, 2880 [SFAB_SATA_S_H_CLK] = &sfab_sata_s_h_clk.clkr, 2881 [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr, 2882 [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr, 2883 [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr, 2884 [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr, 2885 [SATA_H_CLK] = &sata_h_clk.clkr, 2886 [SATA_CLK_SRC] = &sata_ref_src.clkr, 2887 [SATA_RXOOB_CLK] = &sata_rxoob_clk.clkr, 2888 [SATA_PMALIVE_CLK] = &sata_pmalive_clk.clkr, 2889 [SATA_PHY_REF_CLK] = &sata_phy_ref_clk.clkr, 2890 [SATA_A_CLK] = &sata_a_clk.clkr, 2891 [SATA_PHY_CFG_CLK] = &sata_phy_cfg_clk.clkr, 2892 [PCIE_ALT_REF_SRC] = &pcie_ref_src.clkr, 2893 [PCIE_ALT_REF_CLK] = &pcie_ref_src_clk.clkr, 2894 [PCIE_1_A_CLK] = &pcie1_a_clk.clkr, 2895 [PCIE_1_AUX_CLK] = &pcie1_aux_clk.clkr, 2896 [PCIE_1_H_CLK] = &pcie1_h_clk.clkr, 2897 [PCIE_1_PHY_CLK] = &pcie1_phy_clk.clkr, 2898 [PCIE_1_ALT_REF_SRC] = &pcie1_ref_src.clkr, 2899 [PCIE_1_ALT_REF_CLK] = &pcie1_ref_src_clk.clkr, 2900 [PCIE_2_A_CLK] = &pcie2_a_clk.clkr, 2901 [PCIE_2_AUX_CLK] = &pcie2_aux_clk.clkr, 2902 [PCIE_2_H_CLK] = &pcie2_h_clk.clkr, 2903 [PCIE_2_PHY_CLK] = &pcie2_phy_clk.clkr, 2904 [PCIE_2_ALT_REF_SRC] = &pcie2_ref_src.clkr, 2905 [PCIE_2_ALT_REF_CLK] = &pcie2_ref_src_clk.clkr, 2906 [USB30_MASTER_SRC] = &usb30_master_clk_src.clkr, 2907 [USB30_0_MASTER_CLK] = &usb30_0_branch_clk.clkr, 2908 [USB30_1_MASTER_CLK] = &usb30_1_branch_clk.clkr, 2909 [USB30_UTMI_SRC] = &usb30_utmi_clk.clkr, 2910 [USB30_0_UTMI_CLK] = &usb30_0_utmi_clk_ctl.clkr, 2911 [USB30_1_UTMI_CLK] = &usb30_1_utmi_clk_ctl.clkr, 2912 [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr, 2913 [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_clk_src.clkr, 2914 [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr, 2915 [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr, 2916 [USB_FS1_XCVR_SRC] = &usb_fs1_xcvr_clk_src.clkr, 2917 [USB_FS1_XCVR_CLK] = &usb_fs1_xcvr_clk.clkr, 2918 [USB_FS1_SYSTEM_CLK] = &usb_fs1_sys_clk.clkr, 2919 [EBI2_CLK] = &ebi2_clk.clkr, 2920 [EBI2_AON_CLK] = &ebi2_aon_clk.clkr, 2921 [GMAC_CORE1_CLK_SRC] = &gmac_core1_src.clkr, 2922 [GMAC_CORE1_CLK] = &gmac_core1_clk.clkr, 2923 [GMAC_CORE2_CLK_SRC] = &gmac_core2_src.clkr, 2924 [GMAC_CORE2_CLK] = &gmac_core2_clk.clkr, 2925 [GMAC_CORE3_CLK_SRC] = &gmac_core3_src.clkr, 2926 [GMAC_CORE3_CLK] = &gmac_core3_clk.clkr, 2927 [GMAC_CORE4_CLK_SRC] = &gmac_core4_src.clkr, 2928 [GMAC_CORE4_CLK] = &gmac_core4_clk.clkr, 2929 [UBI32_CORE1_CLK_SRC] = &ubi32_core1_src_clk.clkr, 2930 [UBI32_CORE2_CLK_SRC] = &ubi32_core2_src_clk.clkr, 2931 [NSSTCM_CLK_SRC] = &nss_tcm_src.clkr, 2932 [NSSTCM_CLK] = &nss_tcm_clk.clkr, 2933 [PLL9] = &hfpll0.clkr, 2934 [PLL10] = &hfpll1.clkr, 2935 [PLL12] = &hfpll_l2.clkr, 2936 }; 2937 2938 static const struct qcom_reset_map gcc_ipq806x_resets[] = { 2939 [QDSS_STM_RESET] = { 0x2060, 6 }, 2940 [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 }, 2941 [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 }, 2942 [AFAB_SMPSS_M0_RESET] = { 0x20b8, 0 }, 2943 [AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 }, 2944 [AFAB_EBI1_CH1_RESET] = { 0x20c4, 7 }, 2945 [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 }, 2946 [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 }, 2947 [SFAB_ADM0_M2_RESET] = { 0x21e8, 7 }, 2948 [ADM0_C2_RESET] = { 0x220c, 4 }, 2949 [ADM0_C1_RESET] = { 0x220c, 3 }, 2950 [ADM0_C0_RESET] = { 0x220c, 2 }, 2951 [ADM0_PBUS_RESET] = { 0x220c, 1 }, 2952 [ADM0_RESET] = { 0x220c, 0 }, 2953 [QDSS_CLKS_SW_RESET] = { 0x2260, 5 }, 2954 [QDSS_POR_RESET] = { 0x2260, 4 }, 2955 [QDSS_TSCTR_RESET] = { 0x2260, 3 }, 2956 [QDSS_HRESET_RESET] = { 0x2260, 2 }, 2957 [QDSS_AXI_RESET] = { 0x2260, 1 }, 2958 [QDSS_DBG_RESET] = { 0x2260, 0 }, 2959 [SFAB_PCIE_M_RESET] = { 0x22d8, 1 }, 2960 [SFAB_PCIE_S_RESET] = { 0x22d8, 0 }, 2961 [PCIE_EXT_RESET] = { 0x22dc, 6 }, 2962 [PCIE_PHY_RESET] = { 0x22dc, 5 }, 2963 [PCIE_PCI_RESET] = { 0x22dc, 4 }, 2964 [PCIE_POR_RESET] = { 0x22dc, 3 }, 2965 [PCIE_HCLK_RESET] = { 0x22dc, 2 }, 2966 [PCIE_ACLK_RESET] = { 0x22dc, 0 }, 2967 [SFAB_LPASS_RESET] = { 0x23a0, 7 }, 2968 [SFAB_AFAB_M_RESET] = { 0x23e0, 7 }, 2969 [AFAB_SFAB_M0_RESET] = { 0x2420, 7 }, 2970 [AFAB_SFAB_M1_RESET] = { 0x2424, 7 }, 2971 [SFAB_SATA_S_RESET] = { 0x2480, 7 }, 2972 [SFAB_DFAB_M_RESET] = { 0x2500, 7 }, 2973 [DFAB_SFAB_M_RESET] = { 0x2520, 7 }, 2974 [DFAB_SWAY0_RESET] = { 0x2540, 7 }, 2975 [DFAB_SWAY1_RESET] = { 0x2544, 7 }, 2976 [DFAB_ARB0_RESET] = { 0x2560, 7 }, 2977 [DFAB_ARB1_RESET] = { 0x2564, 7 }, 2978 [PPSS_PROC_RESET] = { 0x2594, 1 }, 2979 [PPSS_RESET] = { 0x2594, 0 }, 2980 [DMA_BAM_RESET] = { 0x25c0, 7 }, 2981 [SPS_TIC_H_RESET] = { 0x2600, 7 }, 2982 [SFAB_CFPB_M_RESET] = { 0x2680, 7 }, 2983 [SFAB_CFPB_S_RESET] = { 0x26c0, 7 }, 2984 [TSIF_H_RESET] = { 0x2700, 7 }, 2985 [CE1_H_RESET] = { 0x2720, 7 }, 2986 [CE1_CORE_RESET] = { 0x2724, 7 }, 2987 [CE1_SLEEP_RESET] = { 0x2728, 7 }, 2988 [CE2_H_RESET] = { 0x2740, 7 }, 2989 [CE2_CORE_RESET] = { 0x2744, 7 }, 2990 [SFAB_SFPB_M_RESET] = { 0x2780, 7 }, 2991 [SFAB_SFPB_S_RESET] = { 0x27a0, 7 }, 2992 [RPM_PROC_RESET] = { 0x27c0, 7 }, 2993 [PMIC_SSBI2_RESET] = { 0x280c, 12 }, 2994 [SDC1_RESET] = { 0x2830, 0 }, 2995 [SDC2_RESET] = { 0x2850, 0 }, 2996 [SDC3_RESET] = { 0x2870, 0 }, 2997 [SDC4_RESET] = { 0x2890, 0 }, 2998 [USB_HS1_RESET] = { 0x2910, 0 }, 2999 [USB_HSIC_RESET] = { 0x2934, 0 }, 3000 [USB_FS1_XCVR_RESET] = { 0x2974, 1 }, 3001 [USB_FS1_RESET] = { 0x2974, 0 }, 3002 [GSBI1_RESET] = { 0x29dc, 0 }, 3003 [GSBI2_RESET] = { 0x29fc, 0 }, 3004 [GSBI3_RESET] = { 0x2a1c, 0 }, 3005 [GSBI4_RESET] = { 0x2a3c, 0 }, 3006 [GSBI5_RESET] = { 0x2a5c, 0 }, 3007 [GSBI6_RESET] = { 0x2a7c, 0 }, 3008 [GSBI7_RESET] = { 0x2a9c, 0 }, 3009 [SPDM_RESET] = { 0x2b6c, 0 }, 3010 [SEC_CTRL_RESET] = { 0x2b80, 7 }, 3011 [TLMM_H_RESET] = { 0x2ba0, 7 }, 3012 [SFAB_SATA_M_RESET] = { 0x2c18, 0 }, 3013 [SATA_RESET] = { 0x2c1c, 0 }, 3014 [TSSC_RESET] = { 0x2ca0, 7 }, 3015 [PDM_RESET] = { 0x2cc0, 12 }, 3016 [MPM_H_RESET] = { 0x2da0, 7 }, 3017 [MPM_RESET] = { 0x2da4, 0 }, 3018 [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 }, 3019 [PRNG_RESET] = { 0x2e80, 12 }, 3020 [SFAB_CE3_M_RESET] = { 0x36c8, 1 }, 3021 [SFAB_CE3_S_RESET] = { 0x36c8, 0 }, 3022 [CE3_SLEEP_RESET] = { 0x36d0, 7 }, 3023 [PCIE_1_M_RESET] = { 0x3a98, 1 }, 3024 [PCIE_1_S_RESET] = { 0x3a98, 0 }, 3025 [PCIE_1_EXT_RESET] = { 0x3a9c, 6 }, 3026 [PCIE_1_PHY_RESET] = { 0x3a9c, 5 }, 3027 [PCIE_1_PCI_RESET] = { 0x3a9c, 4 }, 3028 [PCIE_1_POR_RESET] = { 0x3a9c, 3 }, 3029 [PCIE_1_HCLK_RESET] = { 0x3a9c, 2 }, 3030 [PCIE_1_ACLK_RESET] = { 0x3a9c, 0 }, 3031 [PCIE_2_M_RESET] = { 0x3ad8, 1 }, 3032 [PCIE_2_S_RESET] = { 0x3ad8, 0 }, 3033 [PCIE_2_EXT_RESET] = { 0x3adc, 6 }, 3034 [PCIE_2_PHY_RESET] = { 0x3adc, 5 }, 3035 [PCIE_2_PCI_RESET] = { 0x3adc, 4 }, 3036 [PCIE_2_POR_RESET] = { 0x3adc, 3 }, 3037 [PCIE_2_HCLK_RESET] = { 0x3adc, 2 }, 3038 [PCIE_2_ACLK_RESET] = { 0x3adc, 0 }, 3039 [SFAB_USB30_S_RESET] = { 0x3b54, 1 }, 3040 [SFAB_USB30_M_RESET] = { 0x3b54, 0 }, 3041 [USB30_0_PORT2_HS_PHY_RESET] = { 0x3b50, 5 }, 3042 [USB30_0_MASTER_RESET] = { 0x3b50, 4 }, 3043 [USB30_0_SLEEP_RESET] = { 0x3b50, 3 }, 3044 [USB30_0_UTMI_PHY_RESET] = { 0x3b50, 2 }, 3045 [USB30_0_POWERON_RESET] = { 0x3b50, 1 }, 3046 [USB30_0_PHY_RESET] = { 0x3b50, 0 }, 3047 [USB30_1_MASTER_RESET] = { 0x3b58, 4 }, 3048 [USB30_1_SLEEP_RESET] = { 0x3b58, 3 }, 3049 [USB30_1_UTMI_PHY_RESET] = { 0x3b58, 2 }, 3050 [USB30_1_POWERON_RESET] = { 0x3b58, 1 }, 3051 [USB30_1_PHY_RESET] = { 0x3b58, 0 }, 3052 [NSSFB0_RESET] = { 0x3b60, 6 }, 3053 [NSSFB1_RESET] = { 0x3b60, 7 }, 3054 [UBI32_CORE1_CLKRST_CLAMP_RESET] = { 0x3d3c, 3}, 3055 [UBI32_CORE1_CLAMP_RESET] = { 0x3d3c, 2 }, 3056 [UBI32_CORE1_AHB_RESET] = { 0x3d3c, 1 }, 3057 [UBI32_CORE1_AXI_RESET] = { 0x3d3c, 0 }, 3058 [UBI32_CORE2_CLKRST_CLAMP_RESET] = { 0x3d5c, 3 }, 3059 [UBI32_CORE2_CLAMP_RESET] = { 0x3d5c, 2 }, 3060 [UBI32_CORE2_AHB_RESET] = { 0x3d5c, 1 }, 3061 [UBI32_CORE2_AXI_RESET] = { 0x3d5c, 0 }, 3062 [GMAC_CORE1_RESET] = { 0x3cbc, 0 }, 3063 [GMAC_CORE2_RESET] = { 0x3cdc, 0 }, 3064 [GMAC_CORE3_RESET] = { 0x3cfc, 0 }, 3065 [GMAC_CORE4_RESET] = { 0x3d1c, 0 }, 3066 [GMAC_AHB_RESET] = { 0x3e24, 0 }, 3067 [NSS_CH0_RST_RX_CLK_N_RESET] = { 0x3b60, 0 }, 3068 [NSS_CH0_RST_TX_CLK_N_RESET] = { 0x3b60, 1 }, 3069 [NSS_CH0_RST_RX_125M_N_RESET] = { 0x3b60, 2 }, 3070 [NSS_CH0_HW_RST_RX_125M_N_RESET] = { 0x3b60, 3 }, 3071 [NSS_CH0_RST_TX_125M_N_RESET] = { 0x3b60, 4 }, 3072 [NSS_CH1_RST_RX_CLK_N_RESET] = { 0x3b60, 5 }, 3073 [NSS_CH1_RST_TX_CLK_N_RESET] = { 0x3b60, 6 }, 3074 [NSS_CH1_RST_RX_125M_N_RESET] = { 0x3b60, 7 }, 3075 [NSS_CH1_HW_RST_RX_125M_N_RESET] = { 0x3b60, 8 }, 3076 [NSS_CH1_RST_TX_125M_N_RESET] = { 0x3b60, 9 }, 3077 [NSS_CH2_RST_RX_CLK_N_RESET] = { 0x3b60, 10 }, 3078 [NSS_CH2_RST_TX_CLK_N_RESET] = { 0x3b60, 11 }, 3079 [NSS_CH2_RST_RX_125M_N_RESET] = { 0x3b60, 12 }, 3080 [NSS_CH2_HW_RST_RX_125M_N_RESET] = { 0x3b60, 13 }, 3081 [NSS_CH2_RST_TX_125M_N_RESET] = { 0x3b60, 14 }, 3082 [NSS_CH3_RST_RX_CLK_N_RESET] = { 0x3b60, 15 }, 3083 [NSS_CH3_RST_TX_CLK_N_RESET] = { 0x3b60, 16 }, 3084 [NSS_CH3_RST_RX_125M_N_RESET] = { 0x3b60, 17 }, 3085 [NSS_CH3_HW_RST_RX_125M_N_RESET] = { 0x3b60, 18 }, 3086 [NSS_CH3_RST_TX_125M_N_RESET] = { 0x3b60, 19 }, 3087 [NSS_RST_RX_250M_125M_N_RESET] = { 0x3b60, 20 }, 3088 [NSS_RST_TX_250M_125M_N_RESET] = { 0x3b60, 21 }, 3089 [NSS_QSGMII_TXPI_RST_N_RESET] = { 0x3b60, 22 }, 3090 [NSS_QSGMII_CDR_RST_N_RESET] = { 0x3b60, 23 }, 3091 [NSS_SGMII2_CDR_RST_N_RESET] = { 0x3b60, 24 }, 3092 [NSS_SGMII3_CDR_RST_N_RESET] = { 0x3b60, 25 }, 3093 [NSS_CAL_PRBS_RST_N_RESET] = { 0x3b60, 26 }, 3094 [NSS_LCKDT_RST_N_RESET] = { 0x3b60, 27 }, 3095 [NSS_SRDS_N_RESET] = { 0x3b60, 28 }, 3096 }; 3097 3098 static const struct regmap_config gcc_ipq806x_regmap_config = { 3099 .reg_bits = 32, 3100 .reg_stride = 4, 3101 .val_bits = 32, 3102 .max_register = 0x3e40, 3103 .fast_io = true, 3104 }; 3105 3106 static const struct qcom_cc_desc gcc_ipq806x_desc = { 3107 .config = &gcc_ipq806x_regmap_config, 3108 .clks = gcc_ipq806x_clks, 3109 .num_clks = ARRAY_SIZE(gcc_ipq806x_clks), 3110 .resets = gcc_ipq806x_resets, 3111 .num_resets = ARRAY_SIZE(gcc_ipq806x_resets), 3112 }; 3113 3114 static const struct of_device_id gcc_ipq806x_match_table[] = { 3115 { .compatible = "qcom,gcc-ipq8064" }, 3116 { } 3117 }; 3118 MODULE_DEVICE_TABLE(of, gcc_ipq806x_match_table); 3119 3120 static int gcc_ipq806x_probe(struct platform_device *pdev) 3121 { 3122 struct device *dev = &pdev->dev; 3123 struct regmap *regmap; 3124 int ret; 3125 3126 ret = qcom_cc_register_board_clk(dev, "cxo_board", "cxo", 25000000); 3127 if (ret) 3128 return ret; 3129 3130 ret = qcom_cc_register_board_clk(dev, "pxo_board", "pxo", 25000000); 3131 if (ret) 3132 return ret; 3133 3134 ret = qcom_cc_probe(pdev, &gcc_ipq806x_desc); 3135 if (ret) 3136 return ret; 3137 3138 regmap = dev_get_regmap(dev, NULL); 3139 if (!regmap) 3140 return -ENODEV; 3141 3142 /* Setup PLL18 static bits */ 3143 regmap_update_bits(regmap, 0x31a4, 0xffffffc0, 0x40000400); 3144 regmap_write(regmap, 0x31b0, 0x3080); 3145 3146 /* Set GMAC footswitch sleep/wakeup values */ 3147 regmap_write(regmap, 0x3cb8, 8); 3148 regmap_write(regmap, 0x3cd8, 8); 3149 regmap_write(regmap, 0x3cf8, 8); 3150 regmap_write(regmap, 0x3d18, 8); 3151 3152 return of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev); 3153 } 3154 3155 static struct platform_driver gcc_ipq806x_driver = { 3156 .probe = gcc_ipq806x_probe, 3157 .driver = { 3158 .name = "gcc-ipq806x", 3159 .of_match_table = gcc_ipq806x_match_table, 3160 }, 3161 }; 3162 3163 static int __init gcc_ipq806x_init(void) 3164 { 3165 return platform_driver_register(&gcc_ipq806x_driver); 3166 } 3167 core_initcall(gcc_ipq806x_init); 3168 3169 static void __exit gcc_ipq806x_exit(void) 3170 { 3171 platform_driver_unregister(&gcc_ipq806x_driver); 3172 } 3173 module_exit(gcc_ipq806x_exit); 3174 3175 MODULE_DESCRIPTION("QCOM GCC IPQ806x Driver"); 3176 MODULE_LICENSE("GPL v2"); 3177 MODULE_ALIAS("platform:gcc-ipq806x"); 3178