1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 /* 3 * Copyright (c) 2023, The Linux Foundation. All rights reserved. 4 */ 5 #include <linux/clk-provider.h> 6 #include <linux/module.h> 7 #include <linux/of_device.h> 8 #include <linux/regmap.h> 9 10 #include <dt-bindings/clock/qcom,gcc-ipq5018.h> 11 #include <dt-bindings/reset/qcom,gcc-ipq5018.h> 12 13 #include "clk-alpha-pll.h" 14 #include "clk-branch.h" 15 #include "clk-rcg.h" 16 #include "clk-regmap.h" 17 #include "clk-regmap-divider.h" 18 #include "clk-regmap-mux.h" 19 #include "clk-regmap-phy-mux.h" 20 #include "reset.h" 21 22 /* Need to match the order of clocks in DT binding */ 23 enum { 24 DT_XO, 25 DT_SLEEP_CLK, 26 DT_PCIE20_PHY0_PIPE_CLK, 27 DT_PCIE20_PHY1_PIPE_CLK, 28 DT_USB3_PHY0_CC_PIPE_CLK, 29 DT_GEPHY_RX_CLK, 30 DT_GEPHY_TX_CLK, 31 DT_UNIPHY_RX_CLK, 32 DT_UNIPHY_TX_CLK, 33 }; 34 35 enum { 36 P_XO, 37 P_CORE_PI_SLEEP_CLK, 38 P_PCIE20_PHY0_PIPE, 39 P_PCIE20_PHY1_PIPE, 40 P_USB3PHY_0_PIPE, 41 P_GEPHY_RX, 42 P_GEPHY_TX, 43 P_UNIPHY_RX, 44 P_UNIPHY_TX, 45 P_GPLL0, 46 P_GPLL0_DIV2, 47 P_GPLL2, 48 P_GPLL4, 49 P_UBI32_PLL, 50 }; 51 52 static const struct clk_parent_data gcc_xo_data[] = { 53 { .index = DT_XO }, 54 }; 55 56 static const struct clk_parent_data gcc_sleep_clk_data[] = { 57 { .index = DT_SLEEP_CLK }, 58 }; 59 60 static struct clk_alpha_pll gpll0_main = { 61 .offset = 0x21000, 62 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 63 .clkr = { 64 .enable_reg = 0x0b000, 65 .enable_mask = BIT(0), 66 .hw.init = &(struct clk_init_data) { 67 .name = "gpll0_main", 68 .parent_data = gcc_xo_data, 69 .num_parents = ARRAY_SIZE(gcc_xo_data), 70 .ops = &clk_alpha_pll_stromer_ops, 71 }, 72 }, 73 }; 74 75 static struct clk_alpha_pll gpll2_main = { 76 .offset = 0x4a000, 77 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 78 .clkr = { 79 .enable_reg = 0x0b000, 80 .enable_mask = BIT(2), 81 .hw.init = &(struct clk_init_data) { 82 .name = "gpll2_main", 83 .parent_data = gcc_xo_data, 84 .num_parents = ARRAY_SIZE(gcc_xo_data), 85 .ops = &clk_alpha_pll_stromer_ops, 86 }, 87 }, 88 }; 89 90 static struct clk_alpha_pll gpll4_main = { 91 .offset = 0x24000, 92 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 93 .clkr = { 94 .enable_reg = 0x0b000, 95 .enable_mask = BIT(5), 96 .hw.init = &(struct clk_init_data) { 97 .name = "gpll4_main", 98 .parent_data = gcc_xo_data, 99 .num_parents = ARRAY_SIZE(gcc_xo_data), 100 .ops = &clk_alpha_pll_stromer_ops, 101 }, 102 }, 103 }; 104 105 static struct clk_alpha_pll ubi32_pll_main = { 106 .offset = 0x25000, 107 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 108 .clkr = { 109 .enable_reg = 0x0b000, 110 .enable_mask = BIT(6), 111 .hw.init = &(struct clk_init_data) { 112 .name = "ubi32_pll_main", 113 .parent_data = gcc_xo_data, 114 .num_parents = ARRAY_SIZE(gcc_xo_data), 115 .ops = &clk_alpha_pll_stromer_ops, 116 }, 117 }, 118 }; 119 120 static struct clk_alpha_pll_postdiv gpll0 = { 121 .offset = 0x21000, 122 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 123 .width = 4, 124 .clkr.hw.init = &(struct clk_init_data) { 125 .name = "gpll0", 126 .parent_hws = (const struct clk_hw *[]) { 127 &gpll0_main.clkr.hw, 128 }, 129 .num_parents = 1, 130 .ops = &clk_alpha_pll_postdiv_ro_ops, 131 }, 132 }; 133 134 static struct clk_alpha_pll_postdiv gpll2 = { 135 .offset = 0x4a000, 136 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 137 .width = 4, 138 .clkr.hw.init = &(struct clk_init_data) { 139 .name = "gpll2", 140 .parent_hws = (const struct clk_hw *[]) { 141 &gpll2_main.clkr.hw, 142 }, 143 .num_parents = 1, 144 .ops = &clk_alpha_pll_postdiv_ro_ops, 145 }, 146 }; 147 148 static struct clk_alpha_pll_postdiv gpll4 = { 149 .offset = 0x24000, 150 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 151 .width = 4, 152 .clkr.hw.init = &(struct clk_init_data) { 153 .name = "gpll4", 154 .parent_hws = (const struct clk_hw *[]) { 155 &gpll4_main.clkr.hw, 156 }, 157 .num_parents = 1, 158 .ops = &clk_alpha_pll_postdiv_ro_ops, 159 }, 160 }; 161 162 static struct clk_alpha_pll_postdiv ubi32_pll = { 163 .offset = 0x25000, 164 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 165 .width = 4, 166 .clkr.hw.init = &(struct clk_init_data) { 167 .name = "ubi32_pll", 168 .parent_hws = (const struct clk_hw *[]) { 169 &ubi32_pll_main.clkr.hw, 170 }, 171 .num_parents = 1, 172 .ops = &clk_alpha_pll_postdiv_ro_ops, 173 .flags = CLK_SET_RATE_PARENT, 174 }, 175 }; 176 177 static struct clk_fixed_factor gpll0_out_main_div2 = { 178 .mult = 1, 179 .div = 2, 180 .hw.init = &(struct clk_init_data) { 181 .name = "gpll0_out_main_div2", 182 .parent_hws = (const struct clk_hw *[]) { 183 &gpll0_main.clkr.hw, 184 }, 185 .num_parents = 1, 186 .ops = &clk_fixed_factor_ops, 187 .flags = CLK_SET_RATE_PARENT, 188 }, 189 }; 190 191 static const struct clk_parent_data gcc_xo_gpll0_gpll0_out_main_div2[] = { 192 { .index = DT_XO }, 193 { .hw = &gpll0.clkr.hw }, 194 { .hw = &gpll0_out_main_div2.hw }, 195 }; 196 197 static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = { 198 { P_XO, 0 }, 199 { P_GPLL0, 1 }, 200 { P_GPLL0_DIV2, 4 }, 201 }; 202 203 static const struct clk_parent_data gcc_xo_gpll0[] = { 204 { .index = DT_XO }, 205 { .hw = &gpll0.clkr.hw }, 206 }; 207 208 static const struct parent_map gcc_xo_gpll0_map[] = { 209 { P_XO, 0 }, 210 { P_GPLL0, 1 }, 211 }; 212 213 static const struct clk_parent_data gcc_xo_gpll0_out_main_div2_gpll0[] = { 214 { .index = DT_XO }, 215 { .hw = &gpll0_out_main_div2.hw }, 216 { .hw = &gpll0.clkr.hw }, 217 }; 218 219 static const struct parent_map gcc_xo_gpll0_out_main_div2_gpll0_map[] = { 220 { P_XO, 0 }, 221 { P_GPLL0_DIV2, 2 }, 222 { P_GPLL0, 1 }, 223 }; 224 225 static const struct clk_parent_data gcc_xo_ubi32_gpll0[] = { 226 { .index = DT_XO }, 227 { .hw = &ubi32_pll.clkr.hw }, 228 { .hw = &gpll0.clkr.hw }, 229 }; 230 231 static const struct parent_map gcc_xo_ubi32_gpll0_map[] = { 232 { P_XO, 0 }, 233 { P_UBI32_PLL, 1 }, 234 { P_GPLL0, 2 }, 235 }; 236 237 static const struct clk_parent_data gcc_xo_gpll0_gpll2[] = { 238 { .index = DT_XO }, 239 { .hw = &gpll0.clkr.hw }, 240 { .hw = &gpll2.clkr.hw }, 241 }; 242 243 static const struct parent_map gcc_xo_gpll0_gpll2_map[] = { 244 { P_XO, 0 }, 245 { P_GPLL0, 1 }, 246 { P_GPLL2, 2 }, 247 }; 248 249 static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll4[] = { 250 { .index = DT_XO }, 251 { .hw = &gpll0.clkr.hw }, 252 { .hw = &gpll2.clkr.hw }, 253 { .hw = &gpll4.clkr.hw }, 254 }; 255 256 static const struct parent_map gcc_xo_gpll0_gpll2_gpll4_map[] = { 257 { P_XO, 0 }, 258 { P_GPLL0, 1 }, 259 { P_GPLL2, 2 }, 260 { P_GPLL4, 3 }, 261 }; 262 263 static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = { 264 { .index = DT_XO }, 265 { .hw = &gpll0.clkr.hw }, 266 { .hw = &gpll4.clkr.hw }, 267 }; 268 269 static const struct parent_map gcc_xo_gpll0_gpll4_map[] = { 270 { P_XO, 0 }, 271 { P_GPLL0, 1 }, 272 { P_GPLL4, 2 }, 273 }; 274 275 static const struct clk_parent_data gcc_xo_gpll0_core_pi_sleep_clk[] = { 276 { .index = DT_XO }, 277 { .hw = &gpll0.clkr.hw }, 278 { .index = DT_SLEEP_CLK }, 279 }; 280 281 static const struct parent_map gcc_xo_gpll0_core_pi_sleep_clk_map[] = { 282 { P_XO, 0 }, 283 { P_GPLL0, 2 }, 284 { P_CORE_PI_SLEEP_CLK, 6 }, 285 }; 286 287 static const struct clk_parent_data gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk[] = { 288 { .index = DT_XO }, 289 { .hw = &gpll0.clkr.hw }, 290 { .hw = &gpll0_out_main_div2.hw }, 291 { .index = DT_SLEEP_CLK }, 292 }; 293 294 static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk_map[] = { 295 { P_XO, 0 }, 296 { P_GPLL0, 1 }, 297 { P_GPLL0_DIV2, 4 }, 298 { P_CORE_PI_SLEEP_CLK, 6 }, 299 }; 300 301 static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll0_out_main_div2[] = { 302 { .index = DT_XO }, 303 { .hw = &gpll0.clkr.hw }, 304 { .hw = &gpll2.clkr.hw }, 305 { .hw = &gpll0_out_main_div2.hw }, 306 }; 307 308 static const struct parent_map gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map[] = { 309 { P_XO, 0 }, 310 { P_GPLL0, 1 }, 311 { P_GPLL2, 2 }, 312 { P_GPLL0_DIV2, 4 }, 313 }; 314 315 static const struct clk_parent_data gcc_xo_gpll4_gpll0_gpll0_out_main_div2[] = { 316 { .index = DT_XO }, 317 { .hw = &gpll4.clkr.hw }, 318 { .hw = &gpll0.clkr.hw }, 319 { .hw = &gpll0_out_main_div2.hw }, 320 }; 321 322 static const struct parent_map gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map1[] = { 323 { P_XO, 0 }, 324 { P_GPLL4, 1 }, 325 { P_GPLL0, 2 }, 326 { P_GPLL0_DIV2, 4 }, 327 }; 328 329 static const struct parent_map gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map2[] = { 330 { P_XO, 0 }, 331 { P_GPLL4, 1 }, 332 { P_GPLL0, 3 }, 333 { P_GPLL0_DIV2, 4 }, 334 }; 335 336 static const struct clk_parent_data gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0[] = { 337 { .index = DT_XO }, 338 { .index = DT_GEPHY_RX_CLK }, 339 { .index = DT_GEPHY_TX_CLK }, 340 { .hw = &ubi32_pll.clkr.hw }, 341 { .hw = &gpll0.clkr.hw }, 342 }; 343 344 static const struct parent_map gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0_map[] = { 345 { P_XO, 0 }, 346 { P_GEPHY_RX, 1 }, 347 { P_GEPHY_TX, 2 }, 348 { P_UBI32_PLL, 3 }, 349 { P_GPLL0, 4 }, 350 }; 351 352 static const struct clk_parent_data gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0[] = { 353 { .index = DT_XO }, 354 { .index = DT_GEPHY_TX_CLK }, 355 { .index = DT_GEPHY_RX_CLK }, 356 { .hw = &ubi32_pll.clkr.hw }, 357 { .hw = &gpll0.clkr.hw }, 358 }; 359 360 static const struct parent_map gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0_map[] = { 361 { P_XO, 0 }, 362 { P_GEPHY_TX, 1 }, 363 { P_GEPHY_RX, 2 }, 364 { P_UBI32_PLL, 3 }, 365 { P_GPLL0, 4 }, 366 }; 367 368 static const struct clk_parent_data gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0[] = { 369 { .index = DT_XO }, 370 { .index = DT_UNIPHY_RX_CLK }, 371 { .index = DT_UNIPHY_TX_CLK }, 372 { .hw = &ubi32_pll.clkr.hw }, 373 { .hw = &gpll0.clkr.hw }, 374 }; 375 376 static const struct parent_map gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0_map[] = { 377 { P_XO, 0 }, 378 { P_UNIPHY_RX, 1 }, 379 { P_UNIPHY_TX, 2 }, 380 { P_UBI32_PLL, 3 }, 381 { P_GPLL0, 4 }, 382 }; 383 384 static const struct clk_parent_data gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0[] = { 385 { .index = DT_XO }, 386 { .index = DT_UNIPHY_TX_CLK }, 387 { .index = DT_UNIPHY_RX_CLK }, 388 { .hw = &ubi32_pll.clkr.hw }, 389 { .hw = &gpll0.clkr.hw }, 390 }; 391 392 static const struct parent_map gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0_map[] = { 393 { P_XO, 0 }, 394 { P_UNIPHY_TX, 1 }, 395 { P_UNIPHY_RX, 2 }, 396 { P_UBI32_PLL, 3 }, 397 { P_GPLL0, 4 }, 398 }; 399 400 static const struct clk_parent_data gcc_pcie20_phy0_pipe_clk_xo[] = { 401 { .index = DT_PCIE20_PHY0_PIPE_CLK }, 402 { .index = DT_XO }, 403 }; 404 405 static const struct parent_map gcc_pcie20_phy0_pipe_clk_xo_map[] = { 406 { P_PCIE20_PHY0_PIPE, 0 }, 407 { P_XO, 2 }, 408 }; 409 410 static const struct clk_parent_data gcc_pcie20_phy1_pipe_clk_xo[] = { 411 { .index = DT_PCIE20_PHY1_PIPE_CLK }, 412 { .index = DT_XO }, 413 }; 414 415 static const struct parent_map gcc_pcie20_phy1_pipe_clk_xo_map[] = { 416 { P_PCIE20_PHY1_PIPE, 0 }, 417 { P_XO, 2 }, 418 }; 419 420 static const struct clk_parent_data gcc_usb3phy_0_cc_pipe_clk_xo[] = { 421 { .index = DT_USB3_PHY0_CC_PIPE_CLK }, 422 { .index = DT_XO }, 423 }; 424 425 static const struct parent_map gcc_usb3phy_0_cc_pipe_clk_xo_map[] = { 426 { P_USB3PHY_0_PIPE, 0 }, 427 { P_XO, 2 }, 428 }; 429 430 static const struct freq_tbl ftbl_adss_pwm_clk_src[] = { 431 F(24000000, P_XO, 1, 0, 0), 432 F(100000000, P_GPLL0, 8, 0, 0), 433 { } 434 }; 435 436 static struct clk_rcg2 adss_pwm_clk_src = { 437 .cmd_rcgr = 0x1f008, 438 .freq_tbl = ftbl_adss_pwm_clk_src, 439 .hid_width = 5, 440 .parent_map = gcc_xo_gpll0_map, 441 .clkr.hw.init = &(struct clk_init_data) { 442 .name = "adss_pwm_clk_src", 443 .parent_data = gcc_xo_gpll0, 444 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 445 .ops = &clk_rcg2_ops, 446 }, 447 }; 448 449 static const struct freq_tbl ftbl_blsp1_qup_i2c_apps_clk_src[] = { 450 F(50000000, P_GPLL0, 16, 0, 0), 451 { } 452 }; 453 454 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { 455 .cmd_rcgr = 0x0200c, 456 .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src, 457 .hid_width = 5, 458 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 459 .clkr.hw.init = &(struct clk_init_data) { 460 .name = "blsp1_qup1_i2c_apps_clk_src", 461 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, 462 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), 463 .ops = &clk_rcg2_ops, 464 }, 465 }; 466 467 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { 468 .cmd_rcgr = 0x03000, 469 .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src, 470 .hid_width = 5, 471 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 472 .clkr.hw.init = &(struct clk_init_data) { 473 .name = "blsp1_qup2_i2c_apps_clk_src", 474 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, 475 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), 476 .ops = &clk_rcg2_ops, 477 }, 478 }; 479 480 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { 481 .cmd_rcgr = 0x04000, 482 .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src, 483 .hid_width = 5, 484 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 485 .clkr.hw.init = &(struct clk_init_data) { 486 .name = "blsp1_qup3_i2c_apps_clk_src", 487 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, 488 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), 489 .ops = &clk_rcg2_ops, 490 }, 491 }; 492 493 static const struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src[] = { 494 F(960000, P_XO, 10, 2, 5), 495 F(4800000, P_XO, 5, 0, 0), 496 F(9600000, P_XO, 2, 4, 5), 497 F(16000000, P_GPLL0, 10, 1, 5), 498 F(24000000, P_XO, 1, 0, 0), 499 F(50000000, P_GPLL0, 16, 0, 0), 500 { } 501 }; 502 503 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { 504 .cmd_rcgr = 0x02024, 505 .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src, 506 .mnd_width = 8, 507 .hid_width = 5, 508 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 509 .clkr.hw.init = &(struct clk_init_data) { 510 .name = "blsp1_qup1_spi_apps_clk_src", 511 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, 512 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), 513 .ops = &clk_rcg2_ops, 514 }, 515 }; 516 517 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { 518 .cmd_rcgr = 0x03014, 519 .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src, 520 .mnd_width = 8, 521 .hid_width = 5, 522 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 523 .clkr.hw.init = &(struct clk_init_data) { 524 .name = "blsp1_qup2_spi_apps_clk_src", 525 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, 526 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), 527 .ops = &clk_rcg2_ops, 528 }, 529 }; 530 531 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { 532 .cmd_rcgr = 0x04014, 533 .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src, 534 .mnd_width = 8, 535 .hid_width = 5, 536 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 537 .clkr.hw.init = &(struct clk_init_data) { 538 .name = "blsp1_qup3_spi_apps_clk_src", 539 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, 540 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), 541 .ops = &clk_rcg2_ops, 542 }, 543 }; 544 545 static const struct freq_tbl ftbl_blsp1_uart_apps_clk_src[] = { 546 F(3686400, P_GPLL0_DIV2, 1, 144, 15625), 547 F(7372800, P_GPLL0_DIV2, 1, 288, 15625), 548 F(14745600, P_GPLL0_DIV2, 1, 576, 15625), 549 F(24000000, P_XO, 1, 0, 0), 550 F(25000000, P_GPLL0, 16, 1, 2), 551 F(40000000, P_GPLL0, 1, 1, 20), 552 F(46400000, P_GPLL0, 1, 29, 500), 553 F(48000000, P_GPLL0, 1, 3, 50), 554 F(51200000, P_GPLL0, 1, 8, 125), 555 F(56000000, P_GPLL0, 1, 7, 100), 556 F(58982400, P_GPLL0, 1, 1152, 15625), 557 F(60000000, P_GPLL0, 1, 3, 40), 558 F(64000000, P_GPLL0, 10, 4, 5), 559 { } 560 }; 561 562 static struct clk_rcg2 blsp1_uart1_apps_clk_src = { 563 .cmd_rcgr = 0x02044, 564 .freq_tbl = ftbl_blsp1_uart_apps_clk_src, 565 .mnd_width = 16, 566 .hid_width = 5, 567 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 568 .clkr.hw.init = &(struct clk_init_data) { 569 .name = "blsp1_uart1_apps_clk_src", 570 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, 571 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), 572 .ops = &clk_rcg2_ops, 573 }, 574 }; 575 576 static struct clk_rcg2 blsp1_uart2_apps_clk_src = { 577 .cmd_rcgr = 0x03034, 578 .freq_tbl = ftbl_blsp1_uart_apps_clk_src, 579 .mnd_width = 16, 580 .hid_width = 5, 581 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 582 .clkr.hw.init = &(struct clk_init_data) { 583 .name = "blsp1_uart2_apps_clk_src", 584 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, 585 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), 586 .ops = &clk_rcg2_ops, 587 }, 588 }; 589 590 static const struct freq_tbl ftbl_crypto_clk_src[] = { 591 F(160000000, P_GPLL0, 5, 0, 0), 592 { } 593 }; 594 595 static struct clk_rcg2 crypto_clk_src = { 596 .cmd_rcgr = 0x16004, 597 .freq_tbl = ftbl_crypto_clk_src, 598 .hid_width = 5, 599 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 600 .clkr.hw.init = &(struct clk_init_data) { 601 .name = "crypto_clk_src", 602 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, 603 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), 604 .ops = &clk_rcg2_ops, 605 }, 606 }; 607 608 static const struct freq_tbl ftbl_gmac0_tx_clk_src[] = { 609 F(2500000, P_GEPHY_TX, 5, 0, 0), 610 F(24000000, P_XO, 1, 0, 0), 611 F(25000000, P_GEPHY_TX, 5, 0, 0), 612 F(125000000, P_GEPHY_TX, 1, 0, 0), 613 { } 614 }; 615 616 static struct clk_rcg2 gmac0_rx_clk_src = { 617 .cmd_rcgr = 0x68020, 618 .parent_map = gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0_map, 619 .hid_width = 5, 620 .freq_tbl = ftbl_gmac0_tx_clk_src, 621 .clkr.hw.init = &(struct clk_init_data) { 622 .name = "gmac0_rx_clk_src", 623 .parent_data = gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0, 624 .num_parents = ARRAY_SIZE(gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0), 625 .ops = &clk_rcg2_ops, 626 }, 627 }; 628 629 static struct clk_regmap_div gmac0_rx_div_clk_src = { 630 .reg = 0x68420, 631 .shift = 0, 632 .width = 4, 633 .clkr = { 634 .hw.init = &(struct clk_init_data) { 635 .name = "gmac0_rx_div_clk_src", 636 .parent_hws = (const struct clk_hw *[]) { 637 &gmac0_rx_clk_src.clkr.hw, 638 }, 639 .num_parents = 1, 640 .ops = &clk_regmap_div_ops, 641 .flags = CLK_SET_RATE_PARENT, 642 }, 643 }, 644 }; 645 646 static struct clk_rcg2 gmac0_tx_clk_src = { 647 .cmd_rcgr = 0x68028, 648 .parent_map = gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0_map, 649 .hid_width = 5, 650 .freq_tbl = ftbl_gmac0_tx_clk_src, 651 .clkr.hw.init = &(struct clk_init_data) { 652 .name = "gmac0_tx_clk_src", 653 .parent_data = gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0, 654 .num_parents = ARRAY_SIZE(gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0), 655 .ops = &clk_rcg2_ops, 656 }, 657 }; 658 659 static struct clk_regmap_div gmac0_tx_div_clk_src = { 660 .reg = 0x68424, 661 .shift = 0, 662 .width = 4, 663 .clkr = { 664 .hw.init = &(struct clk_init_data) { 665 .name = "gmac0_tx_div_clk_src", 666 .parent_hws = (const struct clk_hw *[]) { 667 &gmac0_tx_clk_src.clkr.hw, 668 }, 669 .num_parents = 1, 670 .ops = &clk_regmap_div_ops, 671 .flags = CLK_SET_RATE_PARENT, 672 }, 673 }, 674 }; 675 676 static const struct freq_tbl ftbl_gmac1_rx_clk_src[] = { 677 F(2500000, P_UNIPHY_RX, 12.5, 0, 0), 678 F(24000000, P_XO, 1, 0, 0), 679 F(25000000, P_UNIPHY_RX, 2.5, 0, 0), 680 F(125000000, P_UNIPHY_RX, 2.5, 0, 0), 681 F(125000000, P_UNIPHY_RX, 1, 0, 0), 682 F(312500000, P_UNIPHY_RX, 1, 0, 0), 683 { } 684 }; 685 686 static struct clk_rcg2 gmac1_rx_clk_src = { 687 .cmd_rcgr = 0x68030, 688 .parent_map = gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0_map, 689 .hid_width = 5, 690 .freq_tbl = ftbl_gmac1_rx_clk_src, 691 .clkr.hw.init = &(struct clk_init_data) { 692 .name = "gmac1_rx_clk_src", 693 .parent_data = gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0, 694 .num_parents = ARRAY_SIZE(gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0), 695 .ops = &clk_rcg2_ops, 696 }, 697 }; 698 699 static struct clk_regmap_div gmac1_rx_div_clk_src = { 700 .reg = 0x68430, 701 .shift = 0, 702 .width = 4, 703 .clkr = { 704 .hw.init = &(struct clk_init_data) { 705 .name = "gmac1_rx_div_clk_src", 706 .parent_hws = (const struct clk_hw *[]) { 707 &gmac1_rx_clk_src.clkr.hw, 708 }, 709 .num_parents = 1, 710 .ops = &clk_regmap_div_ops, 711 .flags = CLK_SET_RATE_PARENT, 712 }, 713 }, 714 }; 715 716 static const struct freq_tbl ftbl_gmac1_tx_clk_src[] = { 717 F(2500000, P_UNIPHY_TX, 12.5, 0, 0), 718 F(24000000, P_XO, 1, 0, 0), 719 F(25000000, P_UNIPHY_TX, 2.5, 0, 0), 720 F(125000000, P_UNIPHY_TX, 2.5, 0, 0), 721 F(125000000, P_UNIPHY_TX, 1, 0, 0), 722 F(312500000, P_UNIPHY_TX, 1, 0, 0), 723 { } 724 }; 725 726 static struct clk_rcg2 gmac1_tx_clk_src = { 727 .cmd_rcgr = 0x68038, 728 .parent_map = gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0_map, 729 .hid_width = 5, 730 .freq_tbl = ftbl_gmac1_tx_clk_src, 731 .clkr.hw.init = &(struct clk_init_data) { 732 .name = "gmac1_tx_clk_src", 733 .parent_data = gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0, 734 .num_parents = ARRAY_SIZE(gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0), 735 .ops = &clk_rcg2_ops, 736 }, 737 }; 738 739 static struct clk_regmap_div gmac1_tx_div_clk_src = { 740 .reg = 0x68434, 741 .shift = 0, 742 .width = 4, 743 .clkr = { 744 .hw.init = &(struct clk_init_data) { 745 .name = "gmac1_tx_div_clk_src", 746 .parent_hws = (const struct clk_hw *[]) { 747 &gmac1_tx_clk_src.clkr.hw, 748 }, 749 .num_parents = 1, 750 .ops = &clk_regmap_div_ops, 751 .flags = CLK_SET_RATE_PARENT, 752 }, 753 }, 754 }; 755 756 static const struct freq_tbl ftbl_gmac_clk_src[] = { 757 F(240000000, P_GPLL4, 5, 0, 0), 758 { } 759 }; 760 761 static struct clk_rcg2 gmac_clk_src = { 762 .cmd_rcgr = 0x68080, 763 .parent_map = gcc_xo_gpll0_gpll4_map, 764 .hid_width = 5, 765 .freq_tbl = ftbl_gmac_clk_src, 766 .clkr.hw.init = &(struct clk_init_data) { 767 .name = "gmac_clk_src", 768 .parent_data = gcc_xo_gpll0_gpll4, 769 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4), 770 .ops = &clk_rcg2_ops, 771 }, 772 }; 773 774 static const struct freq_tbl ftbl_gp_clk_src[] = { 775 F(200000000, P_GPLL0, 4, 0, 0), 776 { } 777 }; 778 779 static struct clk_rcg2 gp1_clk_src = { 780 .cmd_rcgr = 0x08004, 781 .freq_tbl = ftbl_gp_clk_src, 782 .mnd_width = 8, 783 .hid_width = 5, 784 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk_map, 785 .clkr.hw.init = &(struct clk_init_data) { 786 .name = "gp1_clk_src", 787 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk, 788 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk), 789 .ops = &clk_rcg2_ops, 790 }, 791 }; 792 793 static struct clk_rcg2 gp2_clk_src = { 794 .cmd_rcgr = 0x09004, 795 .freq_tbl = ftbl_gp_clk_src, 796 .mnd_width = 8, 797 .hid_width = 5, 798 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk_map, 799 .clkr.hw.init = &(struct clk_init_data) { 800 .name = "gp2_clk_src", 801 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk, 802 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk), 803 .ops = &clk_rcg2_ops, 804 }, 805 }; 806 807 static struct clk_rcg2 gp3_clk_src = { 808 .cmd_rcgr = 0x0a004, 809 .freq_tbl = ftbl_gp_clk_src, 810 .mnd_width = 8, 811 .hid_width = 5, 812 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk_map, 813 .clkr.hw.init = &(struct clk_init_data) { 814 .name = "gp3_clk_src", 815 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk, 816 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk), 817 .ops = &clk_rcg2_ops, 818 }, 819 }; 820 821 static const struct freq_tbl ftbl_lpass_axim_clk_src[] = { 822 F(133333334, P_GPLL0, 6, 0, 0), 823 { } 824 }; 825 826 static struct clk_rcg2 lpass_axim_clk_src = { 827 .cmd_rcgr = 0x2e028, 828 .freq_tbl = ftbl_lpass_axim_clk_src, 829 .hid_width = 5, 830 .parent_map = gcc_xo_gpll0_map, 831 .clkr.hw.init = &(struct clk_init_data) { 832 .name = "lpass_axim_clk_src", 833 .parent_data = gcc_xo_gpll0, 834 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 835 .ops = &clk_rcg2_ops, 836 }, 837 }; 838 839 static const struct freq_tbl ftbl_lpass_sway_clk_src[] = { 840 F(66666667, P_GPLL0, 12, 0, 0), 841 { } 842 }; 843 844 static struct clk_rcg2 lpass_sway_clk_src = { 845 .cmd_rcgr = 0x2e040, 846 .freq_tbl = ftbl_lpass_sway_clk_src, 847 .hid_width = 5, 848 .parent_map = gcc_xo_gpll0_map, 849 .clkr.hw.init = &(struct clk_init_data) { 850 .name = "lpass_sway_clk_src", 851 .parent_data = gcc_xo_gpll0, 852 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 853 .ops = &clk_rcg2_ops, 854 }, 855 }; 856 857 static const struct freq_tbl ftbl_pcie0_aux_clk_src[] = { 858 F(2000000, P_XO, 12, 0, 0), 859 }; 860 861 static struct clk_rcg2 pcie0_aux_clk_src = { 862 .cmd_rcgr = 0x75020, 863 .freq_tbl = ftbl_pcie0_aux_clk_src, 864 .mnd_width = 16, 865 .hid_width = 5, 866 .parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map, 867 .clkr.hw.init = &(struct clk_init_data) { 868 .name = "pcie0_aux_clk_src", 869 .parent_data = gcc_xo_gpll0_core_pi_sleep_clk, 870 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_core_pi_sleep_clk), 871 .ops = &clk_rcg2_ops, 872 }, 873 }; 874 875 static const struct freq_tbl ftbl_pcie0_axi_clk_src[] = { 876 F(240000000, P_GPLL4, 5, 0, 0), 877 { } 878 }; 879 880 static struct clk_rcg2 pcie0_axi_clk_src = { 881 .cmd_rcgr = 0x75050, 882 .freq_tbl = ftbl_pcie0_axi_clk_src, 883 .hid_width = 5, 884 .parent_map = gcc_xo_gpll0_gpll4_map, 885 .clkr.hw.init = &(struct clk_init_data) { 886 .name = "pcie0_axi_clk_src", 887 .parent_data = gcc_xo_gpll0_gpll4, 888 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4), 889 .ops = &clk_rcg2_ops, 890 }, 891 }; 892 893 static struct clk_rcg2 pcie1_aux_clk_src = { 894 .cmd_rcgr = 0x76020, 895 .freq_tbl = ftbl_pcie0_aux_clk_src, 896 .mnd_width = 16, 897 .hid_width = 5, 898 .parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map, 899 .clkr.hw.init = &(struct clk_init_data) { 900 .name = "pcie1_aux_clk_src", 901 .parent_data = gcc_xo_gpll0_core_pi_sleep_clk, 902 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_core_pi_sleep_clk), 903 .ops = &clk_rcg2_ops, 904 }, 905 }; 906 907 static struct clk_rcg2 pcie1_axi_clk_src = { 908 .cmd_rcgr = 0x76050, 909 .freq_tbl = ftbl_gp_clk_src, 910 .hid_width = 5, 911 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 912 .clkr.hw.init = &(struct clk_init_data) { 913 .name = "pcie1_axi_clk_src", 914 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, 915 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), 916 .ops = &clk_rcg2_ops, 917 }, 918 }; 919 920 static struct clk_regmap_mux pcie0_pipe_clk_src = { 921 .reg = 0x7501c, 922 .shift = 8, 923 .width = 2, 924 .parent_map = gcc_pcie20_phy0_pipe_clk_xo_map, 925 .clkr = { 926 .hw.init = &(struct clk_init_data) { 927 .name = "pcie0_pipe_clk_src", 928 .parent_data = gcc_pcie20_phy0_pipe_clk_xo, 929 .num_parents = ARRAY_SIZE(gcc_pcie20_phy0_pipe_clk_xo), 930 .ops = &clk_regmap_mux_closest_ops, 931 .flags = CLK_SET_RATE_PARENT, 932 }, 933 }, 934 }; 935 936 static struct clk_regmap_mux pcie1_pipe_clk_src = { 937 .reg = 0x7601c, 938 .shift = 8, 939 .width = 2, 940 .parent_map = gcc_pcie20_phy1_pipe_clk_xo_map, .clkr = { 941 .hw.init = &(struct clk_init_data) { 942 .name = "pcie1_pipe_clk_src", 943 .parent_data = gcc_pcie20_phy1_pipe_clk_xo, 944 .num_parents = ARRAY_SIZE(gcc_pcie20_phy1_pipe_clk_xo), 945 .ops = &clk_regmap_mux_closest_ops, 946 .flags = CLK_SET_RATE_PARENT, 947 }, 948 }, 949 }; 950 951 static const struct freq_tbl ftbl_pcnoc_bfdcd_clk_src[] = { 952 F(100000000, P_GPLL0, 8, 0, 0), 953 { } 954 }; 955 956 static struct clk_rcg2 pcnoc_bfdcd_clk_src = { 957 .cmd_rcgr = 0x27000, 958 .freq_tbl = ftbl_pcnoc_bfdcd_clk_src, 959 .hid_width = 5, 960 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 961 .clkr.hw.init = &(struct clk_init_data) { 962 .name = "pcnoc_bfdcd_clk_src", 963 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, 964 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), 965 .ops = &clk_rcg2_ops, 966 }, 967 }; 968 969 static struct clk_fixed_factor pcnoc_clk_src = { 970 .mult = 1, 971 .div = 1, 972 .hw.init = &(struct clk_init_data) { 973 .name = "pcnoc_clk_src", 974 .parent_hws = (const struct clk_hw *[]) { 975 &pcnoc_bfdcd_clk_src.clkr.hw, 976 }, 977 .num_parents = 1, 978 .ops = &clk_fixed_factor_ops, 979 .flags = CLK_SET_RATE_PARENT, 980 }, 981 }; 982 983 static const struct freq_tbl ftbl_qdss_at_clk_src[] = { 984 F(240000000, P_GPLL4, 5, 0, 0), 985 { } 986 }; 987 988 static struct clk_rcg2 qdss_at_clk_src = { 989 .cmd_rcgr = 0x2900c, 990 .freq_tbl = ftbl_qdss_at_clk_src, 991 .hid_width = 5, 992 .parent_map = gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map1, 993 .clkr.hw.init = &(struct clk_init_data) { 994 .name = "qdss_at_clk_src", 995 .parent_data = gcc_xo_gpll4_gpll0_gpll0_out_main_div2, 996 .num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_out_main_div2), 997 .ops = &clk_rcg2_ops, 998 }, 999 }; 1000 1001 static const struct freq_tbl ftbl_qdss_stm_clk_src[] = { 1002 F(200000000, P_GPLL0, 4, 0, 0), 1003 { } 1004 }; 1005 1006 static struct clk_rcg2 qdss_stm_clk_src = { 1007 .cmd_rcgr = 0x2902c, 1008 .freq_tbl = ftbl_qdss_stm_clk_src, 1009 .hid_width = 5, 1010 .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, 1011 .clkr.hw.init = &(struct clk_init_data) { 1012 .name = "qdss_stm_clk_src", 1013 .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, 1014 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), 1015 .ops = &clk_rcg2_ops, 1016 }, 1017 }; 1018 1019 static const struct freq_tbl ftbl_qdss_traceclkin_clk_src[] = { 1020 F(266666667, P_GPLL0, 3, 0, 0), 1021 { } 1022 }; 1023 1024 static struct clk_rcg2 qdss_traceclkin_clk_src = { 1025 .cmd_rcgr = 0x29048, 1026 .freq_tbl = ftbl_qdss_traceclkin_clk_src, 1027 .hid_width = 5, 1028 .parent_map = gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map1, 1029 .clkr.hw.init = &(struct clk_init_data) { 1030 .name = "qdss_traceclkin_clk_src", 1031 .parent_data = gcc_xo_gpll4_gpll0_gpll0_out_main_div2, 1032 .num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_out_main_div2), 1033 .ops = &clk_rcg2_ops, 1034 }, 1035 }; 1036 1037 static const struct freq_tbl ftbl_qdss_tsctr_clk_src[] = { 1038 F(600000000, P_GPLL4, 2, 0, 0), 1039 { } 1040 }; 1041 1042 static struct clk_rcg2 qdss_tsctr_clk_src = { 1043 .cmd_rcgr = 0x29064, 1044 .freq_tbl = ftbl_qdss_tsctr_clk_src, 1045 .hid_width = 5, 1046 .parent_map = gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map1, 1047 .clkr.hw.init = &(struct clk_init_data) { 1048 .name = "qdss_tsctr_clk_src", 1049 .parent_data = gcc_xo_gpll4_gpll0_gpll0_out_main_div2, 1050 .num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_out_main_div2), 1051 .ops = &clk_rcg2_ops, 1052 }, 1053 }; 1054 1055 static struct clk_fixed_factor qdss_tsctr_div2_clk_src = { 1056 .mult = 1, 1057 .div = 2, 1058 .hw.init = &(struct clk_init_data) { 1059 .name = "qdss_tsctr_div2_clk_src", 1060 .parent_hws = (const struct clk_hw *[]) { 1061 &qdss_tsctr_clk_src.clkr.hw, 1062 }, 1063 .num_parents = 1, 1064 .flags = CLK_SET_RATE_PARENT, 1065 .ops = &clk_fixed_factor_ops, 1066 }, 1067 }; 1068 1069 static struct clk_fixed_factor qdss_dap_sync_clk_src = { 1070 .mult = 1, 1071 .div = 4, 1072 .hw.init = &(struct clk_init_data) { 1073 .name = "qdss_dap_sync_clk_src", 1074 .parent_hws = (const struct clk_hw *[]) { 1075 &qdss_tsctr_clk_src.clkr.hw, 1076 }, 1077 .num_parents = 1, 1078 .ops = &clk_fixed_factor_ops, 1079 }, 1080 }; 1081 1082 static struct clk_fixed_factor eud_at_clk_src = { 1083 .mult = 1, 1084 .div = 6, 1085 .hw.init = &(struct clk_init_data) { 1086 .name = "eud_at_clk_src", 1087 .parent_hws = (const struct clk_hw *[]) { 1088 &qdss_at_clk_src.clkr.hw, 1089 }, 1090 .num_parents = 1, 1091 .ops = &clk_fixed_factor_ops, 1092 .flags = CLK_SET_RATE_PARENT, 1093 }, 1094 }; 1095 1096 static const struct freq_tbl ftbl_qpic_io_macro_clk_src[] = { 1097 F(24000000, P_XO, 1, 0, 0), 1098 F(100000000, P_GPLL0, 8, 0, 0), 1099 F(200000000, P_GPLL0, 4, 0, 0), 1100 F(320000000, P_GPLL0, 2.5, 0, 0), 1101 }; 1102 1103 static struct clk_rcg2 qpic_io_macro_clk_src = { 1104 .cmd_rcgr = 0x57010, 1105 .freq_tbl = ftbl_qpic_io_macro_clk_src, 1106 .hid_width = 5, 1107 .parent_map = gcc_xo_gpll0_gpll2_map, 1108 .clkr.hw.init = &(struct clk_init_data) { 1109 .name = "qpic_io_macro_clk_src", 1110 .parent_data = gcc_xo_gpll0_gpll2, 1111 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2), 1112 .ops = &clk_rcg2_ops, 1113 }, 1114 }; 1115 1116 static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = { 1117 F(143713, P_XO, 1, 1, 167), 1118 F(400000, P_XO, 1, 1, 60), 1119 F(24000000, P_XO, 1, 0, 0), 1120 F(48000000, P_GPLL2, 12, 1, 2), 1121 F(96000000, P_GPLL2, 12, 0, 0), 1122 F(177777778, P_GPLL0, 1, 2, 9), 1123 F(192000000, P_GPLL2, 6, 0, 0), 1124 F(200000000, P_GPLL0, 4, 0, 0), 1125 { } 1126 }; 1127 1128 static struct clk_rcg2 sdcc1_apps_clk_src = { 1129 .cmd_rcgr = 0x42004, 1130 .freq_tbl = ftbl_sdcc1_apps_clk_src, 1131 .mnd_width = 8, 1132 .hid_width = 5, 1133 .parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map, 1134 .clkr.hw.init = &(struct clk_init_data) { 1135 .name = "sdcc1_apps_clk_src", 1136 .parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2, 1137 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll0_out_main_div2), 1138 .ops = &clk_rcg2_floor_ops, 1139 }, 1140 }; 1141 1142 static const struct freq_tbl ftbl_system_noc_bfdcd_clk_src[] = { 1143 F(266666667, P_GPLL0, 3, 0, 0), 1144 { } 1145 }; 1146 1147 static struct clk_rcg2 system_noc_bfdcd_clk_src = { 1148 .cmd_rcgr = 0x26004, 1149 .freq_tbl = ftbl_system_noc_bfdcd_clk_src, 1150 .hid_width = 5, 1151 .parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map, 1152 .clkr.hw.init = &(struct clk_init_data) { 1153 .name = "system_noc_bfdcd_clk_src", 1154 .parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2, 1155 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll0_out_main_div2), 1156 .ops = &clk_rcg2_ops, 1157 }, 1158 }; 1159 1160 static struct clk_fixed_factor system_noc_clk_src = { 1161 .mult = 1, 1162 .div = 1, 1163 .hw.init = &(struct clk_init_data) { 1164 .name = "system_noc_clk_src", 1165 .parent_hws = (const struct clk_hw *[]) { 1166 &system_noc_bfdcd_clk_src.clkr.hw, 1167 }, 1168 .num_parents = 1, 1169 .ops = &clk_fixed_factor_ops, 1170 .flags = CLK_SET_RATE_PARENT, 1171 }, 1172 }; 1173 1174 static const struct freq_tbl ftbl_apss_axi_clk_src[] = { 1175 F(400000000, P_GPLL0, 2, 0, 0), 1176 { } 1177 }; 1178 1179 static struct clk_rcg2 ubi0_axi_clk_src = { 1180 .cmd_rcgr = 0x68088, 1181 .freq_tbl = ftbl_apss_axi_clk_src, 1182 .hid_width = 5, 1183 .parent_map = gcc_xo_gpll0_gpll2_map, 1184 .clkr.hw.init = &(struct clk_init_data) { 1185 .name = "ubi0_axi_clk_src", 1186 .parent_data = gcc_xo_gpll0_gpll2, 1187 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2), 1188 .ops = &clk_rcg2_ops, 1189 .flags = CLK_SET_RATE_PARENT, 1190 }, 1191 }; 1192 1193 static const struct freq_tbl ftbl_ubi0_core_clk_src[] = { 1194 F(850000000, P_UBI32_PLL, 1, 0, 0), 1195 F(1000000000, P_UBI32_PLL, 1, 0, 0), 1196 }; 1197 1198 static struct clk_rcg2 ubi0_core_clk_src = { 1199 .cmd_rcgr = 0x68100, 1200 .freq_tbl = ftbl_ubi0_core_clk_src, 1201 .hid_width = 5, 1202 .parent_map = gcc_xo_ubi32_gpll0_map, 1203 .clkr.hw.init = &(struct clk_init_data) { 1204 .name = "ubi0_core_clk_src", 1205 .parent_data = gcc_xo_ubi32_gpll0, 1206 .num_parents = ARRAY_SIZE(gcc_xo_ubi32_gpll0), 1207 .ops = &clk_rcg2_ops, 1208 .flags = CLK_SET_RATE_PARENT, 1209 }, 1210 }; 1211 1212 static struct clk_rcg2 usb0_aux_clk_src = { 1213 .cmd_rcgr = 0x3e05c, 1214 .freq_tbl = ftbl_pcie0_aux_clk_src, 1215 .mnd_width = 16, 1216 .hid_width = 5, 1217 .parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map, 1218 .clkr.hw.init = &(struct clk_init_data) { 1219 .name = "usb0_aux_clk_src", 1220 .parent_data = gcc_xo_gpll0_core_pi_sleep_clk, 1221 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_core_pi_sleep_clk), 1222 .ops = &clk_rcg2_ops, 1223 }, 1224 }; 1225 1226 static const struct freq_tbl ftbl_usb0_lfps_clk_src[] = { 1227 F(25000000, P_GPLL0, 16, 1, 2), 1228 { } 1229 }; 1230 1231 static struct clk_rcg2 usb0_lfps_clk_src = { 1232 .cmd_rcgr = 0x3e090, 1233 .freq_tbl = ftbl_usb0_lfps_clk_src, 1234 .mnd_width = 8, 1235 .hid_width = 5, 1236 .parent_map = gcc_xo_gpll0_map, 1237 .clkr.hw.init = &(struct clk_init_data) { 1238 .name = "usb0_lfps_clk_src", 1239 .parent_data = gcc_xo_gpll0, 1240 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1241 .ops = &clk_rcg2_ops, 1242 }, 1243 }; 1244 1245 static struct clk_rcg2 usb0_master_clk_src = { 1246 .cmd_rcgr = 0x3e00c, 1247 .freq_tbl = ftbl_gp_clk_src, 1248 .mnd_width = 8, 1249 .hid_width = 5, 1250 .parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map, 1251 .clkr.hw.init = &(struct clk_init_data) { 1252 .name = "usb0_master_clk_src", 1253 .parent_data = gcc_xo_gpll0_out_main_div2_gpll0, 1254 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_out_main_div2_gpll0), 1255 .ops = &clk_rcg2_ops, 1256 }, 1257 }; 1258 1259 static const struct freq_tbl ftbl_usb0_mock_utmi_clk_src[] = { 1260 F(60000000, P_GPLL4, 10, 1, 2), 1261 { } 1262 }; 1263 1264 static struct clk_rcg2 usb0_mock_utmi_clk_src = { 1265 .cmd_rcgr = 0x3e020, 1266 .freq_tbl = ftbl_usb0_mock_utmi_clk_src, 1267 .mnd_width = 8, 1268 .hid_width = 5, 1269 .parent_map = gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map2, 1270 .clkr.hw.init = &(struct clk_init_data) { 1271 .name = "usb0_mock_utmi_clk_src", 1272 .parent_data = gcc_xo_gpll4_gpll0_gpll0_out_main_div2, 1273 .num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_out_main_div2), 1274 .ops = &clk_rcg2_ops, 1275 }, 1276 }; 1277 1278 static struct clk_regmap_mux usb0_pipe_clk_src = { 1279 .reg = 0x3e048, 1280 .shift = 8, 1281 .width = 2, 1282 .parent_map = gcc_usb3phy_0_cc_pipe_clk_xo_map, 1283 .clkr = { 1284 .hw.init = &(struct clk_init_data) { 1285 .name = "usb0_pipe_clk_src", 1286 .parent_data = gcc_usb3phy_0_cc_pipe_clk_xo, 1287 .num_parents = ARRAY_SIZE(gcc_usb3phy_0_cc_pipe_clk_xo), 1288 .ops = &clk_regmap_mux_closest_ops, 1289 .flags = CLK_SET_RATE_PARENT, 1290 }, 1291 }, 1292 }; 1293 1294 static const struct freq_tbl ftbl_q6_axi_clk_src[] = { 1295 F(400000000, P_GPLL0, 2, 0, 0), 1296 { } 1297 }; 1298 1299 static struct clk_rcg2 q6_axi_clk_src = { 1300 .cmd_rcgr = 0x59120, 1301 .freq_tbl = ftbl_q6_axi_clk_src, 1302 .hid_width = 5, 1303 .parent_map = gcc_xo_gpll0_gpll2_gpll4_map, 1304 .clkr.hw.init = &(struct clk_init_data) { 1305 .name = "q6_axi_clk_src", 1306 .parent_data = gcc_xo_gpll0_gpll2_gpll4, 1307 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll4), 1308 .ops = &clk_rcg2_ops, 1309 }, 1310 }; 1311 1312 static const struct freq_tbl ftbl_wcss_ahb_clk_src[] = { 1313 F(133333333, P_GPLL0, 6, 0, 0), 1314 { } 1315 }; 1316 1317 static struct clk_rcg2 wcss_ahb_clk_src = { 1318 .cmd_rcgr = 0x59020, 1319 .freq_tbl = ftbl_wcss_ahb_clk_src, 1320 .hid_width = 5, 1321 .parent_map = gcc_xo_gpll0_map, 1322 .clkr.hw.init = &(struct clk_init_data) { 1323 .name = "wcss_ahb_clk_src", 1324 .parent_data = gcc_xo_gpll0, 1325 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1326 .ops = &clk_rcg2_ops, 1327 }, 1328 }; 1329 1330 static struct clk_branch gcc_sleep_clk_src = { 1331 .halt_reg = 0x30000, 1332 .clkr = { 1333 .enable_reg = 0x30000, 1334 .enable_mask = BIT(1), 1335 .hw.init = &(struct clk_init_data) { 1336 .name = "gcc_sleep_clk_src", 1337 .parent_data = gcc_sleep_clk_data, 1338 .num_parents = ARRAY_SIZE(gcc_sleep_clk_data), 1339 .ops = &clk_branch2_ops, 1340 }, 1341 }, 1342 }; 1343 1344 static struct clk_branch gcc_xo_clk_src = { 1345 .halt_reg = 0x30018, 1346 .clkr = { 1347 .enable_reg = 0x30018, 1348 .enable_mask = BIT(1), 1349 .hw.init = &(struct clk_init_data) { 1350 .name = "gcc_xo_clk_src", 1351 .parent_data = gcc_xo_data, 1352 .num_parents = ARRAY_SIZE(gcc_xo_data), 1353 .flags = CLK_SET_RATE_PARENT, 1354 .ops = &clk_branch2_ops, 1355 }, 1356 }, 1357 }; 1358 1359 static struct clk_branch gcc_xo_clk = { 1360 .halt_reg = 0x30030, 1361 .clkr = { 1362 .enable_reg = 0x30030, 1363 .enable_mask = BIT(0), 1364 .hw.init = &(struct clk_init_data) { 1365 .name = "gcc_xo_clk", 1366 .parent_hws = (const struct clk_hw *[]) { 1367 &gcc_xo_clk_src.clkr.hw, 1368 }, 1369 .num_parents = 1, 1370 .flags = CLK_SET_RATE_PARENT, 1371 .ops = &clk_branch2_ops, 1372 }, 1373 }, 1374 }; 1375 1376 static struct clk_branch gcc_adss_pwm_clk = { 1377 .halt_reg = 0x1f020, 1378 .clkr = { 1379 .enable_reg = 0x1f020, 1380 .enable_mask = BIT(0), 1381 .hw.init = &(struct clk_init_data) { 1382 .name = "gcc_adss_pwm_clk", 1383 .parent_hws = (const struct clk_hw *[]) { 1384 &adss_pwm_clk_src.clkr.hw, 1385 }, 1386 .num_parents = 1, 1387 .flags = CLK_SET_RATE_PARENT, 1388 .ops = &clk_branch2_ops, 1389 }, 1390 }, 1391 }; 1392 1393 static struct clk_branch gcc_blsp1_ahb_clk = { 1394 .halt_reg = 0x01008, 1395 .halt_check = BRANCH_HALT_VOTED, 1396 .clkr = { 1397 .enable_reg = 0x0b004, 1398 .enable_mask = BIT(10), 1399 .hw.init = &(struct clk_init_data) { 1400 .name = "gcc_blsp1_ahb_clk", 1401 .parent_hws = (const struct clk_hw *[]) { 1402 &pcnoc_clk_src.hw, 1403 }, 1404 .num_parents = 1, 1405 .flags = CLK_SET_RATE_PARENT, 1406 .ops = &clk_branch2_ops, 1407 }, 1408 }, 1409 }; 1410 1411 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { 1412 .halt_reg = 0x02008, 1413 .clkr = { 1414 .enable_reg = 0x02008, 1415 .enable_mask = BIT(0), 1416 .hw.init = &(struct clk_init_data) { 1417 .name = "gcc_blsp1_qup1_i2c_apps_clk", 1418 .parent_hws = (const struct clk_hw *[]) { 1419 &blsp1_qup1_i2c_apps_clk_src.clkr.hw, 1420 }, 1421 .num_parents = 1, 1422 .flags = CLK_SET_RATE_PARENT, 1423 .ops = &clk_branch2_ops, 1424 }, 1425 }, 1426 }; 1427 1428 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { 1429 .halt_reg = 0x02004, 1430 .clkr = { 1431 .enable_reg = 0x02004, 1432 .enable_mask = BIT(0), 1433 .hw.init = &(struct clk_init_data) { 1434 .name = "gcc_blsp1_qup1_spi_apps_clk", 1435 .parent_hws = (const struct clk_hw *[]) { 1436 &blsp1_qup1_spi_apps_clk_src.clkr.hw, 1437 }, 1438 .num_parents = 1, 1439 .flags = CLK_SET_RATE_PARENT, 1440 .ops = &clk_branch2_ops, 1441 }, 1442 }, 1443 }; 1444 1445 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { 1446 .halt_reg = 0x03010, 1447 .clkr = { 1448 .enable_reg = 0x03010, 1449 .enable_mask = BIT(0), 1450 .hw.init = &(struct clk_init_data) { 1451 .name = "gcc_blsp1_qup2_i2c_apps_clk", 1452 .parent_hws = (const struct clk_hw *[]) { 1453 &blsp1_qup2_i2c_apps_clk_src.clkr.hw, 1454 }, 1455 .num_parents = 1, 1456 .flags = CLK_SET_RATE_PARENT, 1457 .ops = &clk_branch2_ops, 1458 }, 1459 }, 1460 }; 1461 1462 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { 1463 .halt_reg = 0x0300c, 1464 .clkr = { 1465 .enable_reg = 0x0300c, 1466 .enable_mask = BIT(0), 1467 .hw.init = &(struct clk_init_data) { 1468 .name = "gcc_blsp1_qup2_spi_apps_clk", 1469 .parent_hws = (const struct clk_hw *[]) { 1470 &blsp1_qup2_spi_apps_clk_src.clkr.hw, 1471 }, 1472 .num_parents = 1, 1473 .flags = CLK_SET_RATE_PARENT, 1474 .ops = &clk_branch2_ops, 1475 }, 1476 }, 1477 }; 1478 1479 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = { 1480 .halt_reg = 0x04010, 1481 .clkr = { 1482 .enable_reg = 0x04010, 1483 .enable_mask = BIT(0), 1484 .hw.init = &(struct clk_init_data) { 1485 .name = "gcc_blsp1_qup3_i2c_apps_clk", 1486 .parent_hws = (const struct clk_hw *[]) { 1487 &blsp1_qup3_i2c_apps_clk_src.clkr.hw, 1488 }, 1489 .num_parents = 1, 1490 .flags = CLK_SET_RATE_PARENT, 1491 .ops = &clk_branch2_ops, 1492 }, 1493 }, 1494 }; 1495 1496 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = { 1497 .halt_reg = 0x0400c, 1498 .clkr = { 1499 .enable_reg = 0x0400c, 1500 .enable_mask = BIT(0), 1501 .hw.init = &(struct clk_init_data) { 1502 .name = "gcc_blsp1_qup3_spi_apps_clk", 1503 .parent_hws = (const struct clk_hw *[]) { 1504 &blsp1_qup3_spi_apps_clk_src.clkr.hw, 1505 }, 1506 .num_parents = 1, 1507 .flags = CLK_SET_RATE_PARENT, 1508 .ops = &clk_branch2_ops, 1509 }, 1510 }, 1511 }; 1512 1513 static struct clk_branch gcc_blsp1_uart1_apps_clk = { 1514 .halt_reg = 0x0203c, 1515 .clkr = { 1516 .enable_reg = 0x0203c, 1517 .enable_mask = BIT(0), 1518 .hw.init = &(struct clk_init_data) { 1519 .name = "gcc_blsp1_uart1_apps_clk", 1520 .parent_hws = (const struct clk_hw *[]) { 1521 &blsp1_uart1_apps_clk_src.clkr.hw, 1522 }, 1523 .num_parents = 1, 1524 .flags = CLK_SET_RATE_PARENT, 1525 .ops = &clk_branch2_ops, 1526 }, 1527 }, 1528 }; 1529 1530 static struct clk_branch gcc_blsp1_uart2_apps_clk = { 1531 .halt_reg = 0x0302c, 1532 .clkr = { 1533 .enable_reg = 0x0302c, 1534 .enable_mask = BIT(0), 1535 .hw.init = &(struct clk_init_data) { 1536 .name = "gcc_blsp1_uart2_apps_clk", 1537 .parent_hws = (const struct clk_hw *[]) { 1538 &blsp1_uart2_apps_clk_src.clkr.hw, 1539 }, 1540 .num_parents = 1, 1541 .flags = CLK_SET_RATE_PARENT, 1542 .ops = &clk_branch2_ops, 1543 }, 1544 }, 1545 }; 1546 1547 static struct clk_branch gcc_btss_lpo_clk = { 1548 .halt_reg = 0x1c004, 1549 .clkr = { 1550 .enable_reg = 0x1c004, 1551 .enable_mask = BIT(0), 1552 .hw.init = &(struct clk_init_data) { 1553 .name = "gcc_btss_lpo_clk", 1554 .ops = &clk_branch2_ops, 1555 }, 1556 }, 1557 }; 1558 1559 static struct clk_branch gcc_cmn_blk_ahb_clk = { 1560 .halt_reg = 0x56308, 1561 .clkr = { 1562 .enable_reg = 0x56308, 1563 .enable_mask = BIT(0), 1564 .hw.init = &(struct clk_init_data) { 1565 .name = "gcc_cmn_blk_ahb_clk", 1566 .parent_hws = (const struct clk_hw *[]) { 1567 &pcnoc_clk_src.hw, 1568 }, 1569 .num_parents = 1, 1570 .flags = CLK_SET_RATE_PARENT, 1571 .ops = &clk_branch2_ops, 1572 }, 1573 }, 1574 }; 1575 1576 static struct clk_branch gcc_cmn_blk_sys_clk = { 1577 .halt_reg = 0x5630c, 1578 .clkr = { 1579 .enable_reg = 0x5630c, 1580 .enable_mask = BIT(0), 1581 .hw.init = &(struct clk_init_data) { 1582 .name = "gcc_cmn_blk_sys_clk", 1583 .parent_hws = (const struct clk_hw *[]) { 1584 &gcc_xo_clk_src.clkr.hw, 1585 }, 1586 .num_parents = 1, 1587 .flags = CLK_SET_RATE_PARENT, 1588 .ops = &clk_branch2_ops, 1589 }, 1590 }, 1591 }; 1592 1593 static struct clk_branch gcc_crypto_ahb_clk = { 1594 .halt_reg = 0x16024, 1595 .halt_check = BRANCH_HALT_VOTED, 1596 .clkr = { 1597 .enable_reg = 0x0b004, 1598 .enable_mask = BIT(0), 1599 .hw.init = &(struct clk_init_data) { 1600 .name = "gcc_crypto_ahb_clk", 1601 .parent_hws = (const struct clk_hw *[]) { 1602 &pcnoc_clk_src.hw, 1603 }, 1604 .num_parents = 1, 1605 .flags = CLK_SET_RATE_PARENT, 1606 .ops = &clk_branch2_ops, 1607 }, 1608 }, 1609 }; 1610 1611 static struct clk_branch gcc_crypto_axi_clk = { 1612 .halt_reg = 0x16020, 1613 .halt_check = BRANCH_HALT_VOTED, 1614 .clkr = { 1615 .enable_reg = 0x0b004, 1616 .enable_mask = BIT(1), 1617 .hw.init = &(struct clk_init_data) { 1618 .name = "gcc_crypto_axi_clk", 1619 .parent_hws = (const struct clk_hw *[]) { 1620 &pcnoc_clk_src.hw, 1621 }, 1622 .num_parents = 1, 1623 .flags = CLK_SET_RATE_PARENT, 1624 .ops = &clk_branch2_ops, 1625 }, 1626 }, 1627 }; 1628 1629 static struct clk_branch gcc_crypto_clk = { 1630 .halt_reg = 0x1601c, 1631 .halt_check = BRANCH_HALT_VOTED, 1632 .clkr = { 1633 .enable_reg = 0x0b004, 1634 .enable_mask = BIT(2), 1635 .hw.init = &(struct clk_init_data) { 1636 .name = "gcc_crypto_clk", 1637 .parent_hws = (const struct clk_hw *[]) { 1638 &crypto_clk_src.clkr.hw, 1639 }, 1640 .num_parents = 1, 1641 .flags = CLK_SET_RATE_PARENT, 1642 .ops = &clk_branch2_ops, 1643 }, 1644 }, 1645 }; 1646 1647 static struct clk_branch gcc_dcc_clk = { 1648 .halt_reg = 0x77004, 1649 .clkr = { 1650 .enable_reg = 0x77004, 1651 .enable_mask = BIT(0), 1652 .hw.init = &(struct clk_init_data) { 1653 .name = "gcc_dcc_clk", 1654 .parent_hws = (const struct clk_hw *[]) { 1655 &pcnoc_clk_src.hw, 1656 }, 1657 .num_parents = 1, 1658 .flags = CLK_SET_RATE_PARENT, 1659 .ops = &clk_branch2_ops, 1660 }, 1661 }, 1662 }; 1663 1664 static struct clk_branch gcc_gephy_rx_clk = { 1665 .halt_reg = 0x56010, 1666 .halt_check = BRANCH_HALT_DELAY, 1667 .clkr = { 1668 .enable_reg = 0x56010, 1669 .enable_mask = BIT(0), 1670 .hw.init = &(struct clk_init_data) { 1671 .name = "gcc_gephy_rx_clk", 1672 .parent_hws = (const struct clk_hw *[]) { 1673 &gmac0_rx_div_clk_src.clkr.hw, 1674 }, 1675 .num_parents = 1, 1676 .ops = &clk_branch2_ops, 1677 .flags = CLK_SET_RATE_PARENT, 1678 }, 1679 }, 1680 }; 1681 1682 static struct clk_branch gcc_gephy_tx_clk = { 1683 .halt_reg = 0x56014, 1684 .halt_check = BRANCH_HALT_DELAY, 1685 .clkr = { 1686 .enable_reg = 0x56014, 1687 .enable_mask = BIT(0), 1688 .hw.init = &(struct clk_init_data) { 1689 .name = "gcc_gephy_tx_clk", 1690 .parent_hws = (const struct clk_hw *[]) { 1691 &gmac0_tx_div_clk_src.clkr.hw, 1692 }, 1693 .num_parents = 1, 1694 .ops = &clk_branch2_ops, 1695 .flags = CLK_SET_RATE_PARENT, 1696 }, 1697 }, 1698 }; 1699 1700 static struct clk_branch gcc_gmac0_cfg_clk = { 1701 .halt_reg = 0x68304, 1702 .clkr = { 1703 .enable_reg = 0x68304, 1704 .enable_mask = BIT(0), 1705 .hw.init = &(struct clk_init_data) { 1706 .name = "gcc_gmac0_cfg_clk", 1707 .parent_hws = (const struct clk_hw *[]) { 1708 &gmac_clk_src.clkr.hw, 1709 }, 1710 .num_parents = 1, 1711 .flags = CLK_SET_RATE_PARENT, 1712 .ops = &clk_branch2_ops, 1713 }, 1714 }, 1715 }; 1716 1717 static struct clk_branch gcc_gmac0_ptp_clk = { 1718 .halt_reg = 0x68300, 1719 .clkr = { 1720 .enable_reg = 0x68300, 1721 .enable_mask = BIT(0), 1722 .hw.init = &(struct clk_init_data) { 1723 .name = "gcc_gmac0_ptp_clk", 1724 .parent_hws = (const struct clk_hw *[]) { 1725 &gmac_clk_src.clkr.hw, 1726 }, 1727 .num_parents = 1, 1728 .flags = CLK_SET_RATE_PARENT, 1729 .ops = &clk_branch2_ops, 1730 }, 1731 }, 1732 }; 1733 1734 static struct clk_branch gcc_gmac0_rx_clk = { 1735 .halt_reg = 0x68240, 1736 .clkr = { 1737 .enable_reg = 0x68240, 1738 .enable_mask = BIT(0), 1739 .hw.init = &(struct clk_init_data) { 1740 .name = "gcc_gmac0_rx_clk", 1741 .parent_hws = (const struct clk_hw *[]) { 1742 &gmac0_rx_div_clk_src.clkr.hw, 1743 }, 1744 .num_parents = 1, 1745 .ops = &clk_branch2_ops, 1746 .flags = CLK_SET_RATE_PARENT, 1747 }, 1748 }, 1749 }; 1750 1751 static struct clk_branch gcc_gmac0_sys_clk = { 1752 .halt_reg = 0x68190, 1753 .halt_check = BRANCH_HALT_DELAY, 1754 .halt_bit = 31, 1755 .clkr = { 1756 .enable_reg = 0x68190, 1757 .enable_mask = BIT(0), 1758 .hw.init = &(struct clk_init_data) { 1759 .name = "gcc_gmac0_sys_clk", 1760 .parent_hws = (const struct clk_hw *[]) { 1761 &gmac_clk_src.clkr.hw, 1762 }, 1763 .num_parents = 1, 1764 .flags = CLK_SET_RATE_PARENT, 1765 .ops = &clk_branch2_ops, 1766 }, 1767 }, 1768 }; 1769 1770 static struct clk_branch gcc_gmac0_tx_clk = { 1771 .halt_reg = 0x68244, 1772 .clkr = { 1773 .enable_reg = 0x68244, 1774 .enable_mask = BIT(0), 1775 .hw.init = &(struct clk_init_data) { 1776 .name = "gcc_gmac0_tx_clk", 1777 .parent_hws = (const struct clk_hw *[]) { 1778 &gmac0_tx_div_clk_src.clkr.hw, 1779 }, 1780 .num_parents = 1, 1781 .ops = &clk_branch2_ops, 1782 .flags = CLK_SET_RATE_PARENT, 1783 }, 1784 }, 1785 }; 1786 1787 static struct clk_branch gcc_gmac1_cfg_clk = { 1788 .halt_reg = 0x68324, 1789 .clkr = { 1790 .enable_reg = 0x68324, 1791 .enable_mask = BIT(0), 1792 .hw.init = &(struct clk_init_data) { 1793 .name = "gcc_gmac1_cfg_clk", 1794 .parent_hws = (const struct clk_hw *[]) { 1795 &gmac_clk_src.clkr.hw, 1796 }, 1797 .num_parents = 1, 1798 .flags = CLK_SET_RATE_PARENT, 1799 .ops = &clk_branch2_ops, 1800 }, 1801 }, 1802 }; 1803 1804 static struct clk_branch gcc_gmac1_ptp_clk = { 1805 .halt_reg = 0x68320, 1806 .clkr = { 1807 .enable_reg = 0x68320, 1808 .enable_mask = BIT(0), 1809 .hw.init = &(struct clk_init_data) { 1810 .name = "gcc_gmac1_ptp_clk", 1811 .parent_hws = (const struct clk_hw *[]) { 1812 &gmac_clk_src.clkr.hw, 1813 }, 1814 .num_parents = 1, 1815 .flags = CLK_SET_RATE_PARENT, 1816 .ops = &clk_branch2_ops, 1817 }, 1818 }, 1819 }; 1820 1821 static struct clk_branch gcc_gmac1_rx_clk = { 1822 .halt_reg = 0x68248, 1823 .clkr = { 1824 .enable_reg = 0x68248, 1825 .enable_mask = BIT(0), 1826 .hw.init = &(struct clk_init_data) { 1827 .name = "gcc_gmac1_rx_clk", 1828 .parent_hws = (const struct clk_hw *[]) { 1829 &gmac1_rx_div_clk_src.clkr.hw, 1830 }, 1831 .num_parents = 1, 1832 .ops = &clk_branch2_ops, 1833 .flags = CLK_SET_RATE_PARENT, 1834 }, 1835 }, 1836 }; 1837 1838 static struct clk_branch gcc_gmac1_sys_clk = { 1839 .halt_reg = 0x68310, 1840 .clkr = { 1841 .enable_reg = 0x68310, 1842 .enable_mask = BIT(0), 1843 .hw.init = &(struct clk_init_data) { 1844 .name = "gcc_gmac1_sys_clk", 1845 .parent_hws = (const struct clk_hw *[]) { 1846 &gmac_clk_src.clkr.hw, 1847 }, 1848 .num_parents = 1, 1849 .flags = CLK_SET_RATE_PARENT, 1850 .ops = &clk_branch2_ops, 1851 }, 1852 }, 1853 }; 1854 1855 static struct clk_branch gcc_gmac1_tx_clk = { 1856 .halt_reg = 0x6824c, 1857 .clkr = { 1858 .enable_reg = 0x6824c, 1859 .enable_mask = BIT(0), 1860 .hw.init = &(struct clk_init_data) { 1861 .name = "gcc_gmac1_tx_clk", 1862 .parent_hws = (const struct clk_hw *[]) { 1863 &gmac1_tx_div_clk_src.clkr.hw, 1864 }, 1865 .num_parents = 1, 1866 .ops = &clk_branch2_ops, 1867 .flags = CLK_SET_RATE_PARENT, 1868 }, 1869 }, 1870 }; 1871 1872 static struct clk_branch gcc_gp1_clk = { 1873 .halt_reg = 0x08000, 1874 .clkr = { 1875 .enable_reg = 0x08000, 1876 .enable_mask = BIT(0), 1877 .hw.init = &(struct clk_init_data) { 1878 .name = "gcc_gp1_clk", 1879 .parent_hws = (const struct clk_hw *[]) { 1880 &gp1_clk_src.clkr.hw, 1881 }, 1882 .num_parents = 1, 1883 .flags = CLK_SET_RATE_PARENT, 1884 .ops = &clk_branch2_ops, 1885 }, 1886 }, 1887 }; 1888 1889 static struct clk_branch gcc_gp2_clk = { 1890 .halt_reg = 0x09000, 1891 .clkr = { 1892 .enable_reg = 0x09000, 1893 .enable_mask = BIT(0), 1894 .hw.init = &(struct clk_init_data) { 1895 .name = "gcc_gp2_clk", 1896 .parent_hws = (const struct clk_hw *[]) { 1897 &gp2_clk_src.clkr.hw, 1898 }, 1899 .num_parents = 1, 1900 .flags = CLK_SET_RATE_PARENT, 1901 .ops = &clk_branch2_ops, 1902 }, 1903 }, 1904 }; 1905 1906 static struct clk_branch gcc_gp3_clk = { 1907 .halt_reg = 0x0a000, 1908 .clkr = { 1909 .enable_reg = 0x0a000, 1910 .enable_mask = BIT(0), 1911 .hw.init = &(struct clk_init_data) { 1912 .name = "gcc_gp3_clk", 1913 .parent_hws = (const struct clk_hw *[]) { 1914 &gp3_clk_src.clkr.hw, 1915 }, 1916 .num_parents = 1, 1917 .flags = CLK_SET_RATE_PARENT, 1918 .ops = &clk_branch2_ops, 1919 }, 1920 }, 1921 }; 1922 1923 static struct clk_branch gcc_lpass_core_axim_clk = { 1924 .halt_reg = 0x2e048, 1925 .halt_check = BRANCH_VOTED, 1926 .clkr = { 1927 .enable_reg = 0x2e048, 1928 .enable_mask = BIT(0), 1929 .hw.init = &(struct clk_init_data) { 1930 .name = "gcc_lpass_core_axim_clk", 1931 .parent_hws = (const struct clk_hw *[]) { 1932 &lpass_axim_clk_src.clkr.hw, 1933 }, 1934 .num_parents = 1, 1935 .flags = CLK_SET_RATE_PARENT, 1936 .ops = &clk_branch2_ops, 1937 }, 1938 }, 1939 }; 1940 1941 static struct clk_branch gcc_lpass_sway_clk = { 1942 .halt_reg = 0x2e04c, 1943 .clkr = { 1944 .enable_reg = 0x2e04c, 1945 .enable_mask = BIT(0), 1946 .hw.init = &(struct clk_init_data) { 1947 .name = "gcc_lpass_sway_clk", 1948 .parent_hws = (const struct clk_hw *[]) { 1949 &lpass_sway_clk_src.clkr.hw, 1950 }, 1951 .num_parents = 1, 1952 .flags = CLK_SET_RATE_PARENT, 1953 .ops = &clk_branch2_ops, 1954 }, 1955 }, 1956 }; 1957 1958 static struct clk_branch gcc_mdio0_ahb_clk = { 1959 .halt_reg = 0x58004, 1960 .clkr = { 1961 .enable_reg = 0x58004, 1962 .enable_mask = BIT(0), 1963 .hw.init = &(struct clk_init_data) { 1964 .name = "gcc_mdioi0_ahb_clk", 1965 .parent_hws = (const struct clk_hw *[]) { 1966 &pcnoc_clk_src.hw, 1967 }, 1968 .num_parents = 1, 1969 .flags = CLK_SET_RATE_PARENT, 1970 .ops = &clk_branch2_ops, 1971 }, 1972 }, 1973 }; 1974 1975 static struct clk_branch gcc_mdio1_ahb_clk = { 1976 .halt_reg = 0x58014, 1977 .clkr = { 1978 .enable_reg = 0x58014, 1979 .enable_mask = BIT(0), 1980 .hw.init = &(struct clk_init_data) { 1981 .name = "gcc_mdio1_ahb_clk", 1982 .parent_hws = (const struct clk_hw *[]) { 1983 &pcnoc_clk_src.hw, 1984 }, 1985 .num_parents = 1, 1986 .flags = CLK_SET_RATE_PARENT, 1987 .ops = &clk_branch2_ops, 1988 }, 1989 }, 1990 }; 1991 1992 static struct clk_branch gcc_pcie0_ahb_clk = { 1993 .halt_reg = 0x75010, 1994 .clkr = { 1995 .enable_reg = 0x75010, 1996 .enable_mask = BIT(0), 1997 .hw.init = &(struct clk_init_data) { 1998 .name = "gcc_pcie0_ahb_clk", 1999 .parent_hws = (const struct clk_hw *[]) { 2000 &pcnoc_clk_src.hw, 2001 }, 2002 .num_parents = 1, 2003 .flags = CLK_SET_RATE_PARENT, 2004 .ops = &clk_branch2_ops, 2005 }, 2006 }, 2007 }; 2008 2009 static struct clk_branch gcc_pcie0_aux_clk = { 2010 .halt_reg = 0x75014, 2011 .clkr = { 2012 .enable_reg = 0x75014, 2013 .enable_mask = BIT(0), 2014 .hw.init = &(struct clk_init_data) { 2015 .name = "gcc_pcie0_aux_clk", 2016 .parent_hws = (const struct clk_hw *[]) { 2017 &pcie0_aux_clk_src.clkr.hw, 2018 }, 2019 .num_parents = 1, 2020 .flags = CLK_SET_RATE_PARENT, 2021 .ops = &clk_branch2_ops, 2022 }, 2023 }, 2024 }; 2025 2026 static struct clk_branch gcc_pcie0_axi_m_clk = { 2027 .halt_reg = 0x75008, 2028 .clkr = { 2029 .enable_reg = 0x75008, 2030 .enable_mask = BIT(0), 2031 .hw.init = &(struct clk_init_data) { 2032 .name = "gcc_pcie0_axi_m_clk", 2033 .parent_hws = (const struct clk_hw *[]) { 2034 &pcie0_axi_clk_src.clkr.hw, 2035 }, 2036 .num_parents = 1, 2037 .flags = CLK_SET_RATE_PARENT, 2038 .ops = &clk_branch2_ops, 2039 }, 2040 }, 2041 }; 2042 2043 static struct clk_branch gcc_pcie0_axi_s_bridge_clk = { 2044 .halt_reg = 0x75048, 2045 .clkr = { 2046 .enable_reg = 0x75048, 2047 .enable_mask = BIT(0), 2048 .hw.init = &(struct clk_init_data) { 2049 .name = "gcc_pcie0_axi_s_bridge_clk", 2050 .parent_hws = (const struct clk_hw *[]) { 2051 &pcie0_axi_clk_src.clkr.hw, 2052 }, 2053 .num_parents = 1, 2054 .flags = CLK_SET_RATE_PARENT, 2055 .ops = &clk_branch2_ops, 2056 }, 2057 }, 2058 }; 2059 2060 static struct clk_branch gcc_pcie0_axi_s_clk = { 2061 .halt_reg = 0x7500c, 2062 .clkr = { 2063 .enable_reg = 0x7500c, 2064 .enable_mask = BIT(0), 2065 .hw.init = &(struct clk_init_data) { 2066 .name = "gcc_pcie0_axi_s_clk", 2067 .parent_hws = (const struct clk_hw *[]) { 2068 &pcie0_axi_clk_src.clkr.hw, 2069 }, 2070 .num_parents = 1, 2071 .flags = CLK_SET_RATE_PARENT, 2072 .ops = &clk_branch2_ops, 2073 }, 2074 }, 2075 }; 2076 2077 static struct clk_branch gcc_pcie0_pipe_clk = { 2078 .halt_reg = 0x75018, 2079 .halt_check = BRANCH_HALT_DELAY, 2080 .halt_bit = 31, 2081 .clkr = { 2082 .enable_reg = 0x75018, 2083 .enable_mask = BIT(0), 2084 .hw.init = &(struct clk_init_data) { 2085 .name = "gcc_pcie0_pipe_clk", 2086 .parent_hws = (const struct clk_hw *[]) { 2087 &pcie0_pipe_clk_src.clkr.hw, 2088 }, 2089 .num_parents = 1, 2090 .flags = CLK_SET_RATE_PARENT, 2091 .ops = &clk_branch2_ops, 2092 }, 2093 }, 2094 }; 2095 2096 static struct clk_branch gcc_pcie1_ahb_clk = { 2097 .halt_reg = 0x76010, 2098 .clkr = { 2099 .enable_reg = 0x76010, 2100 .enable_mask = BIT(0), 2101 .hw.init = &(struct clk_init_data) { 2102 .name = "gcc_pcie1_ahb_clk", 2103 .parent_hws = (const struct clk_hw *[]) { 2104 &pcnoc_clk_src.hw, 2105 }, 2106 .num_parents = 1, 2107 .flags = CLK_SET_RATE_PARENT, 2108 .ops = &clk_branch2_ops, 2109 }, 2110 }, 2111 }; 2112 2113 static struct clk_branch gcc_pcie1_aux_clk = { 2114 .halt_reg = 0x76014, 2115 .clkr = { 2116 .enable_reg = 0x76014, 2117 .enable_mask = BIT(0), 2118 .hw.init = &(struct clk_init_data) { 2119 .name = "gcc_pcie1_aux_clk", 2120 .parent_hws = (const struct clk_hw *[]) { 2121 &pcie1_aux_clk_src.clkr.hw, 2122 }, 2123 .num_parents = 1, 2124 .flags = CLK_SET_RATE_PARENT, 2125 .ops = &clk_branch2_ops, 2126 }, 2127 }, 2128 }; 2129 2130 static struct clk_branch gcc_pcie1_axi_m_clk = { 2131 .halt_reg = 0x76008, 2132 .clkr = { 2133 .enable_reg = 0x76008, 2134 .enable_mask = BIT(0), 2135 .hw.init = &(struct clk_init_data) { 2136 .name = "gcc_pcie1_axi_m_clk", 2137 .parent_hws = (const struct clk_hw *[]) { 2138 &pcie1_axi_clk_src.clkr.hw, 2139 }, 2140 .num_parents = 1, 2141 .flags = CLK_SET_RATE_PARENT, 2142 .ops = &clk_branch2_ops, 2143 }, 2144 }, 2145 }; 2146 2147 static struct clk_branch gcc_pcie1_axi_s_bridge_clk = { 2148 .halt_reg = 0x76048, 2149 .clkr = { 2150 .enable_reg = 0x76048, 2151 .enable_mask = BIT(0), 2152 .hw.init = &(struct clk_init_data) { 2153 .name = "gcc_pcie1_axi_s_bridge_clk", 2154 .parent_hws = (const struct clk_hw *[]) { 2155 &pcie1_axi_clk_src.clkr.hw, 2156 }, 2157 .num_parents = 1, 2158 .flags = CLK_SET_RATE_PARENT, 2159 .ops = &clk_branch2_ops, 2160 }, 2161 }, 2162 }; 2163 2164 static struct clk_branch gcc_pcie1_axi_s_clk = { 2165 .halt_reg = 0x7600c, 2166 .clkr = { 2167 .enable_reg = 0x7600c, 2168 .enable_mask = BIT(0), 2169 .hw.init = &(struct clk_init_data) { 2170 .name = "gcc_pcie1_axi_s_clk", 2171 .parent_hws = (const struct clk_hw *[]) { 2172 &pcie1_axi_clk_src.clkr.hw, 2173 }, 2174 .num_parents = 1, 2175 .flags = CLK_SET_RATE_PARENT, 2176 .ops = &clk_branch2_ops, 2177 }, 2178 }, 2179 }; 2180 2181 static struct clk_branch gcc_pcie1_pipe_clk = { 2182 .halt_reg = 8, 2183 .halt_check = BRANCH_HALT_DELAY, 2184 .halt_bit = 31, 2185 .clkr = { 2186 .enable_reg = 0x76018, 2187 .enable_mask = BIT(0), 2188 .hw.init = &(struct clk_init_data) { 2189 .name = "gcc_pcie1_pipe_clk", 2190 .parent_hws = (const struct clk_hw *[]) { 2191 &pcie1_pipe_clk_src.clkr.hw, 2192 }, 2193 .num_parents = 1, 2194 .flags = CLK_SET_RATE_PARENT, 2195 .ops = &clk_branch2_ops, 2196 }, 2197 }, 2198 }; 2199 2200 static struct clk_branch gcc_prng_ahb_clk = { 2201 .halt_reg = 0x13004, 2202 .halt_check = BRANCH_HALT_VOTED, 2203 .clkr = { 2204 .enable_reg = 0x0b004, 2205 .enable_mask = BIT(8), 2206 .hw.init = &(struct clk_init_data) { 2207 .name = "gcc_prng_ahb_clk", 2208 .parent_hws = (const struct clk_hw *[]) { 2209 &pcnoc_clk_src.hw, 2210 }, 2211 .num_parents = 1, 2212 .flags = CLK_SET_RATE_PARENT, 2213 .ops = &clk_branch2_ops, 2214 }, 2215 }, 2216 }; 2217 2218 static struct clk_branch gcc_q6_ahb_clk = { 2219 .halt_reg = 0x59138, 2220 .clkr = { 2221 .enable_reg = 0x59138, 2222 .enable_mask = BIT(0), 2223 .hw.init = &(struct clk_init_data) { 2224 .name = "gcc_q6_ahb_clk", 2225 .parent_hws = (const struct clk_hw *[]) { 2226 &wcss_ahb_clk_src.clkr.hw, 2227 }, 2228 .num_parents = 1, 2229 .flags = CLK_SET_RATE_PARENT, 2230 .ops = &clk_branch2_ops, 2231 }, 2232 }, 2233 }; 2234 2235 static struct clk_branch gcc_q6_ahb_s_clk = { 2236 .halt_reg = 0x5914c, 2237 .clkr = { 2238 .enable_reg = 0x5914c, 2239 .enable_mask = BIT(0), 2240 .hw.init = &(struct clk_init_data) { 2241 .name = "gcc_q6_ahb_s_clk", 2242 .parent_hws = (const struct clk_hw *[]) { 2243 &wcss_ahb_clk_src.clkr.hw, 2244 }, 2245 .num_parents = 1, 2246 .flags = CLK_SET_RATE_PARENT, 2247 .ops = &clk_branch2_ops, 2248 }, 2249 }, 2250 }; 2251 2252 static struct clk_branch gcc_q6_axim_clk = { 2253 .halt_reg = 0x5913c, 2254 .clkr = { 2255 .enable_reg = 0x5913c, 2256 .enable_mask = BIT(0), 2257 .hw.init = &(struct clk_init_data) { 2258 .name = "gcc_q6_axim_clk", 2259 .parent_hws = (const struct clk_hw *[]) { 2260 &q6_axi_clk_src.clkr.hw, 2261 }, 2262 .num_parents = 1, 2263 .flags = CLK_SET_RATE_PARENT, 2264 .ops = &clk_branch2_ops, 2265 }, 2266 }, 2267 }; 2268 2269 static struct clk_branch gcc_q6_axim2_clk = { 2270 .halt_reg = 0x59150, 2271 .clkr = { 2272 .enable_reg = 0x59150, 2273 .enable_mask = BIT(0), 2274 .hw.init = &(struct clk_init_data) { 2275 .name = "gcc_q6_axim2_clk", 2276 .parent_hws = (const struct clk_hw *[]) { 2277 &q6_axi_clk_src.clkr.hw, 2278 }, 2279 .num_parents = 1, 2280 .flags = CLK_SET_RATE_PARENT, 2281 .ops = &clk_branch2_ops, 2282 }, 2283 }, 2284 }; 2285 2286 static struct clk_branch gcc_q6_axis_clk = { 2287 .halt_reg = 0x59154, 2288 .clkr = { 2289 .enable_reg = 0x59154, 2290 .enable_mask = BIT(0), 2291 .hw.init = &(struct clk_init_data) { 2292 .name = "gcc_q6_axis_clk", 2293 .parent_hws = (const struct clk_hw *[]) { 2294 &system_noc_clk_src.hw, 2295 }, 2296 .num_parents = 1, 2297 .flags = CLK_SET_RATE_PARENT, 2298 .ops = &clk_branch2_ops, 2299 }, 2300 }, 2301 }; 2302 2303 static struct clk_branch gcc_q6_tsctr_1to2_clk = { 2304 .halt_reg = 0x59148, 2305 .clkr = { 2306 .enable_reg = 0x59148, 2307 .enable_mask = BIT(0), 2308 .hw.init = &(struct clk_init_data) { 2309 .name = "gcc_q6_tsctr_1to2_clk", 2310 .parent_hws = (const struct clk_hw *[]) { 2311 &qdss_tsctr_div2_clk_src.hw, 2312 }, 2313 .num_parents = 1, 2314 .flags = CLK_SET_RATE_PARENT, 2315 .ops = &clk_branch2_ops, 2316 }, 2317 }, 2318 }; 2319 2320 static struct clk_branch gcc_q6ss_atbm_clk = { 2321 .halt_reg = 0x59144, 2322 .clkr = { 2323 .enable_reg = 0x59144, 2324 .enable_mask = BIT(0), 2325 .hw.init = &(struct clk_init_data) { 2326 .name = "gcc_q6ss_atbm_clk", 2327 .parent_hws = (const struct clk_hw *[]) { 2328 &qdss_at_clk_src.clkr.hw, 2329 }, 2330 .num_parents = 1, 2331 .flags = CLK_SET_RATE_PARENT, 2332 .ops = &clk_branch2_ops, 2333 }, 2334 }, 2335 }; 2336 2337 static struct clk_branch gcc_q6ss_pclkdbg_clk = { 2338 .halt_reg = 0x59140, 2339 .clkr = { 2340 .enable_reg = 0x59140, 2341 .enable_mask = BIT(0), 2342 .hw.init = &(struct clk_init_data) { 2343 .name = "gcc_q6ss_pclkdbg_clk", 2344 .parent_hws = (const struct clk_hw *[]) { 2345 &qdss_dap_sync_clk_src.hw, 2346 }, 2347 .num_parents = 1, 2348 .flags = CLK_SET_RATE_PARENT, 2349 .ops = &clk_branch2_ops, 2350 }, 2351 }, 2352 }; 2353 2354 static struct clk_branch gcc_q6ss_trig_clk = { 2355 .halt_reg = 0x59128, 2356 .clkr = { 2357 .enable_reg = 0x59128, 2358 .enable_mask = BIT(0), 2359 .hw.init = &(struct clk_init_data) { 2360 .name = "gcc_q6ss_trig_clk", 2361 .parent_hws = (const struct clk_hw *[]) { 2362 &qdss_dap_sync_clk_src.hw, 2363 }, 2364 .num_parents = 1, 2365 .flags = CLK_SET_RATE_PARENT, 2366 .ops = &clk_branch2_ops, 2367 }, 2368 }, 2369 }; 2370 2371 static struct clk_branch gcc_qdss_at_clk = { 2372 .halt_reg = 0x29024, 2373 .clkr = { 2374 .enable_reg = 0x29024, 2375 .enable_mask = BIT(0), 2376 .hw.init = &(struct clk_init_data) { 2377 .name = "gcc_qdss_at_clk", 2378 .parent_hws = (const struct clk_hw *[]) { 2379 &qdss_at_clk_src.clkr.hw, 2380 }, 2381 .num_parents = 1, 2382 .flags = CLK_SET_RATE_PARENT, 2383 .ops = &clk_branch2_ops, 2384 }, 2385 }, 2386 }; 2387 2388 static struct clk_branch gcc_qdss_dap_clk = { 2389 .halt_reg = 0x29084, 2390 .clkr = { 2391 .enable_reg = 0x29084, 2392 .enable_mask = BIT(0), 2393 .hw.init = &(struct clk_init_data) { 2394 .name = "gcc_qdss_dap_clk", 2395 .parent_hws = (const struct clk_hw *[]) { 2396 &qdss_tsctr_clk_src.clkr.hw, 2397 }, 2398 .num_parents = 1, 2399 .flags = CLK_SET_RATE_PARENT, 2400 .ops = &clk_branch2_ops, 2401 }, 2402 }, 2403 }; 2404 2405 static struct clk_branch gcc_qdss_cfg_ahb_clk = { 2406 .halt_reg = 0x29008, 2407 .clkr = { 2408 .enable_reg = 0x29008, 2409 .enable_mask = BIT(0), 2410 .hw.init = &(struct clk_init_data) { 2411 .name = "gcc_qdss_cfg_ahb_clk", 2412 .parent_hws = (const struct clk_hw *[]) { 2413 &pcnoc_clk_src.hw, 2414 }, 2415 .num_parents = 1, 2416 .flags = CLK_SET_RATE_PARENT, 2417 .ops = &clk_branch2_ops, 2418 }, 2419 }, 2420 }; 2421 2422 static struct clk_branch gcc_qdss_dap_ahb_clk = { 2423 .halt_reg = 0x29004, 2424 .clkr = { 2425 .enable_reg = 0x29004, 2426 .enable_mask = BIT(0), 2427 .hw.init = &(struct clk_init_data) { 2428 .name = "gcc_qdss_dap_ahb_clk", 2429 .parent_hws = (const struct clk_hw *[]) { 2430 &pcnoc_clk_src.hw, 2431 }, 2432 .num_parents = 1, 2433 .flags = CLK_SET_RATE_PARENT, 2434 .ops = &clk_branch2_ops, 2435 }, 2436 }, 2437 }; 2438 2439 static struct clk_branch gcc_qdss_etr_usb_clk = { 2440 .halt_reg = 0x29028, 2441 .clkr = { 2442 .enable_reg = 0x29028, 2443 .enable_mask = BIT(0), 2444 .hw.init = &(struct clk_init_data) { 2445 .name = "gcc_qdss_etr_usb_clk", 2446 .parent_hws = (const struct clk_hw *[]) { 2447 &system_noc_clk_src.hw, 2448 }, 2449 .num_parents = 1, 2450 .flags = CLK_SET_RATE_PARENT, 2451 .ops = &clk_branch2_ops, 2452 }, 2453 }, 2454 }; 2455 2456 static struct clk_branch gcc_qdss_eud_at_clk = { 2457 .halt_reg = 0x29020, 2458 .clkr = { 2459 .enable_reg = 0x29020, 2460 .enable_mask = BIT(0), 2461 .hw.init = &(struct clk_init_data) { 2462 .name = "gcc_qdss_eud_at_clk", 2463 .parent_hws = (const struct clk_hw *[]) { 2464 &eud_at_clk_src.hw, 2465 }, 2466 .num_parents = 1, 2467 .flags = CLK_SET_RATE_PARENT, 2468 .ops = &clk_branch2_ops, 2469 }, 2470 }, 2471 }; 2472 2473 static struct clk_branch gcc_qdss_stm_clk = { 2474 .halt_reg = 0x29044, 2475 .clkr = { 2476 .enable_reg = 0x29044, 2477 .enable_mask = BIT(0), 2478 .hw.init = &(struct clk_init_data) { 2479 .name = "gcc_qdss_stm_clk", 2480 .parent_hws = (const struct clk_hw *[]) { 2481 &qdss_stm_clk_src.clkr.hw, 2482 }, 2483 .num_parents = 1, 2484 .flags = CLK_SET_RATE_PARENT, 2485 .ops = &clk_branch2_ops, 2486 }, 2487 }, 2488 }; 2489 2490 static struct clk_branch gcc_qdss_traceclkin_clk = { 2491 .halt_reg = 0x29060, 2492 .clkr = { 2493 .enable_reg = 0x29060, 2494 .enable_mask = BIT(0), 2495 .hw.init = &(struct clk_init_data) { 2496 .name = "gcc_qdss_traceclkin_clk", 2497 .parent_hws = (const struct clk_hw *[]) { 2498 &qdss_traceclkin_clk_src.clkr.hw, 2499 }, 2500 .num_parents = 1, 2501 .flags = CLK_SET_RATE_PARENT, 2502 .ops = &clk_branch2_ops, 2503 }, 2504 }, 2505 }; 2506 2507 static struct clk_branch gcc_qdss_tsctr_div8_clk = { 2508 .halt_reg = 0x2908c, 2509 .clkr = { 2510 .enable_reg = 0x2908c, 2511 .enable_mask = BIT(0), 2512 .hw.init = &(struct clk_init_data) { 2513 .name = "gcc_qdss_tsctr_div8_clk", 2514 .parent_hws = (const struct clk_hw *[]) { 2515 &qdss_tsctr_clk_src.clkr.hw, 2516 }, 2517 .num_parents = 1, 2518 .flags = CLK_SET_RATE_PARENT, 2519 .ops = &clk_branch2_ops, 2520 }, 2521 }, 2522 }; 2523 2524 static struct clk_branch gcc_qpic_ahb_clk = { 2525 .halt_reg = 0x57024, 2526 .clkr = { 2527 .enable_reg = 0x57024, 2528 .enable_mask = BIT(0), 2529 .hw.init = &(struct clk_init_data) { 2530 .name = "gcc_qpic_ahb_clk", 2531 .parent_hws = (const struct clk_hw *[]) { 2532 &pcnoc_clk_src.hw, 2533 }, 2534 .num_parents = 1, 2535 .flags = CLK_SET_RATE_PARENT, 2536 .ops = &clk_branch2_ops, 2537 }, 2538 }, 2539 }; 2540 2541 static struct clk_branch gcc_qpic_clk = { 2542 .halt_reg = 0x57020, 2543 .clkr = { 2544 .enable_reg = 0x57020, 2545 .enable_mask = BIT(0), 2546 .hw.init = &(struct clk_init_data) { 2547 .name = "gcc_qpic_clk", 2548 .parent_hws = (const struct clk_hw *[]) { 2549 &pcnoc_clk_src.hw, 2550 }, 2551 .num_parents = 1, 2552 .flags = CLK_SET_RATE_PARENT, 2553 .ops = &clk_branch2_ops, 2554 }, 2555 }, 2556 }; 2557 2558 static struct clk_branch gcc_qpic_io_macro_clk = { 2559 .halt_reg = 0x5701c, 2560 .clkr = { 2561 .enable_reg = 0x5701c, 2562 .enable_mask = BIT(0), 2563 .hw.init = &(struct clk_init_data) { 2564 .name = "gcc_qpic_io_macro_clk", 2565 .parent_hws = (const struct clk_hw *[]) { 2566 &qpic_io_macro_clk_src.clkr.hw, 2567 }, 2568 .num_parents = 1, 2569 .flags = CLK_SET_RATE_PARENT, 2570 .ops = &clk_branch2_ops, 2571 }, 2572 }, 2573 }; 2574 2575 static struct clk_branch gcc_sdcc1_ahb_clk = { 2576 .halt_reg = 0x4201c, 2577 .clkr = { 2578 .enable_reg = 0x4201c, 2579 .enable_mask = BIT(0), 2580 .hw.init = &(struct clk_init_data) { 2581 .name = "gcc_sdcc1_ahb_clk", 2582 .parent_hws = (const struct clk_hw *[]) { 2583 &pcnoc_clk_src.hw, 2584 }, 2585 .num_parents = 1, 2586 .flags = CLK_SET_RATE_PARENT, 2587 .ops = &clk_branch2_ops, 2588 }, 2589 }, 2590 }; 2591 2592 static struct clk_branch gcc_sdcc1_apps_clk = { 2593 .halt_reg = 0x42018, 2594 .clkr = { 2595 .enable_reg = 0x42018, 2596 .enable_mask = BIT(0), 2597 .hw.init = &(struct clk_init_data) { 2598 .name = "gcc_sdcc1_apps_clk", 2599 .parent_hws = (const struct clk_hw *[]) { 2600 &sdcc1_apps_clk_src.clkr.hw, 2601 }, 2602 .num_parents = 1, 2603 .flags = CLK_SET_RATE_PARENT, 2604 .ops = &clk_branch2_ops, 2605 }, 2606 }, 2607 }; 2608 2609 static struct clk_branch gcc_snoc_gmac0_ahb_clk = { 2610 .halt_reg = 0x260a0, 2611 .clkr = { 2612 .enable_reg = 0x260a0, 2613 .enable_mask = BIT(0), 2614 .hw.init = &(struct clk_init_data) { 2615 .name = "gcc_snoc_gmac0_ahb_clk", 2616 .parent_hws = (const struct clk_hw *[]) { 2617 &gmac_clk_src.clkr.hw, 2618 }, 2619 .num_parents = 1, 2620 .flags = CLK_SET_RATE_PARENT, 2621 .ops = &clk_branch2_ops, 2622 }, 2623 }, 2624 }; 2625 2626 static struct clk_branch gcc_snoc_gmac0_axi_clk = { 2627 .halt_reg = 0x26084, 2628 .clkr = { 2629 .enable_reg = 0x26084, 2630 .enable_mask = BIT(0), 2631 .hw.init = &(struct clk_init_data) { 2632 .name = "gcc_snoc_gmac0_axi_clk", 2633 .parent_hws = (const struct clk_hw *[]) { 2634 &gmac_clk_src.clkr.hw, 2635 }, 2636 .num_parents = 1, 2637 .flags = CLK_SET_RATE_PARENT, 2638 .ops = &clk_branch2_ops, 2639 }, 2640 }, 2641 }; 2642 2643 static struct clk_branch gcc_snoc_gmac1_ahb_clk = { 2644 .halt_reg = 0x260a4, 2645 .clkr = { 2646 .enable_reg = 0x260a4, 2647 .enable_mask = BIT(0), 2648 .hw.init = &(struct clk_init_data) { 2649 .name = "gcc_snoc_gmac1_ahb_clk", 2650 .parent_hws = (const struct clk_hw *[]) { 2651 &gmac_clk_src.clkr.hw, 2652 }, 2653 .num_parents = 1, 2654 .flags = CLK_SET_RATE_PARENT, 2655 .ops = &clk_branch2_ops, 2656 }, 2657 }, 2658 }; 2659 2660 static struct clk_branch gcc_snoc_gmac1_axi_clk = { 2661 .halt_reg = 0x26088, 2662 .clkr = { 2663 .enable_reg = 0x26088, 2664 .enable_mask = BIT(0), 2665 .hw.init = &(struct clk_init_data) { 2666 .name = "gcc_snoc_gmac1_axi_clk", 2667 .parent_hws = (const struct clk_hw *[]) { 2668 &gmac_clk_src.clkr.hw, 2669 }, 2670 .num_parents = 1, 2671 .flags = CLK_SET_RATE_PARENT, 2672 .ops = &clk_branch2_ops, 2673 }, 2674 }, 2675 }; 2676 2677 static struct clk_branch gcc_snoc_lpass_axim_clk = { 2678 .halt_reg = 0x26074, 2679 .clkr = { 2680 .enable_reg = 0x26074, 2681 .enable_mask = BIT(0), 2682 .hw.init = &(struct clk_init_data) { 2683 .name = "gcc_snoc_lpass_axim_clk", 2684 .parent_hws = (const struct clk_hw *[]) { 2685 &lpass_axim_clk_src.clkr.hw, 2686 }, 2687 .num_parents = 1, 2688 .flags = CLK_SET_RATE_PARENT, 2689 .ops = &clk_branch2_ops, 2690 }, 2691 }, 2692 }; 2693 2694 static struct clk_branch gcc_snoc_lpass_sway_clk = { 2695 .halt_reg = 0x26078, 2696 .clkr = { 2697 .enable_reg = 0x26078, 2698 .enable_mask = BIT(0), 2699 .hw.init = &(struct clk_init_data) { 2700 .name = "gcc_snoc_lpass_sway_clk", 2701 .parent_hws = (const struct clk_hw *[]) { 2702 &lpass_sway_clk_src.clkr.hw, 2703 }, 2704 .num_parents = 1, 2705 .flags = CLK_SET_RATE_PARENT, 2706 .ops = &clk_branch2_ops, 2707 }, 2708 }, 2709 }; 2710 2711 static struct clk_branch gcc_snoc_ubi0_axi_clk = { 2712 .halt_reg = 0x26094, 2713 .clkr = { 2714 .enable_reg = 0x26094, 2715 .enable_mask = BIT(0), 2716 .hw.init = &(struct clk_init_data) { 2717 .name = "gcc_snoc_ubi0_axi_clk", 2718 .parent_hws = (const struct clk_hw *[]) { 2719 &ubi0_axi_clk_src.clkr.hw, 2720 }, 2721 .num_parents = 1, 2722 .flags = CLK_SET_RATE_PARENT, 2723 .ops = &clk_branch2_ops, 2724 }, 2725 }, 2726 }; 2727 2728 static struct clk_branch gcc_sys_noc_pcie0_axi_clk = { 2729 .halt_reg = 0x26048, 2730 .clkr = { 2731 .enable_reg = 0x26048, 2732 .enable_mask = BIT(0), 2733 .hw.init = &(struct clk_init_data) { 2734 .name = "gcc_sys_noc_pcie0_axi_clk", 2735 .parent_hws = (const struct clk_hw *[]) { 2736 &pcie0_axi_clk_src.clkr.hw, 2737 }, 2738 .num_parents = 1, 2739 .flags = CLK_SET_RATE_PARENT, 2740 .ops = &clk_branch2_ops, 2741 }, 2742 }, 2743 }; 2744 2745 static struct clk_branch gcc_sys_noc_pcie1_axi_clk = { 2746 .halt_reg = 0x2604c, 2747 .clkr = { 2748 .enable_reg = 0x2604c, 2749 .enable_mask = BIT(0), 2750 .hw.init = &(struct clk_init_data) { 2751 .name = "gcc_sys_noc_pcie1_axi_clk", 2752 .parent_hws = (const struct clk_hw *[]) { 2753 &pcie1_axi_clk_src.clkr.hw, 2754 }, 2755 .num_parents = 1, 2756 .flags = CLK_SET_RATE_PARENT, 2757 .ops = &clk_branch2_ops, 2758 }, 2759 }, 2760 }; 2761 2762 static struct clk_branch gcc_sys_noc_qdss_stm_axi_clk = { 2763 .halt_reg = 0x26024, 2764 .clkr = { 2765 .enable_reg = 0x26024, 2766 .enable_mask = BIT(0), 2767 .hw.init = &(struct clk_init_data) { 2768 .name = "gcc_sys_noc_qdss_stm_axi_clk", 2769 .parent_hws = (const struct clk_hw *[]) { 2770 &qdss_stm_clk_src.clkr.hw, 2771 }, 2772 .num_parents = 1, 2773 .flags = CLK_SET_RATE_PARENT, 2774 .ops = &clk_branch2_ops, 2775 }, 2776 }, 2777 }; 2778 2779 static struct clk_branch gcc_sys_noc_usb0_axi_clk = { 2780 .halt_reg = 0x26040, 2781 .clkr = { 2782 .enable_reg = 0x26040, 2783 .enable_mask = BIT(0), 2784 .hw.init = &(struct clk_init_data) { 2785 .name = "gcc_sys_noc_usb0_axi_clk", 2786 .parent_hws = (const struct clk_hw *[]) { 2787 &usb0_master_clk_src.clkr.hw, 2788 }, 2789 .num_parents = 1, 2790 .flags = CLK_SET_RATE_PARENT, 2791 .ops = &clk_branch2_ops, 2792 }, 2793 }, 2794 }; 2795 2796 static struct clk_branch gcc_sys_noc_wcss_ahb_clk = { 2797 .halt_reg = 0x26034, 2798 .clkr = { 2799 .enable_reg = 0x26034, 2800 .enable_mask = BIT(0), 2801 .hw.init = &(struct clk_init_data) { 2802 .name = "gcc_sys_noc_wcss_ahb_clk", 2803 .parent_hws = (const struct clk_hw *[]) { 2804 &wcss_ahb_clk_src.clkr.hw, 2805 }, 2806 .num_parents = 1, 2807 .flags = CLK_SET_RATE_PARENT, 2808 .ops = &clk_branch2_ops, 2809 }, 2810 }, 2811 }; 2812 2813 static struct clk_branch gcc_ubi0_axi_clk = { 2814 .halt_reg = 0x68200, 2815 .halt_check = BRANCH_HALT_DELAY, 2816 .clkr = { 2817 .enable_reg = 0x68200, 2818 .enable_mask = BIT(0), 2819 .hw.init = &(struct clk_init_data) { 2820 .name = "gcc_ubi0_axi_clk", 2821 .parent_hws = (const struct clk_hw *[]) { 2822 &ubi0_axi_clk_src.clkr.hw, 2823 }, 2824 .num_parents = 1, 2825 .flags = CLK_SET_RATE_PARENT, 2826 .ops = &clk_branch2_ops, 2827 }, 2828 }, 2829 }; 2830 2831 static struct clk_branch gcc_ubi0_cfg_clk = { 2832 .halt_reg = 0x68160, 2833 .halt_check = BRANCH_HALT_DELAY, 2834 .clkr = { 2835 .enable_reg = 0x68160, 2836 .enable_mask = BIT(0), 2837 .hw.init = &(struct clk_init_data) { 2838 .name = "gcc_ubi0_cfg_clk", 2839 .parent_hws = (const struct clk_hw *[]) { 2840 &pcnoc_clk_src.hw, 2841 }, 2842 .num_parents = 1, 2843 .flags = CLK_SET_RATE_PARENT, 2844 .ops = &clk_branch2_ops, 2845 }, 2846 }, 2847 }; 2848 2849 static struct clk_branch gcc_ubi0_dbg_clk = { 2850 .halt_reg = 0x68214, 2851 .halt_check = BRANCH_HALT_DELAY, 2852 .clkr = { 2853 .enable_reg = 0x68214, 2854 .enable_mask = BIT(0), 2855 .hw.init = &(struct clk_init_data) { 2856 .name = "gcc_ubi0_dbg_clk", 2857 .parent_hws = (const struct clk_hw *[]) { 2858 &qdss_tsctr_clk_src.clkr.hw, 2859 }, 2860 .num_parents = 1, 2861 .flags = CLK_SET_RATE_PARENT, 2862 .ops = &clk_branch2_ops, 2863 }, 2864 }, 2865 }; 2866 2867 static struct clk_branch gcc_ubi0_core_clk = { 2868 .halt_reg = 0x68210, 2869 .halt_check = BRANCH_HALT_DELAY, 2870 .clkr = { 2871 .enable_reg = 0x68210, 2872 .enable_mask = BIT(0), 2873 .hw.init = &(struct clk_init_data) { 2874 .name = "gcc_ubi0_core_clk", 2875 .parent_hws = (const struct clk_hw *[]) { 2876 &ubi0_core_clk_src.clkr.hw, 2877 }, 2878 .num_parents = 1, 2879 .flags = CLK_SET_RATE_PARENT, 2880 .ops = &clk_branch2_ops, 2881 }, 2882 }, 2883 }; 2884 2885 static struct clk_branch gcc_ubi0_nc_axi_clk = { 2886 .halt_reg = 0x68204, 2887 .halt_check = BRANCH_HALT_DELAY, 2888 .clkr = { 2889 .enable_reg = 0x68204, 2890 .enable_mask = BIT(0), 2891 .hw.init = &(struct clk_init_data) { 2892 .name = "gcc_ubi0_nc_axi_clk", 2893 .parent_hws = (const struct clk_hw *[]) { 2894 &system_noc_clk_src.hw, 2895 }, 2896 .num_parents = 1, 2897 .flags = CLK_SET_RATE_PARENT, 2898 .ops = &clk_branch2_ops, 2899 }, 2900 }, 2901 }; 2902 2903 static struct clk_branch gcc_ubi0_utcm_clk = { 2904 .halt_reg = 0x68208, 2905 .halt_check = BRANCH_HALT_DELAY, 2906 .clkr = { 2907 .enable_reg = 0x68208, 2908 .enable_mask = BIT(0), 2909 .hw.init = &(struct clk_init_data) { 2910 .name = "gcc_ubi0_utcm_clk", 2911 .parent_hws = (const struct clk_hw *[]) { 2912 &system_noc_clk_src.hw, 2913 }, 2914 .num_parents = 1, 2915 .flags = CLK_SET_RATE_PARENT, 2916 .ops = &clk_branch2_ops, 2917 }, 2918 }, 2919 }; 2920 2921 static struct clk_branch gcc_uniphy_ahb_clk = { 2922 .halt_reg = 0x56108, 2923 .clkr = { 2924 .enable_reg = 0x56108, 2925 .enable_mask = BIT(0), 2926 .hw.init = &(struct clk_init_data) { 2927 .name = "gcc_uniphy_ahb_clk", 2928 .parent_hws = (const struct clk_hw *[]) { 2929 &pcnoc_clk_src.hw, 2930 }, 2931 .num_parents = 1, 2932 .flags = CLK_SET_RATE_PARENT, 2933 .ops = &clk_branch2_ops, 2934 }, 2935 }, 2936 }; 2937 2938 static struct clk_branch gcc_uniphy_rx_clk = { 2939 .halt_reg = 0x56110, 2940 .clkr = { 2941 .enable_reg = 0x56110, 2942 .enable_mask = BIT(0), 2943 .hw.init = &(struct clk_init_data) { 2944 .name = "gcc_uniphy_rx_clk", 2945 .parent_hws = (const struct clk_hw *[]) { 2946 &gmac1_rx_div_clk_src.clkr.hw, 2947 }, 2948 .num_parents = 1, 2949 .ops = &clk_branch2_ops, 2950 .flags = CLK_SET_RATE_PARENT, 2951 }, 2952 }, 2953 }; 2954 2955 static struct clk_branch gcc_uniphy_tx_clk = { 2956 .halt_reg = 0x56114, 2957 .clkr = { 2958 .enable_reg = 0x56114, 2959 .enable_mask = BIT(0), 2960 .hw.init = &(struct clk_init_data) { 2961 .name = "gcc_uniphy_tx_clk", 2962 .parent_hws = (const struct clk_hw *[]) { 2963 &gmac1_tx_div_clk_src.clkr.hw, 2964 }, 2965 .num_parents = 1, 2966 .ops = &clk_branch2_ops, 2967 .flags = CLK_SET_RATE_PARENT, 2968 }, 2969 }, 2970 }; 2971 2972 static struct clk_branch gcc_uniphy_sys_clk = { 2973 .halt_reg = 0x5610c, 2974 .clkr = { 2975 .enable_reg = 0x5610c, 2976 .enable_mask = BIT(0), 2977 .hw.init = &(struct clk_init_data) { 2978 .name = "gcc_uniphy_sys_clk", 2979 .parent_hws = (const struct clk_hw *[]) { 2980 &gcc_xo_clk_src.clkr.hw, 2981 }, 2982 .num_parents = 1, 2983 .flags = CLK_SET_RATE_PARENT, 2984 .ops = &clk_branch2_ops, 2985 }, 2986 }, 2987 }; 2988 2989 static struct clk_branch gcc_usb0_aux_clk = { 2990 .halt_reg = 0x3e044, 2991 .clkr = { 2992 .enable_reg = 0x3e044, 2993 .enable_mask = BIT(0), 2994 .hw.init = &(struct clk_init_data) { 2995 .name = "gcc_usb0_aux_clk", 2996 .parent_hws = (const struct clk_hw *[]) { 2997 &usb0_aux_clk_src.clkr.hw, 2998 }, 2999 .num_parents = 1, 3000 .flags = CLK_SET_RATE_PARENT, 3001 .ops = &clk_branch2_ops, 3002 }, 3003 }, 3004 }; 3005 3006 static struct clk_branch gcc_usb0_eud_at_clk = { 3007 .halt_reg = 0x3e04c, 3008 .halt_check = BRANCH_HALT_VOTED, 3009 .clkr = { 3010 .enable_reg = 0x3e04c, 3011 .enable_mask = BIT(0), 3012 .hw.init = &(struct clk_init_data) { 3013 .name = "gcc_usb0_eud_at_clk", 3014 .parent_hws = (const struct clk_hw *[]) { 3015 &eud_at_clk_src.hw, 3016 }, 3017 .num_parents = 1, 3018 .flags = CLK_SET_RATE_PARENT, 3019 .ops = &clk_branch2_ops, 3020 }, 3021 }, 3022 }; 3023 3024 static struct clk_branch gcc_usb0_lfps_clk = { 3025 .halt_reg = 0x3e050, 3026 .clkr = { 3027 .enable_reg = 0x3e050, 3028 .enable_mask = BIT(0), 3029 .hw.init = &(struct clk_init_data) { 3030 .name = "gcc_usb0_lfps_clk", 3031 .parent_hws = (const struct clk_hw *[]) { 3032 &usb0_lfps_clk_src.clkr.hw, 3033 }, 3034 .num_parents = 1, 3035 .flags = CLK_SET_RATE_PARENT, 3036 .ops = &clk_branch2_ops, 3037 }, 3038 }, 3039 }; 3040 3041 static struct clk_branch gcc_usb0_master_clk = { 3042 .halt_reg = 0x3e000, 3043 .clkr = { 3044 .enable_reg = 0x3e000, 3045 .enable_mask = BIT(0), 3046 .hw.init = &(struct clk_init_data) { 3047 .name = "gcc_usb0_master_clk", 3048 .parent_hws = (const struct clk_hw *[]) { 3049 &usb0_master_clk_src.clkr.hw, 3050 }, 3051 .num_parents = 1, 3052 .flags = CLK_SET_RATE_PARENT, 3053 .ops = &clk_branch2_ops, 3054 }, 3055 }, 3056 }; 3057 3058 static struct clk_branch gcc_usb0_mock_utmi_clk = { 3059 .halt_reg = 0x3e008, 3060 .clkr = { 3061 .enable_reg = 0x3e008, 3062 .enable_mask = BIT(0), 3063 .hw.init = &(struct clk_init_data) { 3064 .name = "gcc_usb0_mock_utmi_clk", 3065 .parent_hws = (const struct clk_hw *[]) { 3066 &usb0_mock_utmi_clk_src.clkr.hw, 3067 }, 3068 .num_parents = 1, 3069 .flags = CLK_SET_RATE_PARENT, 3070 .ops = &clk_branch2_ops, 3071 }, 3072 }, 3073 }; 3074 3075 static struct clk_branch gcc_usb0_phy_cfg_ahb_clk = { 3076 .halt_reg = 0x3e080, 3077 .clkr = { 3078 .enable_reg = 0x3e080, 3079 .enable_mask = BIT(0), 3080 .hw.init = &(struct clk_init_data) { 3081 .name = "gcc_usb0_phy_cfg_ahb_clk", 3082 .parent_hws = (const struct clk_hw *[]) { 3083 &pcnoc_clk_src.hw, 3084 }, 3085 .num_parents = 1, 3086 .flags = CLK_SET_RATE_PARENT, 3087 .ops = &clk_branch2_ops, 3088 }, 3089 }, 3090 }; 3091 3092 static struct clk_branch gcc_usb0_sleep_clk = { 3093 .halt_reg = 0x3e004, 3094 .clkr = { 3095 .enable_reg = 0x3e004, 3096 .enable_mask = BIT(0), 3097 .hw.init = &(struct clk_init_data) { 3098 .name = "gcc_usb0_sleep_clk", 3099 .parent_hws = (const struct clk_hw *[]) { 3100 &gcc_sleep_clk_src.clkr.hw, 3101 }, 3102 .num_parents = 1, 3103 .flags = CLK_SET_RATE_PARENT, 3104 .ops = &clk_branch2_ops, 3105 }, 3106 }, 3107 }; 3108 3109 static struct clk_branch gcc_usb0_pipe_clk = { 3110 .halt_reg = 0x3e040, 3111 .halt_check = BRANCH_HALT_DELAY, 3112 .clkr = { 3113 .enable_reg = 0x3e040, 3114 .enable_mask = BIT(0), 3115 .hw.init = &(struct clk_init_data) { 3116 .name = "gcc_usb0_pipe_clk", 3117 .parent_hws = (const struct clk_hw *[]) { 3118 &usb0_pipe_clk_src.clkr.hw, 3119 }, 3120 .num_parents = 1, 3121 .flags = CLK_SET_RATE_PARENT, 3122 .ops = &clk_branch2_ops, 3123 }, 3124 }, 3125 }; 3126 3127 static struct clk_branch gcc_wcss_acmt_clk = { 3128 .halt_reg = 0x59064, 3129 .clkr = { 3130 .enable_reg = 0x59064, 3131 .enable_mask = BIT(0), 3132 .hw.init = &(struct clk_init_data) { 3133 .name = "gcc_wcss_acmt_clk", 3134 .parent_hws = (const struct clk_hw *[]) { 3135 &wcss_ahb_clk_src.clkr.hw, 3136 }, 3137 .num_parents = 1, 3138 .flags = CLK_SET_RATE_PARENT, 3139 .ops = &clk_branch2_ops, 3140 }, 3141 }, 3142 }; 3143 3144 static struct clk_branch gcc_wcss_ahb_s_clk = { 3145 .halt_reg = 0x59034, 3146 .clkr = { 3147 .enable_reg = 0x59034, 3148 .enable_mask = BIT(0), 3149 .hw.init = &(struct clk_init_data) { 3150 .name = "gcc_wcss_ahb_s_clk", 3151 .parent_hws = (const struct clk_hw *[]) { 3152 &wcss_ahb_clk_src.clkr.hw, 3153 }, 3154 .num_parents = 1, 3155 .flags = CLK_SET_RATE_PARENT, 3156 .ops = &clk_branch2_ops, 3157 }, 3158 }, 3159 }; 3160 3161 static struct clk_branch gcc_wcss_axi_m_clk = { 3162 .halt_reg = 0x5903c, 3163 .clkr = { 3164 .enable_reg = 0x5903c, 3165 .enable_mask = BIT(0), 3166 .hw.init = &(struct clk_init_data) { 3167 .name = "gcc_wcss_axi_m_clk", 3168 .parent_hws = (const struct clk_hw *[]) { 3169 &system_noc_clk_src.hw, 3170 }, 3171 .num_parents = 1, 3172 .flags = CLK_SET_RATE_PARENT, 3173 .ops = &clk_branch2_ops, 3174 }, 3175 }, 3176 }; 3177 3178 static struct clk_branch gcc_wcss_axi_s_clk = { 3179 .halt_reg = 0x59068, 3180 .clkr = { 3181 .enable_reg = 0x59068, 3182 .enable_mask = BIT(0), 3183 .hw.init = &(struct clk_init_data) { 3184 .name = "gcc_wi_s_clk", 3185 .parent_hws = (const struct clk_hw *[]) { 3186 &system_noc_clk_src.hw, 3187 }, 3188 .num_parents = 1, 3189 .flags = CLK_SET_RATE_PARENT, 3190 .ops = &clk_branch2_ops, 3191 }, 3192 }, 3193 }; 3194 3195 static struct clk_branch gcc_wcss_dbg_ifc_apb_bdg_clk = { 3196 .halt_reg = 0x59050, 3197 .clkr = { 3198 .enable_reg = 0x59050, 3199 .enable_mask = BIT(0), 3200 .hw.init = &(struct clk_init_data) { 3201 .name = "gcc_wcss_dbg_ifc_apb_bdg_clk", 3202 .parent_hws = (const struct clk_hw *[]) { 3203 &qdss_dap_sync_clk_src.hw, 3204 }, 3205 .num_parents = 1, 3206 .flags = CLK_SET_RATE_PARENT, 3207 .ops = &clk_branch2_ops, 3208 }, 3209 }, 3210 }; 3211 3212 static struct clk_branch gcc_wcss_dbg_ifc_apb_clk = { 3213 .halt_reg = 0x59040, 3214 .clkr = { 3215 .enable_reg = 0x59040, 3216 .enable_mask = BIT(0), 3217 .hw.init = &(struct clk_init_data) { 3218 .name = "gcc_wcss_dbg_ifc_apb_clk", 3219 .parent_hws = (const struct clk_hw *[]) { 3220 &qdss_dap_sync_clk_src.hw, 3221 }, 3222 .num_parents = 1, 3223 .flags = CLK_SET_RATE_PARENT, 3224 .ops = &clk_branch2_ops, 3225 }, 3226 }, 3227 }; 3228 3229 static struct clk_branch gcc_wcss_dbg_ifc_atb_bdg_clk = { 3230 .halt_reg = 0x59054, 3231 .clkr = { 3232 .enable_reg = 0x59054, 3233 .enable_mask = BIT(0), 3234 .hw.init = &(struct clk_init_data) { 3235 .name = "gcc_wcss_dbg_ifc_atb_bdg_clk", 3236 .parent_hws = (const struct clk_hw *[]) { 3237 &qdss_at_clk_src.clkr.hw, 3238 }, 3239 .num_parents = 1, 3240 .flags = CLK_SET_RATE_PARENT, 3241 .ops = &clk_branch2_ops, 3242 }, 3243 }, 3244 }; 3245 3246 static struct clk_branch gcc_wcss_dbg_ifc_atb_clk = { 3247 .halt_reg = 0x59044, 3248 .clkr = { 3249 .enable_reg = 0x59044, 3250 .enable_mask = BIT(0), 3251 .hw.init = &(struct clk_init_data) { 3252 .name = "gcc_wcss_dbg_ifc_atb_clk", 3253 .parent_hws = (const struct clk_hw *[]) { 3254 &qdss_at_clk_src.clkr.hw, 3255 }, 3256 .num_parents = 1, 3257 .flags = CLK_SET_RATE_PARENT, 3258 .ops = &clk_branch2_ops, 3259 }, 3260 }, 3261 }; 3262 3263 static struct clk_branch gcc_wcss_dbg_ifc_dapbus_bdg_clk = { 3264 .halt_reg = 0x59060, 3265 .clkr = { 3266 .enable_reg = 0x59060, 3267 .enable_mask = BIT(0), 3268 .hw.init = &(struct clk_init_data) { 3269 .name = "gcc_wcss_dbg_ifc_dapbus_bdg_clk", 3270 .parent_hws = (const struct clk_hw *[]) { 3271 &qdss_dap_sync_clk_src.hw, 3272 }, 3273 .num_parents = 1, 3274 .flags = CLK_SET_RATE_PARENT, 3275 .ops = &clk_branch2_ops, 3276 }, 3277 }, 3278 }; 3279 3280 static struct clk_branch gcc_wcss_dbg_ifc_dapbus_clk = { 3281 .halt_reg = 0x5905c, 3282 .clkr = { 3283 .enable_reg = 0x5905c, 3284 .enable_mask = BIT(0), 3285 .hw.init = &(struct clk_init_data) { 3286 .name = "gcc_wcss_dbg_ifc_dapbus_clk", 3287 .parent_hws = (const struct clk_hw *[]) { 3288 &qdss_dap_sync_clk_src.hw, 3289 }, 3290 .num_parents = 1, 3291 .flags = CLK_SET_RATE_PARENT, 3292 .ops = &clk_branch2_ops, 3293 }, 3294 }, 3295 }; 3296 3297 static struct clk_branch gcc_wcss_dbg_ifc_nts_bdg_clk = { 3298 .halt_reg = 0x59058, 3299 .clkr = { 3300 .enable_reg = 0x59058, 3301 .enable_mask = BIT(0), 3302 .hw.init = &(struct clk_init_data) { 3303 .name = "gcc_wcss_dbg_ifc_nts_bdg_clk", 3304 .parent_hws = (const struct clk_hw *[]) { 3305 &qdss_tsctr_div2_clk_src.hw, 3306 }, 3307 .num_parents = 1, 3308 .flags = CLK_SET_RATE_PARENT, 3309 .ops = &clk_branch2_ops, 3310 }, 3311 }, 3312 }; 3313 3314 static struct clk_branch gcc_wcss_dbg_ifc_nts_clk = { 3315 .halt_reg = 0x59048, 3316 .clkr = { 3317 .enable_reg = 0x59048, 3318 .enable_mask = BIT(0), 3319 .hw.init = &(struct clk_init_data) { 3320 .name = "gcc_wcss_dbg_ifc_nts_clk", 3321 .parent_hws = (const struct clk_hw *[]) { 3322 &qdss_tsctr_div2_clk_src.hw, 3323 }, 3324 .num_parents = 1, 3325 .flags = CLK_SET_RATE_PARENT, 3326 .ops = &clk_branch2_ops, 3327 }, 3328 }, 3329 }; 3330 3331 static struct clk_branch gcc_wcss_ecahb_clk = { 3332 .halt_reg = 0x59038, 3333 .clkr = { 3334 .enable_reg = 0x59038, 3335 .enable_mask = BIT(0), 3336 .hw.init = &(struct clk_init_data) { 3337 .name = "gcc_wcss_ecahb_clk", 3338 .parent_hws = (const struct clk_hw *[]) { 3339 &wcss_ahb_clk_src.clkr.hw, 3340 }, 3341 .num_parents = 1, 3342 .flags = CLK_SET_RATE_PARENT, 3343 .ops = &clk_branch2_ops, 3344 }, 3345 }, 3346 }; 3347 3348 static struct clk_hw *gcc_ipq5018_hws[] = { 3349 &gpll0_out_main_div2.hw, 3350 &pcnoc_clk_src.hw, 3351 &system_noc_clk_src.hw, 3352 &qdss_dap_sync_clk_src.hw, 3353 &qdss_tsctr_div2_clk_src.hw, 3354 &eud_at_clk_src.hw, 3355 }; 3356 3357 static const struct alpha_pll_config ubi32_pll_config = { 3358 .l = 0x29, 3359 .alpha = 0xaaaaaaaa, 3360 .alpha_hi = 0xaa, 3361 .config_ctl_val = 0x4001075b, 3362 .main_output_mask = BIT(0), 3363 .aux_output_mask = BIT(1), 3364 .alpha_en_mask = BIT(24), 3365 .vco_val = 0x1, 3366 .vco_mask = GENMASK(21, 20), 3367 .test_ctl_val = 0x0, 3368 .test_ctl_hi_val = 0x0, 3369 }; 3370 3371 static struct clk_regmap *gcc_ipq5018_clks[] = { 3372 [GPLL0_MAIN] = &gpll0_main.clkr, 3373 [GPLL0] = &gpll0.clkr, 3374 [GPLL2_MAIN] = &gpll2_main.clkr, 3375 [GPLL2] = &gpll2.clkr, 3376 [GPLL4_MAIN] = &gpll4_main.clkr, 3377 [GPLL4] = &gpll4.clkr, 3378 [UBI32_PLL_MAIN] = &ubi32_pll_main.clkr, 3379 [UBI32_PLL] = &ubi32_pll.clkr, 3380 [ADSS_PWM_CLK_SRC] = &adss_pwm_clk_src.clkr, 3381 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr, 3382 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr, 3383 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr, 3384 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr, 3385 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr, 3386 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr, 3387 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr, 3388 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr, 3389 [CRYPTO_CLK_SRC] = &crypto_clk_src.clkr, 3390 [GCC_ADSS_PWM_CLK] = &gcc_adss_pwm_clk.clkr, 3391 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr, 3392 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr, 3393 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr, 3394 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr, 3395 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr, 3396 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr, 3397 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr, 3398 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, 3399 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr, 3400 [GCC_BTSS_LPO_CLK] = &gcc_btss_lpo_clk.clkr, 3401 [GCC_CMN_BLK_AHB_CLK] = &gcc_cmn_blk_ahb_clk.clkr, 3402 [GCC_CMN_BLK_SYS_CLK] = &gcc_cmn_blk_sys_clk.clkr, 3403 [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr, 3404 [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr, 3405 [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr, 3406 [GCC_DCC_CLK] = &gcc_dcc_clk.clkr, 3407 [GCC_GEPHY_RX_CLK] = &gcc_gephy_rx_clk.clkr, 3408 [GCC_GEPHY_TX_CLK] = &gcc_gephy_tx_clk.clkr, 3409 [GCC_GMAC0_CFG_CLK] = &gcc_gmac0_cfg_clk.clkr, 3410 [GCC_GMAC0_PTP_CLK] = &gcc_gmac0_ptp_clk.clkr, 3411 [GCC_GMAC0_RX_CLK] = &gcc_gmac0_rx_clk.clkr, 3412 [GCC_GMAC0_SYS_CLK] = &gcc_gmac0_sys_clk.clkr, 3413 [GCC_GMAC0_TX_CLK] = &gcc_gmac0_tx_clk.clkr, 3414 [GCC_GMAC1_CFG_CLK] = &gcc_gmac1_cfg_clk.clkr, 3415 [GCC_GMAC1_PTP_CLK] = &gcc_gmac1_ptp_clk.clkr, 3416 [GCC_GMAC1_RX_CLK] = &gcc_gmac1_rx_clk.clkr, 3417 [GCC_GMAC1_SYS_CLK] = &gcc_gmac1_sys_clk.clkr, 3418 [GCC_GMAC1_TX_CLK] = &gcc_gmac1_tx_clk.clkr, 3419 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 3420 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 3421 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 3422 [GCC_LPASS_CORE_AXIM_CLK] = &gcc_lpass_core_axim_clk.clkr, 3423 [GCC_LPASS_SWAY_CLK] = &gcc_lpass_sway_clk.clkr, 3424 [GCC_MDIO0_AHB_CLK] = &gcc_mdio0_ahb_clk.clkr, 3425 [GCC_MDIO1_AHB_CLK] = &gcc_mdio1_ahb_clk.clkr, 3426 [GCC_PCIE0_AHB_CLK] = &gcc_pcie0_ahb_clk.clkr, 3427 [GCC_PCIE0_AUX_CLK] = &gcc_pcie0_aux_clk.clkr, 3428 [GCC_PCIE0_AXI_M_CLK] = &gcc_pcie0_axi_m_clk.clkr, 3429 [GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr, 3430 [GCC_PCIE0_AXI_S_CLK] = &gcc_pcie0_axi_s_clk.clkr, 3431 [GCC_PCIE1_AHB_CLK] = &gcc_pcie1_ahb_clk.clkr, 3432 [GCC_PCIE1_AUX_CLK] = &gcc_pcie1_aux_clk.clkr, 3433 [GCC_PCIE1_AXI_M_CLK] = &gcc_pcie1_axi_m_clk.clkr, 3434 [GCC_PCIE1_AXI_S_BRIDGE_CLK] = &gcc_pcie1_axi_s_bridge_clk.clkr, 3435 [GCC_PCIE1_AXI_S_CLK] = &gcc_pcie1_axi_s_clk.clkr, 3436 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, 3437 [GCC_Q6_AXIM_CLK] = &gcc_q6_axim_clk.clkr, 3438 [GCC_Q6_AXIM2_CLK] = &gcc_q6_axim2_clk.clkr, 3439 [GCC_Q6_AXIS_CLK] = &gcc_q6_axis_clk.clkr, 3440 [GCC_Q6_AHB_CLK] = &gcc_q6_ahb_clk.clkr, 3441 [GCC_Q6_AHB_S_CLK] = &gcc_q6_ahb_s_clk.clkr, 3442 [GCC_Q6_TSCTR_1TO2_CLK] = &gcc_q6_tsctr_1to2_clk.clkr, 3443 [GCC_Q6SS_ATBM_CLK] = &gcc_q6ss_atbm_clk.clkr, 3444 [GCC_Q6SS_PCLKDBG_CLK] = &gcc_q6ss_pclkdbg_clk.clkr, 3445 [GCC_Q6SS_TRIG_CLK] = &gcc_q6ss_trig_clk.clkr, 3446 [GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr, 3447 [GCC_QDSS_CFG_AHB_CLK] = &gcc_qdss_cfg_ahb_clk.clkr, 3448 [GCC_QDSS_DAP_AHB_CLK] = &gcc_qdss_dap_ahb_clk.clkr, 3449 [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr, 3450 [GCC_QDSS_ETR_USB_CLK] = &gcc_qdss_etr_usb_clk.clkr, 3451 [GCC_QDSS_EUD_AT_CLK] = &gcc_qdss_eud_at_clk.clkr, 3452 [GCC_QDSS_STM_CLK] = &gcc_qdss_stm_clk.clkr, 3453 [GCC_QDSS_TRACECLKIN_CLK] = &gcc_qdss_traceclkin_clk.clkr, 3454 [GCC_QDSS_TSCTR_DIV8_CLK] = &gcc_qdss_tsctr_div8_clk.clkr, 3455 [GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr, 3456 [GCC_QPIC_CLK] = &gcc_qpic_clk.clkr, 3457 [GCC_QPIC_IO_MACRO_CLK] = &gcc_qpic_io_macro_clk.clkr, 3458 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, 3459 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, 3460 [GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr, 3461 [GCC_SNOC_GMAC0_AHB_CLK] = &gcc_snoc_gmac0_ahb_clk.clkr, 3462 [GCC_SNOC_GMAC0_AXI_CLK] = &gcc_snoc_gmac0_axi_clk.clkr, 3463 [GCC_SNOC_GMAC1_AHB_CLK] = &gcc_snoc_gmac1_ahb_clk.clkr, 3464 [GCC_SNOC_GMAC1_AXI_CLK] = &gcc_snoc_gmac1_axi_clk.clkr, 3465 [GCC_SNOC_LPASS_AXIM_CLK] = &gcc_snoc_lpass_axim_clk.clkr, 3466 [GCC_SNOC_LPASS_SWAY_CLK] = &gcc_snoc_lpass_sway_clk.clkr, 3467 [GCC_SNOC_UBI0_AXI_CLK] = &gcc_snoc_ubi0_axi_clk.clkr, 3468 [GCC_SYS_NOC_PCIE0_AXI_CLK] = &gcc_sys_noc_pcie0_axi_clk.clkr, 3469 [GCC_SYS_NOC_PCIE1_AXI_CLK] = &gcc_sys_noc_pcie1_axi_clk.clkr, 3470 [GCC_SYS_NOC_QDSS_STM_AXI_CLK] = &gcc_sys_noc_qdss_stm_axi_clk.clkr, 3471 [GCC_SYS_NOC_USB0_AXI_CLK] = &gcc_sys_noc_usb0_axi_clk.clkr, 3472 [GCC_SYS_NOC_WCSS_AHB_CLK] = &gcc_sys_noc_wcss_ahb_clk.clkr, 3473 [GCC_UBI0_AXI_CLK] = &gcc_ubi0_axi_clk.clkr, 3474 [GCC_UBI0_CFG_CLK] = &gcc_ubi0_cfg_clk.clkr, 3475 [GCC_UBI0_CORE_CLK] = &gcc_ubi0_core_clk.clkr, 3476 [GCC_UBI0_DBG_CLK] = &gcc_ubi0_dbg_clk.clkr, 3477 [GCC_UBI0_NC_AXI_CLK] = &gcc_ubi0_nc_axi_clk.clkr, 3478 [GCC_UBI0_UTCM_CLK] = &gcc_ubi0_utcm_clk.clkr, 3479 [GCC_UNIPHY_AHB_CLK] = &gcc_uniphy_ahb_clk.clkr, 3480 [GCC_UNIPHY_RX_CLK] = &gcc_uniphy_rx_clk.clkr, 3481 [GCC_UNIPHY_SYS_CLK] = &gcc_uniphy_sys_clk.clkr, 3482 [GCC_UNIPHY_TX_CLK] = &gcc_uniphy_tx_clk.clkr, 3483 [GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr, 3484 [GCC_USB0_EUD_AT_CLK] = &gcc_usb0_eud_at_clk.clkr, 3485 [GCC_USB0_LFPS_CLK] = &gcc_usb0_lfps_clk.clkr, 3486 [GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr, 3487 [GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr, 3488 [GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr, 3489 [GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr, 3490 [GCC_WCSS_ACMT_CLK] = &gcc_wcss_acmt_clk.clkr, 3491 [GCC_WCSS_AHB_S_CLK] = &gcc_wcss_ahb_s_clk.clkr, 3492 [GCC_WCSS_AXI_M_CLK] = &gcc_wcss_axi_m_clk.clkr, 3493 [GCC_WCSS_AXI_S_CLK] = &gcc_wcss_axi_s_clk.clkr, 3494 [GCC_WCSS_DBG_IFC_APB_BDG_CLK] = &gcc_wcss_dbg_ifc_apb_bdg_clk.clkr, 3495 [GCC_WCSS_DBG_IFC_APB_CLK] = &gcc_wcss_dbg_ifc_apb_clk.clkr, 3496 [GCC_WCSS_DBG_IFC_ATB_BDG_CLK] = &gcc_wcss_dbg_ifc_atb_bdg_clk.clkr, 3497 [GCC_WCSS_DBG_IFC_ATB_CLK] = &gcc_wcss_dbg_ifc_atb_clk.clkr, 3498 [GCC_WCSS_DBG_IFC_DAPBUS_BDG_CLK] = &gcc_wcss_dbg_ifc_dapbus_bdg_clk.clkr, 3499 [GCC_WCSS_DBG_IFC_DAPBUS_CLK] = &gcc_wcss_dbg_ifc_dapbus_clk.clkr, 3500 [GCC_WCSS_DBG_IFC_NTS_BDG_CLK] = &gcc_wcss_dbg_ifc_nts_bdg_clk.clkr, 3501 [GCC_WCSS_DBG_IFC_NTS_CLK] = &gcc_wcss_dbg_ifc_nts_clk.clkr, 3502 [GCC_WCSS_ECAHB_CLK] = &gcc_wcss_ecahb_clk.clkr, 3503 [GCC_XO_CLK] = &gcc_xo_clk.clkr, 3504 [GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr, 3505 [GMAC0_RX_CLK_SRC] = &gmac0_rx_clk_src.clkr, 3506 [GMAC0_RX_DIV_CLK_SRC] = &gmac0_rx_div_clk_src.clkr, 3507 [GMAC0_TX_CLK_SRC] = &gmac0_tx_clk_src.clkr, 3508 [GMAC0_TX_DIV_CLK_SRC] = &gmac0_tx_div_clk_src.clkr, 3509 [GMAC1_RX_CLK_SRC] = &gmac1_rx_clk_src.clkr, 3510 [GMAC1_RX_DIV_CLK_SRC] = &gmac1_rx_div_clk_src.clkr, 3511 [GMAC1_TX_CLK_SRC] = &gmac1_tx_clk_src.clkr, 3512 [GMAC1_TX_DIV_CLK_SRC] = &gmac1_tx_div_clk_src.clkr, 3513 [GMAC_CLK_SRC] = &gmac_clk_src.clkr, 3514 [GP1_CLK_SRC] = &gp1_clk_src.clkr, 3515 [GP2_CLK_SRC] = &gp2_clk_src.clkr, 3516 [GP3_CLK_SRC] = &gp3_clk_src.clkr, 3517 [LPASS_AXIM_CLK_SRC] = &lpass_axim_clk_src.clkr, 3518 [LPASS_SWAY_CLK_SRC] = &lpass_sway_clk_src.clkr, 3519 [PCIE0_AUX_CLK_SRC] = &pcie0_aux_clk_src.clkr, 3520 [PCIE0_AXI_CLK_SRC] = &pcie0_axi_clk_src.clkr, 3521 [PCIE1_AUX_CLK_SRC] = &pcie1_aux_clk_src.clkr, 3522 [PCIE1_AXI_CLK_SRC] = &pcie1_axi_clk_src.clkr, 3523 [PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr, 3524 [Q6_AXI_CLK_SRC] = &q6_axi_clk_src.clkr, 3525 [QDSS_AT_CLK_SRC] = &qdss_at_clk_src.clkr, 3526 [QDSS_STM_CLK_SRC] = &qdss_stm_clk_src.clkr, 3527 [QDSS_TSCTR_CLK_SRC] = &qdss_tsctr_clk_src.clkr, 3528 [QDSS_TRACECLKIN_CLK_SRC] = &qdss_traceclkin_clk_src.clkr, 3529 [QPIC_IO_MACRO_CLK_SRC] = &qpic_io_macro_clk_src.clkr, 3530 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr, 3531 [SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr, 3532 [UBI0_AXI_CLK_SRC] = &ubi0_axi_clk_src.clkr, 3533 [UBI0_CORE_CLK_SRC] = &ubi0_core_clk_src.clkr, 3534 [USB0_AUX_CLK_SRC] = &usb0_aux_clk_src.clkr, 3535 [USB0_LFPS_CLK_SRC] = &usb0_lfps_clk_src.clkr, 3536 [USB0_MASTER_CLK_SRC] = &usb0_master_clk_src.clkr, 3537 [USB0_MOCK_UTMI_CLK_SRC] = &usb0_mock_utmi_clk_src.clkr, 3538 [WCSS_AHB_CLK_SRC] = &wcss_ahb_clk_src.clkr, 3539 [PCIE0_PIPE_CLK_SRC] = &pcie0_pipe_clk_src.clkr, 3540 [PCIE1_PIPE_CLK_SRC] = &pcie1_pipe_clk_src.clkr, 3541 [GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr, 3542 [GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr, 3543 [USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr, 3544 [GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr, 3545 }; 3546 3547 static const struct qcom_reset_map gcc_ipq5018_resets[] = { 3548 [GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x78000, 0 }, 3549 [GCC_BLSP1_BCR] = { 0x01000, 0 }, 3550 [GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 }, 3551 [GCC_BLSP1_QUP2_BCR] = { 0x03008, 0 }, 3552 [GCC_BLSP1_QUP3_BCR] = { 0x04008, 0 }, 3553 [GCC_BLSP1_UART1_BCR] = { 0x02038, 0 }, 3554 [GCC_BLSP1_UART2_BCR] = { 0x03028, 0 }, 3555 [GCC_BOOT_ROM_BCR] = { 0x13008, 0 }, 3556 [GCC_BTSS_BCR] = { 0x1c000, 0 }, 3557 [GCC_CMN_BLK_BCR] = { 0x56300, 0 }, 3558 [GCC_CMN_LDO_BCR] = { 0x33000, 0 }, 3559 [GCC_CE_BCR] = { 0x33014, 0 }, 3560 [GCC_CRYPTO_BCR] = { 0x16000, 0 }, 3561 [GCC_DCC_BCR] = { 0x77000, 0 }, 3562 [GCC_DCD_BCR] = { 0x2a000, 0 }, 3563 [GCC_DDRSS_BCR] = { 0x1e000, 0 }, 3564 [GCC_EDPD_BCR] = { 0x3a000, 0 }, 3565 [GCC_GEPHY_BCR] = { 0x56000, 0 }, 3566 [GCC_GEPHY_MDC_SW_ARES] = { 0x56004, 0 }, 3567 [GCC_GEPHY_DSP_HW_ARES] = { 0x56004, 1 }, 3568 [GCC_GEPHY_RX_ARES] = { 0x56004, 2 }, 3569 [GCC_GEPHY_TX_ARES] = { 0x56004, 3 }, 3570 [GCC_GMAC0_BCR] = { 0x19000, 0 }, 3571 [GCC_GMAC0_CFG_ARES] = { 0x68428, 0 }, 3572 [GCC_GMAC0_SYS_ARES] = { 0x68428, 1 }, 3573 [GCC_GMAC1_BCR] = { 0x19100, 0 }, 3574 [GCC_GMAC1_CFG_ARES] = { 0x68438, 0 }, 3575 [GCC_GMAC1_SYS_ARES] = { 0x68438, 1 }, 3576 [GCC_IMEM_BCR] = { 0x0e000, 0 }, 3577 [GCC_LPASS_BCR] = { 0x2e000, 0 }, 3578 [GCC_MDIO0_BCR] = { 0x58000, 0 }, 3579 [GCC_MDIO1_BCR] = { 0x58010, 0 }, 3580 [GCC_MPM_BCR] = { 0x2c000, 0 }, 3581 [GCC_PCIE0_BCR] = { 0x75004, 0 }, 3582 [GCC_PCIE0_LINK_DOWN_BCR] = { 0x750a8, 0 }, 3583 [GCC_PCIE0_PHY_BCR] = { 0x75038, 0 }, 3584 [GCC_PCIE0PHY_PHY_BCR] = { 0x7503c, 0 }, 3585 [GCC_PCIE0_PIPE_ARES] = { 0x75040, 0 }, 3586 [GCC_PCIE0_SLEEP_ARES] = { 0x75040, 1 }, 3587 [GCC_PCIE0_CORE_STICKY_ARES] = { 0x75040, 2 }, 3588 [GCC_PCIE0_AXI_MASTER_ARES] = { 0x75040, 3 }, 3589 [GCC_PCIE0_AXI_SLAVE_ARES] = { 0x75040, 4 }, 3590 [GCC_PCIE0_AHB_ARES] = { 0x75040, 5 }, 3591 [GCC_PCIE0_AXI_MASTER_STICKY_ARES] = { 0x75040, 6 }, 3592 [GCC_PCIE0_AXI_SLAVE_STICKY_ARES] = { 0x75040, 7 }, 3593 [GCC_PCIE1_BCR] = { 0x76004, 0 }, 3594 [GCC_PCIE1_LINK_DOWN_BCR] = { 0x76044, 0 }, 3595 [GCC_PCIE1_PHY_BCR] = { 0x76038, 0 }, 3596 [GCC_PCIE1PHY_PHY_BCR] = { 0x7603c, 0 }, 3597 [GCC_PCIE1_PIPE_ARES] = { 0x76040, 0 }, 3598 [GCC_PCIE1_SLEEP_ARES] = { 0x76040, 1 }, 3599 [GCC_PCIE1_CORE_STICKY_ARES] = { 0x76040, 2 }, 3600 [GCC_PCIE1_AXI_MASTER_ARES] = { 0x76040, 3 }, 3601 [GCC_PCIE1_AXI_SLAVE_ARES] = { 0x76040, 4 }, 3602 [GCC_PCIE1_AHB_ARES] = { 0x76040, 5 }, 3603 [GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 }, 3604 [GCC_PCIE1_AXI_SLAVE_STICKY_ARES] = { 0x76040, 7 }, 3605 [GCC_PCNOC_BCR] = { 0x27018, 0 }, 3606 [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000, 0 }, 3607 [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008, 0 }, 3608 [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010, 0 }, 3609 [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018, 0 }, 3610 [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020, 0 }, 3611 [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028, 0 }, 3612 [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030, 0 }, 3613 [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038, 0 }, 3614 [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040, 0 }, 3615 [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048, 0 }, 3616 [GCC_PCNOC_BUS_TIMEOUT10_BCR] = { 0x48050, 0 }, 3617 [GCC_PCNOC_BUS_TIMEOUT11_BCR] = { 0x48058, 0 }, 3618 [GCC_PRNG_BCR] = { 0x13000, 0 }, 3619 [GCC_Q6SS_DBG_ARES] = { 0x59110, 0 }, 3620 [GCC_Q6_AHB_S_ARES] = { 0x59110, 1 }, 3621 [GCC_Q6_AHB_ARES] = { 0x59110, 2 }, 3622 [GCC_Q6_AXIM2_ARES] = { 0x59110, 3 }, 3623 [GCC_Q6_AXIM_ARES] = { 0x59110, 4 }, 3624 [GCC_Q6_AXIS_ARES] = { 0x59158, 0 }, 3625 [GCC_QDSS_BCR] = { 0x29000, 0 }, 3626 [GCC_QPIC_BCR] = { 0x57018, 0 }, 3627 [GCC_QUSB2_0_PHY_BCR] = { 0x41030, 0 }, 3628 [GCC_SDCC1_BCR] = { 0x42000, 0 }, 3629 [GCC_SEC_CTRL_BCR] = { 0x1a000, 0 }, 3630 [GCC_SPDM_BCR] = { 0x2f000, 0 }, 3631 [GCC_SYSTEM_NOC_BCR] = { 0x26000, 0 }, 3632 [GCC_TCSR_BCR] = { 0x28000, 0 }, 3633 [GCC_TLMM_BCR] = { 0x34000, 0 }, 3634 [GCC_UBI0_AXI_ARES] = { 0x680}, 3635 [GCC_UBI0_AHB_ARES] = { 0x68010, 1 }, 3636 [GCC_UBI0_NC_AXI_ARES] = { 0x68010, 2 }, 3637 [GCC_UBI0_DBG_ARES] = { 0x68010, 3 }, 3638 [GCC_UBI0_UTCM_ARES] = { 0x68010, 6 }, 3639 [GCC_UBI0_CORE_ARES] = { 0x68010, 7 }, 3640 [GCC_UBI32_BCR] = { 0x19064, 0 }, 3641 [GCC_UNIPHY_BCR] = { 0x56100, 0 }, 3642 [GCC_UNIPHY_AHB_ARES] = { 0x56104, 0 }, 3643 [GCC_UNIPHY_SYS_ARES] = { 0x56104, 1 }, 3644 [GCC_UNIPHY_RX_ARES] = { 0x56104, 4 }, 3645 [GCC_UNIPHY_TX_ARES] = { 0x56104, 5 }, 3646 [GCC_UNIPHY_SOFT_RESET] = {0x56104, 0 }, 3647 [GCC_USB0_BCR] = { 0x3e070, 0 }, 3648 [GCC_USB0_PHY_BCR] = { 0x3e034, 0 }, 3649 [GCC_WCSS_BCR] = { 0x18000, 0 }, 3650 [GCC_WCSS_DBG_ARES] = { 0x59008, 0 }, 3651 [GCC_WCSS_ECAHB_ARES] = { 0x59008, 1 }, 3652 [GCC_WCSS_ACMT_ARES] = { 0x59008, 2 }, 3653 [GCC_WCSS_DBG_BDG_ARES] = { 0x59008, 3 }, 3654 [GCC_WCSS_AHB_S_ARES] = { 0x59008, 4 }, 3655 [GCC_WCSS_AXI_M_ARES] = { 0x59008, 5 }, 3656 [GCC_WCSS_AXI_S_ARES] = { 0x59008, 6 }, 3657 [GCC_WCSS_Q6_BCR] = { 0x18004, 0 }, 3658 [GCC_WCSSAON_RESET] = { 0x59010, 0}, 3659 [GCC_GEPHY_MISC_ARES] = { 0x56004, 0 }, 3660 }; 3661 3662 static const struct of_device_id gcc_ipq5018_match_table[] = { 3663 { .compatible = "qcom,gcc-ipq5018" }, 3664 { } 3665 }; 3666 MODULE_DEVICE_TABLE(of, gcc_ipq5018_match_table); 3667 3668 static const struct regmap_config gcc_ipq5018_regmap_config = { 3669 .reg_bits = 32, 3670 .reg_stride = 4, 3671 .val_bits = 32, 3672 .max_register = 0x7fffc, 3673 .fast_io = true, 3674 }; 3675 3676 static const struct qcom_cc_desc gcc_ipq5018_desc = { 3677 .config = &gcc_ipq5018_regmap_config, 3678 .clks = gcc_ipq5018_clks, 3679 .num_clks = ARRAY_SIZE(gcc_ipq5018_clks), 3680 .resets = gcc_ipq5018_resets, 3681 .num_resets = ARRAY_SIZE(gcc_ipq5018_resets), 3682 .clk_hws = gcc_ipq5018_hws, 3683 .num_clk_hws = ARRAY_SIZE(gcc_ipq5018_hws), 3684 }; 3685 3686 static int gcc_ipq5018_probe(struct platform_device *pdev) 3687 { 3688 struct regmap *regmap; 3689 struct qcom_cc_desc ipq5018_desc = gcc_ipq5018_desc; 3690 3691 regmap = qcom_cc_map(pdev, &ipq5018_desc); 3692 if (IS_ERR(regmap)) 3693 return PTR_ERR(regmap); 3694 3695 clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config); 3696 3697 return qcom_cc_really_probe(pdev, &ipq5018_desc, regmap); 3698 } 3699 3700 static struct platform_driver gcc_ipq5018_driver = { 3701 .probe = gcc_ipq5018_probe, 3702 .driver = { 3703 .name = "qcom,gcc-ipq5018", 3704 .of_match_table = gcc_ipq5018_match_table, 3705 }, 3706 }; 3707 3708 static int __init gcc_ipq5018_init(void) 3709 { 3710 return platform_driver_register(&gcc_ipq5018_driver); 3711 } 3712 core_initcall(gcc_ipq5018_init); 3713 3714 static void __exit gcc_ipq5018_exit(void) 3715 { 3716 platform_driver_unregister(&gcc_ipq5018_driver); 3717 } 3718 module_exit(gcc_ipq5018_exit); 3719 3720 MODULE_DESCRIPTION("Qualcomm Technologies, Inc. GCC IPQ5018 Driver"); 3721 MODULE_LICENSE("GPL"); 3722