1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015 The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/err.h> 8 #include <linux/platform_device.h> 9 #include <linux/module.h> 10 #include <linux/of.h> 11 #include <linux/of_device.h> 12 #include <linux/clk-provider.h> 13 #include <linux/regmap.h> 14 #include <linux/reset-controller.h> 15 #include <linux/math64.h> 16 #include <linux/delay.h> 17 #include <linux/clk.h> 18 19 #include <dt-bindings/clock/qcom,gcc-ipq4019.h> 20 21 #include "common.h" 22 #include "clk-regmap.h" 23 #include "clk-rcg.h" 24 #include "clk-branch.h" 25 #include "reset.h" 26 #include "clk-regmap-divider.h" 27 28 #define to_clk_regmap_div(_hw) container_of(to_clk_regmap(_hw),\ 29 struct clk_regmap_div, clkr) 30 31 #define to_clk_fepll(_hw) container_of(to_clk_regmap_div(_hw),\ 32 struct clk_fepll, cdiv) 33 34 enum { 35 P_XO, 36 P_FEPLL200, 37 P_FEPLL500, 38 P_DDRPLL, 39 P_FEPLLWCSS2G, 40 P_FEPLLWCSS5G, 41 P_FEPLL125DLY, 42 P_DDRPLLAPSS, 43 }; 44 45 /* 46 * struct clk_fepll_vco - vco feedback divider corresponds for FEPLL clocks 47 * @fdbkdiv_shift: lowest bit for FDBKDIV 48 * @fdbkdiv_width: number of bits in FDBKDIV 49 * @refclkdiv_shift: lowest bit for REFCLKDIV 50 * @refclkdiv_width: number of bits in REFCLKDIV 51 * @reg: PLL_DIV register address 52 */ 53 struct clk_fepll_vco { 54 u32 fdbkdiv_shift; 55 u32 fdbkdiv_width; 56 u32 refclkdiv_shift; 57 u32 refclkdiv_width; 58 u32 reg; 59 }; 60 61 /* 62 * struct clk_fepll - clk divider corresponds to FEPLL clocks 63 * @fixed_div: fixed divider value if divider is fixed 64 * @parent_map: map from software's parent index to hardware's src_sel field 65 * @cdiv: divider values for PLL_DIV 66 * @pll_vco: vco feedback divider 67 * @div_table: mapping for actual divider value to register divider value 68 * in case of non fixed divider 69 * @freq_tbl: frequency table 70 */ 71 struct clk_fepll { 72 u32 fixed_div; 73 const u8 *parent_map; 74 struct clk_regmap_div cdiv; 75 const struct clk_fepll_vco *pll_vco; 76 const struct clk_div_table *div_table; 77 const struct freq_tbl *freq_tbl; 78 }; 79 80 /* 81 * Contains index for safe clock during APSS freq change. 82 * fepll500 is being used as safe clock so initialize it 83 * with its index in parents list gcc_xo_ddr_500_200. 84 */ 85 static const int gcc_ipq4019_cpu_safe_parent = 2; 86 87 /* Calculates the VCO rate for FEPLL. */ 88 static u64 clk_fepll_vco_calc_rate(struct clk_fepll *pll_div, 89 unsigned long parent_rate) 90 { 91 const struct clk_fepll_vco *pll_vco = pll_div->pll_vco; 92 u32 fdbkdiv, refclkdiv, cdiv; 93 u64 vco; 94 95 regmap_read(pll_div->cdiv.clkr.regmap, pll_vco->reg, &cdiv); 96 refclkdiv = (cdiv >> pll_vco->refclkdiv_shift) & 97 (BIT(pll_vco->refclkdiv_width) - 1); 98 fdbkdiv = (cdiv >> pll_vco->fdbkdiv_shift) & 99 (BIT(pll_vco->fdbkdiv_width) - 1); 100 101 vco = parent_rate / refclkdiv; 102 vco *= 2; 103 vco *= fdbkdiv; 104 105 return vco; 106 } 107 108 static const struct clk_fepll_vco gcc_apss_ddrpll_vco = { 109 .fdbkdiv_shift = 16, 110 .fdbkdiv_width = 8, 111 .refclkdiv_shift = 24, 112 .refclkdiv_width = 5, 113 .reg = 0x2e020, 114 }; 115 116 static const struct clk_fepll_vco gcc_fepll_vco = { 117 .fdbkdiv_shift = 16, 118 .fdbkdiv_width = 8, 119 .refclkdiv_shift = 24, 120 .refclkdiv_width = 5, 121 .reg = 0x2f020, 122 }; 123 124 /* 125 * Round rate function for APSS CPU PLL Clock divider. 126 * It looks up the frequency table and returns the next higher frequency 127 * supported in hardware. 128 */ 129 static long clk_cpu_div_round_rate(struct clk_hw *hw, unsigned long rate, 130 unsigned long *p_rate) 131 { 132 struct clk_fepll *pll = to_clk_fepll(hw); 133 struct clk_hw *p_hw; 134 const struct freq_tbl *f; 135 136 f = qcom_find_freq(pll->freq_tbl, rate); 137 if (!f) 138 return -EINVAL; 139 140 p_hw = clk_hw_get_parent_by_index(hw, f->src); 141 *p_rate = clk_hw_get_rate(p_hw); 142 143 return f->freq; 144 }; 145 146 /* 147 * Clock set rate function for APSS CPU PLL Clock divider. 148 * It looks up the frequency table and updates the PLL divider to corresponding 149 * divider value. 150 */ 151 static int clk_cpu_div_set_rate(struct clk_hw *hw, unsigned long rate, 152 unsigned long parent_rate) 153 { 154 struct clk_fepll *pll = to_clk_fepll(hw); 155 const struct freq_tbl *f; 156 u32 mask; 157 158 f = qcom_find_freq(pll->freq_tbl, rate); 159 if (!f) 160 return -EINVAL; 161 162 mask = (BIT(pll->cdiv.width) - 1) << pll->cdiv.shift; 163 regmap_update_bits(pll->cdiv.clkr.regmap, 164 pll->cdiv.reg, mask, 165 f->pre_div << pll->cdiv.shift); 166 /* 167 * There is no status bit which can be checked for successful CPU 168 * divider update operation so using delay for the same. 169 */ 170 udelay(1); 171 172 return 0; 173 }; 174 175 /* 176 * Clock frequency calculation function for APSS CPU PLL Clock divider. 177 * This clock divider is nonlinear so this function calculates the actual 178 * divider and returns the output frequency by dividing VCO Frequency 179 * with this actual divider value. 180 */ 181 static unsigned long 182 clk_cpu_div_recalc_rate(struct clk_hw *hw, 183 unsigned long parent_rate) 184 { 185 struct clk_fepll *pll = to_clk_fepll(hw); 186 u32 cdiv, pre_div; 187 u64 rate; 188 189 regmap_read(pll->cdiv.clkr.regmap, pll->cdiv.reg, &cdiv); 190 cdiv = (cdiv >> pll->cdiv.shift) & (BIT(pll->cdiv.width) - 1); 191 192 /* 193 * Some dividers have value in 0.5 fraction so multiply both VCO 194 * frequency(parent_rate) and pre_div with 2 to make integer 195 * calculation. 196 */ 197 if (cdiv > 10) 198 pre_div = (cdiv + 1) * 2; 199 else 200 pre_div = cdiv + 12; 201 202 rate = clk_fepll_vco_calc_rate(pll, parent_rate) * 2; 203 do_div(rate, pre_div); 204 205 return rate; 206 }; 207 208 static const struct clk_ops clk_regmap_cpu_div_ops = { 209 .round_rate = clk_cpu_div_round_rate, 210 .set_rate = clk_cpu_div_set_rate, 211 .recalc_rate = clk_cpu_div_recalc_rate, 212 }; 213 214 static const struct freq_tbl ftbl_apss_ddr_pll[] = { 215 { 384000000, P_XO, 0xd, 0, 0 }, 216 { 413000000, P_XO, 0xc, 0, 0 }, 217 { 448000000, P_XO, 0xb, 0, 0 }, 218 { 488000000, P_XO, 0xa, 0, 0 }, 219 { 512000000, P_XO, 0x9, 0, 0 }, 220 { 537000000, P_XO, 0x8, 0, 0 }, 221 { 565000000, P_XO, 0x7, 0, 0 }, 222 { 597000000, P_XO, 0x6, 0, 0 }, 223 { 632000000, P_XO, 0x5, 0, 0 }, 224 { 672000000, P_XO, 0x4, 0, 0 }, 225 { 716000000, P_XO, 0x3, 0, 0 }, 226 { 768000000, P_XO, 0x2, 0, 0 }, 227 { 823000000, P_XO, 0x1, 0, 0 }, 228 { 896000000, P_XO, 0x0, 0, 0 }, 229 { } 230 }; 231 232 static struct clk_fepll gcc_apss_cpu_plldiv_clk = { 233 .cdiv.reg = 0x2e020, 234 .cdiv.shift = 4, 235 .cdiv.width = 4, 236 .cdiv.clkr = { 237 .enable_reg = 0x2e000, 238 .enable_mask = BIT(0), 239 .hw.init = &(struct clk_init_data){ 240 .name = "ddrpllapss", 241 .parent_data = &(const struct clk_parent_data){ 242 .fw_name = "xo", 243 .name = "xo", 244 }, 245 .num_parents = 1, 246 .ops = &clk_regmap_cpu_div_ops, 247 }, 248 }, 249 .freq_tbl = ftbl_apss_ddr_pll, 250 .pll_vco = &gcc_apss_ddrpll_vco, 251 }; 252 253 /* Calculates the rate for PLL divider. 254 * If the divider value is not fixed then it gets the actual divider value 255 * from divider table. Then, it calculate the clock rate by dividing the 256 * parent rate with actual divider value. 257 */ 258 static unsigned long 259 clk_regmap_clk_div_recalc_rate(struct clk_hw *hw, 260 unsigned long parent_rate) 261 { 262 struct clk_fepll *pll = to_clk_fepll(hw); 263 u32 cdiv, pre_div = 1; 264 u64 rate; 265 const struct clk_div_table *clkt; 266 267 if (pll->fixed_div) { 268 pre_div = pll->fixed_div; 269 } else { 270 regmap_read(pll->cdiv.clkr.regmap, pll->cdiv.reg, &cdiv); 271 cdiv = (cdiv >> pll->cdiv.shift) & (BIT(pll->cdiv.width) - 1); 272 273 for (clkt = pll->div_table; clkt->div; clkt++) { 274 if (clkt->val == cdiv) 275 pre_div = clkt->div; 276 } 277 } 278 279 rate = clk_fepll_vco_calc_rate(pll, parent_rate); 280 do_div(rate, pre_div); 281 282 return rate; 283 }; 284 285 static const struct clk_ops clk_fepll_div_ops = { 286 .recalc_rate = clk_regmap_clk_div_recalc_rate, 287 }; 288 289 static struct clk_fepll gcc_apss_sdcc_clk = { 290 .fixed_div = 28, 291 .cdiv.clkr = { 292 .hw.init = &(struct clk_init_data){ 293 .name = "ddrpllsdcc", 294 .parent_data = &(const struct clk_parent_data){ 295 .fw_name = "xo", 296 .name = "xo", 297 }, 298 .num_parents = 1, 299 .ops = &clk_fepll_div_ops, 300 }, 301 }, 302 .pll_vco = &gcc_apss_ddrpll_vco, 303 }; 304 305 static struct clk_fepll gcc_fepll125_clk = { 306 .fixed_div = 32, 307 .cdiv.clkr = { 308 .hw.init = &(struct clk_init_data){ 309 .name = "fepll125", 310 .parent_data = &(const struct clk_parent_data){ 311 .fw_name = "xo", 312 .name = "xo", 313 }, 314 .num_parents = 1, 315 .ops = &clk_fepll_div_ops, 316 }, 317 }, 318 .pll_vco = &gcc_fepll_vco, 319 }; 320 321 static struct clk_fepll gcc_fepll125dly_clk = { 322 .fixed_div = 32, 323 .cdiv.clkr = { 324 .hw.init = &(struct clk_init_data){ 325 .name = "fepll125dly", 326 .parent_data = &(const struct clk_parent_data){ 327 .fw_name = "xo", 328 .name = "xo", 329 }, 330 .num_parents = 1, 331 .ops = &clk_fepll_div_ops, 332 }, 333 }, 334 .pll_vco = &gcc_fepll_vco, 335 }; 336 337 static struct clk_fepll gcc_fepll200_clk = { 338 .fixed_div = 20, 339 .cdiv.clkr = { 340 .hw.init = &(struct clk_init_data){ 341 .name = "fepll200", 342 .parent_data = &(const struct clk_parent_data){ 343 .fw_name = "xo", 344 .name = "xo", 345 }, 346 .num_parents = 1, 347 .ops = &clk_fepll_div_ops, 348 }, 349 }, 350 .pll_vco = &gcc_fepll_vco, 351 }; 352 353 static struct clk_fepll gcc_fepll500_clk = { 354 .fixed_div = 8, 355 .cdiv.clkr = { 356 .hw.init = &(struct clk_init_data){ 357 .name = "fepll500", 358 .parent_data = &(const struct clk_parent_data){ 359 .fw_name = "xo", 360 .name = "xo", 361 }, 362 .num_parents = 1, 363 .ops = &clk_fepll_div_ops, 364 }, 365 }, 366 .pll_vco = &gcc_fepll_vco, 367 }; 368 369 static const struct clk_div_table fepllwcss_clk_div_table[] = { 370 { 0, 15 }, 371 { 1, 16 }, 372 { 2, 18 }, 373 { 3, 20 }, 374 { }, 375 }; 376 377 static struct clk_fepll gcc_fepllwcss2g_clk = { 378 .cdiv.reg = 0x2f020, 379 .cdiv.shift = 8, 380 .cdiv.width = 2, 381 .cdiv.clkr = { 382 .hw.init = &(struct clk_init_data){ 383 .name = "fepllwcss2g", 384 .parent_data = &(const struct clk_parent_data){ 385 .fw_name = "xo", 386 .name = "xo", 387 }, 388 .num_parents = 1, 389 .ops = &clk_fepll_div_ops, 390 }, 391 }, 392 .div_table = fepllwcss_clk_div_table, 393 .pll_vco = &gcc_fepll_vco, 394 }; 395 396 static struct clk_fepll gcc_fepllwcss5g_clk = { 397 .cdiv.reg = 0x2f020, 398 .cdiv.shift = 12, 399 .cdiv.width = 2, 400 .cdiv.clkr = { 401 .hw.init = &(struct clk_init_data){ 402 .name = "fepllwcss5g", 403 .parent_data = &(const struct clk_parent_data){ 404 .fw_name = "xo", 405 .name = "xo", 406 }, 407 .num_parents = 1, 408 .ops = &clk_fepll_div_ops, 409 }, 410 }, 411 .div_table = fepllwcss_clk_div_table, 412 .pll_vco = &gcc_fepll_vco, 413 }; 414 415 static struct parent_map gcc_xo_200_500_map[] = { 416 { P_XO, 0 }, 417 { P_FEPLL200, 1 }, 418 { P_FEPLL500, 2 }, 419 }; 420 421 static const struct clk_parent_data gcc_xo_200_500[] = { 422 { .fw_name = "xo", .name = "xo" }, 423 { .hw = &gcc_fepll200_clk.cdiv.clkr.hw }, 424 { .hw = &gcc_fepll500_clk.cdiv.clkr.hw }, 425 }; 426 427 static const struct freq_tbl ftbl_gcc_pcnoc_ahb_clk[] = { 428 F(48000000, P_XO, 1, 0, 0), 429 F(100000000, P_FEPLL200, 2, 0, 0), 430 { } 431 }; 432 433 static struct clk_rcg2 gcc_pcnoc_ahb_clk_src = { 434 .cmd_rcgr = 0x21024, 435 .hid_width = 5, 436 .parent_map = gcc_xo_200_500_map, 437 .freq_tbl = ftbl_gcc_pcnoc_ahb_clk, 438 .clkr.hw.init = &(struct clk_init_data){ 439 .name = "gcc_pcnoc_ahb_clk_src", 440 .parent_data = gcc_xo_200_500, 441 .num_parents = ARRAY_SIZE(gcc_xo_200_500), 442 .ops = &clk_rcg2_ops, 443 }, 444 }; 445 446 static struct clk_branch pcnoc_clk_src = { 447 .halt_reg = 0x21030, 448 .clkr = { 449 .enable_reg = 0x21030, 450 .enable_mask = BIT(0), 451 .hw.init = &(struct clk_init_data){ 452 .name = "pcnoc_clk_src", 453 .parent_hws = (const struct clk_hw *[]){ 454 &gcc_pcnoc_ahb_clk_src.clkr.hw }, 455 .num_parents = 1, 456 .ops = &clk_branch2_ops, 457 .flags = CLK_SET_RATE_PARENT | 458 CLK_IS_CRITICAL, 459 }, 460 }, 461 }; 462 463 static struct parent_map gcc_xo_200_map[] = { 464 { P_XO, 0 }, 465 { P_FEPLL200, 1 }, 466 }; 467 468 static const struct clk_parent_data gcc_xo_200[] = { 469 { .fw_name = "xo", .name = "xo" }, 470 { .hw = &gcc_fepll200_clk.cdiv.clkr.hw }, 471 }; 472 473 static const struct freq_tbl ftbl_gcc_audio_pwm_clk[] = { 474 F(48000000, P_XO, 1, 0, 0), 475 F(200000000, P_FEPLL200, 1, 0, 0), 476 { } 477 }; 478 479 static struct clk_rcg2 audio_clk_src = { 480 .cmd_rcgr = 0x1b000, 481 .hid_width = 5, 482 .parent_map = gcc_xo_200_map, 483 .freq_tbl = ftbl_gcc_audio_pwm_clk, 484 .clkr.hw.init = &(struct clk_init_data){ 485 .name = "audio_clk_src", 486 .parent_data = gcc_xo_200, 487 .num_parents = ARRAY_SIZE(gcc_xo_200), 488 .ops = &clk_rcg2_ops, 489 490 }, 491 }; 492 493 static struct clk_branch gcc_audio_ahb_clk = { 494 .halt_reg = 0x1b010, 495 .clkr = { 496 .enable_reg = 0x1b010, 497 .enable_mask = BIT(0), 498 .hw.init = &(struct clk_init_data){ 499 .name = "gcc_audio_ahb_clk", 500 .parent_hws = (const struct clk_hw *[]){ 501 &pcnoc_clk_src.clkr.hw }, 502 .flags = CLK_SET_RATE_PARENT, 503 .num_parents = 1, 504 .ops = &clk_branch2_ops, 505 }, 506 }, 507 }; 508 509 static struct clk_branch gcc_audio_pwm_clk = { 510 .halt_reg = 0x1b00C, 511 .clkr = { 512 .enable_reg = 0x1b00C, 513 .enable_mask = BIT(0), 514 .hw.init = &(struct clk_init_data){ 515 .name = "gcc_audio_pwm_clk", 516 .parent_hws = (const struct clk_hw *[]){ 517 &audio_clk_src.clkr.hw }, 518 .flags = CLK_SET_RATE_PARENT, 519 .num_parents = 1, 520 .ops = &clk_branch2_ops, 521 }, 522 }, 523 }; 524 525 static const struct freq_tbl ftbl_gcc_blsp1_qup1_2_i2c_apps_clk[] = { 526 F(19050000, P_FEPLL200, 10.5, 1, 1), 527 { } 528 }; 529 530 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { 531 .cmd_rcgr = 0x200c, 532 .hid_width = 5, 533 .parent_map = gcc_xo_200_map, 534 .freq_tbl = ftbl_gcc_blsp1_qup1_2_i2c_apps_clk, 535 .clkr.hw.init = &(struct clk_init_data){ 536 .name = "blsp1_qup1_i2c_apps_clk_src", 537 .parent_data = gcc_xo_200, 538 .num_parents = ARRAY_SIZE(gcc_xo_200), 539 .ops = &clk_rcg2_ops, 540 }, 541 }; 542 543 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { 544 .halt_reg = 0x2008, 545 .clkr = { 546 .enable_reg = 0x2008, 547 .enable_mask = BIT(0), 548 .hw.init = &(struct clk_init_data){ 549 .name = "gcc_blsp1_qup1_i2c_apps_clk", 550 .parent_hws = (const struct clk_hw *[]){ 551 &blsp1_qup1_i2c_apps_clk_src.clkr.hw }, 552 .num_parents = 1, 553 .ops = &clk_branch2_ops, 554 .flags = CLK_SET_RATE_PARENT, 555 }, 556 }, 557 }; 558 559 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { 560 .cmd_rcgr = 0x3000, 561 .hid_width = 5, 562 .parent_map = gcc_xo_200_map, 563 .freq_tbl = ftbl_gcc_blsp1_qup1_2_i2c_apps_clk, 564 .clkr.hw.init = &(struct clk_init_data){ 565 .name = "blsp1_qup2_i2c_apps_clk_src", 566 .parent_data = gcc_xo_200, 567 .num_parents = ARRAY_SIZE(gcc_xo_200), 568 .ops = &clk_rcg2_ops, 569 }, 570 }; 571 572 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { 573 .halt_reg = 0x3010, 574 .clkr = { 575 .enable_reg = 0x3010, 576 .enable_mask = BIT(0), 577 .hw.init = &(struct clk_init_data){ 578 .name = "gcc_blsp1_qup2_i2c_apps_clk", 579 .parent_hws = (const struct clk_hw *[]){ 580 &blsp1_qup2_i2c_apps_clk_src.clkr.hw }, 581 .num_parents = 1, 582 .ops = &clk_branch2_ops, 583 .flags = CLK_SET_RATE_PARENT, 584 }, 585 }, 586 }; 587 588 static struct parent_map gcc_xo_200_spi_map[] = { 589 { P_XO, 0 }, 590 { P_FEPLL200, 2 }, 591 }; 592 593 static const struct clk_parent_data gcc_xo_200_spi[] = { 594 { .fw_name = "xo", .name = "xo" }, 595 { .hw = &gcc_fepll200_clk.cdiv.clkr.hw }, 596 }; 597 598 static const struct freq_tbl ftbl_gcc_blsp1_qup1_2_spi_apps_clk[] = { 599 F(960000, P_XO, 12, 1, 4), 600 F(4800000, P_XO, 1, 1, 10), 601 F(9600000, P_XO, 1, 1, 5), 602 F(15000000, P_XO, 1, 1, 3), 603 F(19200000, P_XO, 1, 2, 5), 604 F(24000000, P_XO, 1, 1, 2), 605 F(48000000, P_XO, 1, 0, 0), 606 { } 607 }; 608 609 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { 610 .cmd_rcgr = 0x2024, 611 .mnd_width = 8, 612 .hid_width = 5, 613 .parent_map = gcc_xo_200_spi_map, 614 .freq_tbl = ftbl_gcc_blsp1_qup1_2_spi_apps_clk, 615 .clkr.hw.init = &(struct clk_init_data){ 616 .name = "blsp1_qup1_spi_apps_clk_src", 617 .parent_data = gcc_xo_200_spi, 618 .num_parents = ARRAY_SIZE(gcc_xo_200_spi), 619 .ops = &clk_rcg2_ops, 620 }, 621 }; 622 623 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { 624 .halt_reg = 0x2004, 625 .clkr = { 626 .enable_reg = 0x2004, 627 .enable_mask = BIT(0), 628 .hw.init = &(struct clk_init_data){ 629 .name = "gcc_blsp1_qup1_spi_apps_clk", 630 .parent_hws = (const struct clk_hw *[]){ 631 &blsp1_qup1_spi_apps_clk_src.clkr.hw }, 632 .num_parents = 1, 633 .ops = &clk_branch2_ops, 634 .flags = CLK_SET_RATE_PARENT, 635 }, 636 }, 637 }; 638 639 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { 640 .cmd_rcgr = 0x3014, 641 .mnd_width = 8, 642 .hid_width = 5, 643 .freq_tbl = ftbl_gcc_blsp1_qup1_2_spi_apps_clk, 644 .parent_map = gcc_xo_200_spi_map, 645 .clkr.hw.init = &(struct clk_init_data){ 646 .name = "blsp1_qup2_spi_apps_clk_src", 647 .parent_data = gcc_xo_200_spi, 648 .num_parents = ARRAY_SIZE(gcc_xo_200_spi), 649 .ops = &clk_rcg2_ops, 650 }, 651 }; 652 653 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { 654 .halt_reg = 0x300c, 655 .clkr = { 656 .enable_reg = 0x300c, 657 .enable_mask = BIT(0), 658 .hw.init = &(struct clk_init_data){ 659 .name = "gcc_blsp1_qup2_spi_apps_clk", 660 .parent_hws = (const struct clk_hw *[]){ 661 &blsp1_qup2_spi_apps_clk_src.clkr.hw }, 662 .num_parents = 1, 663 .ops = &clk_branch2_ops, 664 .flags = CLK_SET_RATE_PARENT, 665 }, 666 }, 667 }; 668 669 static const struct freq_tbl ftbl_gcc_blsp1_uart1_2_apps_clk[] = { 670 F(1843200, P_FEPLL200, 1, 144, 15625), 671 F(3686400, P_FEPLL200, 1, 288, 15625), 672 F(7372800, P_FEPLL200, 1, 576, 15625), 673 F(14745600, P_FEPLL200, 1, 1152, 15625), 674 F(16000000, P_FEPLL200, 1, 2, 25), 675 F(24000000, P_XO, 1, 1, 2), 676 F(32000000, P_FEPLL200, 1, 4, 25), 677 F(40000000, P_FEPLL200, 1, 1, 5), 678 F(46400000, P_FEPLL200, 1, 29, 125), 679 F(48000000, P_XO, 1, 0, 0), 680 { } 681 }; 682 683 static struct clk_rcg2 blsp1_uart1_apps_clk_src = { 684 .cmd_rcgr = 0x2044, 685 .mnd_width = 16, 686 .hid_width = 5, 687 .freq_tbl = ftbl_gcc_blsp1_uart1_2_apps_clk, 688 .parent_map = gcc_xo_200_spi_map, 689 .clkr.hw.init = &(struct clk_init_data){ 690 .name = "blsp1_uart1_apps_clk_src", 691 .parent_data = gcc_xo_200_spi, 692 .num_parents = ARRAY_SIZE(gcc_xo_200_spi), 693 .ops = &clk_rcg2_ops, 694 }, 695 }; 696 697 static struct clk_branch gcc_blsp1_uart1_apps_clk = { 698 .halt_reg = 0x203c, 699 .clkr = { 700 .enable_reg = 0x203c, 701 .enable_mask = BIT(0), 702 .hw.init = &(struct clk_init_data){ 703 .name = "gcc_blsp1_uart1_apps_clk", 704 .parent_hws = (const struct clk_hw *[]){ 705 &blsp1_uart1_apps_clk_src.clkr.hw }, 706 .flags = CLK_SET_RATE_PARENT, 707 .num_parents = 1, 708 .ops = &clk_branch2_ops, 709 }, 710 }, 711 }; 712 713 static struct clk_rcg2 blsp1_uart2_apps_clk_src = { 714 .cmd_rcgr = 0x3034, 715 .mnd_width = 16, 716 .hid_width = 5, 717 .freq_tbl = ftbl_gcc_blsp1_uart1_2_apps_clk, 718 .parent_map = gcc_xo_200_spi_map, 719 .clkr.hw.init = &(struct clk_init_data){ 720 .name = "blsp1_uart2_apps_clk_src", 721 .parent_data = gcc_xo_200_spi, 722 .num_parents = ARRAY_SIZE(gcc_xo_200_spi), 723 .ops = &clk_rcg2_ops, 724 }, 725 }; 726 727 static struct clk_branch gcc_blsp1_uart2_apps_clk = { 728 .halt_reg = 0x302c, 729 .clkr = { 730 .enable_reg = 0x302c, 731 .enable_mask = BIT(0), 732 .hw.init = &(struct clk_init_data){ 733 .name = "gcc_blsp1_uart2_apps_clk", 734 .parent_hws = (const struct clk_hw *[]){ 735 &blsp1_uart2_apps_clk_src.clkr.hw }, 736 .num_parents = 1, 737 .ops = &clk_branch2_ops, 738 .flags = CLK_SET_RATE_PARENT, 739 }, 740 }, 741 }; 742 743 static const struct freq_tbl ftbl_gcc_gp_clk[] = { 744 F(1250000, P_FEPLL200, 1, 16, 0), 745 F(2500000, P_FEPLL200, 1, 8, 0), 746 F(5000000, P_FEPLL200, 1, 4, 0), 747 { } 748 }; 749 750 static struct clk_rcg2 gp1_clk_src = { 751 .cmd_rcgr = 0x8004, 752 .mnd_width = 8, 753 .hid_width = 5, 754 .freq_tbl = ftbl_gcc_gp_clk, 755 .parent_map = gcc_xo_200_map, 756 .clkr.hw.init = &(struct clk_init_data){ 757 .name = "gp1_clk_src", 758 .parent_data = gcc_xo_200, 759 .num_parents = ARRAY_SIZE(gcc_xo_200), 760 .ops = &clk_rcg2_ops, 761 }, 762 }; 763 764 static struct clk_branch gcc_gp1_clk = { 765 .halt_reg = 0x8000, 766 .clkr = { 767 .enable_reg = 0x8000, 768 .enable_mask = BIT(0), 769 .hw.init = &(struct clk_init_data){ 770 .name = "gcc_gp1_clk", 771 .parent_hws = (const struct clk_hw *[]){ 772 &gp1_clk_src.clkr.hw }, 773 .num_parents = 1, 774 .ops = &clk_branch2_ops, 775 .flags = CLK_SET_RATE_PARENT, 776 }, 777 }, 778 }; 779 780 static struct clk_rcg2 gp2_clk_src = { 781 .cmd_rcgr = 0x9004, 782 .mnd_width = 8, 783 .hid_width = 5, 784 .freq_tbl = ftbl_gcc_gp_clk, 785 .parent_map = gcc_xo_200_map, 786 .clkr.hw.init = &(struct clk_init_data){ 787 .name = "gp2_clk_src", 788 .parent_data = gcc_xo_200, 789 .num_parents = ARRAY_SIZE(gcc_xo_200), 790 .ops = &clk_rcg2_ops, 791 }, 792 }; 793 794 static struct clk_branch gcc_gp2_clk = { 795 .halt_reg = 0x9000, 796 .clkr = { 797 .enable_reg = 0x9000, 798 .enable_mask = BIT(0), 799 .hw.init = &(struct clk_init_data){ 800 .name = "gcc_gp2_clk", 801 .parent_hws = (const struct clk_hw *[]){ 802 &gp2_clk_src.clkr.hw }, 803 .num_parents = 1, 804 .ops = &clk_branch2_ops, 805 .flags = CLK_SET_RATE_PARENT, 806 }, 807 }, 808 }; 809 810 static struct clk_rcg2 gp3_clk_src = { 811 .cmd_rcgr = 0xa004, 812 .mnd_width = 8, 813 .hid_width = 5, 814 .freq_tbl = ftbl_gcc_gp_clk, 815 .parent_map = gcc_xo_200_map, 816 .clkr.hw.init = &(struct clk_init_data){ 817 .name = "gp3_clk_src", 818 .parent_data = gcc_xo_200, 819 .num_parents = ARRAY_SIZE(gcc_xo_200), 820 .ops = &clk_rcg2_ops, 821 }, 822 }; 823 824 static struct clk_branch gcc_gp3_clk = { 825 .halt_reg = 0xa000, 826 .clkr = { 827 .enable_reg = 0xa000, 828 .enable_mask = BIT(0), 829 .hw.init = &(struct clk_init_data){ 830 .name = "gcc_gp3_clk", 831 .parent_hws = (const struct clk_hw *[]){ 832 &gp3_clk_src.clkr.hw }, 833 .num_parents = 1, 834 .ops = &clk_branch2_ops, 835 .flags = CLK_SET_RATE_PARENT, 836 }, 837 }, 838 }; 839 840 static struct parent_map gcc_xo_sdcc1_500_map[] = { 841 { P_XO, 0 }, 842 { P_DDRPLL, 1 }, 843 { P_FEPLL500, 2 }, 844 }; 845 846 static const struct clk_parent_data gcc_xo_sdcc1_500[] = { 847 { .fw_name = "xo", .name = "xo" }, 848 { .hw = &gcc_apss_sdcc_clk.cdiv.clkr.hw }, 849 { .hw = &gcc_fepll500_clk.cdiv.clkr.hw }, 850 }; 851 852 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk[] = { 853 F(144000, P_XO, 1, 3, 240), 854 F(400000, P_XO, 1, 1, 0), 855 F(20000000, P_FEPLL500, 1, 1, 25), 856 F(25000000, P_FEPLL500, 1, 1, 20), 857 F(50000000, P_FEPLL500, 1, 1, 10), 858 F(100000000, P_FEPLL500, 1, 1, 5), 859 F(192000000, P_DDRPLL, 1, 0, 0), 860 { } 861 }; 862 863 static struct clk_rcg2 sdcc1_apps_clk_src = { 864 .cmd_rcgr = 0x18004, 865 .hid_width = 5, 866 .freq_tbl = ftbl_gcc_sdcc1_apps_clk, 867 .parent_map = gcc_xo_sdcc1_500_map, 868 .clkr.hw.init = &(struct clk_init_data){ 869 .name = "sdcc1_apps_clk_src", 870 .parent_data = gcc_xo_sdcc1_500, 871 .num_parents = ARRAY_SIZE(gcc_xo_sdcc1_500), 872 .ops = &clk_rcg2_ops, 873 .flags = CLK_SET_RATE_PARENT, 874 }, 875 }; 876 877 static const struct freq_tbl ftbl_gcc_apps_clk[] = { 878 F(48000000, P_XO, 1, 0, 0), 879 F(200000000, P_FEPLL200, 1, 0, 0), 880 F(384000000, P_DDRPLLAPSS, 1, 0, 0), 881 F(413000000, P_DDRPLLAPSS, 1, 0, 0), 882 F(448000000, P_DDRPLLAPSS, 1, 0, 0), 883 F(488000000, P_DDRPLLAPSS, 1, 0, 0), 884 F(500000000, P_FEPLL500, 1, 0, 0), 885 F(512000000, P_DDRPLLAPSS, 1, 0, 0), 886 F(537000000, P_DDRPLLAPSS, 1, 0, 0), 887 F(565000000, P_DDRPLLAPSS, 1, 0, 0), 888 F(597000000, P_DDRPLLAPSS, 1, 0, 0), 889 F(632000000, P_DDRPLLAPSS, 1, 0, 0), 890 F(672000000, P_DDRPLLAPSS, 1, 0, 0), 891 F(716000000, P_DDRPLLAPSS, 1, 0, 0), 892 { } 893 }; 894 895 static struct parent_map gcc_xo_ddr_500_200_map[] = { 896 { P_XO, 0 }, 897 { P_FEPLL200, 3 }, 898 { P_FEPLL500, 2 }, 899 { P_DDRPLLAPSS, 1 }, 900 }; 901 902 static const struct clk_parent_data gcc_xo_ddr_500_200[] = { 903 { .fw_name = "xo", .name = "xo" }, 904 { .hw = &gcc_fepll200_clk.cdiv.clkr.hw }, 905 { .hw = &gcc_fepll500_clk.cdiv.clkr.hw }, 906 { .hw = &gcc_apss_cpu_plldiv_clk.cdiv.clkr.hw }, 907 }; 908 909 static struct clk_rcg2 apps_clk_src = { 910 .cmd_rcgr = 0x1900c, 911 .hid_width = 5, 912 .freq_tbl = ftbl_gcc_apps_clk, 913 .parent_map = gcc_xo_ddr_500_200_map, 914 .clkr.hw.init = &(struct clk_init_data){ 915 .name = "apps_clk_src", 916 .parent_data = gcc_xo_ddr_500_200, 917 .num_parents = ARRAY_SIZE(gcc_xo_ddr_500_200), 918 .ops = &clk_rcg2_ops, 919 .flags = CLK_SET_RATE_PARENT, 920 }, 921 }; 922 923 static const struct freq_tbl ftbl_gcc_apps_ahb_clk[] = { 924 F(48000000, P_XO, 1, 0, 0), 925 F(100000000, P_FEPLL200, 2, 0, 0), 926 { } 927 }; 928 929 static struct clk_rcg2 apps_ahb_clk_src = { 930 .cmd_rcgr = 0x19014, 931 .hid_width = 5, 932 .parent_map = gcc_xo_200_500_map, 933 .freq_tbl = ftbl_gcc_apps_ahb_clk, 934 .clkr.hw.init = &(struct clk_init_data){ 935 .name = "apps_ahb_clk_src", 936 .parent_data = gcc_xo_200_500, 937 .num_parents = ARRAY_SIZE(gcc_xo_200_500), 938 .ops = &clk_rcg2_ops, 939 }, 940 }; 941 942 static struct clk_branch gcc_apss_ahb_clk = { 943 .halt_reg = 0x19004, 944 .halt_check = BRANCH_HALT_VOTED, 945 .clkr = { 946 .enable_reg = 0x6000, 947 .enable_mask = BIT(14), 948 .hw.init = &(struct clk_init_data){ 949 .name = "gcc_apss_ahb_clk", 950 .parent_hws = (const struct clk_hw *[]){ 951 &apps_ahb_clk_src.clkr.hw }, 952 .num_parents = 1, 953 .ops = &clk_branch2_ops, 954 .flags = CLK_SET_RATE_PARENT, 955 }, 956 }, 957 }; 958 959 static struct clk_branch gcc_blsp1_ahb_clk = { 960 .halt_reg = 0x1008, 961 .halt_check = BRANCH_HALT_VOTED, 962 .clkr = { 963 .enable_reg = 0x6000, 964 .enable_mask = BIT(10), 965 .hw.init = &(struct clk_init_data){ 966 .name = "gcc_blsp1_ahb_clk", 967 .parent_hws = (const struct clk_hw *[]){ 968 &pcnoc_clk_src.clkr.hw }, 969 .num_parents = 1, 970 .ops = &clk_branch2_ops, 971 }, 972 }, 973 }; 974 975 static struct clk_branch gcc_dcd_xo_clk = { 976 .halt_reg = 0x2103c, 977 .clkr = { 978 .enable_reg = 0x2103c, 979 .enable_mask = BIT(0), 980 .hw.init = &(struct clk_init_data){ 981 .name = "gcc_dcd_xo_clk", 982 .parent_data = &(const struct clk_parent_data){ 983 .fw_name = "xo", 984 .name = "xo", 985 }, 986 .num_parents = 1, 987 .ops = &clk_branch2_ops, 988 }, 989 }, 990 }; 991 992 static struct clk_branch gcc_boot_rom_ahb_clk = { 993 .halt_reg = 0x1300c, 994 .clkr = { 995 .enable_reg = 0x1300c, 996 .enable_mask = BIT(0), 997 .hw.init = &(struct clk_init_data){ 998 .name = "gcc_boot_rom_ahb_clk", 999 .parent_hws = (const struct clk_hw *[]){ 1000 &pcnoc_clk_src.clkr.hw }, 1001 .num_parents = 1, 1002 .ops = &clk_branch2_ops, 1003 .flags = CLK_SET_RATE_PARENT, 1004 }, 1005 }, 1006 }; 1007 1008 static struct clk_branch gcc_crypto_ahb_clk = { 1009 .halt_reg = 0x16024, 1010 .halt_check = BRANCH_HALT_VOTED, 1011 .clkr = { 1012 .enable_reg = 0x6000, 1013 .enable_mask = BIT(0), 1014 .hw.init = &(struct clk_init_data){ 1015 .name = "gcc_crypto_ahb_clk", 1016 .parent_hws = (const struct clk_hw *[]){ 1017 &pcnoc_clk_src.clkr.hw }, 1018 .num_parents = 1, 1019 .ops = &clk_branch2_ops, 1020 }, 1021 }, 1022 }; 1023 1024 static struct clk_branch gcc_crypto_axi_clk = { 1025 .halt_reg = 0x16020, 1026 .halt_check = BRANCH_HALT_VOTED, 1027 .clkr = { 1028 .enable_reg = 0x6000, 1029 .enable_mask = BIT(1), 1030 .hw.init = &(struct clk_init_data){ 1031 .name = "gcc_crypto_axi_clk", 1032 .parent_hws = (const struct clk_hw *[]){ 1033 &gcc_fepll125_clk.cdiv.clkr.hw }, 1034 .num_parents = 1, 1035 .ops = &clk_branch2_ops, 1036 }, 1037 }, 1038 }; 1039 1040 static struct clk_branch gcc_crypto_clk = { 1041 .halt_reg = 0x1601c, 1042 .halt_check = BRANCH_HALT_VOTED, 1043 .clkr = { 1044 .enable_reg = 0x6000, 1045 .enable_mask = BIT(2), 1046 .hw.init = &(struct clk_init_data){ 1047 .name = "gcc_crypto_clk", 1048 .parent_hws = (const struct clk_hw *[]){ 1049 &gcc_fepll125_clk.cdiv.clkr.hw }, 1050 .num_parents = 1, 1051 .ops = &clk_branch2_ops, 1052 }, 1053 }, 1054 }; 1055 1056 static struct parent_map gcc_xo_125_dly_map[] = { 1057 { P_XO, 0 }, 1058 { P_FEPLL125DLY, 1 }, 1059 }; 1060 1061 static const struct clk_parent_data gcc_xo_125_dly[] = { 1062 { .fw_name = "xo", .name = "xo" }, 1063 { .hw = &gcc_fepll125dly_clk.cdiv.clkr.hw }, 1064 }; 1065 1066 static const struct freq_tbl ftbl_gcc_fephy_dly_clk[] = { 1067 F(125000000, P_FEPLL125DLY, 1, 0, 0), 1068 { } 1069 }; 1070 1071 static struct clk_rcg2 fephy_125m_dly_clk_src = { 1072 .cmd_rcgr = 0x12000, 1073 .hid_width = 5, 1074 .parent_map = gcc_xo_125_dly_map, 1075 .freq_tbl = ftbl_gcc_fephy_dly_clk, 1076 .clkr.hw.init = &(struct clk_init_data){ 1077 .name = "fephy_125m_dly_clk_src", 1078 .parent_data = gcc_xo_125_dly, 1079 .num_parents = ARRAY_SIZE(gcc_xo_125_dly), 1080 .ops = &clk_rcg2_ops, 1081 }, 1082 }; 1083 1084 static struct clk_branch gcc_ess_clk = { 1085 .halt_reg = 0x12010, 1086 .clkr = { 1087 .enable_reg = 0x12010, 1088 .enable_mask = BIT(0), 1089 .hw.init = &(struct clk_init_data){ 1090 .name = "gcc_ess_clk", 1091 .parent_hws = (const struct clk_hw *[]){ 1092 &fephy_125m_dly_clk_src.clkr.hw }, 1093 .num_parents = 1, 1094 .ops = &clk_branch2_ops, 1095 .flags = CLK_SET_RATE_PARENT, 1096 }, 1097 }, 1098 }; 1099 1100 static struct clk_branch gcc_imem_axi_clk = { 1101 .halt_reg = 0xe004, 1102 .halt_check = BRANCH_HALT_VOTED, 1103 .clkr = { 1104 .enable_reg = 0x6000, 1105 .enable_mask = BIT(17), 1106 .hw.init = &(struct clk_init_data){ 1107 .name = "gcc_imem_axi_clk", 1108 .parent_hws = (const struct clk_hw *[]){ 1109 &gcc_fepll200_clk.cdiv.clkr.hw }, 1110 .num_parents = 1, 1111 .ops = &clk_branch2_ops, 1112 }, 1113 }, 1114 }; 1115 1116 static struct clk_branch gcc_imem_cfg_ahb_clk = { 1117 .halt_reg = 0xe008, 1118 .clkr = { 1119 .enable_reg = 0xe008, 1120 .enable_mask = BIT(0), 1121 .hw.init = &(struct clk_init_data){ 1122 .name = "gcc_imem_cfg_ahb_clk", 1123 .parent_hws = (const struct clk_hw *[]){ 1124 &pcnoc_clk_src.clkr.hw }, 1125 .num_parents = 1, 1126 .ops = &clk_branch2_ops, 1127 }, 1128 }, 1129 }; 1130 1131 static struct clk_branch gcc_pcie_ahb_clk = { 1132 .halt_reg = 0x1d00c, 1133 .clkr = { 1134 .enable_reg = 0x1d00c, 1135 .enable_mask = BIT(0), 1136 .hw.init = &(struct clk_init_data){ 1137 .name = "gcc_pcie_ahb_clk", 1138 .parent_hws = (const struct clk_hw *[]){ 1139 &pcnoc_clk_src.clkr.hw }, 1140 .num_parents = 1, 1141 .ops = &clk_branch2_ops, 1142 }, 1143 }, 1144 }; 1145 1146 static struct clk_branch gcc_pcie_axi_m_clk = { 1147 .halt_reg = 0x1d004, 1148 .clkr = { 1149 .enable_reg = 0x1d004, 1150 .enable_mask = BIT(0), 1151 .hw.init = &(struct clk_init_data){ 1152 .name = "gcc_pcie_axi_m_clk", 1153 .parent_hws = (const struct clk_hw *[]){ 1154 &gcc_fepll200_clk.cdiv.clkr.hw }, 1155 .num_parents = 1, 1156 .ops = &clk_branch2_ops, 1157 }, 1158 }, 1159 }; 1160 1161 static struct clk_branch gcc_pcie_axi_s_clk = { 1162 .halt_reg = 0x1d008, 1163 .clkr = { 1164 .enable_reg = 0x1d008, 1165 .enable_mask = BIT(0), 1166 .hw.init = &(struct clk_init_data){ 1167 .name = "gcc_pcie_axi_s_clk", 1168 .parent_hws = (const struct clk_hw *[]){ 1169 &gcc_fepll200_clk.cdiv.clkr.hw }, 1170 .num_parents = 1, 1171 .ops = &clk_branch2_ops, 1172 }, 1173 }, 1174 }; 1175 1176 static struct clk_branch gcc_prng_ahb_clk = { 1177 .halt_reg = 0x13004, 1178 .halt_check = BRANCH_HALT_VOTED, 1179 .clkr = { 1180 .enable_reg = 0x6000, 1181 .enable_mask = BIT(8), 1182 .hw.init = &(struct clk_init_data){ 1183 .name = "gcc_prng_ahb_clk", 1184 .parent_hws = (const struct clk_hw *[]){ 1185 &pcnoc_clk_src.clkr.hw }, 1186 .num_parents = 1, 1187 .ops = &clk_branch2_ops, 1188 }, 1189 }, 1190 }; 1191 1192 static struct clk_branch gcc_qpic_ahb_clk = { 1193 .halt_reg = 0x1c008, 1194 .clkr = { 1195 .enable_reg = 0x1c008, 1196 .enable_mask = BIT(0), 1197 .hw.init = &(struct clk_init_data){ 1198 .name = "gcc_qpic_ahb_clk", 1199 .parent_hws = (const struct clk_hw *[]){ 1200 &pcnoc_clk_src.clkr.hw }, 1201 .num_parents = 1, 1202 .ops = &clk_branch2_ops, 1203 }, 1204 }, 1205 }; 1206 1207 static struct clk_branch gcc_qpic_clk = { 1208 .halt_reg = 0x1c004, 1209 .clkr = { 1210 .enable_reg = 0x1c004, 1211 .enable_mask = BIT(0), 1212 .hw.init = &(struct clk_init_data){ 1213 .name = "gcc_qpic_clk", 1214 .parent_hws = (const struct clk_hw *[]){ 1215 &pcnoc_clk_src.clkr.hw }, 1216 .num_parents = 1, 1217 .ops = &clk_branch2_ops, 1218 }, 1219 }, 1220 }; 1221 1222 static struct clk_branch gcc_sdcc1_ahb_clk = { 1223 .halt_reg = 0x18010, 1224 .clkr = { 1225 .enable_reg = 0x18010, 1226 .enable_mask = BIT(0), 1227 .hw.init = &(struct clk_init_data){ 1228 .name = "gcc_sdcc1_ahb_clk", 1229 .parent_hws = (const struct clk_hw *[]){ 1230 &pcnoc_clk_src.clkr.hw }, 1231 .num_parents = 1, 1232 .ops = &clk_branch2_ops, 1233 }, 1234 }, 1235 }; 1236 1237 static struct clk_branch gcc_sdcc1_apps_clk = { 1238 .halt_reg = 0x1800c, 1239 .clkr = { 1240 .enable_reg = 0x1800c, 1241 .enable_mask = BIT(0), 1242 .hw.init = &(struct clk_init_data){ 1243 .name = "gcc_sdcc1_apps_clk", 1244 .parent_hws = (const struct clk_hw *[]){ 1245 &sdcc1_apps_clk_src.clkr.hw }, 1246 .num_parents = 1, 1247 .ops = &clk_branch2_ops, 1248 .flags = CLK_SET_RATE_PARENT, 1249 }, 1250 }, 1251 }; 1252 1253 static struct clk_branch gcc_tlmm_ahb_clk = { 1254 .halt_reg = 0x5004, 1255 .halt_check = BRANCH_HALT_VOTED, 1256 .clkr = { 1257 .enable_reg = 0x6000, 1258 .enable_mask = BIT(5), 1259 .hw.init = &(struct clk_init_data){ 1260 .name = "gcc_tlmm_ahb_clk", 1261 .parent_hws = (const struct clk_hw *[]){ 1262 &pcnoc_clk_src.clkr.hw }, 1263 .num_parents = 1, 1264 .ops = &clk_branch2_ops, 1265 }, 1266 }, 1267 }; 1268 1269 static struct clk_branch gcc_usb2_master_clk = { 1270 .halt_reg = 0x1e00c, 1271 .clkr = { 1272 .enable_reg = 0x1e00c, 1273 .enable_mask = BIT(0), 1274 .hw.init = &(struct clk_init_data){ 1275 .name = "gcc_usb2_master_clk", 1276 .parent_hws = (const struct clk_hw *[]){ 1277 &pcnoc_clk_src.clkr.hw }, 1278 .num_parents = 1, 1279 .ops = &clk_branch2_ops, 1280 }, 1281 }, 1282 }; 1283 1284 static struct clk_branch gcc_usb2_sleep_clk = { 1285 .halt_reg = 0x1e010, 1286 .clkr = { 1287 .enable_reg = 0x1e010, 1288 .enable_mask = BIT(0), 1289 .hw.init = &(struct clk_init_data){ 1290 .name = "gcc_usb2_sleep_clk", 1291 .parent_data = &(const struct clk_parent_data){ 1292 .fw_name = "sleep_clk", 1293 .name = "gcc_sleep_clk_src", 1294 }, 1295 .num_parents = 1, 1296 .ops = &clk_branch2_ops, 1297 }, 1298 }, 1299 }; 1300 1301 static const struct freq_tbl ftbl_gcc_usb30_mock_utmi_clk[] = { 1302 F(2000000, P_FEPLL200, 10, 0, 0), 1303 { } 1304 }; 1305 1306 static struct clk_rcg2 usb30_mock_utmi_clk_src = { 1307 .cmd_rcgr = 0x1e000, 1308 .hid_width = 5, 1309 .parent_map = gcc_xo_200_map, 1310 .freq_tbl = ftbl_gcc_usb30_mock_utmi_clk, 1311 .clkr.hw.init = &(struct clk_init_data){ 1312 .name = "usb30_mock_utmi_clk_src", 1313 .parent_data = gcc_xo_200, 1314 .num_parents = ARRAY_SIZE(gcc_xo_200), 1315 .ops = &clk_rcg2_ops, 1316 }, 1317 }; 1318 1319 static struct clk_branch gcc_usb2_mock_utmi_clk = { 1320 .halt_reg = 0x1e014, 1321 .clkr = { 1322 .enable_reg = 0x1e014, 1323 .enable_mask = BIT(0), 1324 .hw.init = &(struct clk_init_data){ 1325 .name = "gcc_usb2_mock_utmi_clk", 1326 .parent_hws = (const struct clk_hw *[]){ 1327 &usb30_mock_utmi_clk_src.clkr.hw }, 1328 .num_parents = 1, 1329 .ops = &clk_branch2_ops, 1330 .flags = CLK_SET_RATE_PARENT, 1331 }, 1332 }, 1333 }; 1334 1335 static struct clk_branch gcc_usb3_master_clk = { 1336 .halt_reg = 0x1e028, 1337 .clkr = { 1338 .enable_reg = 0x1e028, 1339 .enable_mask = BIT(0), 1340 .hw.init = &(struct clk_init_data){ 1341 .name = "gcc_usb3_master_clk", 1342 .parent_hws = (const struct clk_hw *[]){ 1343 &gcc_fepll125_clk.cdiv.clkr.hw }, 1344 .num_parents = 1, 1345 .ops = &clk_branch2_ops, 1346 }, 1347 }, 1348 }; 1349 1350 static struct clk_branch gcc_usb3_sleep_clk = { 1351 .halt_reg = 0x1e02C, 1352 .clkr = { 1353 .enable_reg = 0x1e02C, 1354 .enable_mask = BIT(0), 1355 .hw.init = &(struct clk_init_data){ 1356 .name = "gcc_usb3_sleep_clk", 1357 .parent_data = &(const struct clk_parent_data){ 1358 .fw_name = "sleep_clk", 1359 .name = "gcc_sleep_clk_src", 1360 }, 1361 .num_parents = 1, 1362 .ops = &clk_branch2_ops, 1363 }, 1364 }, 1365 }; 1366 1367 static struct clk_branch gcc_usb3_mock_utmi_clk = { 1368 .halt_reg = 0x1e030, 1369 .clkr = { 1370 .enable_reg = 0x1e030, 1371 .enable_mask = BIT(0), 1372 .hw.init = &(struct clk_init_data){ 1373 .name = "gcc_usb3_mock_utmi_clk", 1374 .parent_hws = (const struct clk_hw *[]){ 1375 &usb30_mock_utmi_clk_src.clkr.hw }, 1376 .num_parents = 1, 1377 .ops = &clk_branch2_ops, 1378 .flags = CLK_SET_RATE_PARENT, 1379 }, 1380 }, 1381 }; 1382 1383 static struct parent_map gcc_xo_wcss2g_map[] = { 1384 { P_XO, 0 }, 1385 { P_FEPLLWCSS2G, 1 }, 1386 }; 1387 1388 static const struct clk_parent_data gcc_xo_wcss2g[] = { 1389 { .fw_name = "xo", .name = "xo" }, 1390 { .hw = &gcc_fepllwcss2g_clk.cdiv.clkr.hw }, 1391 }; 1392 1393 static const struct freq_tbl ftbl_gcc_wcss2g_clk[] = { 1394 F(48000000, P_XO, 1, 0, 0), 1395 F(250000000, P_FEPLLWCSS2G, 1, 0, 0), 1396 { } 1397 }; 1398 1399 static struct clk_rcg2 wcss2g_clk_src = { 1400 .cmd_rcgr = 0x1f000, 1401 .hid_width = 5, 1402 .freq_tbl = ftbl_gcc_wcss2g_clk, 1403 .parent_map = gcc_xo_wcss2g_map, 1404 .clkr.hw.init = &(struct clk_init_data){ 1405 .name = "wcss2g_clk_src", 1406 .parent_data = gcc_xo_wcss2g, 1407 .num_parents = ARRAY_SIZE(gcc_xo_wcss2g), 1408 .ops = &clk_rcg2_ops, 1409 .flags = CLK_SET_RATE_PARENT, 1410 }, 1411 }; 1412 1413 static struct clk_branch gcc_wcss2g_clk = { 1414 .halt_reg = 0x1f00C, 1415 .clkr = { 1416 .enable_reg = 0x1f00C, 1417 .enable_mask = BIT(0), 1418 .hw.init = &(struct clk_init_data){ 1419 .name = "gcc_wcss2g_clk", 1420 .parent_hws = (const struct clk_hw *[]){ 1421 &wcss2g_clk_src.clkr.hw }, 1422 .num_parents = 1, 1423 .ops = &clk_branch2_ops, 1424 .flags = CLK_SET_RATE_PARENT, 1425 }, 1426 }, 1427 }; 1428 1429 static struct clk_branch gcc_wcss2g_ref_clk = { 1430 .halt_reg = 0x1f00C, 1431 .clkr = { 1432 .enable_reg = 0x1f00C, 1433 .enable_mask = BIT(0), 1434 .hw.init = &(struct clk_init_data){ 1435 .name = "gcc_wcss2g_ref_clk", 1436 .parent_data = &(const struct clk_parent_data){ 1437 .fw_name = "xo", 1438 .name = "xo", 1439 }, 1440 .num_parents = 1, 1441 .ops = &clk_branch2_ops, 1442 .flags = CLK_SET_RATE_PARENT, 1443 }, 1444 }, 1445 }; 1446 1447 static struct clk_branch gcc_wcss2g_rtc_clk = { 1448 .halt_reg = 0x1f010, 1449 .clkr = { 1450 .enable_reg = 0x1f010, 1451 .enable_mask = BIT(0), 1452 .hw.init = &(struct clk_init_data){ 1453 .name = "gcc_wcss2g_rtc_clk", 1454 .parent_data = &(const struct clk_parent_data){ 1455 .fw_name = "sleep_clk", 1456 .name = "gcc_sleep_clk_src", 1457 }, 1458 .num_parents = 1, 1459 .ops = &clk_branch2_ops, 1460 }, 1461 }, 1462 }; 1463 1464 static struct parent_map gcc_xo_wcss5g_map[] = { 1465 { P_XO, 0 }, 1466 { P_FEPLLWCSS5G, 1 }, 1467 }; 1468 1469 static const struct clk_parent_data gcc_xo_wcss5g[] = { 1470 { .fw_name = "xo", .name = "xo" }, 1471 { .hw = &gcc_fepllwcss5g_clk.cdiv.clkr.hw }, 1472 }; 1473 1474 static const struct freq_tbl ftbl_gcc_wcss5g_clk[] = { 1475 F(48000000, P_XO, 1, 0, 0), 1476 F(250000000, P_FEPLLWCSS5G, 1, 0, 0), 1477 { } 1478 }; 1479 1480 static struct clk_rcg2 wcss5g_clk_src = { 1481 .cmd_rcgr = 0x20000, 1482 .hid_width = 5, 1483 .parent_map = gcc_xo_wcss5g_map, 1484 .freq_tbl = ftbl_gcc_wcss5g_clk, 1485 .clkr.hw.init = &(struct clk_init_data){ 1486 .name = "wcss5g_clk_src", 1487 .parent_data = gcc_xo_wcss5g, 1488 .num_parents = ARRAY_SIZE(gcc_xo_wcss5g), 1489 .ops = &clk_rcg2_ops, 1490 }, 1491 }; 1492 1493 static struct clk_branch gcc_wcss5g_clk = { 1494 .halt_reg = 0x2000c, 1495 .clkr = { 1496 .enable_reg = 0x2000c, 1497 .enable_mask = BIT(0), 1498 .hw.init = &(struct clk_init_data){ 1499 .name = "gcc_wcss5g_clk", 1500 .parent_hws = (const struct clk_hw *[]){ 1501 &wcss5g_clk_src.clkr.hw }, 1502 .num_parents = 1, 1503 .ops = &clk_branch2_ops, 1504 .flags = CLK_SET_RATE_PARENT, 1505 }, 1506 }, 1507 }; 1508 1509 static struct clk_branch gcc_wcss5g_ref_clk = { 1510 .halt_reg = 0x2000c, 1511 .clkr = { 1512 .enable_reg = 0x2000c, 1513 .enable_mask = BIT(0), 1514 .hw.init = &(struct clk_init_data){ 1515 .name = "gcc_wcss5g_ref_clk", 1516 .parent_data = &(const struct clk_parent_data){ 1517 .fw_name = "xo", 1518 .name = "xo", 1519 }, 1520 .num_parents = 1, 1521 .ops = &clk_branch2_ops, 1522 .flags = CLK_SET_RATE_PARENT, 1523 }, 1524 }, 1525 }; 1526 1527 static struct clk_branch gcc_wcss5g_rtc_clk = { 1528 .halt_reg = 0x20010, 1529 .clkr = { 1530 .enable_reg = 0x20010, 1531 .enable_mask = BIT(0), 1532 .hw.init = &(struct clk_init_data){ 1533 .name = "gcc_wcss5g_rtc_clk", 1534 .parent_data = &(const struct clk_parent_data){ 1535 .fw_name = "sleep_clk", 1536 .name = "gcc_sleep_clk_src", 1537 }, 1538 .num_parents = 1, 1539 .ops = &clk_branch2_ops, 1540 .flags = CLK_SET_RATE_PARENT, 1541 }, 1542 }, 1543 }; 1544 1545 static struct clk_regmap *gcc_ipq4019_clocks[] = { 1546 [AUDIO_CLK_SRC] = &audio_clk_src.clkr, 1547 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr, 1548 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr, 1549 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr, 1550 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr, 1551 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr, 1552 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr, 1553 [GCC_USB3_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr, 1554 [GCC_APPS_CLK_SRC] = &apps_clk_src.clkr, 1555 [GCC_APPS_AHB_CLK_SRC] = &apps_ahb_clk_src.clkr, 1556 [GP1_CLK_SRC] = &gp1_clk_src.clkr, 1557 [GP2_CLK_SRC] = &gp2_clk_src.clkr, 1558 [GP3_CLK_SRC] = &gp3_clk_src.clkr, 1559 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr, 1560 [FEPHY_125M_DLY_CLK_SRC] = &fephy_125m_dly_clk_src.clkr, 1561 [WCSS2G_CLK_SRC] = &wcss2g_clk_src.clkr, 1562 [WCSS5G_CLK_SRC] = &wcss5g_clk_src.clkr, 1563 [GCC_APSS_AHB_CLK] = &gcc_apss_ahb_clk.clkr, 1564 [GCC_AUDIO_AHB_CLK] = &gcc_audio_ahb_clk.clkr, 1565 [GCC_AUDIO_PWM_CLK] = &gcc_audio_pwm_clk.clkr, 1566 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr, 1567 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr, 1568 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr, 1569 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr, 1570 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr, 1571 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, 1572 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr, 1573 [GCC_DCD_XO_CLK] = &gcc_dcd_xo_clk.clkr, 1574 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 1575 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 1576 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 1577 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 1578 [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr, 1579 [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr, 1580 [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr, 1581 [GCC_ESS_CLK] = &gcc_ess_clk.clkr, 1582 [GCC_IMEM_AXI_CLK] = &gcc_imem_axi_clk.clkr, 1583 [GCC_IMEM_CFG_AHB_CLK] = &gcc_imem_cfg_ahb_clk.clkr, 1584 [GCC_PCIE_AHB_CLK] = &gcc_pcie_ahb_clk.clkr, 1585 [GCC_PCIE_AXI_M_CLK] = &gcc_pcie_axi_m_clk.clkr, 1586 [GCC_PCIE_AXI_S_CLK] = &gcc_pcie_axi_s_clk.clkr, 1587 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, 1588 [GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr, 1589 [GCC_QPIC_CLK] = &gcc_qpic_clk.clkr, 1590 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, 1591 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, 1592 [GCC_TLMM_AHB_CLK] = &gcc_tlmm_ahb_clk.clkr, 1593 [GCC_USB2_MASTER_CLK] = &gcc_usb2_master_clk.clkr, 1594 [GCC_USB2_SLEEP_CLK] = &gcc_usb2_sleep_clk.clkr, 1595 [GCC_USB2_MOCK_UTMI_CLK] = &gcc_usb2_mock_utmi_clk.clkr, 1596 [GCC_USB3_MASTER_CLK] = &gcc_usb3_master_clk.clkr, 1597 [GCC_USB3_SLEEP_CLK] = &gcc_usb3_sleep_clk.clkr, 1598 [GCC_USB3_MOCK_UTMI_CLK] = &gcc_usb3_mock_utmi_clk.clkr, 1599 [GCC_WCSS2G_CLK] = &gcc_wcss2g_clk.clkr, 1600 [GCC_WCSS2G_REF_CLK] = &gcc_wcss2g_ref_clk.clkr, 1601 [GCC_WCSS2G_RTC_CLK] = &gcc_wcss2g_rtc_clk.clkr, 1602 [GCC_WCSS5G_CLK] = &gcc_wcss5g_clk.clkr, 1603 [GCC_WCSS5G_REF_CLK] = &gcc_wcss5g_ref_clk.clkr, 1604 [GCC_WCSS5G_RTC_CLK] = &gcc_wcss5g_rtc_clk.clkr, 1605 [GCC_SDCC_PLLDIV_CLK] = &gcc_apss_sdcc_clk.cdiv.clkr, 1606 [GCC_FEPLL125_CLK] = &gcc_fepll125_clk.cdiv.clkr, 1607 [GCC_FEPLL125DLY_CLK] = &gcc_fepll125dly_clk.cdiv.clkr, 1608 [GCC_FEPLL200_CLK] = &gcc_fepll200_clk.cdiv.clkr, 1609 [GCC_FEPLL500_CLK] = &gcc_fepll500_clk.cdiv.clkr, 1610 [GCC_FEPLL_WCSS2G_CLK] = &gcc_fepllwcss2g_clk.cdiv.clkr, 1611 [GCC_FEPLL_WCSS5G_CLK] = &gcc_fepllwcss5g_clk.cdiv.clkr, 1612 [GCC_APSS_CPU_PLLDIV_CLK] = &gcc_apss_cpu_plldiv_clk.cdiv.clkr, 1613 [GCC_PCNOC_AHB_CLK_SRC] = &gcc_pcnoc_ahb_clk_src.clkr, 1614 [GCC_PCNOC_AHB_CLK] = &pcnoc_clk_src.clkr, 1615 }; 1616 1617 static const struct qcom_reset_map gcc_ipq4019_resets[] = { 1618 [WIFI0_CPU_INIT_RESET] = { 0x1f008, 5 }, 1619 [WIFI0_RADIO_SRIF_RESET] = { 0x1f008, 4 }, 1620 [WIFI0_RADIO_WARM_RESET] = { 0x1f008, 3 }, 1621 [WIFI0_RADIO_COLD_RESET] = { 0x1f008, 2 }, 1622 [WIFI0_CORE_WARM_RESET] = { 0x1f008, 1 }, 1623 [WIFI0_CORE_COLD_RESET] = { 0x1f008, 0 }, 1624 [WIFI1_CPU_INIT_RESET] = { 0x20008, 5 }, 1625 [WIFI1_RADIO_SRIF_RESET] = { 0x20008, 4 }, 1626 [WIFI1_RADIO_WARM_RESET] = { 0x20008, 3 }, 1627 [WIFI1_RADIO_COLD_RESET] = { 0x20008, 2 }, 1628 [WIFI1_CORE_WARM_RESET] = { 0x20008, 1 }, 1629 [WIFI1_CORE_COLD_RESET] = { 0x20008, 0 }, 1630 [USB3_UNIPHY_PHY_ARES] = { 0x1e038, 5 }, 1631 [USB3_HSPHY_POR_ARES] = { 0x1e038, 4 }, 1632 [USB3_HSPHY_S_ARES] = { 0x1e038, 2 }, 1633 [USB2_HSPHY_POR_ARES] = { 0x1e01c, 4 }, 1634 [USB2_HSPHY_S_ARES] = { 0x1e01c, 2 }, 1635 [PCIE_PHY_AHB_ARES] = { 0x1d010, 11 }, 1636 [PCIE_AHB_ARES] = { 0x1d010, 10 }, 1637 [PCIE_PWR_ARES] = { 0x1d010, 9 }, 1638 [PCIE_PIPE_STICKY_ARES] = { 0x1d010, 8 }, 1639 [PCIE_AXI_M_STICKY_ARES] = { 0x1d010, 7 }, 1640 [PCIE_PHY_ARES] = { 0x1d010, 6 }, 1641 [PCIE_PARF_XPU_ARES] = { 0x1d010, 5 }, 1642 [PCIE_AXI_S_XPU_ARES] = { 0x1d010, 4 }, 1643 [PCIE_AXI_M_VMIDMT_ARES] = { 0x1d010, 3 }, 1644 [PCIE_PIPE_ARES] = { 0x1d010, 2 }, 1645 [PCIE_AXI_S_ARES] = { 0x1d010, 1 }, 1646 [PCIE_AXI_M_ARES] = { 0x1d010, 0 }, 1647 [ESS_RESET] = { 0x12008, 0}, 1648 [GCC_BLSP1_BCR] = {0x01000, 0}, 1649 [GCC_BLSP1_QUP1_BCR] = {0x02000, 0}, 1650 [GCC_BLSP1_UART1_BCR] = {0x02038, 0}, 1651 [GCC_BLSP1_QUP2_BCR] = {0x03008, 0}, 1652 [GCC_BLSP1_UART2_BCR] = {0x03028, 0}, 1653 [GCC_BIMC_BCR] = {0x04000, 0}, 1654 [GCC_TLMM_BCR] = {0x05000, 0}, 1655 [GCC_IMEM_BCR] = {0x0E000, 0}, 1656 [GCC_ESS_BCR] = {0x12008, 0}, 1657 [GCC_PRNG_BCR] = {0x13000, 0}, 1658 [GCC_BOOT_ROM_BCR] = {0x13008, 0}, 1659 [GCC_CRYPTO_BCR] = {0x16000, 0}, 1660 [GCC_SDCC1_BCR] = {0x18000, 0}, 1661 [GCC_SEC_CTRL_BCR] = {0x1A000, 0}, 1662 [GCC_AUDIO_BCR] = {0x1B008, 0}, 1663 [GCC_QPIC_BCR] = {0x1C000, 0}, 1664 [GCC_PCIE_BCR] = {0x1D000, 0}, 1665 [GCC_USB2_BCR] = {0x1E008, 0}, 1666 [GCC_USB2_PHY_BCR] = {0x1E018, 0}, 1667 [GCC_USB3_BCR] = {0x1E024, 0}, 1668 [GCC_USB3_PHY_BCR] = {0x1E034, 0}, 1669 [GCC_SYSTEM_NOC_BCR] = {0x21000, 0}, 1670 [GCC_PCNOC_BCR] = {0x2102C, 0}, 1671 [GCC_DCD_BCR] = {0x21038, 0}, 1672 [GCC_SNOC_BUS_TIMEOUT0_BCR] = {0x21064, 0}, 1673 [GCC_SNOC_BUS_TIMEOUT1_BCR] = {0x2106C, 0}, 1674 [GCC_SNOC_BUS_TIMEOUT2_BCR] = {0x21074, 0}, 1675 [GCC_SNOC_BUS_TIMEOUT3_BCR] = {0x2107C, 0}, 1676 [GCC_PCNOC_BUS_TIMEOUT0_BCR] = {0x21084, 0}, 1677 [GCC_PCNOC_BUS_TIMEOUT1_BCR] = {0x2108C, 0}, 1678 [GCC_PCNOC_BUS_TIMEOUT2_BCR] = {0x21094, 0}, 1679 [GCC_PCNOC_BUS_TIMEOUT3_BCR] = {0x2109C, 0}, 1680 [GCC_PCNOC_BUS_TIMEOUT4_BCR] = {0x210A4, 0}, 1681 [GCC_PCNOC_BUS_TIMEOUT5_BCR] = {0x210AC, 0}, 1682 [GCC_PCNOC_BUS_TIMEOUT6_BCR] = {0x210B4, 0}, 1683 [GCC_PCNOC_BUS_TIMEOUT7_BCR] = {0x210BC, 0}, 1684 [GCC_PCNOC_BUS_TIMEOUT8_BCR] = {0x210C4, 0}, 1685 [GCC_PCNOC_BUS_TIMEOUT9_BCR] = {0x210CC, 0}, 1686 [GCC_TCSR_BCR] = {0x22000, 0}, 1687 [GCC_MPM_BCR] = {0x24000, 0}, 1688 [GCC_SPDM_BCR] = {0x25000, 0}, 1689 }; 1690 1691 static const struct regmap_config gcc_ipq4019_regmap_config = { 1692 .reg_bits = 32, 1693 .reg_stride = 4, 1694 .val_bits = 32, 1695 .max_register = 0x2ffff, 1696 .fast_io = true, 1697 }; 1698 1699 static const struct qcom_cc_desc gcc_ipq4019_desc = { 1700 .config = &gcc_ipq4019_regmap_config, 1701 .clks = gcc_ipq4019_clocks, 1702 .num_clks = ARRAY_SIZE(gcc_ipq4019_clocks), 1703 .resets = gcc_ipq4019_resets, 1704 .num_resets = ARRAY_SIZE(gcc_ipq4019_resets), 1705 }; 1706 1707 static const struct of_device_id gcc_ipq4019_match_table[] = { 1708 { .compatible = "qcom,gcc-ipq4019" }, 1709 { } 1710 }; 1711 MODULE_DEVICE_TABLE(of, gcc_ipq4019_match_table); 1712 1713 static int 1714 gcc_ipq4019_cpu_clk_notifier_fn(struct notifier_block *nb, 1715 unsigned long action, void *data) 1716 { 1717 int err = 0; 1718 1719 if (action == PRE_RATE_CHANGE) 1720 err = clk_rcg2_ops.set_parent(&apps_clk_src.clkr.hw, 1721 gcc_ipq4019_cpu_safe_parent); 1722 1723 return notifier_from_errno(err); 1724 } 1725 1726 static struct notifier_block gcc_ipq4019_cpu_clk_notifier = { 1727 .notifier_call = gcc_ipq4019_cpu_clk_notifier_fn, 1728 }; 1729 1730 static int gcc_ipq4019_probe(struct platform_device *pdev) 1731 { 1732 int err; 1733 1734 err = qcom_cc_probe(pdev, &gcc_ipq4019_desc); 1735 if (err) 1736 return err; 1737 1738 return devm_clk_notifier_register(&pdev->dev, apps_clk_src.clkr.hw.clk, 1739 &gcc_ipq4019_cpu_clk_notifier); 1740 } 1741 1742 static struct platform_driver gcc_ipq4019_driver = { 1743 .probe = gcc_ipq4019_probe, 1744 .driver = { 1745 .name = "qcom,gcc-ipq4019", 1746 .of_match_table = gcc_ipq4019_match_table, 1747 }, 1748 }; 1749 1750 static int __init gcc_ipq4019_init(void) 1751 { 1752 return platform_driver_register(&gcc_ipq4019_driver); 1753 } 1754 core_initcall(gcc_ipq4019_init); 1755 1756 static void __exit gcc_ipq4019_exit(void) 1757 { 1758 platform_driver_unregister(&gcc_ipq4019_driver); 1759 } 1760 module_exit(gcc_ipq4019_exit); 1761 1762 MODULE_ALIAS("platform:gcc-ipq4019"); 1763 MODULE_LICENSE("GPL v2"); 1764 MODULE_DESCRIPTION("QCOM GCC IPQ4019 driver"); 1765