1 /* 2 * Copyright (c) 2015 The Linux Foundation. All rights reserved. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include <linux/kernel.h> 15 #include <linux/err.h> 16 #include <linux/platform_device.h> 17 #include <linux/module.h> 18 #include <linux/of.h> 19 #include <linux/of_device.h> 20 #include <linux/clk-provider.h> 21 #include <linux/regmap.h> 22 #include <linux/reset-controller.h> 23 24 #include <dt-bindings/clock/qcom,gcc-ipq4019.h> 25 26 #include "common.h" 27 #include "clk-regmap.h" 28 #include "clk-rcg.h" 29 #include "clk-branch.h" 30 #include "reset.h" 31 32 enum { 33 P_XO, 34 P_FEPLL200, 35 P_FEPLL500, 36 P_DDRPLL, 37 P_FEPLLWCSS2G, 38 P_FEPLLWCSS5G, 39 P_FEPLL125DLY, 40 P_DDRPLLAPSS, 41 }; 42 43 static struct parent_map gcc_xo_200_500_map[] = { 44 { P_XO, 0 }, 45 { P_FEPLL200, 1 }, 46 { P_FEPLL500, 2 }, 47 }; 48 49 static const char * const gcc_xo_200_500[] = { 50 "xo", 51 "fepll200", 52 "fepll500", 53 }; 54 55 static struct parent_map gcc_xo_200_map[] = { 56 { P_XO, 0 }, 57 { P_FEPLL200, 1 }, 58 }; 59 60 static const char * const gcc_xo_200[] = { 61 "xo", 62 "fepll200", 63 }; 64 65 static struct parent_map gcc_xo_200_spi_map[] = { 66 { P_XO, 0 }, 67 { P_FEPLL200, 2 }, 68 }; 69 70 static const char * const gcc_xo_200_spi[] = { 71 "xo", 72 "fepll200", 73 }; 74 75 static struct parent_map gcc_xo_sdcc1_500_map[] = { 76 { P_XO, 0 }, 77 { P_DDRPLL, 1 }, 78 { P_FEPLL500, 2 }, 79 }; 80 81 static const char * const gcc_xo_sdcc1_500[] = { 82 "xo", 83 "ddrpll", 84 "fepll500", 85 }; 86 87 static struct parent_map gcc_xo_wcss2g_map[] = { 88 { P_XO, 0 }, 89 { P_FEPLLWCSS2G, 1 }, 90 }; 91 92 static const char * const gcc_xo_wcss2g[] = { 93 "xo", 94 "fepllwcss2g", 95 }; 96 97 static struct parent_map gcc_xo_wcss5g_map[] = { 98 { P_XO, 0 }, 99 { P_FEPLLWCSS5G, 1 }, 100 }; 101 102 static const char * const gcc_xo_wcss5g[] = { 103 "xo", 104 "fepllwcss5g", 105 }; 106 107 static struct parent_map gcc_xo_125_dly_map[] = { 108 { P_XO, 0 }, 109 { P_FEPLL125DLY, 1 }, 110 }; 111 112 static const char * const gcc_xo_125_dly[] = { 113 "xo", 114 "fepll125dly", 115 }; 116 117 static struct parent_map gcc_xo_ddr_500_200_map[] = { 118 { P_XO, 0 }, 119 { P_FEPLL200, 3 }, 120 { P_FEPLL500, 2 }, 121 { P_DDRPLLAPSS, 1 }, 122 }; 123 124 static const char * const gcc_xo_ddr_500_200[] = { 125 "xo", 126 "fepll200", 127 "fepll500", 128 "ddrpllapss", 129 }; 130 131 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } 132 133 static const struct freq_tbl ftbl_gcc_audio_pwm_clk[] = { 134 F(48000000, P_XO, 1, 0, 0), 135 F(200000000, P_FEPLL200, 1, 0, 0), 136 { } 137 }; 138 139 static struct clk_rcg2 audio_clk_src = { 140 .cmd_rcgr = 0x1b000, 141 .hid_width = 5, 142 .parent_map = gcc_xo_200_map, 143 .freq_tbl = ftbl_gcc_audio_pwm_clk, 144 .clkr.hw.init = &(struct clk_init_data){ 145 .name = "audio_clk_src", 146 .parent_names = gcc_xo_200, 147 .num_parents = 2, 148 .ops = &clk_rcg2_ops, 149 150 }, 151 }; 152 153 static struct clk_branch gcc_audio_ahb_clk = { 154 .halt_reg = 0x1b010, 155 .clkr = { 156 .enable_reg = 0x1b010, 157 .enable_mask = BIT(0), 158 .hw.init = &(struct clk_init_data){ 159 .name = "gcc_audio_ahb_clk", 160 .parent_names = (const char *[]){ 161 "pcnoc_clk_src", 162 }, 163 .flags = CLK_SET_RATE_PARENT, 164 .num_parents = 1, 165 .ops = &clk_branch2_ops, 166 }, 167 }, 168 }; 169 170 static struct clk_branch gcc_audio_pwm_clk = { 171 .halt_reg = 0x1b00C, 172 .clkr = { 173 .enable_reg = 0x1b00C, 174 .enable_mask = BIT(0), 175 .hw.init = &(struct clk_init_data){ 176 .name = "gcc_audio_pwm_clk", 177 .parent_names = (const char *[]){ 178 "audio_clk_src", 179 }, 180 .flags = CLK_SET_RATE_PARENT, 181 .num_parents = 1, 182 .ops = &clk_branch2_ops, 183 }, 184 }, 185 }; 186 187 static const struct freq_tbl ftbl_gcc_blsp1_qup1_2_i2c_apps_clk[] = { 188 F(19200000, P_XO, 1, 2, 5), 189 F(24000000, P_XO, 1, 1, 2), 190 { } 191 }; 192 193 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { 194 .cmd_rcgr = 0x200c, 195 .hid_width = 5, 196 .parent_map = gcc_xo_200_map, 197 .freq_tbl = ftbl_gcc_blsp1_qup1_2_i2c_apps_clk, 198 .clkr.hw.init = &(struct clk_init_data){ 199 .name = "blsp1_qup1_i2c_apps_clk_src", 200 .parent_names = gcc_xo_200, 201 .num_parents = 2, 202 .ops = &clk_rcg2_ops, 203 }, 204 }; 205 206 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { 207 .halt_reg = 0x2008, 208 .clkr = { 209 .enable_reg = 0x2008, 210 .enable_mask = BIT(0), 211 .hw.init = &(struct clk_init_data){ 212 .name = "gcc_blsp1_qup1_i2c_apps_clk", 213 .parent_names = (const char *[]){ 214 "blsp1_qup1_i2c_apps_clk_src", 215 }, 216 .num_parents = 1, 217 .ops = &clk_branch2_ops, 218 .flags = CLK_SET_RATE_PARENT, 219 }, 220 }, 221 }; 222 223 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { 224 .cmd_rcgr = 0x3000, 225 .hid_width = 5, 226 .parent_map = gcc_xo_200_map, 227 .freq_tbl = ftbl_gcc_blsp1_qup1_2_i2c_apps_clk, 228 .clkr.hw.init = &(struct clk_init_data){ 229 .name = "blsp1_qup2_i2c_apps_clk_src", 230 .parent_names = gcc_xo_200, 231 .num_parents = 2, 232 .ops = &clk_rcg2_ops, 233 }, 234 }; 235 236 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { 237 .halt_reg = 0x3010, 238 .clkr = { 239 .enable_reg = 0x3010, 240 .enable_mask = BIT(0), 241 .hw.init = &(struct clk_init_data){ 242 .name = "gcc_blsp1_qup2_i2c_apps_clk", 243 .parent_names = (const char *[]){ 244 "blsp1_qup2_i2c_apps_clk_src", 245 }, 246 .num_parents = 1, 247 .ops = &clk_branch2_ops, 248 .flags = CLK_SET_RATE_PARENT, 249 }, 250 }, 251 }; 252 253 static const struct freq_tbl ftbl_gcc_blsp1_qup1_2_spi_apps_clk[] = { 254 F(960000, P_XO, 12, 1, 4), 255 F(4800000, P_XO, 1, 1, 10), 256 F(9600000, P_XO, 1, 1, 5), 257 F(15000000, P_XO, 1, 1, 3), 258 F(19200000, P_XO, 1, 2, 5), 259 F(24000000, P_XO, 1, 1, 2), 260 F(48000000, P_XO, 1, 0, 0), 261 { } 262 }; 263 264 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { 265 .cmd_rcgr = 0x2024, 266 .mnd_width = 8, 267 .hid_width = 5, 268 .parent_map = gcc_xo_200_spi_map, 269 .freq_tbl = ftbl_gcc_blsp1_qup1_2_spi_apps_clk, 270 .clkr.hw.init = &(struct clk_init_data){ 271 .name = "blsp1_qup1_spi_apps_clk_src", 272 .parent_names = gcc_xo_200_spi, 273 .num_parents = 2, 274 .ops = &clk_rcg2_ops, 275 }, 276 }; 277 278 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { 279 .halt_reg = 0x2004, 280 .clkr = { 281 .enable_reg = 0x2004, 282 .enable_mask = BIT(0), 283 .hw.init = &(struct clk_init_data){ 284 .name = "gcc_blsp1_qup1_spi_apps_clk", 285 .parent_names = (const char *[]){ 286 "blsp1_qup1_spi_apps_clk_src", 287 }, 288 .num_parents = 1, 289 .ops = &clk_branch2_ops, 290 .flags = CLK_SET_RATE_PARENT, 291 }, 292 }, 293 }; 294 295 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { 296 .cmd_rcgr = 0x3014, 297 .mnd_width = 8, 298 .hid_width = 5, 299 .freq_tbl = ftbl_gcc_blsp1_qup1_2_spi_apps_clk, 300 .parent_map = gcc_xo_200_spi_map, 301 .clkr.hw.init = &(struct clk_init_data){ 302 .name = "blsp1_qup2_spi_apps_clk_src", 303 .parent_names = gcc_xo_200_spi, 304 .num_parents = 2, 305 .ops = &clk_rcg2_ops, 306 }, 307 }; 308 309 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { 310 .halt_reg = 0x300c, 311 .clkr = { 312 .enable_reg = 0x300c, 313 .enable_mask = BIT(0), 314 .hw.init = &(struct clk_init_data){ 315 .name = "gcc_blsp1_qup2_spi_apps_clk", 316 .parent_names = (const char *[]){ 317 "blsp1_qup2_spi_apps_clk_src", 318 }, 319 .num_parents = 1, 320 .ops = &clk_branch2_ops, 321 .flags = CLK_SET_RATE_PARENT, 322 }, 323 }, 324 }; 325 326 static const struct freq_tbl ftbl_gcc_blsp1_uart1_2_apps_clk[] = { 327 F(1843200, P_FEPLL200, 1, 144, 15625), 328 F(3686400, P_FEPLL200, 1, 288, 15625), 329 F(7372800, P_FEPLL200, 1, 576, 15625), 330 F(14745600, P_FEPLL200, 1, 1152, 15625), 331 F(16000000, P_FEPLL200, 1, 2, 25), 332 F(24000000, P_XO, 1, 1, 2), 333 F(32000000, P_FEPLL200, 1, 4, 25), 334 F(40000000, P_FEPLL200, 1, 1, 5), 335 F(46400000, P_FEPLL200, 1, 29, 125), 336 F(48000000, P_XO, 1, 0, 0), 337 { } 338 }; 339 340 static struct clk_rcg2 blsp1_uart1_apps_clk_src = { 341 .cmd_rcgr = 0x2044, 342 .mnd_width = 16, 343 .hid_width = 5, 344 .freq_tbl = ftbl_gcc_blsp1_uart1_2_apps_clk, 345 .parent_map = gcc_xo_200_spi_map, 346 .clkr.hw.init = &(struct clk_init_data){ 347 .name = "blsp1_uart1_apps_clk_src", 348 .parent_names = gcc_xo_200_spi, 349 .num_parents = 2, 350 .ops = &clk_rcg2_ops, 351 }, 352 }; 353 354 static struct clk_branch gcc_blsp1_uart1_apps_clk = { 355 .halt_reg = 0x203c, 356 .clkr = { 357 .enable_reg = 0x203c, 358 .enable_mask = BIT(0), 359 .hw.init = &(struct clk_init_data){ 360 .name = "gcc_blsp1_uart1_apps_clk", 361 .parent_names = (const char *[]){ 362 "blsp1_uart1_apps_clk_src", 363 }, 364 .flags = CLK_SET_RATE_PARENT, 365 .num_parents = 1, 366 .ops = &clk_branch2_ops, 367 }, 368 }, 369 }; 370 371 static struct clk_rcg2 blsp1_uart2_apps_clk_src = { 372 .cmd_rcgr = 0x3034, 373 .mnd_width = 16, 374 .hid_width = 5, 375 .freq_tbl = ftbl_gcc_blsp1_uart1_2_apps_clk, 376 .parent_map = gcc_xo_200_spi_map, 377 .clkr.hw.init = &(struct clk_init_data){ 378 .name = "blsp1_uart2_apps_clk_src", 379 .parent_names = gcc_xo_200_spi, 380 .num_parents = 2, 381 .ops = &clk_rcg2_ops, 382 }, 383 }; 384 385 static struct clk_branch gcc_blsp1_uart2_apps_clk = { 386 .halt_reg = 0x302c, 387 .clkr = { 388 .enable_reg = 0x302c, 389 .enable_mask = BIT(0), 390 .hw.init = &(struct clk_init_data){ 391 .name = "gcc_blsp1_uart2_apps_clk", 392 .parent_names = (const char *[]){ 393 "blsp1_uart2_apps_clk_src", 394 }, 395 .num_parents = 1, 396 .ops = &clk_branch2_ops, 397 .flags = CLK_SET_RATE_PARENT, 398 }, 399 }, 400 }; 401 402 static const struct freq_tbl ftbl_gcc_gp_clk[] = { 403 F(1250000, P_FEPLL200, 1, 16, 0), 404 F(2500000, P_FEPLL200, 1, 8, 0), 405 F(5000000, P_FEPLL200, 1, 4, 0), 406 { } 407 }; 408 409 static struct clk_rcg2 gp1_clk_src = { 410 .cmd_rcgr = 0x8004, 411 .mnd_width = 8, 412 .hid_width = 5, 413 .freq_tbl = ftbl_gcc_gp_clk, 414 .parent_map = gcc_xo_200_map, 415 .clkr.hw.init = &(struct clk_init_data){ 416 .name = "gp1_clk_src", 417 .parent_names = gcc_xo_200, 418 .num_parents = 2, 419 .ops = &clk_rcg2_ops, 420 }, 421 }; 422 423 static struct clk_branch gcc_gp1_clk = { 424 .halt_reg = 0x8000, 425 .clkr = { 426 .enable_reg = 0x8000, 427 .enable_mask = BIT(0), 428 .hw.init = &(struct clk_init_data){ 429 .name = "gcc_gp1_clk", 430 .parent_names = (const char *[]){ 431 "gp1_clk_src", 432 }, 433 .num_parents = 1, 434 .ops = &clk_branch2_ops, 435 .flags = CLK_SET_RATE_PARENT, 436 }, 437 }, 438 }; 439 440 static struct clk_rcg2 gp2_clk_src = { 441 .cmd_rcgr = 0x9004, 442 .mnd_width = 8, 443 .hid_width = 5, 444 .freq_tbl = ftbl_gcc_gp_clk, 445 .parent_map = gcc_xo_200_map, 446 .clkr.hw.init = &(struct clk_init_data){ 447 .name = "gp2_clk_src", 448 .parent_names = gcc_xo_200, 449 .num_parents = 2, 450 .ops = &clk_rcg2_ops, 451 }, 452 }; 453 454 static struct clk_branch gcc_gp2_clk = { 455 .halt_reg = 0x9000, 456 .clkr = { 457 .enable_reg = 0x9000, 458 .enable_mask = BIT(0), 459 .hw.init = &(struct clk_init_data){ 460 .name = "gcc_gp2_clk", 461 .parent_names = (const char *[]){ 462 "gp2_clk_src", 463 }, 464 .num_parents = 1, 465 .ops = &clk_branch2_ops, 466 .flags = CLK_SET_RATE_PARENT, 467 }, 468 }, 469 }; 470 471 static struct clk_rcg2 gp3_clk_src = { 472 .cmd_rcgr = 0xa004, 473 .mnd_width = 8, 474 .hid_width = 5, 475 .freq_tbl = ftbl_gcc_gp_clk, 476 .parent_map = gcc_xo_200_map, 477 .clkr.hw.init = &(struct clk_init_data){ 478 .name = "gp3_clk_src", 479 .parent_names = gcc_xo_200, 480 .num_parents = 2, 481 .ops = &clk_rcg2_ops, 482 }, 483 }; 484 485 static struct clk_branch gcc_gp3_clk = { 486 .halt_reg = 0xa000, 487 .clkr = { 488 .enable_reg = 0xa000, 489 .enable_mask = BIT(0), 490 .hw.init = &(struct clk_init_data){ 491 .name = "gcc_gp3_clk", 492 .parent_names = (const char *[]){ 493 "gp3_clk_src", 494 }, 495 .num_parents = 1, 496 .ops = &clk_branch2_ops, 497 .flags = CLK_SET_RATE_PARENT, 498 }, 499 }, 500 }; 501 502 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk[] = { 503 F(144000, P_XO, 1, 3, 240), 504 F(400000, P_XO, 1, 1, 0), 505 F(20000000, P_FEPLL500, 1, 1, 25), 506 F(25000000, P_FEPLL500, 1, 1, 20), 507 F(50000000, P_FEPLL500, 1, 1, 10), 508 F(100000000, P_FEPLL500, 1, 1, 5), 509 F(193000000, P_DDRPLL, 1, 0, 0), 510 { } 511 }; 512 513 static struct clk_rcg2 sdcc1_apps_clk_src = { 514 .cmd_rcgr = 0x18004, 515 .hid_width = 5, 516 .freq_tbl = ftbl_gcc_sdcc1_apps_clk, 517 .parent_map = gcc_xo_sdcc1_500_map, 518 .clkr.hw.init = &(struct clk_init_data){ 519 .name = "sdcc1_apps_clk_src", 520 .parent_names = gcc_xo_sdcc1_500, 521 .num_parents = 3, 522 .ops = &clk_rcg2_ops, 523 .flags = CLK_SET_RATE_PARENT, 524 }, 525 }; 526 527 static const struct freq_tbl ftbl_gcc_apps_clk[] = { 528 F(48000000, P_XO, 1, 0, 0), 529 F(200000000, P_FEPLL200, 1, 0, 0), 530 F(500000000, P_FEPLL500, 1, 0, 0), 531 F(626000000, P_DDRPLLAPSS, 1, 0, 0), 532 { } 533 }; 534 535 static struct clk_rcg2 apps_clk_src = { 536 .cmd_rcgr = 0x1900c, 537 .hid_width = 5, 538 .freq_tbl = ftbl_gcc_apps_clk, 539 .parent_map = gcc_xo_ddr_500_200_map, 540 .clkr.hw.init = &(struct clk_init_data){ 541 .name = "apps_clk_src", 542 .parent_names = gcc_xo_ddr_500_200, 543 .num_parents = 4, 544 .ops = &clk_rcg2_ops, 545 }, 546 }; 547 548 static const struct freq_tbl ftbl_gcc_apps_ahb_clk[] = { 549 F(48000000, P_XO, 1, 0, 0), 550 F(100000000, P_FEPLL200, 2, 0, 0), 551 { } 552 }; 553 554 static struct clk_rcg2 apps_ahb_clk_src = { 555 .cmd_rcgr = 0x19014, 556 .hid_width = 5, 557 .parent_map = gcc_xo_200_500_map, 558 .freq_tbl = ftbl_gcc_apps_ahb_clk, 559 .clkr.hw.init = &(struct clk_init_data){ 560 .name = "apps_ahb_clk_src", 561 .parent_names = gcc_xo_200_500, 562 .num_parents = 3, 563 .ops = &clk_rcg2_ops, 564 }, 565 }; 566 567 static struct clk_branch gcc_apss_ahb_clk = { 568 .halt_reg = 0x19004, 569 .halt_check = BRANCH_HALT_VOTED, 570 .clkr = { 571 .enable_reg = 0x6000, 572 .enable_mask = BIT(14), 573 .hw.init = &(struct clk_init_data){ 574 .name = "gcc_apss_ahb_clk", 575 .parent_names = (const char *[]){ 576 "apps_ahb_clk_src", 577 }, 578 .num_parents = 1, 579 .ops = &clk_branch2_ops, 580 .flags = CLK_SET_RATE_PARENT, 581 }, 582 }, 583 }; 584 585 static struct clk_branch gcc_blsp1_ahb_clk = { 586 .halt_reg = 0x1008, 587 .halt_check = BRANCH_HALT_VOTED, 588 .clkr = { 589 .enable_reg = 0x6000, 590 .enable_mask = BIT(10), 591 .hw.init = &(struct clk_init_data){ 592 .name = "gcc_blsp1_ahb_clk", 593 .parent_names = (const char *[]){ 594 "pcnoc_clk_src", 595 }, 596 .num_parents = 1, 597 .ops = &clk_branch2_ops, 598 }, 599 }, 600 }; 601 602 static struct clk_branch gcc_dcd_xo_clk = { 603 .halt_reg = 0x2103c, 604 .clkr = { 605 .enable_reg = 0x2103c, 606 .enable_mask = BIT(0), 607 .hw.init = &(struct clk_init_data){ 608 .name = "gcc_dcd_xo_clk", 609 .parent_names = (const char *[]){ 610 "xo", 611 }, 612 .num_parents = 1, 613 .ops = &clk_branch2_ops, 614 }, 615 }, 616 }; 617 618 static struct clk_branch gcc_boot_rom_ahb_clk = { 619 .halt_reg = 0x1300c, 620 .clkr = { 621 .enable_reg = 0x1300c, 622 .enable_mask = BIT(0), 623 .hw.init = &(struct clk_init_data){ 624 .name = "gcc_boot_rom_ahb_clk", 625 .parent_names = (const char *[]){ 626 "pcnoc_clk_src", 627 }, 628 .num_parents = 1, 629 .ops = &clk_branch2_ops, 630 .flags = CLK_SET_RATE_PARENT, 631 }, 632 }, 633 }; 634 635 static struct clk_branch gcc_crypto_ahb_clk = { 636 .halt_reg = 0x16024, 637 .halt_check = BRANCH_HALT_VOTED, 638 .clkr = { 639 .enable_reg = 0x6000, 640 .enable_mask = BIT(0), 641 .hw.init = &(struct clk_init_data){ 642 .name = "gcc_crypto_ahb_clk", 643 .parent_names = (const char *[]){ 644 "pcnoc_clk_src", 645 }, 646 .num_parents = 1, 647 .ops = &clk_branch2_ops, 648 }, 649 }, 650 }; 651 652 static struct clk_branch gcc_crypto_axi_clk = { 653 .halt_reg = 0x16020, 654 .halt_check = BRANCH_HALT_VOTED, 655 .clkr = { 656 .enable_reg = 0x6000, 657 .enable_mask = BIT(1), 658 .hw.init = &(struct clk_init_data){ 659 .name = "gcc_crypto_axi_clk", 660 .parent_names = (const char *[]){ 661 "fepll125", 662 }, 663 .num_parents = 1, 664 .ops = &clk_branch2_ops, 665 }, 666 }, 667 }; 668 669 static struct clk_branch gcc_crypto_clk = { 670 .halt_reg = 0x1601c, 671 .halt_check = BRANCH_HALT_VOTED, 672 .clkr = { 673 .enable_reg = 0x6000, 674 .enable_mask = BIT(2), 675 .hw.init = &(struct clk_init_data){ 676 .name = "gcc_crypto_clk", 677 .parent_names = (const char *[]){ 678 "fepll125", 679 }, 680 .num_parents = 1, 681 .ops = &clk_branch2_ops, 682 }, 683 }, 684 }; 685 686 static struct clk_branch gcc_ess_clk = { 687 .halt_reg = 0x12010, 688 .clkr = { 689 .enable_reg = 0x12010, 690 .enable_mask = BIT(0), 691 .hw.init = &(struct clk_init_data){ 692 .name = "gcc_ess_clk", 693 .parent_names = (const char *[]){ 694 "fephy_125m_dly_clk_src", 695 }, 696 .num_parents = 1, 697 .ops = &clk_branch2_ops, 698 .flags = CLK_SET_RATE_PARENT, 699 }, 700 }, 701 }; 702 703 static struct clk_branch gcc_imem_axi_clk = { 704 .halt_reg = 0xe004, 705 .halt_check = BRANCH_HALT_VOTED, 706 .clkr = { 707 .enable_reg = 0x6000, 708 .enable_mask = BIT(17), 709 .hw.init = &(struct clk_init_data){ 710 .name = "gcc_imem_axi_clk", 711 .parent_names = (const char *[]){ 712 "fepll200", 713 }, 714 .num_parents = 1, 715 .ops = &clk_branch2_ops, 716 }, 717 }, 718 }; 719 720 static struct clk_branch gcc_imem_cfg_ahb_clk = { 721 .halt_reg = 0xe008, 722 .clkr = { 723 .enable_reg = 0xe008, 724 .enable_mask = BIT(0), 725 .hw.init = &(struct clk_init_data){ 726 .name = "gcc_imem_cfg_ahb_clk", 727 .parent_names = (const char *[]){ 728 "pcnoc_clk_src", 729 }, 730 .num_parents = 1, 731 .ops = &clk_branch2_ops, 732 }, 733 }, 734 }; 735 736 static struct clk_branch gcc_pcie_ahb_clk = { 737 .halt_reg = 0x1d00c, 738 .clkr = { 739 .enable_reg = 0x1d00c, 740 .enable_mask = BIT(0), 741 .hw.init = &(struct clk_init_data){ 742 .name = "gcc_pcie_ahb_clk", 743 .parent_names = (const char *[]){ 744 "pcnoc_clk_src", 745 }, 746 .num_parents = 1, 747 .ops = &clk_branch2_ops, 748 }, 749 }, 750 }; 751 752 static struct clk_branch gcc_pcie_axi_m_clk = { 753 .halt_reg = 0x1d004, 754 .clkr = { 755 .enable_reg = 0x1d004, 756 .enable_mask = BIT(0), 757 .hw.init = &(struct clk_init_data){ 758 .name = "gcc_pcie_axi_m_clk", 759 .parent_names = (const char *[]){ 760 "fepll200", 761 }, 762 .num_parents = 1, 763 .ops = &clk_branch2_ops, 764 }, 765 }, 766 }; 767 768 static struct clk_branch gcc_pcie_axi_s_clk = { 769 .halt_reg = 0x1d008, 770 .clkr = { 771 .enable_reg = 0x1d008, 772 .enable_mask = BIT(0), 773 .hw.init = &(struct clk_init_data){ 774 .name = "gcc_pcie_axi_s_clk", 775 .parent_names = (const char *[]){ 776 "fepll200", 777 }, 778 .num_parents = 1, 779 .ops = &clk_branch2_ops, 780 }, 781 }, 782 }; 783 784 static struct clk_branch gcc_prng_ahb_clk = { 785 .halt_reg = 0x13004, 786 .halt_check = BRANCH_HALT_VOTED, 787 .clkr = { 788 .enable_reg = 0x6000, 789 .enable_mask = BIT(8), 790 .hw.init = &(struct clk_init_data){ 791 .name = "gcc_prng_ahb_clk", 792 .parent_names = (const char *[]){ 793 "pcnoc_clk_src", 794 }, 795 .num_parents = 1, 796 .ops = &clk_branch2_ops, 797 }, 798 }, 799 }; 800 801 static struct clk_branch gcc_qpic_ahb_clk = { 802 .halt_reg = 0x1c008, 803 .clkr = { 804 .enable_reg = 0x1c008, 805 .enable_mask = BIT(0), 806 .hw.init = &(struct clk_init_data){ 807 .name = "gcc_qpic_ahb_clk", 808 .parent_names = (const char *[]){ 809 "pcnoc_clk_src", 810 }, 811 .num_parents = 1, 812 .ops = &clk_branch2_ops, 813 }, 814 }, 815 }; 816 817 static struct clk_branch gcc_qpic_clk = { 818 .halt_reg = 0x1c004, 819 .clkr = { 820 .enable_reg = 0x1c004, 821 .enable_mask = BIT(0), 822 .hw.init = &(struct clk_init_data){ 823 .name = "gcc_qpic_clk", 824 .parent_names = (const char *[]){ 825 "pcnoc_clk_src", 826 }, 827 .num_parents = 1, 828 .ops = &clk_branch2_ops, 829 }, 830 }, 831 }; 832 833 static struct clk_branch gcc_sdcc1_ahb_clk = { 834 .halt_reg = 0x18010, 835 .clkr = { 836 .enable_reg = 0x18010, 837 .enable_mask = BIT(0), 838 .hw.init = &(struct clk_init_data){ 839 .name = "gcc_sdcc1_ahb_clk", 840 .parent_names = (const char *[]){ 841 "pcnoc_clk_src", 842 }, 843 .num_parents = 1, 844 .ops = &clk_branch2_ops, 845 }, 846 }, 847 }; 848 849 static struct clk_branch gcc_sdcc1_apps_clk = { 850 .halt_reg = 0x1800c, 851 .clkr = { 852 .enable_reg = 0x1800c, 853 .enable_mask = BIT(0), 854 .hw.init = &(struct clk_init_data){ 855 .name = "gcc_sdcc1_apps_clk", 856 .parent_names = (const char *[]){ 857 "sdcc1_apps_clk_src", 858 }, 859 .num_parents = 1, 860 .ops = &clk_branch2_ops, 861 .flags = CLK_SET_RATE_PARENT, 862 }, 863 }, 864 }; 865 866 static struct clk_branch gcc_tlmm_ahb_clk = { 867 .halt_reg = 0x5004, 868 .halt_check = BRANCH_HALT_VOTED, 869 .clkr = { 870 .enable_reg = 0x6000, 871 .enable_mask = BIT(5), 872 .hw.init = &(struct clk_init_data){ 873 .name = "gcc_tlmm_ahb_clk", 874 .parent_names = (const char *[]){ 875 "pcnoc_clk_src", 876 }, 877 .num_parents = 1, 878 .ops = &clk_branch2_ops, 879 }, 880 }, 881 }; 882 883 static struct clk_branch gcc_usb2_master_clk = { 884 .halt_reg = 0x1e00c, 885 .clkr = { 886 .enable_reg = 0x1e00c, 887 .enable_mask = BIT(0), 888 .hw.init = &(struct clk_init_data){ 889 .name = "gcc_usb2_master_clk", 890 .parent_names = (const char *[]){ 891 "pcnoc_clk_src", 892 }, 893 .num_parents = 1, 894 .ops = &clk_branch2_ops, 895 }, 896 }, 897 }; 898 899 static struct clk_branch gcc_usb2_sleep_clk = { 900 .halt_reg = 0x1e010, 901 .clkr = { 902 .enable_reg = 0x1e010, 903 .enable_mask = BIT(0), 904 .hw.init = &(struct clk_init_data){ 905 .name = "gcc_usb2_sleep_clk", 906 .parent_names = (const char *[]){ 907 "gcc_sleep_clk_src", 908 }, 909 .num_parents = 1, 910 .ops = &clk_branch2_ops, 911 }, 912 }, 913 }; 914 915 static struct clk_branch gcc_usb2_mock_utmi_clk = { 916 .halt_reg = 0x1e014, 917 .clkr = { 918 .enable_reg = 0x1e014, 919 .enable_mask = BIT(0), 920 .hw.init = &(struct clk_init_data){ 921 .name = "gcc_usb2_mock_utmi_clk", 922 .parent_names = (const char *[]){ 923 "usb30_mock_utmi_clk_src", 924 }, 925 .num_parents = 1, 926 .ops = &clk_branch2_ops, 927 .flags = CLK_SET_RATE_PARENT, 928 }, 929 }, 930 }; 931 932 static const struct freq_tbl ftbl_gcc_usb30_mock_utmi_clk[] = { 933 F(2000000, P_FEPLL200, 10, 0, 0), 934 { } 935 }; 936 937 static struct clk_rcg2 usb30_mock_utmi_clk_src = { 938 .cmd_rcgr = 0x1e000, 939 .hid_width = 5, 940 .parent_map = gcc_xo_200_map, 941 .freq_tbl = ftbl_gcc_usb30_mock_utmi_clk, 942 .clkr.hw.init = &(struct clk_init_data){ 943 .name = "usb30_mock_utmi_clk_src", 944 .parent_names = gcc_xo_200, 945 .num_parents = 2, 946 .ops = &clk_rcg2_ops, 947 }, 948 }; 949 950 static struct clk_branch gcc_usb3_master_clk = { 951 .halt_reg = 0x1e028, 952 .clkr = { 953 .enable_reg = 0x1e028, 954 .enable_mask = BIT(0), 955 .hw.init = &(struct clk_init_data){ 956 .name = "gcc_usb3_master_clk", 957 .parent_names = (const char *[]){ 958 "fepll125", 959 }, 960 .num_parents = 1, 961 .ops = &clk_branch2_ops, 962 }, 963 }, 964 }; 965 966 static struct clk_branch gcc_usb3_sleep_clk = { 967 .halt_reg = 0x1e02C, 968 .clkr = { 969 .enable_reg = 0x1e02C, 970 .enable_mask = BIT(0), 971 .hw.init = &(struct clk_init_data){ 972 .name = "gcc_usb3_sleep_clk", 973 .parent_names = (const char *[]){ 974 "gcc_sleep_clk_src", 975 }, 976 .num_parents = 1, 977 .ops = &clk_branch2_ops, 978 }, 979 }, 980 }; 981 982 static struct clk_branch gcc_usb3_mock_utmi_clk = { 983 .halt_reg = 0x1e030, 984 .clkr = { 985 .enable_reg = 0x1e030, 986 .enable_mask = BIT(0), 987 .hw.init = &(struct clk_init_data){ 988 .name = "gcc_usb3_mock_utmi_clk", 989 .parent_names = (const char *[]){ 990 "usb30_mock_utmi_clk_src", 991 }, 992 .num_parents = 1, 993 .ops = &clk_branch2_ops, 994 .flags = CLK_SET_RATE_PARENT, 995 }, 996 }, 997 }; 998 999 static const struct freq_tbl ftbl_gcc_fephy_dly_clk[] = { 1000 F(125000000, P_FEPLL125DLY, 1, 0, 0), 1001 { } 1002 }; 1003 1004 static struct clk_rcg2 fephy_125m_dly_clk_src = { 1005 .cmd_rcgr = 0x12000, 1006 .hid_width = 5, 1007 .parent_map = gcc_xo_125_dly_map, 1008 .freq_tbl = ftbl_gcc_fephy_dly_clk, 1009 .clkr.hw.init = &(struct clk_init_data){ 1010 .name = "fephy_125m_dly_clk_src", 1011 .parent_names = gcc_xo_125_dly, 1012 .num_parents = 2, 1013 .ops = &clk_rcg2_ops, 1014 }, 1015 }; 1016 1017 1018 static const struct freq_tbl ftbl_gcc_wcss2g_clk[] = { 1019 F(48000000, P_XO, 1, 0, 0), 1020 F(250000000, P_FEPLLWCSS2G, 1, 0, 0), 1021 { } 1022 }; 1023 1024 static struct clk_rcg2 wcss2g_clk_src = { 1025 .cmd_rcgr = 0x1f000, 1026 .hid_width = 5, 1027 .freq_tbl = ftbl_gcc_wcss2g_clk, 1028 .parent_map = gcc_xo_wcss2g_map, 1029 .clkr.hw.init = &(struct clk_init_data){ 1030 .name = "wcss2g_clk_src", 1031 .parent_names = gcc_xo_wcss2g, 1032 .num_parents = 2, 1033 .ops = &clk_rcg2_ops, 1034 .flags = CLK_SET_RATE_PARENT, 1035 }, 1036 }; 1037 1038 static struct clk_branch gcc_wcss2g_clk = { 1039 .halt_reg = 0x1f00C, 1040 .clkr = { 1041 .enable_reg = 0x1f00C, 1042 .enable_mask = BIT(0), 1043 .hw.init = &(struct clk_init_data){ 1044 .name = "gcc_wcss2g_clk", 1045 .parent_names = (const char *[]){ 1046 "wcss2g_clk_src", 1047 }, 1048 .num_parents = 1, 1049 .ops = &clk_branch2_ops, 1050 .flags = CLK_SET_RATE_PARENT, 1051 }, 1052 }, 1053 }; 1054 1055 static struct clk_branch gcc_wcss2g_ref_clk = { 1056 .halt_reg = 0x1f00C, 1057 .clkr = { 1058 .enable_reg = 0x1f00C, 1059 .enable_mask = BIT(0), 1060 .hw.init = &(struct clk_init_data){ 1061 .name = "gcc_wcss2g_ref_clk", 1062 .parent_names = (const char *[]){ 1063 "xo", 1064 }, 1065 .num_parents = 1, 1066 .ops = &clk_branch2_ops, 1067 .flags = CLK_SET_RATE_PARENT, 1068 }, 1069 }, 1070 }; 1071 1072 static struct clk_branch gcc_wcss2g_rtc_clk = { 1073 .halt_reg = 0x1f010, 1074 .clkr = { 1075 .enable_reg = 0x1f010, 1076 .enable_mask = BIT(0), 1077 .hw.init = &(struct clk_init_data){ 1078 .name = "gcc_wcss2g_rtc_clk", 1079 .parent_names = (const char *[]){ 1080 "gcc_sleep_clk_src", 1081 }, 1082 .num_parents = 1, 1083 .ops = &clk_branch2_ops, 1084 }, 1085 }, 1086 }; 1087 1088 static const struct freq_tbl ftbl_gcc_wcss5g_clk[] = { 1089 F(48000000, P_XO, 1, 0, 0), 1090 F(250000000, P_FEPLLWCSS5G, 1, 0, 0), 1091 { } 1092 }; 1093 1094 static struct clk_rcg2 wcss5g_clk_src = { 1095 .cmd_rcgr = 0x20000, 1096 .hid_width = 5, 1097 .parent_map = gcc_xo_wcss5g_map, 1098 .freq_tbl = ftbl_gcc_wcss5g_clk, 1099 .clkr.hw.init = &(struct clk_init_data){ 1100 .name = "wcss5g_clk_src", 1101 .parent_names = gcc_xo_wcss5g, 1102 .num_parents = 2, 1103 .ops = &clk_rcg2_ops, 1104 }, 1105 }; 1106 1107 static struct clk_branch gcc_wcss5g_clk = { 1108 .halt_reg = 0x2000c, 1109 .clkr = { 1110 .enable_reg = 0x2000c, 1111 .enable_mask = BIT(0), 1112 .hw.init = &(struct clk_init_data){ 1113 .name = "gcc_wcss5g_clk", 1114 .parent_names = (const char *[]){ 1115 "wcss5g_clk_src", 1116 }, 1117 .num_parents = 1, 1118 .ops = &clk_branch2_ops, 1119 .flags = CLK_SET_RATE_PARENT, 1120 }, 1121 }, 1122 }; 1123 1124 static struct clk_branch gcc_wcss5g_ref_clk = { 1125 .halt_reg = 0x2000c, 1126 .clkr = { 1127 .enable_reg = 0x2000c, 1128 .enable_mask = BIT(0), 1129 .hw.init = &(struct clk_init_data){ 1130 .name = "gcc_wcss5g_ref_clk", 1131 .parent_names = (const char *[]){ 1132 "xo", 1133 }, 1134 .num_parents = 1, 1135 .ops = &clk_branch2_ops, 1136 .flags = CLK_SET_RATE_PARENT, 1137 }, 1138 }, 1139 }; 1140 1141 static struct clk_branch gcc_wcss5g_rtc_clk = { 1142 .halt_reg = 0x20010, 1143 .clkr = { 1144 .enable_reg = 0x20010, 1145 .enable_mask = BIT(0), 1146 .hw.init = &(struct clk_init_data){ 1147 .name = "gcc_wcss5g_rtc_clk", 1148 .parent_names = (const char *[]){ 1149 "gcc_sleep_clk_src", 1150 }, 1151 .num_parents = 1, 1152 .ops = &clk_branch2_ops, 1153 .flags = CLK_SET_RATE_PARENT, 1154 }, 1155 }, 1156 }; 1157 1158 static struct clk_regmap *gcc_ipq4019_clocks[] = { 1159 [AUDIO_CLK_SRC] = &audio_clk_src.clkr, 1160 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr, 1161 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr, 1162 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr, 1163 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr, 1164 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr, 1165 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr, 1166 [GCC_USB3_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr, 1167 [GCC_APPS_CLK_SRC] = &apps_clk_src.clkr, 1168 [GCC_APPS_AHB_CLK_SRC] = &apps_ahb_clk_src.clkr, 1169 [GP1_CLK_SRC] = &gp1_clk_src.clkr, 1170 [GP2_CLK_SRC] = &gp2_clk_src.clkr, 1171 [GP3_CLK_SRC] = &gp3_clk_src.clkr, 1172 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr, 1173 [FEPHY_125M_DLY_CLK_SRC] = &fephy_125m_dly_clk_src.clkr, 1174 [WCSS2G_CLK_SRC] = &wcss2g_clk_src.clkr, 1175 [WCSS5G_CLK_SRC] = &wcss5g_clk_src.clkr, 1176 [GCC_APSS_AHB_CLK] = &gcc_apss_ahb_clk.clkr, 1177 [GCC_AUDIO_AHB_CLK] = &gcc_audio_ahb_clk.clkr, 1178 [GCC_AUDIO_PWM_CLK] = &gcc_audio_pwm_clk.clkr, 1179 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr, 1180 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr, 1181 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr, 1182 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr, 1183 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr, 1184 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, 1185 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr, 1186 [GCC_DCD_XO_CLK] = &gcc_dcd_xo_clk.clkr, 1187 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 1188 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 1189 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 1190 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 1191 [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr, 1192 [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr, 1193 [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr, 1194 [GCC_ESS_CLK] = &gcc_ess_clk.clkr, 1195 [GCC_IMEM_AXI_CLK] = &gcc_imem_axi_clk.clkr, 1196 [GCC_IMEM_CFG_AHB_CLK] = &gcc_imem_cfg_ahb_clk.clkr, 1197 [GCC_PCIE_AHB_CLK] = &gcc_pcie_ahb_clk.clkr, 1198 [GCC_PCIE_AXI_M_CLK] = &gcc_pcie_axi_m_clk.clkr, 1199 [GCC_PCIE_AXI_S_CLK] = &gcc_pcie_axi_s_clk.clkr, 1200 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, 1201 [GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr, 1202 [GCC_QPIC_CLK] = &gcc_qpic_clk.clkr, 1203 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, 1204 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, 1205 [GCC_TLMM_AHB_CLK] = &gcc_tlmm_ahb_clk.clkr, 1206 [GCC_USB2_MASTER_CLK] = &gcc_usb2_master_clk.clkr, 1207 [GCC_USB2_SLEEP_CLK] = &gcc_usb2_sleep_clk.clkr, 1208 [GCC_USB2_MOCK_UTMI_CLK] = &gcc_usb2_mock_utmi_clk.clkr, 1209 [GCC_USB3_MASTER_CLK] = &gcc_usb3_master_clk.clkr, 1210 [GCC_USB3_SLEEP_CLK] = &gcc_usb3_sleep_clk.clkr, 1211 [GCC_USB3_MOCK_UTMI_CLK] = &gcc_usb3_mock_utmi_clk.clkr, 1212 [GCC_WCSS2G_CLK] = &gcc_wcss2g_clk.clkr, 1213 [GCC_WCSS2G_REF_CLK] = &gcc_wcss2g_ref_clk.clkr, 1214 [GCC_WCSS2G_RTC_CLK] = &gcc_wcss2g_rtc_clk.clkr, 1215 [GCC_WCSS5G_CLK] = &gcc_wcss5g_clk.clkr, 1216 [GCC_WCSS5G_REF_CLK] = &gcc_wcss5g_ref_clk.clkr, 1217 [GCC_WCSS5G_RTC_CLK] = &gcc_wcss5g_rtc_clk.clkr, 1218 }; 1219 1220 static const struct qcom_reset_map gcc_ipq4019_resets[] = { 1221 [WIFI0_CPU_INIT_RESET] = { 0x1f008, 5 }, 1222 [WIFI0_RADIO_SRIF_RESET] = { 0x1f008, 4 }, 1223 [WIFI0_RADIO_WARM_RESET] = { 0x1f008, 3 }, 1224 [WIFI0_RADIO_COLD_RESET] = { 0x1f008, 2 }, 1225 [WIFI0_CORE_WARM_RESET] = { 0x1f008, 1 }, 1226 [WIFI0_CORE_COLD_RESET] = { 0x1f008, 0 }, 1227 [WIFI1_CPU_INIT_RESET] = { 0x20008, 5 }, 1228 [WIFI1_RADIO_SRIF_RESET] = { 0x20008, 4 }, 1229 [WIFI1_RADIO_WARM_RESET] = { 0x20008, 3 }, 1230 [WIFI1_RADIO_COLD_RESET] = { 0x20008, 2 }, 1231 [WIFI1_CORE_WARM_RESET] = { 0x20008, 1 }, 1232 [WIFI1_CORE_COLD_RESET] = { 0x20008, 0 }, 1233 [USB3_UNIPHY_PHY_ARES] = { 0x1e038, 5 }, 1234 [USB3_HSPHY_POR_ARES] = { 0x1e038, 4 }, 1235 [USB3_HSPHY_S_ARES] = { 0x1e038, 2 }, 1236 [USB2_HSPHY_POR_ARES] = { 0x1e01c, 4 }, 1237 [USB2_HSPHY_S_ARES] = { 0x1e01c, 2 }, 1238 [PCIE_PHY_AHB_ARES] = { 0x1d010, 11 }, 1239 [PCIE_AHB_ARES] = { 0x1d010, 10 }, 1240 [PCIE_PWR_ARES] = { 0x1d010, 9 }, 1241 [PCIE_PIPE_STICKY_ARES] = { 0x1d010, 8 }, 1242 [PCIE_AXI_M_STICKY_ARES] = { 0x1d010, 7 }, 1243 [PCIE_PHY_ARES] = { 0x1d010, 6 }, 1244 [PCIE_PARF_XPU_ARES] = { 0x1d010, 5 }, 1245 [PCIE_AXI_S_XPU_ARES] = { 0x1d010, 4 }, 1246 [PCIE_AXI_M_VMIDMT_ARES] = { 0x1d010, 3 }, 1247 [PCIE_PIPE_ARES] = { 0x1d010, 2 }, 1248 [PCIE_AXI_S_ARES] = { 0x1d010, 1 }, 1249 [PCIE_AXI_M_ARES] = { 0x1d010, 0 }, 1250 [ESS_RESET] = { 0x12008, 0}, 1251 [GCC_BLSP1_BCR] = {0x01000, 0}, 1252 [GCC_BLSP1_QUP1_BCR] = {0x02000, 0}, 1253 [GCC_BLSP1_UART1_BCR] = {0x02038, 0}, 1254 [GCC_BLSP1_QUP2_BCR] = {0x03008, 0}, 1255 [GCC_BLSP1_UART2_BCR] = {0x03028, 0}, 1256 [GCC_BIMC_BCR] = {0x04000, 0}, 1257 [GCC_TLMM_BCR] = {0x05000, 0}, 1258 [GCC_IMEM_BCR] = {0x0E000, 0}, 1259 [GCC_ESS_BCR] = {0x12008, 0}, 1260 [GCC_PRNG_BCR] = {0x13000, 0}, 1261 [GCC_BOOT_ROM_BCR] = {0x13008, 0}, 1262 [GCC_CRYPTO_BCR] = {0x16000, 0}, 1263 [GCC_SDCC1_BCR] = {0x18000, 0}, 1264 [GCC_SEC_CTRL_BCR] = {0x1A000, 0}, 1265 [GCC_AUDIO_BCR] = {0x1B008, 0}, 1266 [GCC_QPIC_BCR] = {0x1C000, 0}, 1267 [GCC_PCIE_BCR] = {0x1D000, 0}, 1268 [GCC_USB2_BCR] = {0x1E008, 0}, 1269 [GCC_USB2_PHY_BCR] = {0x1E018, 0}, 1270 [GCC_USB3_BCR] = {0x1E024, 0}, 1271 [GCC_USB3_PHY_BCR] = {0x1E034, 0}, 1272 [GCC_SYSTEM_NOC_BCR] = {0x21000, 0}, 1273 [GCC_PCNOC_BCR] = {0x2102C, 0}, 1274 [GCC_DCD_BCR] = {0x21038, 0}, 1275 [GCC_SNOC_BUS_TIMEOUT0_BCR] = {0x21064, 0}, 1276 [GCC_SNOC_BUS_TIMEOUT1_BCR] = {0x2106C, 0}, 1277 [GCC_SNOC_BUS_TIMEOUT2_BCR] = {0x21074, 0}, 1278 [GCC_SNOC_BUS_TIMEOUT3_BCR] = {0x2107C, 0}, 1279 [GCC_PCNOC_BUS_TIMEOUT0_BCR] = {0x21084, 0}, 1280 [GCC_PCNOC_BUS_TIMEOUT1_BCR] = {0x2108C, 0}, 1281 [GCC_PCNOC_BUS_TIMEOUT2_BCR] = {0x21094, 0}, 1282 [GCC_PCNOC_BUS_TIMEOUT3_BCR] = {0x2109C, 0}, 1283 [GCC_PCNOC_BUS_TIMEOUT4_BCR] = {0x210A4, 0}, 1284 [GCC_PCNOC_BUS_TIMEOUT5_BCR] = {0x210AC, 0}, 1285 [GCC_PCNOC_BUS_TIMEOUT6_BCR] = {0x210B4, 0}, 1286 [GCC_PCNOC_BUS_TIMEOUT7_BCR] = {0x210BC, 0}, 1287 [GCC_PCNOC_BUS_TIMEOUT8_BCR] = {0x210C4, 0}, 1288 [GCC_PCNOC_BUS_TIMEOUT9_BCR] = {0x210CC, 0}, 1289 [GCC_TCSR_BCR] = {0x22000, 0}, 1290 [GCC_MPM_BCR] = {0x24000, 0}, 1291 [GCC_SPDM_BCR] = {0x25000, 0}, 1292 }; 1293 1294 static const struct regmap_config gcc_ipq4019_regmap_config = { 1295 .reg_bits = 32, 1296 .reg_stride = 4, 1297 .val_bits = 32, 1298 .max_register = 0x2dfff, 1299 .fast_io = true, 1300 }; 1301 1302 static const struct qcom_cc_desc gcc_ipq4019_desc = { 1303 .config = &gcc_ipq4019_regmap_config, 1304 .clks = gcc_ipq4019_clocks, 1305 .num_clks = ARRAY_SIZE(gcc_ipq4019_clocks), 1306 .resets = gcc_ipq4019_resets, 1307 .num_resets = ARRAY_SIZE(gcc_ipq4019_resets), 1308 }; 1309 1310 static const struct of_device_id gcc_ipq4019_match_table[] = { 1311 { .compatible = "qcom,gcc-ipq4019" }, 1312 { } 1313 }; 1314 MODULE_DEVICE_TABLE(of, gcc_ipq4019_match_table); 1315 1316 static int gcc_ipq4019_probe(struct platform_device *pdev) 1317 { 1318 struct device *dev = &pdev->dev; 1319 1320 clk_register_fixed_rate(dev, "fepll125", "xo", 0, 200000000); 1321 clk_register_fixed_rate(dev, "fepll125dly", "xo", 0, 200000000); 1322 clk_register_fixed_rate(dev, "fepllwcss2g", "xo", 0, 200000000); 1323 clk_register_fixed_rate(dev, "fepllwcss5g", "xo", 0, 200000000); 1324 clk_register_fixed_rate(dev, "fepll200", "xo", 0, 200000000); 1325 clk_register_fixed_rate(dev, "fepll500", "xo", 0, 200000000); 1326 clk_register_fixed_rate(dev, "ddrpllapss", "xo", 0, 666000000); 1327 1328 return qcom_cc_probe(pdev, &gcc_ipq4019_desc); 1329 } 1330 1331 static struct platform_driver gcc_ipq4019_driver = { 1332 .probe = gcc_ipq4019_probe, 1333 .driver = { 1334 .name = "qcom,gcc-ipq4019", 1335 .owner = THIS_MODULE, 1336 .of_match_table = gcc_ipq4019_match_table, 1337 }, 1338 }; 1339 1340 static int __init gcc_ipq4019_init(void) 1341 { 1342 return platform_driver_register(&gcc_ipq4019_driver); 1343 } 1344 core_initcall(gcc_ipq4019_init); 1345 1346 static void __exit gcc_ipq4019_exit(void) 1347 { 1348 platform_driver_unregister(&gcc_ipq4019_driver); 1349 } 1350 module_exit(gcc_ipq4019_exit); 1351 1352 MODULE_ALIAS("platform:gcc-ipq4019"); 1353 MODULE_LICENSE("GPL v2"); 1354 MODULE_DESCRIPTION("QCOM GCC IPQ4019 driver"); 1355