1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/module.h> 8 #include <linux/platform_device.h> 9 #include <linux/regmap.h> 10 #include <linux/reset-controller.h> 11 12 #include <dt-bindings/clock/qcom,dispcc-sm8250.h> 13 14 #include "clk-alpha-pll.h" 15 #include "clk-branch.h" 16 #include "clk-rcg.h" 17 #include "clk-regmap-divider.h" 18 #include "common.h" 19 #include "gdsc.h" 20 #include "reset.h" 21 22 enum { 23 P_BI_TCXO, 24 P_DISP_CC_PLL0_OUT_MAIN, 25 P_DISP_CC_PLL1_OUT_EVEN, 26 P_DISP_CC_PLL1_OUT_MAIN, 27 P_DP_PHY_PLL_LINK_CLK, 28 P_DP_PHY_PLL_VCO_DIV_CLK, 29 P_EDP_PHY_PLL_LINK_CLK, 30 P_EDP_PHY_PLL_VCO_DIV_CLK, 31 P_DSI0_PHY_PLL_OUT_BYTECLK, 32 P_DSI0_PHY_PLL_OUT_DSICLK, 33 P_DSI1_PHY_PLL_OUT_BYTECLK, 34 P_DSI1_PHY_PLL_OUT_DSICLK, 35 }; 36 37 static struct pll_vco vco_table[] = { 38 { 249600000, 2000000000, 0 }, 39 }; 40 41 static struct alpha_pll_config disp_cc_pll0_config = { 42 .l = 0x47, 43 .alpha = 0xE000, 44 .config_ctl_val = 0x20485699, 45 .config_ctl_hi_val = 0x00002261, 46 .config_ctl_hi1_val = 0x329A699C, 47 .user_ctl_val = 0x00000000, 48 .user_ctl_hi_val = 0x00000805, 49 .user_ctl_hi1_val = 0x00000000, 50 }; 51 52 static struct clk_init_data disp_cc_pll0_init = { 53 .name = "disp_cc_pll0", 54 .parent_data = &(const struct clk_parent_data){ 55 .fw_name = "bi_tcxo", 56 }, 57 .num_parents = 1, 58 .ops = &clk_alpha_pll_lucid_ops, 59 }; 60 61 static struct clk_alpha_pll disp_cc_pll0 = { 62 .offset = 0x0, 63 .vco_table = vco_table, 64 .num_vco = ARRAY_SIZE(vco_table), 65 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 66 .clkr.hw.init = &disp_cc_pll0_init 67 }; 68 69 static struct alpha_pll_config disp_cc_pll1_config = { 70 .l = 0x1F, 71 .alpha = 0x4000, 72 .config_ctl_val = 0x20485699, 73 .config_ctl_hi_val = 0x00002261, 74 .config_ctl_hi1_val = 0x329A699C, 75 .user_ctl_val = 0x00000000, 76 .user_ctl_hi_val = 0x00000805, 77 .user_ctl_hi1_val = 0x00000000, 78 }; 79 80 static struct clk_init_data disp_cc_pll1_init = { 81 .name = "disp_cc_pll1", 82 .parent_data = &(const struct clk_parent_data){ 83 .fw_name = "bi_tcxo", 84 }, 85 .num_parents = 1, 86 .ops = &clk_alpha_pll_lucid_ops, 87 }; 88 89 static struct clk_alpha_pll disp_cc_pll1 = { 90 .offset = 0x1000, 91 .vco_table = vco_table, 92 .num_vco = ARRAY_SIZE(vco_table), 93 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 94 .clkr.hw.init = &disp_cc_pll1_init 95 }; 96 97 static const struct parent_map disp_cc_parent_map_0[] = { 98 { P_BI_TCXO, 0 }, 99 { P_DP_PHY_PLL_LINK_CLK, 1 }, 100 { P_DP_PHY_PLL_VCO_DIV_CLK, 2 }, 101 }; 102 103 static const struct clk_parent_data disp_cc_parent_data_0[] = { 104 { .fw_name = "bi_tcxo" }, 105 { .fw_name = "dp_phy_pll_link_clk" }, 106 { .fw_name = "dp_phy_pll_vco_div_clk" }, 107 }; 108 109 static const struct parent_map disp_cc_parent_map_1[] = { 110 { P_BI_TCXO, 0 }, 111 }; 112 113 static const struct clk_parent_data disp_cc_parent_data_1[] = { 114 { .fw_name = "bi_tcxo" }, 115 }; 116 117 static const struct parent_map disp_cc_parent_map_2[] = { 118 { P_BI_TCXO, 0 }, 119 { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 }, 120 { P_DSI1_PHY_PLL_OUT_BYTECLK, 2 }, 121 }; 122 123 static const struct clk_parent_data disp_cc_parent_data_2[] = { 124 { .fw_name = "bi_tcxo" }, 125 { .fw_name = "dsi0_phy_pll_out_byteclk" }, 126 { .fw_name = "dsi1_phy_pll_out_byteclk" }, 127 }; 128 129 static const struct parent_map disp_cc_parent_map_3[] = { 130 { P_BI_TCXO, 0 }, 131 { P_DISP_CC_PLL1_OUT_MAIN, 4 }, 132 }; 133 134 static const struct clk_parent_data disp_cc_parent_data_3[] = { 135 { .fw_name = "bi_tcxo" }, 136 { .hw = &disp_cc_pll1.clkr.hw }, 137 }; 138 139 static const struct parent_map disp_cc_parent_map_4[] = { 140 { P_BI_TCXO, 0 }, 141 { P_EDP_PHY_PLL_LINK_CLK, 1 }, 142 { P_EDP_PHY_PLL_VCO_DIV_CLK, 2}, 143 }; 144 145 static const struct clk_parent_data disp_cc_parent_data_4[] = { 146 { .fw_name = "bi_tcxo" }, 147 { .fw_name = "edp_phy_pll_link_clk" }, 148 { .fw_name = "edp_phy_pll_vco_div_clk" }, 149 }; 150 151 static const struct parent_map disp_cc_parent_map_5[] = { 152 { P_BI_TCXO, 0 }, 153 { P_DISP_CC_PLL0_OUT_MAIN, 1 }, 154 { P_DISP_CC_PLL1_OUT_MAIN, 4 }, 155 }; 156 157 static const struct clk_parent_data disp_cc_parent_data_5[] = { 158 { .fw_name = "bi_tcxo" }, 159 { .hw = &disp_cc_pll0.clkr.hw }, 160 { .hw = &disp_cc_pll1.clkr.hw }, 161 }; 162 163 static const struct parent_map disp_cc_parent_map_6[] = { 164 { P_BI_TCXO, 0 }, 165 { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, 166 { P_DSI1_PHY_PLL_OUT_DSICLK, 2 }, 167 }; 168 169 static const struct clk_parent_data disp_cc_parent_data_6[] = { 170 { .fw_name = "bi_tcxo" }, 171 { .fw_name = "dsi0_phy_pll_out_dsiclk" }, 172 { .fw_name = "dsi1_phy_pll_out_dsiclk" }, 173 }; 174 175 static const struct parent_map disp_cc_parent_map_7[] = { 176 { P_BI_TCXO, 0 }, 177 { P_DISP_CC_PLL1_OUT_MAIN, 4 }, 178 /* { P_DISP_CC_PLL1_OUT_EVEN, 5 }, */ 179 }; 180 181 static const struct clk_parent_data disp_cc_parent_data_7[] = { 182 { .fw_name = "bi_tcxo" }, 183 { .hw = &disp_cc_pll1.clkr.hw }, 184 /* { .hw = &disp_cc_pll1_out_even.clkr.hw }, */ 185 }; 186 187 static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = { 188 F(19200000, P_BI_TCXO, 1, 0, 0), 189 F(37500000, P_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0), 190 F(75000000, P_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0), 191 { } 192 }; 193 194 static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = { 195 .cmd_rcgr = 0x22bc, 196 .mnd_width = 0, 197 .hid_width = 5, 198 .parent_map = disp_cc_parent_map_3, 199 .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src, 200 .clkr.hw.init = &(struct clk_init_data){ 201 .name = "disp_cc_mdss_ahb_clk_src", 202 .parent_data = disp_cc_parent_data_3, 203 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 204 .flags = CLK_SET_RATE_PARENT, 205 .ops = &clk_rcg2_shared_ops, 206 }, 207 }; 208 209 static const struct freq_tbl ftbl_disp_cc_mdss_byte0_clk_src[] = { 210 F(19200000, P_BI_TCXO, 1, 0, 0), 211 { } 212 }; 213 214 static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = { 215 .cmd_rcgr = 0x2110, 216 .mnd_width = 0, 217 .hid_width = 5, 218 .parent_map = disp_cc_parent_map_2, 219 .clkr.hw.init = &(struct clk_init_data){ 220 .name = "disp_cc_mdss_byte0_clk_src", 221 .parent_data = disp_cc_parent_data_2, 222 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 223 .flags = CLK_SET_RATE_PARENT, 224 .ops = &clk_byte2_ops, 225 }, 226 }; 227 228 static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = { 229 .cmd_rcgr = 0x212c, 230 .mnd_width = 0, 231 .hid_width = 5, 232 .parent_map = disp_cc_parent_map_2, 233 .clkr.hw.init = &(struct clk_init_data){ 234 .name = "disp_cc_mdss_byte1_clk_src", 235 .parent_data = disp_cc_parent_data_2, 236 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 237 .flags = CLK_SET_RATE_PARENT, 238 .ops = &clk_byte2_ops, 239 }, 240 }; 241 242 static struct clk_rcg2 disp_cc_mdss_dp_aux1_clk_src = { 243 .cmd_rcgr = 0x2240, 244 .mnd_width = 0, 245 .hid_width = 5, 246 .parent_map = disp_cc_parent_map_1, 247 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 248 .clkr.hw.init = &(struct clk_init_data){ 249 .name = "disp_cc_mdss_dp_aux1_clk_src", 250 .parent_data = disp_cc_parent_data_1, 251 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 252 .flags = CLK_SET_RATE_PARENT, 253 .ops = &clk_rcg2_ops, 254 }, 255 }; 256 257 static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = { 258 .cmd_rcgr = 0x21dc, 259 .mnd_width = 0, 260 .hid_width = 5, 261 .parent_map = disp_cc_parent_map_1, 262 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 263 .clkr.hw.init = &(struct clk_init_data){ 264 .name = "disp_cc_mdss_dp_aux_clk_src", 265 .parent_data = disp_cc_parent_data_1, 266 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 267 .flags = CLK_SET_RATE_PARENT, 268 .ops = &clk_rcg2_ops, 269 }, 270 }; 271 272 static const struct freq_tbl ftbl_disp_cc_mdss_dp_link1_clk_src[] = { 273 F(162000000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), 274 F(270000000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), 275 F(540000000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), 276 F(810000000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), 277 { } 278 }; 279 280 static struct clk_rcg2 disp_cc_mdss_dp_link1_clk_src = { 281 .cmd_rcgr = 0x220c, 282 .mnd_width = 0, 283 .hid_width = 5, 284 .parent_map = disp_cc_parent_map_0, 285 .freq_tbl = ftbl_disp_cc_mdss_dp_link1_clk_src, 286 .clkr.hw.init = &(struct clk_init_data){ 287 .name = "disp_cc_mdss_dp_link1_clk_src", 288 .parent_data = disp_cc_parent_data_0, 289 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 290 .ops = &clk_byte2_ops, 291 }, 292 }; 293 294 static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = { 295 .cmd_rcgr = 0x2178, 296 .mnd_width = 0, 297 .hid_width = 5, 298 .parent_map = disp_cc_parent_map_0, 299 .freq_tbl = ftbl_disp_cc_mdss_dp_link1_clk_src, 300 .clkr.hw.init = &(struct clk_init_data){ 301 .name = "disp_cc_mdss_dp_link_clk_src", 302 .parent_data = disp_cc_parent_data_0, 303 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 304 .ops = &clk_byte2_ops, 305 }, 306 }; 307 308 static struct clk_rcg2 disp_cc_mdss_dp_pixel1_clk_src = { 309 .cmd_rcgr = 0x21c4, 310 .mnd_width = 16, 311 .hid_width = 5, 312 .parent_map = disp_cc_parent_map_0, 313 .clkr.hw.init = &(struct clk_init_data){ 314 .name = "disp_cc_mdss_dp_pixel1_clk_src", 315 .parent_data = disp_cc_parent_data_0, 316 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 317 .ops = &clk_dp_ops, 318 }, 319 }; 320 321 static struct clk_rcg2 disp_cc_mdss_dp_pixel2_clk_src = { 322 .cmd_rcgr = 0x21f4, 323 .mnd_width = 16, 324 .hid_width = 5, 325 .parent_map = disp_cc_parent_map_0, 326 .clkr.hw.init = &(struct clk_init_data){ 327 .name = "disp_cc_mdss_dp_pixel2_clk_src", 328 .parent_data = disp_cc_parent_data_0, 329 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 330 .ops = &clk_dp_ops, 331 }, 332 }; 333 334 static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = { 335 .cmd_rcgr = 0x21ac, 336 .mnd_width = 16, 337 .hid_width = 5, 338 .parent_map = disp_cc_parent_map_0, 339 .clkr.hw.init = &(struct clk_init_data){ 340 .name = "disp_cc_mdss_dp_pixel_clk_src", 341 .parent_data = disp_cc_parent_data_0, 342 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 343 .ops = &clk_dp_ops, 344 }, 345 }; 346 347 static struct clk_rcg2 disp_cc_mdss_edp_aux_clk_src = { 348 .cmd_rcgr = 0x228c, 349 .mnd_width = 0, 350 .hid_width = 5, 351 .parent_map = disp_cc_parent_map_1, 352 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 353 .clkr.hw.init = &(struct clk_init_data){ 354 .name = "disp_cc_mdss_edp_aux_clk_src", 355 .parent_data = disp_cc_parent_data_1, 356 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 357 .flags = CLK_SET_RATE_PARENT, 358 .ops = &clk_rcg2_ops, 359 }, 360 }; 361 362 static struct clk_rcg2 disp_cc_mdss_edp_gtc_clk_src = { 363 .cmd_rcgr = 0x22a4, 364 .mnd_width = 0, 365 .hid_width = 5, 366 .parent_map = disp_cc_parent_map_7, 367 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 368 .clkr.hw.init = &(struct clk_init_data){ 369 .name = "disp_cc_mdss_edp_gtc_clk_src", 370 .parent_data = disp_cc_parent_data_7, 371 .num_parents = ARRAY_SIZE(disp_cc_parent_data_7), 372 .flags = CLK_SET_RATE_PARENT, 373 .ops = &clk_rcg2_ops, 374 }, 375 }; 376 377 static struct clk_rcg2 disp_cc_mdss_edp_link_clk_src = { 378 .cmd_rcgr = 0x2270, 379 .mnd_width = 0, 380 .hid_width = 5, 381 .parent_map = disp_cc_parent_map_4, 382 .clkr.hw.init = &(struct clk_init_data){ 383 .name = "disp_cc_mdss_edp_link_clk_src", 384 .parent_data = disp_cc_parent_data_4, 385 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), 386 .flags = CLK_SET_RATE_PARENT, 387 .ops = &clk_byte2_ops, 388 }, 389 }; 390 391 static struct clk_rcg2 disp_cc_mdss_edp_pixel_clk_src = { 392 .cmd_rcgr = 0x2258, 393 .mnd_width = 16, 394 .hid_width = 5, 395 .parent_map = disp_cc_parent_map_4, 396 .clkr.hw.init = &(struct clk_init_data){ 397 .name = "disp_cc_mdss_edp_pixel_clk_src", 398 .parent_data = disp_cc_parent_data_4, 399 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), 400 .ops = &clk_dp_ops, 401 }, 402 }; 403 404 static struct clk_branch disp_cc_mdss_edp_aux_clk = { 405 .halt_reg = 0x2078, 406 .halt_check = BRANCH_HALT, 407 .clkr = { 408 .enable_reg = 0x2078, 409 .enable_mask = BIT(0), 410 .hw.init = &(struct clk_init_data){ 411 .name = "disp_cc_mdss_edp_aux_clk", 412 .parent_hws = (const struct clk_hw*[]){ 413 &disp_cc_mdss_edp_aux_clk_src.clkr.hw, 414 }, 415 .num_parents = 1, 416 .flags = CLK_SET_RATE_PARENT, 417 .ops = &clk_branch2_ops, 418 }, 419 }, 420 }; 421 422 static struct clk_branch disp_cc_mdss_edp_gtc_clk = { 423 .halt_reg = 0x207c, 424 .halt_check = BRANCH_HALT, 425 .clkr = { 426 .enable_reg = 0x207c, 427 .enable_mask = BIT(0), 428 .hw.init = &(struct clk_init_data){ 429 .name = "disp_cc_mdss_edp_gtc_clk", 430 .parent_hws = (const struct clk_hw*[]){ 431 &disp_cc_mdss_edp_gtc_clk_src.clkr.hw, 432 }, 433 .num_parents = 1, 434 .flags = CLK_SET_RATE_PARENT, 435 .ops = &clk_branch2_ops, 436 }, 437 }, 438 }; 439 440 static struct clk_branch disp_cc_mdss_edp_link_clk = { 441 .halt_reg = 0x2070, 442 .halt_check = BRANCH_HALT, 443 .clkr = { 444 .enable_reg = 0x2070, 445 .enable_mask = BIT(0), 446 .hw.init = &(struct clk_init_data){ 447 .name = "disp_cc_mdss_edp_link_clk", 448 .parent_hws = (const struct clk_hw*[]){ 449 &disp_cc_mdss_edp_link_clk_src.clkr.hw, 450 }, 451 .num_parents = 1, 452 .flags = CLK_SET_RATE_PARENT, 453 .ops = &clk_branch2_ops, 454 }, 455 }, 456 }; 457 458 static struct clk_branch disp_cc_mdss_edp_link_intf_clk = { 459 .halt_reg = 0x2074, 460 .halt_check = BRANCH_HALT, 461 .clkr = { 462 .enable_reg = 0x2074, 463 .enable_mask = BIT(0), 464 .hw.init = &(struct clk_init_data){ 465 .name = "disp_cc_mdss_edp_link_intf_clk", 466 .parent_hws = (const struct clk_hw*[]){ 467 &disp_cc_mdss_edp_link_clk_src.clkr.hw, 468 }, 469 .num_parents = 1, 470 .flags = CLK_GET_RATE_NOCACHE, 471 .ops = &clk_branch2_ops, 472 }, 473 }, 474 }; 475 476 static struct clk_branch disp_cc_mdss_edp_pixel_clk = { 477 .halt_reg = 0x206c, 478 .halt_check = BRANCH_HALT, 479 .clkr = { 480 .enable_reg = 0x206c, 481 .enable_mask = BIT(0), 482 .hw.init = &(struct clk_init_data){ 483 .name = "disp_cc_mdss_edp_pixel_clk", 484 .parent_hws = (const struct clk_hw*[]){ 485 &disp_cc_mdss_edp_pixel_clk_src.clkr.hw, 486 }, 487 .num_parents = 1, 488 .flags = CLK_SET_RATE_PARENT, 489 .ops = &clk_branch2_ops, 490 }, 491 }, 492 }; 493 494 static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = { 495 .cmd_rcgr = 0x2148, 496 .mnd_width = 0, 497 .hid_width = 5, 498 .parent_map = disp_cc_parent_map_2, 499 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 500 .clkr.hw.init = &(struct clk_init_data){ 501 .name = "disp_cc_mdss_esc0_clk_src", 502 .parent_data = disp_cc_parent_data_2, 503 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 504 .flags = CLK_SET_RATE_PARENT, 505 .ops = &clk_rcg2_ops, 506 }, 507 }; 508 509 static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = { 510 .cmd_rcgr = 0x2160, 511 .mnd_width = 0, 512 .hid_width = 5, 513 .parent_map = disp_cc_parent_map_2, 514 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 515 .clkr.hw.init = &(struct clk_init_data){ 516 .name = "disp_cc_mdss_esc1_clk_src", 517 .parent_data = disp_cc_parent_data_2, 518 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 519 .flags = CLK_SET_RATE_PARENT, 520 .ops = &clk_rcg2_ops, 521 }, 522 }; 523 524 static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = { 525 F(19200000, P_BI_TCXO, 1, 0, 0), 526 F(85714286, P_DISP_CC_PLL1_OUT_MAIN, 7, 0, 0), 527 F(100000000, P_DISP_CC_PLL1_OUT_MAIN, 6, 0, 0), 528 F(150000000, P_DISP_CC_PLL1_OUT_MAIN, 4, 0, 0), 529 F(200000000, P_DISP_CC_PLL1_OUT_MAIN, 3, 0, 0), 530 F(300000000, P_DISP_CC_PLL1_OUT_MAIN, 2, 0, 0), 531 F(345000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0), 532 F(460000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 533 { } 534 }; 535 536 static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = { 537 .cmd_rcgr = 0x20c8, 538 .mnd_width = 0, 539 .hid_width = 5, 540 .parent_map = disp_cc_parent_map_5, 541 .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src, 542 .clkr.hw.init = &(struct clk_init_data){ 543 .name = "disp_cc_mdss_mdp_clk_src", 544 .parent_data = disp_cc_parent_data_5, 545 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), 546 .flags = CLK_SET_RATE_PARENT, 547 .ops = &clk_rcg2_shared_ops, 548 }, 549 }; 550 551 static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = { 552 .cmd_rcgr = 0x2098, 553 .mnd_width = 8, 554 .hid_width = 5, 555 .parent_map = disp_cc_parent_map_6, 556 .clkr.hw.init = &(struct clk_init_data){ 557 .name = "disp_cc_mdss_pclk0_clk_src", 558 .parent_data = disp_cc_parent_data_6, 559 .num_parents = ARRAY_SIZE(disp_cc_parent_data_6), 560 .flags = CLK_SET_RATE_PARENT, 561 .ops = &clk_pixel_ops, 562 }, 563 }; 564 565 static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = { 566 .cmd_rcgr = 0x20b0, 567 .mnd_width = 8, 568 .hid_width = 5, 569 .parent_map = disp_cc_parent_map_6, 570 .clkr.hw.init = &(struct clk_init_data){ 571 .name = "disp_cc_mdss_pclk1_clk_src", 572 .parent_data = disp_cc_parent_data_6, 573 .num_parents = ARRAY_SIZE(disp_cc_parent_data_6), 574 .flags = CLK_SET_RATE_PARENT, 575 .ops = &clk_pixel_ops, 576 }, 577 }; 578 579 static const struct freq_tbl ftbl_disp_cc_mdss_rot_clk_src[] = { 580 F(19200000, P_BI_TCXO, 1, 0, 0), 581 F(200000000, P_DISP_CC_PLL1_OUT_MAIN, 3, 0, 0), 582 F(300000000, P_DISP_CC_PLL1_OUT_MAIN, 2, 0, 0), 583 F(345000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0), 584 F(460000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 585 { } 586 }; 587 588 static struct clk_rcg2 disp_cc_mdss_rot_clk_src = { 589 .cmd_rcgr = 0x20e0, 590 .mnd_width = 0, 591 .hid_width = 5, 592 .parent_map = disp_cc_parent_map_5, 593 .freq_tbl = ftbl_disp_cc_mdss_rot_clk_src, 594 .clkr.hw.init = &(struct clk_init_data){ 595 .name = "disp_cc_mdss_rot_clk_src", 596 .parent_data = disp_cc_parent_data_5, 597 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), 598 .flags = CLK_SET_RATE_PARENT, 599 .ops = &clk_rcg2_shared_ops, 600 }, 601 }; 602 603 static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = { 604 .cmd_rcgr = 0x20f8, 605 .mnd_width = 0, 606 .hid_width = 5, 607 .parent_map = disp_cc_parent_map_1, 608 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 609 .clkr.hw.init = &(struct clk_init_data){ 610 .name = "disp_cc_mdss_vsync_clk_src", 611 .parent_data = disp_cc_parent_data_1, 612 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 613 .flags = CLK_SET_RATE_PARENT, 614 .ops = &clk_rcg2_ops, 615 }, 616 }; 617 618 static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = { 619 .reg = 0x2128, 620 .shift = 0, 621 .width = 2, 622 .clkr.hw.init = &(struct clk_init_data) { 623 .name = "disp_cc_mdss_byte0_div_clk_src", 624 .parent_hws = (const struct clk_hw*[]){ 625 &disp_cc_mdss_byte0_clk_src.clkr.hw, 626 }, 627 .num_parents = 1, 628 .ops = &clk_regmap_div_ops, 629 }, 630 }; 631 632 633 static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = { 634 .reg = 0x2144, 635 .shift = 0, 636 .width = 2, 637 .clkr.hw.init = &(struct clk_init_data) { 638 .name = "disp_cc_mdss_byte1_div_clk_src", 639 .parent_hws = (const struct clk_hw*[]){ 640 &disp_cc_mdss_byte1_clk_src.clkr.hw, 641 }, 642 .num_parents = 1, 643 .ops = &clk_regmap_div_ops, 644 }, 645 }; 646 647 648 static struct clk_regmap_div disp_cc_mdss_dp_link1_div_clk_src = { 649 .reg = 0x2224, 650 .shift = 0, 651 .width = 2, 652 .clkr.hw.init = &(struct clk_init_data) { 653 .name = "disp_cc_mdss_dp_link1_div_clk_src", 654 .parent_hws = (const struct clk_hw*[]){ 655 &disp_cc_mdss_dp_link1_clk_src.clkr.hw, 656 }, 657 .num_parents = 1, 658 .ops = &clk_regmap_div_ro_ops, 659 }, 660 }; 661 662 663 static struct clk_regmap_div disp_cc_mdss_dp_link_div_clk_src = { 664 .reg = 0x2190, 665 .shift = 0, 666 .width = 2, 667 .clkr.hw.init = &(struct clk_init_data) { 668 .name = "disp_cc_mdss_dp_link_div_clk_src", 669 .parent_hws = (const struct clk_hw*[]){ 670 &disp_cc_mdss_dp_link_clk_src.clkr.hw, 671 }, 672 .num_parents = 1, 673 .ops = &clk_regmap_div_ro_ops, 674 }, 675 }; 676 677 static struct clk_branch disp_cc_mdss_ahb_clk = { 678 .halt_reg = 0x2080, 679 .halt_check = BRANCH_HALT, 680 .clkr = { 681 .enable_reg = 0x2080, 682 .enable_mask = BIT(0), 683 .hw.init = &(struct clk_init_data){ 684 .name = "disp_cc_mdss_ahb_clk", 685 .parent_hws = (const struct clk_hw*[]){ 686 &disp_cc_mdss_ahb_clk_src.clkr.hw, 687 }, 688 .num_parents = 1, 689 .flags = CLK_SET_RATE_PARENT, 690 .ops = &clk_branch2_ops, 691 }, 692 }, 693 }; 694 695 static struct clk_branch disp_cc_mdss_byte0_clk = { 696 .halt_reg = 0x2028, 697 .halt_check = BRANCH_HALT, 698 .clkr = { 699 .enable_reg = 0x2028, 700 .enable_mask = BIT(0), 701 .hw.init = &(struct clk_init_data){ 702 .name = "disp_cc_mdss_byte0_clk", 703 .parent_hws = (const struct clk_hw*[]){ 704 &disp_cc_mdss_byte0_clk_src.clkr.hw, 705 }, 706 .num_parents = 1, 707 .flags = CLK_SET_RATE_PARENT, 708 .ops = &clk_branch2_ops, 709 }, 710 }, 711 }; 712 713 static struct clk_branch disp_cc_mdss_byte0_intf_clk = { 714 .halt_reg = 0x202c, 715 .halt_check = BRANCH_HALT, 716 .clkr = { 717 .enable_reg = 0x202c, 718 .enable_mask = BIT(0), 719 .hw.init = &(struct clk_init_data){ 720 .name = "disp_cc_mdss_byte0_intf_clk", 721 .parent_hws = (const struct clk_hw*[]){ 722 &disp_cc_mdss_byte0_div_clk_src.clkr.hw, 723 }, 724 .num_parents = 1, 725 .flags = CLK_SET_RATE_PARENT, 726 .ops = &clk_branch2_ops, 727 }, 728 }, 729 }; 730 731 static struct clk_branch disp_cc_mdss_byte1_clk = { 732 .halt_reg = 0x2030, 733 .halt_check = BRANCH_HALT, 734 .clkr = { 735 .enable_reg = 0x2030, 736 .enable_mask = BIT(0), 737 .hw.init = &(struct clk_init_data){ 738 .name = "disp_cc_mdss_byte1_clk", 739 .parent_hws = (const struct clk_hw*[]){ 740 &disp_cc_mdss_byte1_clk_src.clkr.hw, 741 }, 742 .num_parents = 1, 743 .flags = CLK_SET_RATE_PARENT, 744 .ops = &clk_branch2_ops, 745 }, 746 }, 747 }; 748 749 static struct clk_branch disp_cc_mdss_byte1_intf_clk = { 750 .halt_reg = 0x2034, 751 .halt_check = BRANCH_HALT, 752 .clkr = { 753 .enable_reg = 0x2034, 754 .enable_mask = BIT(0), 755 .hw.init = &(struct clk_init_data){ 756 .name = "disp_cc_mdss_byte1_intf_clk", 757 .parent_hws = (const struct clk_hw*[]){ 758 &disp_cc_mdss_byte1_div_clk_src.clkr.hw, 759 }, 760 .num_parents = 1, 761 .flags = CLK_SET_RATE_PARENT, 762 .ops = &clk_branch2_ops, 763 }, 764 }, 765 }; 766 767 static struct clk_branch disp_cc_mdss_dp_aux1_clk = { 768 .halt_reg = 0x2068, 769 .halt_check = BRANCH_HALT, 770 .clkr = { 771 .enable_reg = 0x2068, 772 .enable_mask = BIT(0), 773 .hw.init = &(struct clk_init_data){ 774 .name = "disp_cc_mdss_dp_aux1_clk", 775 .parent_hws = (const struct clk_hw*[]){ 776 &disp_cc_mdss_dp_aux1_clk_src.clkr.hw, 777 }, 778 .num_parents = 1, 779 .flags = CLK_SET_RATE_PARENT, 780 .ops = &clk_branch2_ops, 781 }, 782 }, 783 }; 784 785 static struct clk_branch disp_cc_mdss_dp_aux_clk = { 786 .halt_reg = 0x2054, 787 .halt_check = BRANCH_HALT, 788 .clkr = { 789 .enable_reg = 0x2054, 790 .enable_mask = BIT(0), 791 .hw.init = &(struct clk_init_data){ 792 .name = "disp_cc_mdss_dp_aux_clk", 793 .parent_hws = (const struct clk_hw*[]){ 794 &disp_cc_mdss_dp_aux_clk_src.clkr.hw, 795 }, 796 .num_parents = 1, 797 .flags = CLK_SET_RATE_PARENT, 798 .ops = &clk_branch2_ops, 799 }, 800 }, 801 }; 802 803 static struct clk_branch disp_cc_mdss_dp_link1_clk = { 804 .halt_reg = 0x205c, 805 .halt_check = BRANCH_HALT, 806 .clkr = { 807 .enable_reg = 0x205c, 808 .enable_mask = BIT(0), 809 .hw.init = &(struct clk_init_data){ 810 .name = "disp_cc_mdss_dp_link1_clk", 811 .parent_hws = (const struct clk_hw*[]){ 812 &disp_cc_mdss_dp_link1_clk_src.clkr.hw, 813 }, 814 .num_parents = 1, 815 .flags = CLK_SET_RATE_PARENT, 816 .ops = &clk_branch2_ops, 817 }, 818 }, 819 }; 820 821 static struct clk_branch disp_cc_mdss_dp_link1_intf_clk = { 822 .halt_reg = 0x2060, 823 .halt_check = BRANCH_HALT, 824 .clkr = { 825 .enable_reg = 0x2060, 826 .enable_mask = BIT(0), 827 .hw.init = &(struct clk_init_data){ 828 .name = "disp_cc_mdss_dp_link1_intf_clk", 829 .parent_hws = (const struct clk_hw*[]){ 830 &disp_cc_mdss_dp_link1_div_clk_src.clkr.hw, 831 }, 832 .num_parents = 1, 833 .ops = &clk_branch2_ops, 834 }, 835 }, 836 }; 837 838 static struct clk_branch disp_cc_mdss_dp_link_clk = { 839 .halt_reg = 0x2040, 840 .halt_check = BRANCH_HALT, 841 .clkr = { 842 .enable_reg = 0x2040, 843 .enable_mask = BIT(0), 844 .hw.init = &(struct clk_init_data){ 845 .name = "disp_cc_mdss_dp_link_clk", 846 .parent_hws = (const struct clk_hw*[]){ 847 &disp_cc_mdss_dp_link_clk_src.clkr.hw, 848 }, 849 .num_parents = 1, 850 .flags = CLK_SET_RATE_PARENT, 851 .ops = &clk_branch2_ops, 852 }, 853 }, 854 }; 855 856 static struct clk_branch disp_cc_mdss_dp_link_intf_clk = { 857 .halt_reg = 0x2044, 858 .halt_check = BRANCH_HALT, 859 .clkr = { 860 .enable_reg = 0x2044, 861 .enable_mask = BIT(0), 862 .hw.init = &(struct clk_init_data){ 863 .name = "disp_cc_mdss_dp_link_intf_clk", 864 .parent_hws = (const struct clk_hw*[]){ 865 &disp_cc_mdss_dp_link_div_clk_src.clkr.hw, 866 }, 867 .num_parents = 1, 868 .ops = &clk_branch2_ops, 869 }, 870 }, 871 }; 872 873 static struct clk_branch disp_cc_mdss_dp_pixel1_clk = { 874 .halt_reg = 0x2050, 875 .halt_check = BRANCH_HALT, 876 .clkr = { 877 .enable_reg = 0x2050, 878 .enable_mask = BIT(0), 879 .hw.init = &(struct clk_init_data){ 880 .name = "disp_cc_mdss_dp_pixel1_clk", 881 .parent_hws = (const struct clk_hw*[]){ 882 &disp_cc_mdss_dp_pixel1_clk_src.clkr.hw, 883 }, 884 .num_parents = 1, 885 .flags = CLK_SET_RATE_PARENT, 886 .ops = &clk_branch2_ops, 887 }, 888 }, 889 }; 890 891 static struct clk_branch disp_cc_mdss_dp_pixel2_clk = { 892 .halt_reg = 0x2058, 893 .halt_check = BRANCH_HALT, 894 .clkr = { 895 .enable_reg = 0x2058, 896 .enable_mask = BIT(0), 897 .hw.init = &(struct clk_init_data){ 898 .name = "disp_cc_mdss_dp_pixel2_clk", 899 .parent_hws = (const struct clk_hw*[]){ 900 &disp_cc_mdss_dp_pixel2_clk_src.clkr.hw, 901 }, 902 .num_parents = 1, 903 .flags = CLK_SET_RATE_PARENT, 904 .ops = &clk_branch2_ops, 905 }, 906 }, 907 }; 908 909 static struct clk_branch disp_cc_mdss_dp_pixel_clk = { 910 .halt_reg = 0x204c, 911 .halt_check = BRANCH_HALT, 912 .clkr = { 913 .enable_reg = 0x204c, 914 .enable_mask = BIT(0), 915 .hw.init = &(struct clk_init_data){ 916 .name = "disp_cc_mdss_dp_pixel_clk", 917 .parent_hws = (const struct clk_hw*[]){ 918 &disp_cc_mdss_dp_pixel_clk_src.clkr.hw, 919 }, 920 .num_parents = 1, 921 .flags = CLK_SET_RATE_PARENT, 922 .ops = &clk_branch2_ops, 923 }, 924 }, 925 }; 926 927 static struct clk_branch disp_cc_mdss_esc0_clk = { 928 .halt_reg = 0x2038, 929 .halt_check = BRANCH_HALT, 930 .clkr = { 931 .enable_reg = 0x2038, 932 .enable_mask = BIT(0), 933 .hw.init = &(struct clk_init_data){ 934 .name = "disp_cc_mdss_esc0_clk", 935 .parent_hws = (const struct clk_hw*[]){ 936 &disp_cc_mdss_esc0_clk_src.clkr.hw, 937 }, 938 .num_parents = 1, 939 .flags = CLK_SET_RATE_PARENT, 940 .ops = &clk_branch2_ops, 941 }, 942 }, 943 }; 944 945 static struct clk_branch disp_cc_mdss_esc1_clk = { 946 .halt_reg = 0x203c, 947 .halt_check = BRANCH_HALT, 948 .clkr = { 949 .enable_reg = 0x203c, 950 .enable_mask = BIT(0), 951 .hw.init = &(struct clk_init_data){ 952 .name = "disp_cc_mdss_esc1_clk", 953 .parent_hws = (const struct clk_hw*[]){ 954 &disp_cc_mdss_esc1_clk_src.clkr.hw, 955 }, 956 .num_parents = 1, 957 .flags = CLK_SET_RATE_PARENT, 958 .ops = &clk_branch2_ops, 959 }, 960 }, 961 }; 962 963 static struct clk_branch disp_cc_mdss_mdp_clk = { 964 .halt_reg = 0x200c, 965 .halt_check = BRANCH_HALT, 966 .clkr = { 967 .enable_reg = 0x200c, 968 .enable_mask = BIT(0), 969 .hw.init = &(struct clk_init_data){ 970 .name = "disp_cc_mdss_mdp_clk", 971 .parent_hws = (const struct clk_hw*[]){ 972 &disp_cc_mdss_mdp_clk_src.clkr.hw, 973 }, 974 .num_parents = 1, 975 .flags = CLK_SET_RATE_PARENT, 976 .ops = &clk_branch2_ops, 977 }, 978 }, 979 }; 980 981 static struct clk_branch disp_cc_mdss_mdp_lut_clk = { 982 .halt_reg = 0x201c, 983 .halt_check = BRANCH_VOTED, 984 .clkr = { 985 .enable_reg = 0x201c, 986 .enable_mask = BIT(0), 987 .hw.init = &(struct clk_init_data){ 988 .name = "disp_cc_mdss_mdp_lut_clk", 989 .parent_hws = (const struct clk_hw*[]){ 990 &disp_cc_mdss_mdp_clk_src.clkr.hw, 991 }, 992 .num_parents = 1, 993 .ops = &clk_branch2_ops, 994 }, 995 }, 996 }; 997 998 static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = { 999 .halt_reg = 0x4004, 1000 .halt_check = BRANCH_VOTED, 1001 .clkr = { 1002 .enable_reg = 0x4004, 1003 .enable_mask = BIT(0), 1004 .hw.init = &(struct clk_init_data){ 1005 .name = "disp_cc_mdss_non_gdsc_ahb_clk", 1006 .parent_hws = (const struct clk_hw*[]){ 1007 &disp_cc_mdss_ahb_clk_src.clkr.hw, 1008 }, 1009 .num_parents = 1, 1010 .flags = CLK_SET_RATE_PARENT, 1011 .ops = &clk_branch2_ops, 1012 }, 1013 }, 1014 }; 1015 1016 static struct clk_branch disp_cc_mdss_pclk0_clk = { 1017 .halt_reg = 0x2004, 1018 .halt_check = BRANCH_HALT, 1019 .clkr = { 1020 .enable_reg = 0x2004, 1021 .enable_mask = BIT(0), 1022 .hw.init = &(struct clk_init_data){ 1023 .name = "disp_cc_mdss_pclk0_clk", 1024 .parent_hws = (const struct clk_hw*[]){ 1025 &disp_cc_mdss_pclk0_clk_src.clkr.hw, 1026 }, 1027 .num_parents = 1, 1028 .flags = CLK_SET_RATE_PARENT, 1029 .ops = &clk_branch2_ops, 1030 }, 1031 }, 1032 }; 1033 1034 static struct clk_branch disp_cc_mdss_pclk1_clk = { 1035 .halt_reg = 0x2008, 1036 .halt_check = BRANCH_HALT, 1037 .clkr = { 1038 .enable_reg = 0x2008, 1039 .enable_mask = BIT(0), 1040 .hw.init = &(struct clk_init_data){ 1041 .name = "disp_cc_mdss_pclk1_clk", 1042 .parent_hws = (const struct clk_hw*[]){ 1043 &disp_cc_mdss_pclk1_clk_src.clkr.hw, 1044 }, 1045 .num_parents = 1, 1046 .flags = CLK_SET_RATE_PARENT, 1047 .ops = &clk_branch2_ops, 1048 }, 1049 }, 1050 }; 1051 1052 static struct clk_branch disp_cc_mdss_rot_clk = { 1053 .halt_reg = 0x2014, 1054 .halt_check = BRANCH_HALT, 1055 .clkr = { 1056 .enable_reg = 0x2014, 1057 .enable_mask = BIT(0), 1058 .hw.init = &(struct clk_init_data){ 1059 .name = "disp_cc_mdss_rot_clk", 1060 .parent_hws = (const struct clk_hw*[]){ 1061 &disp_cc_mdss_rot_clk_src.clkr.hw, 1062 }, 1063 .num_parents = 1, 1064 .flags = CLK_SET_RATE_PARENT, 1065 .ops = &clk_branch2_ops, 1066 }, 1067 }, 1068 }; 1069 1070 static struct clk_branch disp_cc_mdss_rscc_ahb_clk = { 1071 .halt_reg = 0x400c, 1072 .halt_check = BRANCH_HALT, 1073 .clkr = { 1074 .enable_reg = 0x400c, 1075 .enable_mask = BIT(0), 1076 .hw.init = &(struct clk_init_data){ 1077 .name = "disp_cc_mdss_rscc_ahb_clk", 1078 .parent_hws = (const struct clk_hw*[]){ 1079 &disp_cc_mdss_ahb_clk_src.clkr.hw, 1080 }, 1081 .num_parents = 1, 1082 .flags = CLK_SET_RATE_PARENT, 1083 .ops = &clk_branch2_ops, 1084 }, 1085 }, 1086 }; 1087 1088 static struct clk_branch disp_cc_mdss_rscc_vsync_clk = { 1089 .halt_reg = 0x4008, 1090 .halt_check = BRANCH_HALT, 1091 .clkr = { 1092 .enable_reg = 0x4008, 1093 .enable_mask = BIT(0), 1094 .hw.init = &(struct clk_init_data){ 1095 .name = "disp_cc_mdss_rscc_vsync_clk", 1096 .parent_hws = (const struct clk_hw*[]){ 1097 &disp_cc_mdss_vsync_clk_src.clkr.hw, 1098 }, 1099 .num_parents = 1, 1100 .flags = CLK_SET_RATE_PARENT, 1101 .ops = &clk_branch2_ops, 1102 }, 1103 }, 1104 }; 1105 1106 static struct clk_branch disp_cc_mdss_vsync_clk = { 1107 .halt_reg = 0x2024, 1108 .halt_check = BRANCH_HALT, 1109 .clkr = { 1110 .enable_reg = 0x2024, 1111 .enable_mask = BIT(0), 1112 .hw.init = &(struct clk_init_data){ 1113 .name = "disp_cc_mdss_vsync_clk", 1114 .parent_hws = (const struct clk_hw*[]){ 1115 &disp_cc_mdss_vsync_clk_src.clkr.hw, 1116 }, 1117 .num_parents = 1, 1118 .flags = CLK_SET_RATE_PARENT, 1119 .ops = &clk_branch2_ops, 1120 }, 1121 }, 1122 }; 1123 1124 static struct gdsc mdss_gdsc = { 1125 .gdscr = 0x3000, 1126 .pd = { 1127 .name = "mdss_gdsc", 1128 }, 1129 .pwrsts = PWRSTS_OFF_ON, 1130 .flags = HW_CTRL, 1131 .supply = "mmcx", 1132 }; 1133 1134 static struct clk_regmap *disp_cc_sm8250_clocks[] = { 1135 [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr, 1136 [DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr, 1137 [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr, 1138 [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr, 1139 [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr, 1140 [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr, 1141 [DISP_CC_MDSS_BYTE1_CLK] = &disp_cc_mdss_byte1_clk.clkr, 1142 [DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp_cc_mdss_byte1_clk_src.clkr, 1143 [DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] = &disp_cc_mdss_byte1_div_clk_src.clkr, 1144 [DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp_cc_mdss_byte1_intf_clk.clkr, 1145 [DISP_CC_MDSS_DP_AUX1_CLK] = &disp_cc_mdss_dp_aux1_clk.clkr, 1146 [DISP_CC_MDSS_DP_AUX1_CLK_SRC] = &disp_cc_mdss_dp_aux1_clk_src.clkr, 1147 [DISP_CC_MDSS_DP_AUX_CLK] = &disp_cc_mdss_dp_aux_clk.clkr, 1148 [DISP_CC_MDSS_DP_AUX_CLK_SRC] = &disp_cc_mdss_dp_aux_clk_src.clkr, 1149 [DISP_CC_MDSS_DP_LINK1_CLK] = &disp_cc_mdss_dp_link1_clk.clkr, 1150 [DISP_CC_MDSS_DP_LINK1_CLK_SRC] = &disp_cc_mdss_dp_link1_clk_src.clkr, 1151 [DISP_CC_MDSS_DP_LINK1_DIV_CLK_SRC] = &disp_cc_mdss_dp_link1_div_clk_src.clkr, 1152 [DISP_CC_MDSS_DP_LINK1_INTF_CLK] = &disp_cc_mdss_dp_link1_intf_clk.clkr, 1153 [DISP_CC_MDSS_DP_LINK_CLK] = &disp_cc_mdss_dp_link_clk.clkr, 1154 [DISP_CC_MDSS_DP_LINK_CLK_SRC] = &disp_cc_mdss_dp_link_clk_src.clkr, 1155 [DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dp_link_div_clk_src.clkr, 1156 [DISP_CC_MDSS_DP_LINK_INTF_CLK] = &disp_cc_mdss_dp_link_intf_clk.clkr, 1157 [DISP_CC_MDSS_DP_PIXEL1_CLK] = &disp_cc_mdss_dp_pixel1_clk.clkr, 1158 [DISP_CC_MDSS_DP_PIXEL1_CLK_SRC] = &disp_cc_mdss_dp_pixel1_clk_src.clkr, 1159 [DISP_CC_MDSS_DP_PIXEL2_CLK] = &disp_cc_mdss_dp_pixel2_clk.clkr, 1160 [DISP_CC_MDSS_DP_PIXEL2_CLK_SRC] = &disp_cc_mdss_dp_pixel2_clk_src.clkr, 1161 [DISP_CC_MDSS_DP_PIXEL_CLK] = &disp_cc_mdss_dp_pixel_clk.clkr, 1162 [DISP_CC_MDSS_DP_PIXEL_CLK_SRC] = &disp_cc_mdss_dp_pixel_clk_src.clkr, 1163 [DISP_CC_MDSS_EDP_AUX_CLK] = &disp_cc_mdss_edp_aux_clk.clkr, 1164 [DISP_CC_MDSS_EDP_AUX_CLK_SRC] = &disp_cc_mdss_edp_aux_clk_src.clkr, 1165 [DISP_CC_MDSS_EDP_GTC_CLK] = &disp_cc_mdss_edp_gtc_clk.clkr, 1166 [DISP_CC_MDSS_EDP_GTC_CLK_SRC] = &disp_cc_mdss_edp_gtc_clk_src.clkr, 1167 [DISP_CC_MDSS_EDP_LINK_CLK] = &disp_cc_mdss_edp_link_clk.clkr, 1168 [DISP_CC_MDSS_EDP_LINK_CLK_SRC] = &disp_cc_mdss_edp_link_clk_src.clkr, 1169 [DISP_CC_MDSS_EDP_LINK_INTF_CLK] = &disp_cc_mdss_edp_link_intf_clk.clkr, 1170 [DISP_CC_MDSS_EDP_PIXEL_CLK] = &disp_cc_mdss_edp_pixel_clk.clkr, 1171 [DISP_CC_MDSS_EDP_PIXEL_CLK_SRC] = &disp_cc_mdss_edp_pixel_clk_src.clkr, 1172 [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr, 1173 [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr, 1174 [DISP_CC_MDSS_ESC1_CLK] = &disp_cc_mdss_esc1_clk.clkr, 1175 [DISP_CC_MDSS_ESC1_CLK_SRC] = &disp_cc_mdss_esc1_clk_src.clkr, 1176 [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr, 1177 [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr, 1178 [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr, 1179 [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr, 1180 [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr, 1181 [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr, 1182 [DISP_CC_MDSS_PCLK1_CLK] = &disp_cc_mdss_pclk1_clk.clkr, 1183 [DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp_cc_mdss_pclk1_clk_src.clkr, 1184 [DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr, 1185 [DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr, 1186 [DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr, 1187 [DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr, 1188 [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr, 1189 [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr, 1190 [DISP_CC_PLL0] = &disp_cc_pll0.clkr, 1191 [DISP_CC_PLL1] = &disp_cc_pll1.clkr, 1192 }; 1193 1194 static const struct qcom_reset_map disp_cc_sm8250_resets[] = { 1195 [DISP_CC_MDSS_CORE_BCR] = { 0x2000 }, 1196 [DISP_CC_MDSS_RSCC_BCR] = { 0x4000 }, 1197 }; 1198 1199 static struct gdsc *disp_cc_sm8250_gdscs[] = { 1200 [MDSS_GDSC] = &mdss_gdsc, 1201 }; 1202 1203 static const struct regmap_config disp_cc_sm8250_regmap_config = { 1204 .reg_bits = 32, 1205 .reg_stride = 4, 1206 .val_bits = 32, 1207 .max_register = 0x10000, 1208 .fast_io = true, 1209 }; 1210 1211 static const struct qcom_cc_desc disp_cc_sm8250_desc = { 1212 .config = &disp_cc_sm8250_regmap_config, 1213 .clks = disp_cc_sm8250_clocks, 1214 .num_clks = ARRAY_SIZE(disp_cc_sm8250_clocks), 1215 .resets = disp_cc_sm8250_resets, 1216 .num_resets = ARRAY_SIZE(disp_cc_sm8250_resets), 1217 .gdscs = disp_cc_sm8250_gdscs, 1218 .num_gdscs = ARRAY_SIZE(disp_cc_sm8250_gdscs), 1219 }; 1220 1221 static const struct of_device_id disp_cc_sm8250_match_table[] = { 1222 { .compatible = "qcom,sc8180x-dispcc" }, 1223 { .compatible = "qcom,sm8150-dispcc" }, 1224 { .compatible = "qcom,sm8250-dispcc" }, 1225 { } 1226 }; 1227 MODULE_DEVICE_TABLE(of, disp_cc_sm8250_match_table); 1228 1229 static int disp_cc_sm8250_probe(struct platform_device *pdev) 1230 { 1231 struct regmap *regmap; 1232 1233 regmap = qcom_cc_map(pdev, &disp_cc_sm8250_desc); 1234 if (IS_ERR(regmap)) 1235 return PTR_ERR(regmap); 1236 1237 /* note: trion == lucid, except for the prepare() op */ 1238 BUILD_BUG_ON(CLK_ALPHA_PLL_TYPE_TRION != CLK_ALPHA_PLL_TYPE_LUCID); 1239 if (of_device_is_compatible(pdev->dev.of_node, "qcom,sc8180x-dispcc") || 1240 of_device_is_compatible(pdev->dev.of_node, "qcom,sm8150-dispcc")) { 1241 disp_cc_pll0_config.config_ctl_hi_val = 0x00002267; 1242 disp_cc_pll0_config.config_ctl_hi1_val = 0x00000024; 1243 disp_cc_pll0_config.user_ctl_hi1_val = 0x000000D0; 1244 disp_cc_pll0_init.ops = &clk_alpha_pll_trion_ops; 1245 disp_cc_pll1_config.config_ctl_hi_val = 0x00002267; 1246 disp_cc_pll1_config.config_ctl_hi1_val = 0x00000024; 1247 disp_cc_pll1_config.user_ctl_hi1_val = 0x000000D0; 1248 disp_cc_pll1_init.ops = &clk_alpha_pll_trion_ops; 1249 } 1250 1251 clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); 1252 clk_lucid_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config); 1253 1254 /* Enable clock gating for MDP clocks */ 1255 regmap_update_bits(regmap, 0x8000, 0x10, 0x10); 1256 1257 /* DISP_CC_XO_CLK always-on */ 1258 regmap_update_bits(regmap, 0x605c, BIT(0), BIT(0)); 1259 1260 return qcom_cc_really_probe(pdev, &disp_cc_sm8250_desc, regmap); 1261 } 1262 1263 static struct platform_driver disp_cc_sm8250_driver = { 1264 .probe = disp_cc_sm8250_probe, 1265 .driver = { 1266 .name = "disp_cc-sm8250", 1267 .of_match_table = disp_cc_sm8250_match_table, 1268 }, 1269 }; 1270 1271 static int __init disp_cc_sm8250_init(void) 1272 { 1273 return platform_driver_register(&disp_cc_sm8250_driver); 1274 } 1275 subsys_initcall(disp_cc_sm8250_init); 1276 1277 static void __exit disp_cc_sm8250_exit(void) 1278 { 1279 platform_driver_unregister(&disp_cc_sm8250_driver); 1280 } 1281 module_exit(disp_cc_sm8250_exit); 1282 1283 MODULE_DESCRIPTION("QTI DISPCC SM8250 Driver"); 1284 MODULE_LICENSE("GPL v2"); 1285