1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/module.h> 8 #include <linux/platform_device.h> 9 #include <linux/regmap.h> 10 #include <linux/reset-controller.h> 11 12 #include <dt-bindings/clock/qcom,dispcc-sm8250.h> 13 14 #include "clk-alpha-pll.h" 15 #include "clk-branch.h" 16 #include "clk-rcg.h" 17 #include "clk-regmap-divider.h" 18 #include "common.h" 19 #include "gdsc.h" 20 #include "reset.h" 21 22 enum { 23 P_BI_TCXO, 24 P_DISP_CC_PLL0_OUT_MAIN, 25 P_DISP_CC_PLL1_OUT_EVEN, 26 P_DISP_CC_PLL1_OUT_MAIN, 27 P_DP_PHY_PLL_LINK_CLK, 28 P_DP_PHY_PLL_VCO_DIV_CLK, 29 P_DSI0_PHY_PLL_OUT_BYTECLK, 30 P_DSI0_PHY_PLL_OUT_DSICLK, 31 P_DSI1_PHY_PLL_OUT_BYTECLK, 32 P_DSI1_PHY_PLL_OUT_DSICLK, 33 }; 34 35 static struct pll_vco vco_table[] = { 36 { 249600000, 2000000000, 0 }, 37 }; 38 39 static struct alpha_pll_config disp_cc_pll0_config = { 40 .l = 0x47, 41 .alpha = 0xE000, 42 .config_ctl_val = 0x20485699, 43 .config_ctl_hi_val = 0x00002261, 44 .config_ctl_hi1_val = 0x329A699C, 45 .user_ctl_val = 0x00000000, 46 .user_ctl_hi_val = 0x00000805, 47 .user_ctl_hi1_val = 0x00000000, 48 }; 49 50 static struct clk_init_data disp_cc_pll0_init = { 51 .name = "disp_cc_pll0", 52 .parent_data = &(const struct clk_parent_data){ 53 .fw_name = "bi_tcxo", 54 }, 55 .num_parents = 1, 56 .ops = &clk_alpha_pll_lucid_ops, 57 }; 58 59 static struct clk_alpha_pll disp_cc_pll0 = { 60 .offset = 0x0, 61 .vco_table = vco_table, 62 .num_vco = ARRAY_SIZE(vco_table), 63 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 64 .clkr.hw.init = &disp_cc_pll0_init 65 }; 66 67 static struct alpha_pll_config disp_cc_pll1_config = { 68 .l = 0x1F, 69 .alpha = 0x4000, 70 .config_ctl_val = 0x20485699, 71 .config_ctl_hi_val = 0x00002261, 72 .config_ctl_hi1_val = 0x329A699C, 73 .user_ctl_val = 0x00000000, 74 .user_ctl_hi_val = 0x00000805, 75 .user_ctl_hi1_val = 0x00000000, 76 }; 77 78 static struct clk_init_data disp_cc_pll1_init = { 79 .name = "disp_cc_pll1", 80 .parent_data = &(const struct clk_parent_data){ 81 .fw_name = "bi_tcxo", 82 }, 83 .num_parents = 1, 84 .ops = &clk_alpha_pll_lucid_ops, 85 }; 86 87 static struct clk_alpha_pll disp_cc_pll1 = { 88 .offset = 0x1000, 89 .vco_table = vco_table, 90 .num_vco = ARRAY_SIZE(vco_table), 91 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 92 .clkr.hw.init = &disp_cc_pll1_init 93 }; 94 95 static const struct parent_map disp_cc_parent_map_0[] = { 96 { P_BI_TCXO, 0 }, 97 { P_DP_PHY_PLL_LINK_CLK, 1 }, 98 { P_DP_PHY_PLL_VCO_DIV_CLK, 2 }, 99 }; 100 101 static const struct clk_parent_data disp_cc_parent_data_0[] = { 102 { .fw_name = "bi_tcxo" }, 103 { .fw_name = "dp_phy_pll_link_clk" }, 104 { .fw_name = "dp_phy_pll_vco_div_clk" }, 105 }; 106 107 static const struct parent_map disp_cc_parent_map_1[] = { 108 { P_BI_TCXO, 0 }, 109 }; 110 111 static const struct clk_parent_data disp_cc_parent_data_1[] = { 112 { .fw_name = "bi_tcxo" }, 113 }; 114 115 static const struct parent_map disp_cc_parent_map_2[] = { 116 { P_BI_TCXO, 0 }, 117 { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 }, 118 { P_DSI1_PHY_PLL_OUT_BYTECLK, 2 }, 119 }; 120 121 static const struct clk_parent_data disp_cc_parent_data_2[] = { 122 { .fw_name = "bi_tcxo" }, 123 { .fw_name = "dsi0_phy_pll_out_byteclk" }, 124 { .fw_name = "dsi1_phy_pll_out_byteclk" }, 125 }; 126 127 static const struct parent_map disp_cc_parent_map_3[] = { 128 { P_BI_TCXO, 0 }, 129 { P_DISP_CC_PLL1_OUT_MAIN, 4 }, 130 }; 131 132 static const struct clk_parent_data disp_cc_parent_data_3[] = { 133 { .fw_name = "bi_tcxo" }, 134 { .hw = &disp_cc_pll1.clkr.hw }, 135 }; 136 137 static const struct parent_map disp_cc_parent_map_5[] = { 138 { P_BI_TCXO, 0 }, 139 { P_DISP_CC_PLL0_OUT_MAIN, 1 }, 140 { P_DISP_CC_PLL1_OUT_MAIN, 4 }, 141 }; 142 143 static const struct clk_parent_data disp_cc_parent_data_5[] = { 144 { .fw_name = "bi_tcxo" }, 145 { .hw = &disp_cc_pll0.clkr.hw }, 146 { .hw = &disp_cc_pll1.clkr.hw }, 147 }; 148 149 static const struct parent_map disp_cc_parent_map_6[] = { 150 { P_BI_TCXO, 0 }, 151 { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, 152 { P_DSI1_PHY_PLL_OUT_DSICLK, 2 }, 153 }; 154 155 static const struct clk_parent_data disp_cc_parent_data_6[] = { 156 { .fw_name = "bi_tcxo" }, 157 { .fw_name = "dsi0_phy_pll_out_dsiclk" }, 158 { .fw_name = "dsi1_phy_pll_out_dsiclk" }, 159 }; 160 161 static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = { 162 F(19200000, P_BI_TCXO, 1, 0, 0), 163 F(37500000, P_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0), 164 F(75000000, P_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0), 165 { } 166 }; 167 168 static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = { 169 .cmd_rcgr = 0x22bc, 170 .mnd_width = 0, 171 .hid_width = 5, 172 .parent_map = disp_cc_parent_map_3, 173 .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src, 174 .clkr.hw.init = &(struct clk_init_data){ 175 .name = "disp_cc_mdss_ahb_clk_src", 176 .parent_data = disp_cc_parent_data_3, 177 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 178 .flags = CLK_SET_RATE_PARENT, 179 .ops = &clk_rcg2_shared_ops, 180 }, 181 }; 182 183 static const struct freq_tbl ftbl_disp_cc_mdss_byte0_clk_src[] = { 184 F(19200000, P_BI_TCXO, 1, 0, 0), 185 { } 186 }; 187 188 static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = { 189 .cmd_rcgr = 0x2110, 190 .mnd_width = 0, 191 .hid_width = 5, 192 .parent_map = disp_cc_parent_map_2, 193 .clkr.hw.init = &(struct clk_init_data){ 194 .name = "disp_cc_mdss_byte0_clk_src", 195 .parent_data = disp_cc_parent_data_2, 196 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 197 .flags = CLK_SET_RATE_PARENT, 198 .ops = &clk_byte2_ops, 199 }, 200 }; 201 202 static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = { 203 .cmd_rcgr = 0x212c, 204 .mnd_width = 0, 205 .hid_width = 5, 206 .parent_map = disp_cc_parent_map_2, 207 .clkr.hw.init = &(struct clk_init_data){ 208 .name = "disp_cc_mdss_byte1_clk_src", 209 .parent_data = disp_cc_parent_data_2, 210 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 211 .flags = CLK_SET_RATE_PARENT, 212 .ops = &clk_byte2_ops, 213 }, 214 }; 215 216 static struct clk_rcg2 disp_cc_mdss_dp_aux1_clk_src = { 217 .cmd_rcgr = 0x2240, 218 .mnd_width = 0, 219 .hid_width = 5, 220 .parent_map = disp_cc_parent_map_1, 221 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 222 .clkr.hw.init = &(struct clk_init_data){ 223 .name = "disp_cc_mdss_dp_aux1_clk_src", 224 .parent_data = disp_cc_parent_data_1, 225 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 226 .flags = CLK_SET_RATE_PARENT, 227 .ops = &clk_rcg2_ops, 228 }, 229 }; 230 231 static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = { 232 .cmd_rcgr = 0x21dc, 233 .mnd_width = 0, 234 .hid_width = 5, 235 .parent_map = disp_cc_parent_map_1, 236 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 237 .clkr.hw.init = &(struct clk_init_data){ 238 .name = "disp_cc_mdss_dp_aux_clk_src", 239 .parent_data = disp_cc_parent_data_1, 240 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 241 .flags = CLK_SET_RATE_PARENT, 242 .ops = &clk_rcg2_ops, 243 }, 244 }; 245 246 static const struct freq_tbl ftbl_disp_cc_mdss_dp_link1_clk_src[] = { 247 F(162000000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), 248 F(270000000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), 249 F(540000000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), 250 F(810000000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), 251 { } 252 }; 253 254 static struct clk_rcg2 disp_cc_mdss_dp_link1_clk_src = { 255 .cmd_rcgr = 0x220c, 256 .mnd_width = 0, 257 .hid_width = 5, 258 .parent_map = disp_cc_parent_map_0, 259 .freq_tbl = ftbl_disp_cc_mdss_dp_link1_clk_src, 260 .clkr.hw.init = &(struct clk_init_data){ 261 .name = "disp_cc_mdss_dp_link1_clk_src", 262 .parent_data = disp_cc_parent_data_0, 263 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 264 .ops = &clk_rcg2_ops, 265 }, 266 }; 267 268 static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = { 269 .cmd_rcgr = 0x2178, 270 .mnd_width = 0, 271 .hid_width = 5, 272 .parent_map = disp_cc_parent_map_0, 273 .freq_tbl = ftbl_disp_cc_mdss_dp_link1_clk_src, 274 .clkr.hw.init = &(struct clk_init_data){ 275 .name = "disp_cc_mdss_dp_link_clk_src", 276 .parent_data = disp_cc_parent_data_0, 277 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 278 .ops = &clk_rcg2_ops, 279 }, 280 }; 281 282 static struct clk_rcg2 disp_cc_mdss_dp_pixel1_clk_src = { 283 .cmd_rcgr = 0x21c4, 284 .mnd_width = 16, 285 .hid_width = 5, 286 .parent_map = disp_cc_parent_map_0, 287 .clkr.hw.init = &(struct clk_init_data){ 288 .name = "disp_cc_mdss_dp_pixel1_clk_src", 289 .parent_data = disp_cc_parent_data_0, 290 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 291 .ops = &clk_dp_ops, 292 }, 293 }; 294 295 static struct clk_rcg2 disp_cc_mdss_dp_pixel2_clk_src = { 296 .cmd_rcgr = 0x21f4, 297 .mnd_width = 16, 298 .hid_width = 5, 299 .parent_map = disp_cc_parent_map_0, 300 .clkr.hw.init = &(struct clk_init_data){ 301 .name = "disp_cc_mdss_dp_pixel2_clk_src", 302 .parent_data = disp_cc_parent_data_0, 303 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 304 .ops = &clk_dp_ops, 305 }, 306 }; 307 308 static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = { 309 .cmd_rcgr = 0x21ac, 310 .mnd_width = 16, 311 .hid_width = 5, 312 .parent_map = disp_cc_parent_map_0, 313 .clkr.hw.init = &(struct clk_init_data){ 314 .name = "disp_cc_mdss_dp_pixel_clk_src", 315 .parent_data = disp_cc_parent_data_0, 316 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 317 .ops = &clk_dp_ops, 318 }, 319 }; 320 321 static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = { 322 .cmd_rcgr = 0x2148, 323 .mnd_width = 0, 324 .hid_width = 5, 325 .parent_map = disp_cc_parent_map_2, 326 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 327 .clkr.hw.init = &(struct clk_init_data){ 328 .name = "disp_cc_mdss_esc0_clk_src", 329 .parent_data = disp_cc_parent_data_2, 330 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 331 .flags = CLK_SET_RATE_PARENT, 332 .ops = &clk_rcg2_ops, 333 }, 334 }; 335 336 static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = { 337 .cmd_rcgr = 0x2160, 338 .mnd_width = 0, 339 .hid_width = 5, 340 .parent_map = disp_cc_parent_map_2, 341 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 342 .clkr.hw.init = &(struct clk_init_data){ 343 .name = "disp_cc_mdss_esc1_clk_src", 344 .parent_data = disp_cc_parent_data_2, 345 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 346 .flags = CLK_SET_RATE_PARENT, 347 .ops = &clk_rcg2_ops, 348 }, 349 }; 350 351 static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = { 352 F(19200000, P_BI_TCXO, 1, 0, 0), 353 F(85714286, P_DISP_CC_PLL1_OUT_MAIN, 7, 0, 0), 354 F(100000000, P_DISP_CC_PLL1_OUT_MAIN, 6, 0, 0), 355 F(150000000, P_DISP_CC_PLL1_OUT_MAIN, 4, 0, 0), 356 F(200000000, P_DISP_CC_PLL1_OUT_MAIN, 3, 0, 0), 357 F(300000000, P_DISP_CC_PLL1_OUT_MAIN, 2, 0, 0), 358 F(345000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0), 359 F(460000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 360 { } 361 }; 362 363 static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = { 364 .cmd_rcgr = 0x20c8, 365 .mnd_width = 0, 366 .hid_width = 5, 367 .parent_map = disp_cc_parent_map_5, 368 .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src, 369 .clkr.hw.init = &(struct clk_init_data){ 370 .name = "disp_cc_mdss_mdp_clk_src", 371 .parent_data = disp_cc_parent_data_5, 372 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), 373 .flags = CLK_SET_RATE_PARENT, 374 .ops = &clk_rcg2_shared_ops, 375 }, 376 }; 377 378 static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = { 379 .cmd_rcgr = 0x2098, 380 .mnd_width = 8, 381 .hid_width = 5, 382 .parent_map = disp_cc_parent_map_6, 383 .clkr.hw.init = &(struct clk_init_data){ 384 .name = "disp_cc_mdss_pclk0_clk_src", 385 .parent_data = disp_cc_parent_data_6, 386 .num_parents = ARRAY_SIZE(disp_cc_parent_data_6), 387 .flags = CLK_SET_RATE_PARENT, 388 .ops = &clk_pixel_ops, 389 }, 390 }; 391 392 static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = { 393 .cmd_rcgr = 0x20b0, 394 .mnd_width = 8, 395 .hid_width = 5, 396 .parent_map = disp_cc_parent_map_6, 397 .clkr.hw.init = &(struct clk_init_data){ 398 .name = "disp_cc_mdss_pclk1_clk_src", 399 .parent_data = disp_cc_parent_data_6, 400 .num_parents = ARRAY_SIZE(disp_cc_parent_data_6), 401 .flags = CLK_SET_RATE_PARENT, 402 .ops = &clk_pixel_ops, 403 }, 404 }; 405 406 static const struct freq_tbl ftbl_disp_cc_mdss_rot_clk_src[] = { 407 F(19200000, P_BI_TCXO, 1, 0, 0), 408 F(200000000, P_DISP_CC_PLL1_OUT_MAIN, 3, 0, 0), 409 F(300000000, P_DISP_CC_PLL1_OUT_MAIN, 2, 0, 0), 410 F(345000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0), 411 F(460000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 412 { } 413 }; 414 415 static struct clk_rcg2 disp_cc_mdss_rot_clk_src = { 416 .cmd_rcgr = 0x20e0, 417 .mnd_width = 0, 418 .hid_width = 5, 419 .parent_map = disp_cc_parent_map_5, 420 .freq_tbl = ftbl_disp_cc_mdss_rot_clk_src, 421 .clkr.hw.init = &(struct clk_init_data){ 422 .name = "disp_cc_mdss_rot_clk_src", 423 .parent_data = disp_cc_parent_data_5, 424 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), 425 .flags = CLK_SET_RATE_PARENT, 426 .ops = &clk_rcg2_shared_ops, 427 }, 428 }; 429 430 static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = { 431 .cmd_rcgr = 0x20f8, 432 .mnd_width = 0, 433 .hid_width = 5, 434 .parent_map = disp_cc_parent_map_1, 435 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 436 .clkr.hw.init = &(struct clk_init_data){ 437 .name = "disp_cc_mdss_vsync_clk_src", 438 .parent_data = disp_cc_parent_data_1, 439 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 440 .flags = CLK_SET_RATE_PARENT, 441 .ops = &clk_rcg2_ops, 442 }, 443 }; 444 445 static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = { 446 .reg = 0x2128, 447 .shift = 0, 448 .width = 2, 449 .clkr.hw.init = &(struct clk_init_data) { 450 .name = "disp_cc_mdss_byte0_div_clk_src", 451 .parent_hws = (const struct clk_hw*[]){ 452 &disp_cc_mdss_byte0_clk_src.clkr.hw, 453 }, 454 .num_parents = 1, 455 .ops = &clk_regmap_div_ops, 456 }, 457 }; 458 459 460 static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = { 461 .reg = 0x2144, 462 .shift = 0, 463 .width = 2, 464 .clkr.hw.init = &(struct clk_init_data) { 465 .name = "disp_cc_mdss_byte1_div_clk_src", 466 .parent_hws = (const struct clk_hw*[]){ 467 &disp_cc_mdss_byte1_clk_src.clkr.hw, 468 }, 469 .num_parents = 1, 470 .ops = &clk_regmap_div_ops, 471 }, 472 }; 473 474 475 static struct clk_regmap_div disp_cc_mdss_dp_link1_div_clk_src = { 476 .reg = 0x2224, 477 .shift = 0, 478 .width = 2, 479 .clkr.hw.init = &(struct clk_init_data) { 480 .name = "disp_cc_mdss_dp_link1_div_clk_src", 481 .parent_hws = (const struct clk_hw*[]){ 482 &disp_cc_mdss_dp_link1_clk_src.clkr.hw, 483 }, 484 .num_parents = 1, 485 .ops = &clk_regmap_div_ro_ops, 486 }, 487 }; 488 489 490 static struct clk_regmap_div disp_cc_mdss_dp_link_div_clk_src = { 491 .reg = 0x2190, 492 .shift = 0, 493 .width = 2, 494 .clkr.hw.init = &(struct clk_init_data) { 495 .name = "disp_cc_mdss_dp_link_div_clk_src", 496 .parent_hws = (const struct clk_hw*[]){ 497 &disp_cc_mdss_dp_link_clk_src.clkr.hw, 498 }, 499 .num_parents = 1, 500 .ops = &clk_regmap_div_ro_ops, 501 }, 502 }; 503 504 static struct clk_branch disp_cc_mdss_ahb_clk = { 505 .halt_reg = 0x2080, 506 .halt_check = BRANCH_HALT, 507 .clkr = { 508 .enable_reg = 0x2080, 509 .enable_mask = BIT(0), 510 .hw.init = &(struct clk_init_data){ 511 .name = "disp_cc_mdss_ahb_clk", 512 .parent_hws = (const struct clk_hw*[]){ 513 &disp_cc_mdss_ahb_clk_src.clkr.hw, 514 }, 515 .num_parents = 1, 516 .flags = CLK_SET_RATE_PARENT, 517 .ops = &clk_branch2_ops, 518 }, 519 }, 520 }; 521 522 static struct clk_branch disp_cc_mdss_byte0_clk = { 523 .halt_reg = 0x2028, 524 .halt_check = BRANCH_HALT, 525 .clkr = { 526 .enable_reg = 0x2028, 527 .enable_mask = BIT(0), 528 .hw.init = &(struct clk_init_data){ 529 .name = "disp_cc_mdss_byte0_clk", 530 .parent_hws = (const struct clk_hw*[]){ 531 &disp_cc_mdss_byte0_clk_src.clkr.hw, 532 }, 533 .num_parents = 1, 534 .flags = CLK_SET_RATE_PARENT, 535 .ops = &clk_branch2_ops, 536 }, 537 }, 538 }; 539 540 static struct clk_branch disp_cc_mdss_byte0_intf_clk = { 541 .halt_reg = 0x202c, 542 .halt_check = BRANCH_HALT, 543 .clkr = { 544 .enable_reg = 0x202c, 545 .enable_mask = BIT(0), 546 .hw.init = &(struct clk_init_data){ 547 .name = "disp_cc_mdss_byte0_intf_clk", 548 .parent_hws = (const struct clk_hw*[]){ 549 &disp_cc_mdss_byte0_div_clk_src.clkr.hw, 550 }, 551 .num_parents = 1, 552 .flags = CLK_SET_RATE_PARENT, 553 .ops = &clk_branch2_ops, 554 }, 555 }, 556 }; 557 558 static struct clk_branch disp_cc_mdss_byte1_clk = { 559 .halt_reg = 0x2030, 560 .halt_check = BRANCH_HALT, 561 .clkr = { 562 .enable_reg = 0x2030, 563 .enable_mask = BIT(0), 564 .hw.init = &(struct clk_init_data){ 565 .name = "disp_cc_mdss_byte1_clk", 566 .parent_hws = (const struct clk_hw*[]){ 567 &disp_cc_mdss_byte1_clk_src.clkr.hw, 568 }, 569 .num_parents = 1, 570 .flags = CLK_SET_RATE_PARENT, 571 .ops = &clk_branch2_ops, 572 }, 573 }, 574 }; 575 576 static struct clk_branch disp_cc_mdss_byte1_intf_clk = { 577 .halt_reg = 0x2034, 578 .halt_check = BRANCH_HALT, 579 .clkr = { 580 .enable_reg = 0x2034, 581 .enable_mask = BIT(0), 582 .hw.init = &(struct clk_init_data){ 583 .name = "disp_cc_mdss_byte1_intf_clk", 584 .parent_hws = (const struct clk_hw*[]){ 585 &disp_cc_mdss_byte1_div_clk_src.clkr.hw, 586 }, 587 .num_parents = 1, 588 .flags = CLK_SET_RATE_PARENT, 589 .ops = &clk_branch2_ops, 590 }, 591 }, 592 }; 593 594 static struct clk_branch disp_cc_mdss_dp_aux1_clk = { 595 .halt_reg = 0x2068, 596 .halt_check = BRANCH_HALT, 597 .clkr = { 598 .enable_reg = 0x2068, 599 .enable_mask = BIT(0), 600 .hw.init = &(struct clk_init_data){ 601 .name = "disp_cc_mdss_dp_aux1_clk", 602 .parent_hws = (const struct clk_hw*[]){ 603 &disp_cc_mdss_dp_aux1_clk_src.clkr.hw, 604 }, 605 .num_parents = 1, 606 .flags = CLK_SET_RATE_PARENT, 607 .ops = &clk_branch2_ops, 608 }, 609 }, 610 }; 611 612 static struct clk_branch disp_cc_mdss_dp_aux_clk = { 613 .halt_reg = 0x2054, 614 .halt_check = BRANCH_HALT, 615 .clkr = { 616 .enable_reg = 0x2054, 617 .enable_mask = BIT(0), 618 .hw.init = &(struct clk_init_data){ 619 .name = "disp_cc_mdss_dp_aux_clk", 620 .parent_hws = (const struct clk_hw*[]){ 621 &disp_cc_mdss_dp_aux_clk_src.clkr.hw, 622 }, 623 .num_parents = 1, 624 .flags = CLK_SET_RATE_PARENT, 625 .ops = &clk_branch2_ops, 626 }, 627 }, 628 }; 629 630 static struct clk_branch disp_cc_mdss_dp_link1_clk = { 631 .halt_reg = 0x205c, 632 .halt_check = BRANCH_HALT, 633 .clkr = { 634 .enable_reg = 0x205c, 635 .enable_mask = BIT(0), 636 .hw.init = &(struct clk_init_data){ 637 .name = "disp_cc_mdss_dp_link1_clk", 638 .parent_hws = (const struct clk_hw*[]){ 639 &disp_cc_mdss_dp_link1_clk_src.clkr.hw, 640 }, 641 .num_parents = 1, 642 .flags = CLK_SET_RATE_PARENT, 643 .ops = &clk_branch2_ops, 644 }, 645 }, 646 }; 647 648 static struct clk_branch disp_cc_mdss_dp_link1_intf_clk = { 649 .halt_reg = 0x2060, 650 .halt_check = BRANCH_HALT, 651 .clkr = { 652 .enable_reg = 0x2060, 653 .enable_mask = BIT(0), 654 .hw.init = &(struct clk_init_data){ 655 .name = "disp_cc_mdss_dp_link1_intf_clk", 656 .parent_hws = (const struct clk_hw*[]){ 657 &disp_cc_mdss_dp_link1_div_clk_src.clkr.hw, 658 }, 659 .num_parents = 1, 660 .ops = &clk_branch2_ops, 661 }, 662 }, 663 }; 664 665 static struct clk_branch disp_cc_mdss_dp_link_clk = { 666 .halt_reg = 0x2040, 667 .halt_check = BRANCH_HALT, 668 .clkr = { 669 .enable_reg = 0x2040, 670 .enable_mask = BIT(0), 671 .hw.init = &(struct clk_init_data){ 672 .name = "disp_cc_mdss_dp_link_clk", 673 .parent_hws = (const struct clk_hw*[]){ 674 &disp_cc_mdss_dp_link_clk_src.clkr.hw, 675 }, 676 .num_parents = 1, 677 .flags = CLK_SET_RATE_PARENT, 678 .ops = &clk_branch2_ops, 679 }, 680 }, 681 }; 682 683 static struct clk_branch disp_cc_mdss_dp_link_intf_clk = { 684 .halt_reg = 0x2044, 685 .halt_check = BRANCH_HALT, 686 .clkr = { 687 .enable_reg = 0x2044, 688 .enable_mask = BIT(0), 689 .hw.init = &(struct clk_init_data){ 690 .name = "disp_cc_mdss_dp_link_intf_clk", 691 .parent_hws = (const struct clk_hw*[]){ 692 &disp_cc_mdss_dp_link_div_clk_src.clkr.hw, 693 }, 694 .num_parents = 1, 695 .ops = &clk_branch2_ops, 696 }, 697 }, 698 }; 699 700 static struct clk_branch disp_cc_mdss_dp_pixel1_clk = { 701 .halt_reg = 0x2050, 702 .halt_check = BRANCH_HALT, 703 .clkr = { 704 .enable_reg = 0x2050, 705 .enable_mask = BIT(0), 706 .hw.init = &(struct clk_init_data){ 707 .name = "disp_cc_mdss_dp_pixel1_clk", 708 .parent_hws = (const struct clk_hw*[]){ 709 &disp_cc_mdss_dp_pixel1_clk_src.clkr.hw, 710 }, 711 .num_parents = 1, 712 .flags = CLK_SET_RATE_PARENT, 713 .ops = &clk_branch2_ops, 714 }, 715 }, 716 }; 717 718 static struct clk_branch disp_cc_mdss_dp_pixel2_clk = { 719 .halt_reg = 0x2058, 720 .halt_check = BRANCH_HALT, 721 .clkr = { 722 .enable_reg = 0x2058, 723 .enable_mask = BIT(0), 724 .hw.init = &(struct clk_init_data){ 725 .name = "disp_cc_mdss_dp_pixel2_clk", 726 .parent_hws = (const struct clk_hw*[]){ 727 &disp_cc_mdss_dp_pixel2_clk_src.clkr.hw, 728 }, 729 .num_parents = 1, 730 .flags = CLK_SET_RATE_PARENT, 731 .ops = &clk_branch2_ops, 732 }, 733 }, 734 }; 735 736 static struct clk_branch disp_cc_mdss_dp_pixel_clk = { 737 .halt_reg = 0x204c, 738 .halt_check = BRANCH_HALT, 739 .clkr = { 740 .enable_reg = 0x204c, 741 .enable_mask = BIT(0), 742 .hw.init = &(struct clk_init_data){ 743 .name = "disp_cc_mdss_dp_pixel_clk", 744 .parent_hws = (const struct clk_hw*[]){ 745 &disp_cc_mdss_dp_pixel_clk_src.clkr.hw, 746 }, 747 .num_parents = 1, 748 .flags = CLK_SET_RATE_PARENT, 749 .ops = &clk_branch2_ops, 750 }, 751 }, 752 }; 753 754 static struct clk_branch disp_cc_mdss_esc0_clk = { 755 .halt_reg = 0x2038, 756 .halt_check = BRANCH_HALT, 757 .clkr = { 758 .enable_reg = 0x2038, 759 .enable_mask = BIT(0), 760 .hw.init = &(struct clk_init_data){ 761 .name = "disp_cc_mdss_esc0_clk", 762 .parent_hws = (const struct clk_hw*[]){ 763 &disp_cc_mdss_esc0_clk_src.clkr.hw, 764 }, 765 .num_parents = 1, 766 .flags = CLK_SET_RATE_PARENT, 767 .ops = &clk_branch2_ops, 768 }, 769 }, 770 }; 771 772 static struct clk_branch disp_cc_mdss_esc1_clk = { 773 .halt_reg = 0x203c, 774 .halt_check = BRANCH_HALT, 775 .clkr = { 776 .enable_reg = 0x203c, 777 .enable_mask = BIT(0), 778 .hw.init = &(struct clk_init_data){ 779 .name = "disp_cc_mdss_esc1_clk", 780 .parent_hws = (const struct clk_hw*[]){ 781 &disp_cc_mdss_esc1_clk_src.clkr.hw, 782 }, 783 .num_parents = 1, 784 .flags = CLK_SET_RATE_PARENT, 785 .ops = &clk_branch2_ops, 786 }, 787 }, 788 }; 789 790 static struct clk_branch disp_cc_mdss_mdp_clk = { 791 .halt_reg = 0x200c, 792 .halt_check = BRANCH_HALT, 793 .clkr = { 794 .enable_reg = 0x200c, 795 .enable_mask = BIT(0), 796 .hw.init = &(struct clk_init_data){ 797 .name = "disp_cc_mdss_mdp_clk", 798 .parent_hws = (const struct clk_hw*[]){ 799 &disp_cc_mdss_mdp_clk_src.clkr.hw, 800 }, 801 .num_parents = 1, 802 .flags = CLK_SET_RATE_PARENT, 803 .ops = &clk_branch2_ops, 804 }, 805 }, 806 }; 807 808 static struct clk_branch disp_cc_mdss_mdp_lut_clk = { 809 .halt_reg = 0x201c, 810 .halt_check = BRANCH_VOTED, 811 .clkr = { 812 .enable_reg = 0x201c, 813 .enable_mask = BIT(0), 814 .hw.init = &(struct clk_init_data){ 815 .name = "disp_cc_mdss_mdp_lut_clk", 816 .parent_hws = (const struct clk_hw*[]){ 817 &disp_cc_mdss_mdp_clk_src.clkr.hw, 818 }, 819 .num_parents = 1, 820 .ops = &clk_branch2_ops, 821 }, 822 }, 823 }; 824 825 static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = { 826 .halt_reg = 0x4004, 827 .halt_check = BRANCH_VOTED, 828 .clkr = { 829 .enable_reg = 0x4004, 830 .enable_mask = BIT(0), 831 .hw.init = &(struct clk_init_data){ 832 .name = "disp_cc_mdss_non_gdsc_ahb_clk", 833 .parent_hws = (const struct clk_hw*[]){ 834 &disp_cc_mdss_ahb_clk_src.clkr.hw, 835 }, 836 .num_parents = 1, 837 .flags = CLK_SET_RATE_PARENT, 838 .ops = &clk_branch2_ops, 839 }, 840 }, 841 }; 842 843 static struct clk_branch disp_cc_mdss_pclk0_clk = { 844 .halt_reg = 0x2004, 845 .halt_check = BRANCH_HALT, 846 .clkr = { 847 .enable_reg = 0x2004, 848 .enable_mask = BIT(0), 849 .hw.init = &(struct clk_init_data){ 850 .name = "disp_cc_mdss_pclk0_clk", 851 .parent_hws = (const struct clk_hw*[]){ 852 &disp_cc_mdss_pclk0_clk_src.clkr.hw, 853 }, 854 .num_parents = 1, 855 .flags = CLK_SET_RATE_PARENT, 856 .ops = &clk_branch2_ops, 857 }, 858 }, 859 }; 860 861 static struct clk_branch disp_cc_mdss_pclk1_clk = { 862 .halt_reg = 0x2008, 863 .halt_check = BRANCH_HALT, 864 .clkr = { 865 .enable_reg = 0x2008, 866 .enable_mask = BIT(0), 867 .hw.init = &(struct clk_init_data){ 868 .name = "disp_cc_mdss_pclk1_clk", 869 .parent_hws = (const struct clk_hw*[]){ 870 &disp_cc_mdss_pclk1_clk_src.clkr.hw, 871 }, 872 .num_parents = 1, 873 .flags = CLK_SET_RATE_PARENT, 874 .ops = &clk_branch2_ops, 875 }, 876 }, 877 }; 878 879 static struct clk_branch disp_cc_mdss_rot_clk = { 880 .halt_reg = 0x2014, 881 .halt_check = BRANCH_HALT, 882 .clkr = { 883 .enable_reg = 0x2014, 884 .enable_mask = BIT(0), 885 .hw.init = &(struct clk_init_data){ 886 .name = "disp_cc_mdss_rot_clk", 887 .parent_hws = (const struct clk_hw*[]){ 888 &disp_cc_mdss_rot_clk_src.clkr.hw, 889 }, 890 .num_parents = 1, 891 .flags = CLK_SET_RATE_PARENT, 892 .ops = &clk_branch2_ops, 893 }, 894 }, 895 }; 896 897 static struct clk_branch disp_cc_mdss_rscc_ahb_clk = { 898 .halt_reg = 0x400c, 899 .halt_check = BRANCH_HALT, 900 .clkr = { 901 .enable_reg = 0x400c, 902 .enable_mask = BIT(0), 903 .hw.init = &(struct clk_init_data){ 904 .name = "disp_cc_mdss_rscc_ahb_clk", 905 .parent_hws = (const struct clk_hw*[]){ 906 &disp_cc_mdss_ahb_clk_src.clkr.hw, 907 }, 908 .num_parents = 1, 909 .flags = CLK_SET_RATE_PARENT, 910 .ops = &clk_branch2_ops, 911 }, 912 }, 913 }; 914 915 static struct clk_branch disp_cc_mdss_rscc_vsync_clk = { 916 .halt_reg = 0x4008, 917 .halt_check = BRANCH_HALT, 918 .clkr = { 919 .enable_reg = 0x4008, 920 .enable_mask = BIT(0), 921 .hw.init = &(struct clk_init_data){ 922 .name = "disp_cc_mdss_rscc_vsync_clk", 923 .parent_hws = (const struct clk_hw*[]){ 924 &disp_cc_mdss_vsync_clk_src.clkr.hw, 925 }, 926 .num_parents = 1, 927 .flags = CLK_SET_RATE_PARENT, 928 .ops = &clk_branch2_ops, 929 }, 930 }, 931 }; 932 933 static struct clk_branch disp_cc_mdss_vsync_clk = { 934 .halt_reg = 0x2024, 935 .halt_check = BRANCH_HALT, 936 .clkr = { 937 .enable_reg = 0x2024, 938 .enable_mask = BIT(0), 939 .hw.init = &(struct clk_init_data){ 940 .name = "disp_cc_mdss_vsync_clk", 941 .parent_hws = (const struct clk_hw*[]){ 942 &disp_cc_mdss_vsync_clk_src.clkr.hw, 943 }, 944 .num_parents = 1, 945 .flags = CLK_SET_RATE_PARENT, 946 .ops = &clk_branch2_ops, 947 }, 948 }, 949 }; 950 951 static struct gdsc mdss_gdsc = { 952 .gdscr = 0x3000, 953 .pd = { 954 .name = "mdss_gdsc", 955 }, 956 .pwrsts = PWRSTS_OFF_ON, 957 .flags = HW_CTRL, 958 .supply = "mmcx", 959 }; 960 961 static struct clk_regmap *disp_cc_sm8250_clocks[] = { 962 [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr, 963 [DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr, 964 [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr, 965 [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr, 966 [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr, 967 [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr, 968 [DISP_CC_MDSS_BYTE1_CLK] = &disp_cc_mdss_byte1_clk.clkr, 969 [DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp_cc_mdss_byte1_clk_src.clkr, 970 [DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] = &disp_cc_mdss_byte1_div_clk_src.clkr, 971 [DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp_cc_mdss_byte1_intf_clk.clkr, 972 [DISP_CC_MDSS_DP_AUX1_CLK] = &disp_cc_mdss_dp_aux1_clk.clkr, 973 [DISP_CC_MDSS_DP_AUX1_CLK_SRC] = &disp_cc_mdss_dp_aux1_clk_src.clkr, 974 [DISP_CC_MDSS_DP_AUX_CLK] = &disp_cc_mdss_dp_aux_clk.clkr, 975 [DISP_CC_MDSS_DP_AUX_CLK_SRC] = &disp_cc_mdss_dp_aux_clk_src.clkr, 976 [DISP_CC_MDSS_DP_LINK1_CLK] = &disp_cc_mdss_dp_link1_clk.clkr, 977 [DISP_CC_MDSS_DP_LINK1_CLK_SRC] = &disp_cc_mdss_dp_link1_clk_src.clkr, 978 [DISP_CC_MDSS_DP_LINK1_DIV_CLK_SRC] = &disp_cc_mdss_dp_link1_div_clk_src.clkr, 979 [DISP_CC_MDSS_DP_LINK1_INTF_CLK] = &disp_cc_mdss_dp_link1_intf_clk.clkr, 980 [DISP_CC_MDSS_DP_LINK_CLK] = &disp_cc_mdss_dp_link_clk.clkr, 981 [DISP_CC_MDSS_DP_LINK_CLK_SRC] = &disp_cc_mdss_dp_link_clk_src.clkr, 982 [DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dp_link_div_clk_src.clkr, 983 [DISP_CC_MDSS_DP_LINK_INTF_CLK] = &disp_cc_mdss_dp_link_intf_clk.clkr, 984 [DISP_CC_MDSS_DP_PIXEL1_CLK] = &disp_cc_mdss_dp_pixel1_clk.clkr, 985 [DISP_CC_MDSS_DP_PIXEL1_CLK_SRC] = &disp_cc_mdss_dp_pixel1_clk_src.clkr, 986 [DISP_CC_MDSS_DP_PIXEL2_CLK] = &disp_cc_mdss_dp_pixel2_clk.clkr, 987 [DISP_CC_MDSS_DP_PIXEL2_CLK_SRC] = &disp_cc_mdss_dp_pixel2_clk_src.clkr, 988 [DISP_CC_MDSS_DP_PIXEL_CLK] = &disp_cc_mdss_dp_pixel_clk.clkr, 989 [DISP_CC_MDSS_DP_PIXEL_CLK_SRC] = &disp_cc_mdss_dp_pixel_clk_src.clkr, 990 [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr, 991 [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr, 992 [DISP_CC_MDSS_ESC1_CLK] = &disp_cc_mdss_esc1_clk.clkr, 993 [DISP_CC_MDSS_ESC1_CLK_SRC] = &disp_cc_mdss_esc1_clk_src.clkr, 994 [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr, 995 [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr, 996 [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr, 997 [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr, 998 [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr, 999 [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr, 1000 [DISP_CC_MDSS_PCLK1_CLK] = &disp_cc_mdss_pclk1_clk.clkr, 1001 [DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp_cc_mdss_pclk1_clk_src.clkr, 1002 [DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr, 1003 [DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr, 1004 [DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr, 1005 [DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr, 1006 [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr, 1007 [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr, 1008 [DISP_CC_PLL0] = &disp_cc_pll0.clkr, 1009 [DISP_CC_PLL1] = &disp_cc_pll1.clkr, 1010 }; 1011 1012 static const struct qcom_reset_map disp_cc_sm8250_resets[] = { 1013 [DISP_CC_MDSS_CORE_BCR] = { 0x2000 }, 1014 [DISP_CC_MDSS_RSCC_BCR] = { 0x4000 }, 1015 }; 1016 1017 static struct gdsc *disp_cc_sm8250_gdscs[] = { 1018 [MDSS_GDSC] = &mdss_gdsc, 1019 }; 1020 1021 static const struct regmap_config disp_cc_sm8250_regmap_config = { 1022 .reg_bits = 32, 1023 .reg_stride = 4, 1024 .val_bits = 32, 1025 .max_register = 0x10000, 1026 .fast_io = true, 1027 }; 1028 1029 static const struct qcom_cc_desc disp_cc_sm8250_desc = { 1030 .config = &disp_cc_sm8250_regmap_config, 1031 .clks = disp_cc_sm8250_clocks, 1032 .num_clks = ARRAY_SIZE(disp_cc_sm8250_clocks), 1033 .resets = disp_cc_sm8250_resets, 1034 .num_resets = ARRAY_SIZE(disp_cc_sm8250_resets), 1035 .gdscs = disp_cc_sm8250_gdscs, 1036 .num_gdscs = ARRAY_SIZE(disp_cc_sm8250_gdscs), 1037 }; 1038 1039 static const struct of_device_id disp_cc_sm8250_match_table[] = { 1040 { .compatible = "qcom,sm8150-dispcc" }, 1041 { .compatible = "qcom,sm8250-dispcc" }, 1042 { } 1043 }; 1044 MODULE_DEVICE_TABLE(of, disp_cc_sm8250_match_table); 1045 1046 static int disp_cc_sm8250_probe(struct platform_device *pdev) 1047 { 1048 struct regmap *regmap; 1049 1050 regmap = qcom_cc_map(pdev, &disp_cc_sm8250_desc); 1051 if (IS_ERR(regmap)) 1052 return PTR_ERR(regmap); 1053 1054 /* note: trion == lucid, except for the prepare() op */ 1055 BUILD_BUG_ON(CLK_ALPHA_PLL_TYPE_TRION != CLK_ALPHA_PLL_TYPE_LUCID); 1056 if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8150-dispcc")) { 1057 disp_cc_pll0_config.config_ctl_hi_val = 0x00002267; 1058 disp_cc_pll0_config.config_ctl_hi1_val = 0x00000024; 1059 disp_cc_pll0_config.user_ctl_hi1_val = 0x000000D0; 1060 disp_cc_pll0_init.ops = &clk_alpha_pll_trion_ops; 1061 disp_cc_pll1_config.config_ctl_hi_val = 0x00002267; 1062 disp_cc_pll1_config.config_ctl_hi1_val = 0x00000024; 1063 disp_cc_pll1_config.user_ctl_hi1_val = 0x000000D0; 1064 disp_cc_pll1_init.ops = &clk_alpha_pll_trion_ops; 1065 } 1066 1067 clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); 1068 clk_lucid_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config); 1069 1070 /* Enable clock gating for MDP clocks */ 1071 regmap_update_bits(regmap, 0x8000, 0x10, 0x10); 1072 1073 /* DISP_CC_XO_CLK always-on */ 1074 regmap_update_bits(regmap, 0x605c, BIT(0), BIT(0)); 1075 1076 return qcom_cc_really_probe(pdev, &disp_cc_sm8250_desc, regmap); 1077 } 1078 1079 static struct platform_driver disp_cc_sm8250_driver = { 1080 .probe = disp_cc_sm8250_probe, 1081 .driver = { 1082 .name = "disp_cc-sm8250", 1083 .of_match_table = disp_cc_sm8250_match_table, 1084 }, 1085 }; 1086 1087 static int __init disp_cc_sm8250_init(void) 1088 { 1089 return platform_driver_register(&disp_cc_sm8250_driver); 1090 } 1091 subsys_initcall(disp_cc_sm8250_init); 1092 1093 static void __exit disp_cc_sm8250_exit(void) 1094 { 1095 platform_driver_unregister(&disp_cc_sm8250_driver); 1096 } 1097 module_exit(disp_cc_sm8250_exit); 1098 1099 MODULE_DESCRIPTION("QTI DISPCC SM8250 Driver"); 1100 MODULE_LICENSE("GPL v2"); 1101