1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/module.h> 8 #include <linux/platform_device.h> 9 #include <linux/regmap.h> 10 #include <linux/reset-controller.h> 11 12 #include <dt-bindings/clock/qcom,dispcc-sm8250.h> 13 14 #include "clk-alpha-pll.h" 15 #include "clk-branch.h" 16 #include "clk-rcg.h" 17 #include "clk-regmap-divider.h" 18 #include "common.h" 19 #include "gdsc.h" 20 #include "reset.h" 21 22 enum { 23 P_BI_TCXO, 24 P_DISP_CC_PLL0_OUT_MAIN, 25 P_DISP_CC_PLL1_OUT_EVEN, 26 P_DISP_CC_PLL1_OUT_MAIN, 27 P_DP_PHY_PLL_LINK_CLK, 28 P_DP_PHY_PLL_VCO_DIV_CLK, 29 P_DPTX1_PHY_PLL_LINK_CLK, 30 P_DPTX1_PHY_PLL_VCO_DIV_CLK, 31 P_DPTX2_PHY_PLL_LINK_CLK, 32 P_DPTX2_PHY_PLL_VCO_DIV_CLK, 33 P_EDP_PHY_PLL_LINK_CLK, 34 P_EDP_PHY_PLL_VCO_DIV_CLK, 35 P_DSI0_PHY_PLL_OUT_BYTECLK, 36 P_DSI0_PHY_PLL_OUT_DSICLK, 37 P_DSI1_PHY_PLL_OUT_BYTECLK, 38 P_DSI1_PHY_PLL_OUT_DSICLK, 39 }; 40 41 static struct pll_vco vco_table[] = { 42 { 249600000, 2000000000, 0 }, 43 }; 44 45 static struct alpha_pll_config disp_cc_pll0_config = { 46 .l = 0x47, 47 .alpha = 0xE000, 48 .config_ctl_val = 0x20485699, 49 .config_ctl_hi_val = 0x00002261, 50 .config_ctl_hi1_val = 0x329A699C, 51 .user_ctl_val = 0x00000000, 52 .user_ctl_hi_val = 0x00000805, 53 .user_ctl_hi1_val = 0x00000000, 54 }; 55 56 static struct clk_init_data disp_cc_pll0_init = { 57 .name = "disp_cc_pll0", 58 .parent_data = &(const struct clk_parent_data){ 59 .fw_name = "bi_tcxo", 60 }, 61 .num_parents = 1, 62 .ops = &clk_alpha_pll_lucid_ops, 63 }; 64 65 static struct clk_alpha_pll disp_cc_pll0 = { 66 .offset = 0x0, 67 .vco_table = vco_table, 68 .num_vco = ARRAY_SIZE(vco_table), 69 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 70 .clkr.hw.init = &disp_cc_pll0_init 71 }; 72 73 static struct alpha_pll_config disp_cc_pll1_config = { 74 .l = 0x1F, 75 .alpha = 0x4000, 76 .config_ctl_val = 0x20485699, 77 .config_ctl_hi_val = 0x00002261, 78 .config_ctl_hi1_val = 0x329A699C, 79 .user_ctl_val = 0x00000000, 80 .user_ctl_hi_val = 0x00000805, 81 .user_ctl_hi1_val = 0x00000000, 82 }; 83 84 static struct clk_init_data disp_cc_pll1_init = { 85 .name = "disp_cc_pll1", 86 .parent_data = &(const struct clk_parent_data){ 87 .fw_name = "bi_tcxo", 88 }, 89 .num_parents = 1, 90 .ops = &clk_alpha_pll_lucid_ops, 91 }; 92 93 static struct clk_alpha_pll disp_cc_pll1 = { 94 .offset = 0x1000, 95 .vco_table = vco_table, 96 .num_vco = ARRAY_SIZE(vco_table), 97 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], 98 .clkr.hw.init = &disp_cc_pll1_init 99 }; 100 101 static const struct parent_map disp_cc_parent_map_0[] = { 102 { P_BI_TCXO, 0 }, 103 { P_DP_PHY_PLL_LINK_CLK, 1 }, 104 { P_DP_PHY_PLL_VCO_DIV_CLK, 2 }, 105 { P_DPTX1_PHY_PLL_LINK_CLK, 3 }, 106 { P_DPTX1_PHY_PLL_VCO_DIV_CLK, 4 }, 107 { P_DPTX2_PHY_PLL_LINK_CLK, 5 }, 108 { P_DPTX2_PHY_PLL_VCO_DIV_CLK, 6 }, 109 }; 110 111 static const struct clk_parent_data disp_cc_parent_data_0[] = { 112 { .fw_name = "bi_tcxo" }, 113 { .fw_name = "dp_phy_pll_link_clk" }, 114 { .fw_name = "dp_phy_pll_vco_div_clk" }, 115 { .fw_name = "dptx1_phy_pll_link_clk" }, 116 { .fw_name = "dptx1_phy_pll_vco_div_clk" }, 117 { .fw_name = "dptx2_phy_pll_link_clk" }, 118 { .fw_name = "dptx2_phy_pll_vco_div_clk" }, 119 }; 120 121 static const struct parent_map disp_cc_parent_map_1[] = { 122 { P_BI_TCXO, 0 }, 123 }; 124 125 static const struct clk_parent_data disp_cc_parent_data_1[] = { 126 { .fw_name = "bi_tcxo" }, 127 }; 128 129 static const struct parent_map disp_cc_parent_map_2[] = { 130 { P_BI_TCXO, 0 }, 131 { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 }, 132 { P_DSI1_PHY_PLL_OUT_BYTECLK, 2 }, 133 }; 134 135 static const struct clk_parent_data disp_cc_parent_data_2[] = { 136 { .fw_name = "bi_tcxo" }, 137 { .fw_name = "dsi0_phy_pll_out_byteclk" }, 138 { .fw_name = "dsi1_phy_pll_out_byteclk" }, 139 }; 140 141 static const struct parent_map disp_cc_parent_map_3[] = { 142 { P_BI_TCXO, 0 }, 143 { P_DISP_CC_PLL1_OUT_MAIN, 4 }, 144 }; 145 146 static const struct clk_parent_data disp_cc_parent_data_3[] = { 147 { .fw_name = "bi_tcxo" }, 148 { .hw = &disp_cc_pll1.clkr.hw }, 149 }; 150 151 static const struct parent_map disp_cc_parent_map_4[] = { 152 { P_BI_TCXO, 0 }, 153 { P_EDP_PHY_PLL_LINK_CLK, 1 }, 154 { P_EDP_PHY_PLL_VCO_DIV_CLK, 2}, 155 }; 156 157 static const struct clk_parent_data disp_cc_parent_data_4[] = { 158 { .fw_name = "bi_tcxo" }, 159 { .fw_name = "edp_phy_pll_link_clk" }, 160 { .fw_name = "edp_phy_pll_vco_div_clk" }, 161 }; 162 163 static const struct parent_map disp_cc_parent_map_5[] = { 164 { P_BI_TCXO, 0 }, 165 { P_DISP_CC_PLL0_OUT_MAIN, 1 }, 166 { P_DISP_CC_PLL1_OUT_MAIN, 4 }, 167 }; 168 169 static const struct clk_parent_data disp_cc_parent_data_5[] = { 170 { .fw_name = "bi_tcxo" }, 171 { .hw = &disp_cc_pll0.clkr.hw }, 172 { .hw = &disp_cc_pll1.clkr.hw }, 173 }; 174 175 static const struct parent_map disp_cc_parent_map_6[] = { 176 { P_BI_TCXO, 0 }, 177 { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, 178 { P_DSI1_PHY_PLL_OUT_DSICLK, 2 }, 179 }; 180 181 static const struct clk_parent_data disp_cc_parent_data_6[] = { 182 { .fw_name = "bi_tcxo" }, 183 { .fw_name = "dsi0_phy_pll_out_dsiclk" }, 184 { .fw_name = "dsi1_phy_pll_out_dsiclk" }, 185 }; 186 187 static const struct parent_map disp_cc_parent_map_7[] = { 188 { P_BI_TCXO, 0 }, 189 { P_DISP_CC_PLL1_OUT_MAIN, 4 }, 190 /* { P_DISP_CC_PLL1_OUT_EVEN, 5 }, */ 191 }; 192 193 static const struct clk_parent_data disp_cc_parent_data_7[] = { 194 { .fw_name = "bi_tcxo" }, 195 { .hw = &disp_cc_pll1.clkr.hw }, 196 /* { .hw = &disp_cc_pll1_out_even.clkr.hw }, */ 197 }; 198 199 static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = { 200 F(19200000, P_BI_TCXO, 1, 0, 0), 201 F(37500000, P_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0), 202 F(75000000, P_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0), 203 { } 204 }; 205 206 static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = { 207 .cmd_rcgr = 0x22bc, 208 .mnd_width = 0, 209 .hid_width = 5, 210 .parent_map = disp_cc_parent_map_3, 211 .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src, 212 .clkr.hw.init = &(struct clk_init_data){ 213 .name = "disp_cc_mdss_ahb_clk_src", 214 .parent_data = disp_cc_parent_data_3, 215 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 216 .flags = CLK_SET_RATE_PARENT, 217 .ops = &clk_rcg2_shared_ops, 218 }, 219 }; 220 221 static const struct freq_tbl ftbl_disp_cc_mdss_byte0_clk_src[] = { 222 F(19200000, P_BI_TCXO, 1, 0, 0), 223 { } 224 }; 225 226 static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = { 227 .cmd_rcgr = 0x2110, 228 .mnd_width = 0, 229 .hid_width = 5, 230 .parent_map = disp_cc_parent_map_2, 231 .clkr.hw.init = &(struct clk_init_data){ 232 .name = "disp_cc_mdss_byte0_clk_src", 233 .parent_data = disp_cc_parent_data_2, 234 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 235 .flags = CLK_SET_RATE_PARENT, 236 .ops = &clk_byte2_ops, 237 }, 238 }; 239 240 static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = { 241 .cmd_rcgr = 0x212c, 242 .mnd_width = 0, 243 .hid_width = 5, 244 .parent_map = disp_cc_parent_map_2, 245 .clkr.hw.init = &(struct clk_init_data){ 246 .name = "disp_cc_mdss_byte1_clk_src", 247 .parent_data = disp_cc_parent_data_2, 248 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 249 .flags = CLK_SET_RATE_PARENT, 250 .ops = &clk_byte2_ops, 251 }, 252 }; 253 254 static struct clk_rcg2 disp_cc_mdss_dp_aux1_clk_src = { 255 .cmd_rcgr = 0x2240, 256 .mnd_width = 0, 257 .hid_width = 5, 258 .parent_map = disp_cc_parent_map_1, 259 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 260 .clkr.hw.init = &(struct clk_init_data){ 261 .name = "disp_cc_mdss_dp_aux1_clk_src", 262 .parent_data = disp_cc_parent_data_1, 263 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 264 .flags = CLK_SET_RATE_PARENT, 265 .ops = &clk_rcg2_ops, 266 }, 267 }; 268 269 static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = { 270 .cmd_rcgr = 0x21dc, 271 .mnd_width = 0, 272 .hid_width = 5, 273 .parent_map = disp_cc_parent_map_1, 274 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 275 .clkr.hw.init = &(struct clk_init_data){ 276 .name = "disp_cc_mdss_dp_aux_clk_src", 277 .parent_data = disp_cc_parent_data_1, 278 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 279 .flags = CLK_SET_RATE_PARENT, 280 .ops = &clk_rcg2_ops, 281 }, 282 }; 283 284 static struct clk_rcg2 disp_cc_mdss_dp_link1_clk_src = { 285 .cmd_rcgr = 0x220c, 286 .mnd_width = 0, 287 .hid_width = 5, 288 .parent_map = disp_cc_parent_map_0, 289 .clkr.hw.init = &(struct clk_init_data){ 290 .name = "disp_cc_mdss_dp_link1_clk_src", 291 .parent_data = disp_cc_parent_data_0, 292 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 293 .ops = &clk_byte2_ops, 294 }, 295 }; 296 297 static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = { 298 .cmd_rcgr = 0x2178, 299 .mnd_width = 0, 300 .hid_width = 5, 301 .parent_map = disp_cc_parent_map_0, 302 .clkr.hw.init = &(struct clk_init_data){ 303 .name = "disp_cc_mdss_dp_link_clk_src", 304 .parent_data = disp_cc_parent_data_0, 305 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 306 .ops = &clk_byte2_ops, 307 }, 308 }; 309 310 static struct clk_rcg2 disp_cc_mdss_dp_pixel1_clk_src = { 311 .cmd_rcgr = 0x21c4, 312 .mnd_width = 16, 313 .hid_width = 5, 314 .parent_map = disp_cc_parent_map_0, 315 .clkr.hw.init = &(struct clk_init_data){ 316 .name = "disp_cc_mdss_dp_pixel1_clk_src", 317 .parent_data = disp_cc_parent_data_0, 318 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 319 .ops = &clk_dp_ops, 320 }, 321 }; 322 323 static struct clk_rcg2 disp_cc_mdss_dp_pixel2_clk_src = { 324 .cmd_rcgr = 0x21f4, 325 .mnd_width = 16, 326 .hid_width = 5, 327 .parent_map = disp_cc_parent_map_0, 328 .clkr.hw.init = &(struct clk_init_data){ 329 .name = "disp_cc_mdss_dp_pixel2_clk_src", 330 .parent_data = disp_cc_parent_data_0, 331 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 332 .ops = &clk_dp_ops, 333 }, 334 }; 335 336 static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = { 337 .cmd_rcgr = 0x21ac, 338 .mnd_width = 16, 339 .hid_width = 5, 340 .parent_map = disp_cc_parent_map_0, 341 .clkr.hw.init = &(struct clk_init_data){ 342 .name = "disp_cc_mdss_dp_pixel_clk_src", 343 .parent_data = disp_cc_parent_data_0, 344 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 345 .ops = &clk_dp_ops, 346 }, 347 }; 348 349 static struct clk_rcg2 disp_cc_mdss_edp_aux_clk_src = { 350 .cmd_rcgr = 0x228c, 351 .mnd_width = 0, 352 .hid_width = 5, 353 .parent_map = disp_cc_parent_map_1, 354 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 355 .clkr.hw.init = &(struct clk_init_data){ 356 .name = "disp_cc_mdss_edp_aux_clk_src", 357 .parent_data = disp_cc_parent_data_1, 358 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 359 .flags = CLK_SET_RATE_PARENT, 360 .ops = &clk_rcg2_ops, 361 }, 362 }; 363 364 static struct clk_rcg2 disp_cc_mdss_edp_gtc_clk_src = { 365 .cmd_rcgr = 0x22a4, 366 .mnd_width = 0, 367 .hid_width = 5, 368 .parent_map = disp_cc_parent_map_7, 369 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 370 .clkr.hw.init = &(struct clk_init_data){ 371 .name = "disp_cc_mdss_edp_gtc_clk_src", 372 .parent_data = disp_cc_parent_data_7, 373 .num_parents = ARRAY_SIZE(disp_cc_parent_data_7), 374 .flags = CLK_SET_RATE_PARENT, 375 .ops = &clk_rcg2_ops, 376 }, 377 }; 378 379 static struct clk_rcg2 disp_cc_mdss_edp_link_clk_src = { 380 .cmd_rcgr = 0x2270, 381 .mnd_width = 0, 382 .hid_width = 5, 383 .parent_map = disp_cc_parent_map_4, 384 .clkr.hw.init = &(struct clk_init_data){ 385 .name = "disp_cc_mdss_edp_link_clk_src", 386 .parent_data = disp_cc_parent_data_4, 387 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), 388 .flags = CLK_SET_RATE_PARENT, 389 .ops = &clk_byte2_ops, 390 }, 391 }; 392 393 static struct clk_rcg2 disp_cc_mdss_edp_pixel_clk_src = { 394 .cmd_rcgr = 0x2258, 395 .mnd_width = 16, 396 .hid_width = 5, 397 .parent_map = disp_cc_parent_map_4, 398 .clkr.hw.init = &(struct clk_init_data){ 399 .name = "disp_cc_mdss_edp_pixel_clk_src", 400 .parent_data = disp_cc_parent_data_4, 401 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), 402 .ops = &clk_dp_ops, 403 }, 404 }; 405 406 static struct clk_branch disp_cc_mdss_edp_aux_clk = { 407 .halt_reg = 0x2078, 408 .halt_check = BRANCH_HALT, 409 .clkr = { 410 .enable_reg = 0x2078, 411 .enable_mask = BIT(0), 412 .hw.init = &(struct clk_init_data){ 413 .name = "disp_cc_mdss_edp_aux_clk", 414 .parent_hws = (const struct clk_hw*[]){ 415 &disp_cc_mdss_edp_aux_clk_src.clkr.hw, 416 }, 417 .num_parents = 1, 418 .flags = CLK_SET_RATE_PARENT, 419 .ops = &clk_branch2_ops, 420 }, 421 }, 422 }; 423 424 static struct clk_branch disp_cc_mdss_edp_gtc_clk = { 425 .halt_reg = 0x207c, 426 .halt_check = BRANCH_HALT, 427 .clkr = { 428 .enable_reg = 0x207c, 429 .enable_mask = BIT(0), 430 .hw.init = &(struct clk_init_data){ 431 .name = "disp_cc_mdss_edp_gtc_clk", 432 .parent_hws = (const struct clk_hw*[]){ 433 &disp_cc_mdss_edp_gtc_clk_src.clkr.hw, 434 }, 435 .num_parents = 1, 436 .flags = CLK_SET_RATE_PARENT, 437 .ops = &clk_branch2_ops, 438 }, 439 }, 440 }; 441 442 static struct clk_branch disp_cc_mdss_edp_link_clk = { 443 .halt_reg = 0x2070, 444 .halt_check = BRANCH_HALT, 445 .clkr = { 446 .enable_reg = 0x2070, 447 .enable_mask = BIT(0), 448 .hw.init = &(struct clk_init_data){ 449 .name = "disp_cc_mdss_edp_link_clk", 450 .parent_hws = (const struct clk_hw*[]){ 451 &disp_cc_mdss_edp_link_clk_src.clkr.hw, 452 }, 453 .num_parents = 1, 454 .flags = CLK_SET_RATE_PARENT, 455 .ops = &clk_branch2_ops, 456 }, 457 }, 458 }; 459 460 static struct clk_branch disp_cc_mdss_edp_link_intf_clk = { 461 .halt_reg = 0x2074, 462 .halt_check = BRANCH_HALT, 463 .clkr = { 464 .enable_reg = 0x2074, 465 .enable_mask = BIT(0), 466 .hw.init = &(struct clk_init_data){ 467 .name = "disp_cc_mdss_edp_link_intf_clk", 468 .parent_hws = (const struct clk_hw*[]){ 469 &disp_cc_mdss_edp_link_clk_src.clkr.hw, 470 }, 471 .num_parents = 1, 472 .flags = CLK_GET_RATE_NOCACHE, 473 .ops = &clk_branch2_ops, 474 }, 475 }, 476 }; 477 478 static struct clk_branch disp_cc_mdss_edp_pixel_clk = { 479 .halt_reg = 0x206c, 480 .halt_check = BRANCH_HALT, 481 .clkr = { 482 .enable_reg = 0x206c, 483 .enable_mask = BIT(0), 484 .hw.init = &(struct clk_init_data){ 485 .name = "disp_cc_mdss_edp_pixel_clk", 486 .parent_hws = (const struct clk_hw*[]){ 487 &disp_cc_mdss_edp_pixel_clk_src.clkr.hw, 488 }, 489 .num_parents = 1, 490 .flags = CLK_SET_RATE_PARENT, 491 .ops = &clk_branch2_ops, 492 }, 493 }, 494 }; 495 496 static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = { 497 .cmd_rcgr = 0x2148, 498 .mnd_width = 0, 499 .hid_width = 5, 500 .parent_map = disp_cc_parent_map_2, 501 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 502 .clkr.hw.init = &(struct clk_init_data){ 503 .name = "disp_cc_mdss_esc0_clk_src", 504 .parent_data = disp_cc_parent_data_2, 505 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 506 .flags = CLK_SET_RATE_PARENT, 507 .ops = &clk_rcg2_ops, 508 }, 509 }; 510 511 static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = { 512 .cmd_rcgr = 0x2160, 513 .mnd_width = 0, 514 .hid_width = 5, 515 .parent_map = disp_cc_parent_map_2, 516 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 517 .clkr.hw.init = &(struct clk_init_data){ 518 .name = "disp_cc_mdss_esc1_clk_src", 519 .parent_data = disp_cc_parent_data_2, 520 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 521 .flags = CLK_SET_RATE_PARENT, 522 .ops = &clk_rcg2_ops, 523 }, 524 }; 525 526 static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = { 527 F(19200000, P_BI_TCXO, 1, 0, 0), 528 F(85714286, P_DISP_CC_PLL1_OUT_MAIN, 7, 0, 0), 529 F(100000000, P_DISP_CC_PLL1_OUT_MAIN, 6, 0, 0), 530 F(150000000, P_DISP_CC_PLL1_OUT_MAIN, 4, 0, 0), 531 F(200000000, P_DISP_CC_PLL1_OUT_MAIN, 3, 0, 0), 532 F(300000000, P_DISP_CC_PLL1_OUT_MAIN, 2, 0, 0), 533 F(345000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0), 534 F(460000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 535 { } 536 }; 537 538 static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = { 539 .cmd_rcgr = 0x20c8, 540 .mnd_width = 0, 541 .hid_width = 5, 542 .parent_map = disp_cc_parent_map_5, 543 .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src, 544 .clkr.hw.init = &(struct clk_init_data){ 545 .name = "disp_cc_mdss_mdp_clk_src", 546 .parent_data = disp_cc_parent_data_5, 547 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), 548 .flags = CLK_SET_RATE_PARENT, 549 .ops = &clk_rcg2_shared_ops, 550 }, 551 }; 552 553 static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = { 554 .cmd_rcgr = 0x2098, 555 .mnd_width = 8, 556 .hid_width = 5, 557 .parent_map = disp_cc_parent_map_6, 558 .clkr.hw.init = &(struct clk_init_data){ 559 .name = "disp_cc_mdss_pclk0_clk_src", 560 .parent_data = disp_cc_parent_data_6, 561 .num_parents = ARRAY_SIZE(disp_cc_parent_data_6), 562 .flags = CLK_SET_RATE_PARENT, 563 .ops = &clk_pixel_ops, 564 }, 565 }; 566 567 static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = { 568 .cmd_rcgr = 0x20b0, 569 .mnd_width = 8, 570 .hid_width = 5, 571 .parent_map = disp_cc_parent_map_6, 572 .clkr.hw.init = &(struct clk_init_data){ 573 .name = "disp_cc_mdss_pclk1_clk_src", 574 .parent_data = disp_cc_parent_data_6, 575 .num_parents = ARRAY_SIZE(disp_cc_parent_data_6), 576 .flags = CLK_SET_RATE_PARENT, 577 .ops = &clk_pixel_ops, 578 }, 579 }; 580 581 static const struct freq_tbl ftbl_disp_cc_mdss_rot_clk_src[] = { 582 F(19200000, P_BI_TCXO, 1, 0, 0), 583 F(200000000, P_DISP_CC_PLL1_OUT_MAIN, 3, 0, 0), 584 F(300000000, P_DISP_CC_PLL1_OUT_MAIN, 2, 0, 0), 585 F(345000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0), 586 F(460000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 587 { } 588 }; 589 590 static struct clk_rcg2 disp_cc_mdss_rot_clk_src = { 591 .cmd_rcgr = 0x20e0, 592 .mnd_width = 0, 593 .hid_width = 5, 594 .parent_map = disp_cc_parent_map_5, 595 .freq_tbl = ftbl_disp_cc_mdss_rot_clk_src, 596 .clkr.hw.init = &(struct clk_init_data){ 597 .name = "disp_cc_mdss_rot_clk_src", 598 .parent_data = disp_cc_parent_data_5, 599 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), 600 .flags = CLK_SET_RATE_PARENT, 601 .ops = &clk_rcg2_shared_ops, 602 }, 603 }; 604 605 static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = { 606 .cmd_rcgr = 0x20f8, 607 .mnd_width = 0, 608 .hid_width = 5, 609 .parent_map = disp_cc_parent_map_1, 610 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 611 .clkr.hw.init = &(struct clk_init_data){ 612 .name = "disp_cc_mdss_vsync_clk_src", 613 .parent_data = disp_cc_parent_data_1, 614 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 615 .flags = CLK_SET_RATE_PARENT, 616 .ops = &clk_rcg2_ops, 617 }, 618 }; 619 620 static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = { 621 .reg = 0x2128, 622 .shift = 0, 623 .width = 2, 624 .clkr.hw.init = &(struct clk_init_data) { 625 .name = "disp_cc_mdss_byte0_div_clk_src", 626 .parent_hws = (const struct clk_hw*[]){ 627 &disp_cc_mdss_byte0_clk_src.clkr.hw, 628 }, 629 .num_parents = 1, 630 .ops = &clk_regmap_div_ops, 631 }, 632 }; 633 634 635 static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = { 636 .reg = 0x2144, 637 .shift = 0, 638 .width = 2, 639 .clkr.hw.init = &(struct clk_init_data) { 640 .name = "disp_cc_mdss_byte1_div_clk_src", 641 .parent_hws = (const struct clk_hw*[]){ 642 &disp_cc_mdss_byte1_clk_src.clkr.hw, 643 }, 644 .num_parents = 1, 645 .ops = &clk_regmap_div_ops, 646 }, 647 }; 648 649 650 static struct clk_regmap_div disp_cc_mdss_dp_link1_div_clk_src = { 651 .reg = 0x2224, 652 .shift = 0, 653 .width = 2, 654 .clkr.hw.init = &(struct clk_init_data) { 655 .name = "disp_cc_mdss_dp_link1_div_clk_src", 656 .parent_hws = (const struct clk_hw*[]){ 657 &disp_cc_mdss_dp_link1_clk_src.clkr.hw, 658 }, 659 .num_parents = 1, 660 .ops = &clk_regmap_div_ro_ops, 661 }, 662 }; 663 664 665 static struct clk_regmap_div disp_cc_mdss_dp_link_div_clk_src = { 666 .reg = 0x2190, 667 .shift = 0, 668 .width = 2, 669 .clkr.hw.init = &(struct clk_init_data) { 670 .name = "disp_cc_mdss_dp_link_div_clk_src", 671 .parent_hws = (const struct clk_hw*[]){ 672 &disp_cc_mdss_dp_link_clk_src.clkr.hw, 673 }, 674 .num_parents = 1, 675 .ops = &clk_regmap_div_ro_ops, 676 }, 677 }; 678 679 static struct clk_branch disp_cc_mdss_ahb_clk = { 680 .halt_reg = 0x2080, 681 .halt_check = BRANCH_HALT, 682 .clkr = { 683 .enable_reg = 0x2080, 684 .enable_mask = BIT(0), 685 .hw.init = &(struct clk_init_data){ 686 .name = "disp_cc_mdss_ahb_clk", 687 .parent_hws = (const struct clk_hw*[]){ 688 &disp_cc_mdss_ahb_clk_src.clkr.hw, 689 }, 690 .num_parents = 1, 691 .flags = CLK_SET_RATE_PARENT, 692 .ops = &clk_branch2_ops, 693 }, 694 }, 695 }; 696 697 static struct clk_branch disp_cc_mdss_byte0_clk = { 698 .halt_reg = 0x2028, 699 .halt_check = BRANCH_HALT, 700 .clkr = { 701 .enable_reg = 0x2028, 702 .enable_mask = BIT(0), 703 .hw.init = &(struct clk_init_data){ 704 .name = "disp_cc_mdss_byte0_clk", 705 .parent_hws = (const struct clk_hw*[]){ 706 &disp_cc_mdss_byte0_clk_src.clkr.hw, 707 }, 708 .num_parents = 1, 709 .flags = CLK_SET_RATE_PARENT, 710 .ops = &clk_branch2_ops, 711 }, 712 }, 713 }; 714 715 static struct clk_branch disp_cc_mdss_byte0_intf_clk = { 716 .halt_reg = 0x202c, 717 .halt_check = BRANCH_HALT, 718 .clkr = { 719 .enable_reg = 0x202c, 720 .enable_mask = BIT(0), 721 .hw.init = &(struct clk_init_data){ 722 .name = "disp_cc_mdss_byte0_intf_clk", 723 .parent_hws = (const struct clk_hw*[]){ 724 &disp_cc_mdss_byte0_div_clk_src.clkr.hw, 725 }, 726 .num_parents = 1, 727 .flags = CLK_SET_RATE_PARENT, 728 .ops = &clk_branch2_ops, 729 }, 730 }, 731 }; 732 733 static struct clk_branch disp_cc_mdss_byte1_clk = { 734 .halt_reg = 0x2030, 735 .halt_check = BRANCH_HALT, 736 .clkr = { 737 .enable_reg = 0x2030, 738 .enable_mask = BIT(0), 739 .hw.init = &(struct clk_init_data){ 740 .name = "disp_cc_mdss_byte1_clk", 741 .parent_hws = (const struct clk_hw*[]){ 742 &disp_cc_mdss_byte1_clk_src.clkr.hw, 743 }, 744 .num_parents = 1, 745 .flags = CLK_SET_RATE_PARENT, 746 .ops = &clk_branch2_ops, 747 }, 748 }, 749 }; 750 751 static struct clk_branch disp_cc_mdss_byte1_intf_clk = { 752 .halt_reg = 0x2034, 753 .halt_check = BRANCH_HALT, 754 .clkr = { 755 .enable_reg = 0x2034, 756 .enable_mask = BIT(0), 757 .hw.init = &(struct clk_init_data){ 758 .name = "disp_cc_mdss_byte1_intf_clk", 759 .parent_hws = (const struct clk_hw*[]){ 760 &disp_cc_mdss_byte1_div_clk_src.clkr.hw, 761 }, 762 .num_parents = 1, 763 .flags = CLK_SET_RATE_PARENT, 764 .ops = &clk_branch2_ops, 765 }, 766 }, 767 }; 768 769 static struct clk_branch disp_cc_mdss_dp_aux1_clk = { 770 .halt_reg = 0x2068, 771 .halt_check = BRANCH_HALT, 772 .clkr = { 773 .enable_reg = 0x2068, 774 .enable_mask = BIT(0), 775 .hw.init = &(struct clk_init_data){ 776 .name = "disp_cc_mdss_dp_aux1_clk", 777 .parent_hws = (const struct clk_hw*[]){ 778 &disp_cc_mdss_dp_aux1_clk_src.clkr.hw, 779 }, 780 .num_parents = 1, 781 .flags = CLK_SET_RATE_PARENT, 782 .ops = &clk_branch2_ops, 783 }, 784 }, 785 }; 786 787 static struct clk_branch disp_cc_mdss_dp_aux_clk = { 788 .halt_reg = 0x2054, 789 .halt_check = BRANCH_HALT, 790 .clkr = { 791 .enable_reg = 0x2054, 792 .enable_mask = BIT(0), 793 .hw.init = &(struct clk_init_data){ 794 .name = "disp_cc_mdss_dp_aux_clk", 795 .parent_hws = (const struct clk_hw*[]){ 796 &disp_cc_mdss_dp_aux_clk_src.clkr.hw, 797 }, 798 .num_parents = 1, 799 .flags = CLK_SET_RATE_PARENT, 800 .ops = &clk_branch2_ops, 801 }, 802 }, 803 }; 804 805 static struct clk_branch disp_cc_mdss_dp_link1_clk = { 806 .halt_reg = 0x205c, 807 .halt_check = BRANCH_HALT, 808 .clkr = { 809 .enable_reg = 0x205c, 810 .enable_mask = BIT(0), 811 .hw.init = &(struct clk_init_data){ 812 .name = "disp_cc_mdss_dp_link1_clk", 813 .parent_hws = (const struct clk_hw*[]){ 814 &disp_cc_mdss_dp_link1_clk_src.clkr.hw, 815 }, 816 .num_parents = 1, 817 .flags = CLK_SET_RATE_PARENT, 818 .ops = &clk_branch2_ops, 819 }, 820 }, 821 }; 822 823 static struct clk_branch disp_cc_mdss_dp_link1_intf_clk = { 824 .halt_reg = 0x2060, 825 .halt_check = BRANCH_HALT, 826 .clkr = { 827 .enable_reg = 0x2060, 828 .enable_mask = BIT(0), 829 .hw.init = &(struct clk_init_data){ 830 .name = "disp_cc_mdss_dp_link1_intf_clk", 831 .parent_hws = (const struct clk_hw*[]){ 832 &disp_cc_mdss_dp_link1_div_clk_src.clkr.hw, 833 }, 834 .num_parents = 1, 835 .ops = &clk_branch2_ops, 836 }, 837 }, 838 }; 839 840 static struct clk_branch disp_cc_mdss_dp_link_clk = { 841 .halt_reg = 0x2040, 842 .halt_check = BRANCH_HALT, 843 .clkr = { 844 .enable_reg = 0x2040, 845 .enable_mask = BIT(0), 846 .hw.init = &(struct clk_init_data){ 847 .name = "disp_cc_mdss_dp_link_clk", 848 .parent_hws = (const struct clk_hw*[]){ 849 &disp_cc_mdss_dp_link_clk_src.clkr.hw, 850 }, 851 .num_parents = 1, 852 .flags = CLK_SET_RATE_PARENT, 853 .ops = &clk_branch2_ops, 854 }, 855 }, 856 }; 857 858 static struct clk_branch disp_cc_mdss_dp_link_intf_clk = { 859 .halt_reg = 0x2044, 860 .halt_check = BRANCH_HALT, 861 .clkr = { 862 .enable_reg = 0x2044, 863 .enable_mask = BIT(0), 864 .hw.init = &(struct clk_init_data){ 865 .name = "disp_cc_mdss_dp_link_intf_clk", 866 .parent_hws = (const struct clk_hw*[]){ 867 &disp_cc_mdss_dp_link_div_clk_src.clkr.hw, 868 }, 869 .num_parents = 1, 870 .ops = &clk_branch2_ops, 871 }, 872 }, 873 }; 874 875 static struct clk_branch disp_cc_mdss_dp_pixel1_clk = { 876 .halt_reg = 0x2050, 877 .halt_check = BRANCH_HALT, 878 .clkr = { 879 .enable_reg = 0x2050, 880 .enable_mask = BIT(0), 881 .hw.init = &(struct clk_init_data){ 882 .name = "disp_cc_mdss_dp_pixel1_clk", 883 .parent_hws = (const struct clk_hw*[]){ 884 &disp_cc_mdss_dp_pixel1_clk_src.clkr.hw, 885 }, 886 .num_parents = 1, 887 .flags = CLK_SET_RATE_PARENT, 888 .ops = &clk_branch2_ops, 889 }, 890 }, 891 }; 892 893 static struct clk_branch disp_cc_mdss_dp_pixel2_clk = { 894 .halt_reg = 0x2058, 895 .halt_check = BRANCH_HALT, 896 .clkr = { 897 .enable_reg = 0x2058, 898 .enable_mask = BIT(0), 899 .hw.init = &(struct clk_init_data){ 900 .name = "disp_cc_mdss_dp_pixel2_clk", 901 .parent_hws = (const struct clk_hw*[]){ 902 &disp_cc_mdss_dp_pixel2_clk_src.clkr.hw, 903 }, 904 .num_parents = 1, 905 .flags = CLK_SET_RATE_PARENT, 906 .ops = &clk_branch2_ops, 907 }, 908 }, 909 }; 910 911 static struct clk_branch disp_cc_mdss_dp_pixel_clk = { 912 .halt_reg = 0x204c, 913 .halt_check = BRANCH_HALT, 914 .clkr = { 915 .enable_reg = 0x204c, 916 .enable_mask = BIT(0), 917 .hw.init = &(struct clk_init_data){ 918 .name = "disp_cc_mdss_dp_pixel_clk", 919 .parent_hws = (const struct clk_hw*[]){ 920 &disp_cc_mdss_dp_pixel_clk_src.clkr.hw, 921 }, 922 .num_parents = 1, 923 .flags = CLK_SET_RATE_PARENT, 924 .ops = &clk_branch2_ops, 925 }, 926 }, 927 }; 928 929 static struct clk_branch disp_cc_mdss_esc0_clk = { 930 .halt_reg = 0x2038, 931 .halt_check = BRANCH_HALT, 932 .clkr = { 933 .enable_reg = 0x2038, 934 .enable_mask = BIT(0), 935 .hw.init = &(struct clk_init_data){ 936 .name = "disp_cc_mdss_esc0_clk", 937 .parent_hws = (const struct clk_hw*[]){ 938 &disp_cc_mdss_esc0_clk_src.clkr.hw, 939 }, 940 .num_parents = 1, 941 .flags = CLK_SET_RATE_PARENT, 942 .ops = &clk_branch2_ops, 943 }, 944 }, 945 }; 946 947 static struct clk_branch disp_cc_mdss_esc1_clk = { 948 .halt_reg = 0x203c, 949 .halt_check = BRANCH_HALT, 950 .clkr = { 951 .enable_reg = 0x203c, 952 .enable_mask = BIT(0), 953 .hw.init = &(struct clk_init_data){ 954 .name = "disp_cc_mdss_esc1_clk", 955 .parent_hws = (const struct clk_hw*[]){ 956 &disp_cc_mdss_esc1_clk_src.clkr.hw, 957 }, 958 .num_parents = 1, 959 .flags = CLK_SET_RATE_PARENT, 960 .ops = &clk_branch2_ops, 961 }, 962 }, 963 }; 964 965 static struct clk_branch disp_cc_mdss_mdp_clk = { 966 .halt_reg = 0x200c, 967 .halt_check = BRANCH_HALT, 968 .clkr = { 969 .enable_reg = 0x200c, 970 .enable_mask = BIT(0), 971 .hw.init = &(struct clk_init_data){ 972 .name = "disp_cc_mdss_mdp_clk", 973 .parent_hws = (const struct clk_hw*[]){ 974 &disp_cc_mdss_mdp_clk_src.clkr.hw, 975 }, 976 .num_parents = 1, 977 .flags = CLK_SET_RATE_PARENT, 978 .ops = &clk_branch2_ops, 979 }, 980 }, 981 }; 982 983 static struct clk_branch disp_cc_mdss_mdp_lut_clk = { 984 .halt_reg = 0x201c, 985 .halt_check = BRANCH_VOTED, 986 .clkr = { 987 .enable_reg = 0x201c, 988 .enable_mask = BIT(0), 989 .hw.init = &(struct clk_init_data){ 990 .name = "disp_cc_mdss_mdp_lut_clk", 991 .parent_hws = (const struct clk_hw*[]){ 992 &disp_cc_mdss_mdp_clk_src.clkr.hw, 993 }, 994 .num_parents = 1, 995 .ops = &clk_branch2_ops, 996 }, 997 }, 998 }; 999 1000 static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = { 1001 .halt_reg = 0x4004, 1002 .halt_check = BRANCH_VOTED, 1003 .clkr = { 1004 .enable_reg = 0x4004, 1005 .enable_mask = BIT(0), 1006 .hw.init = &(struct clk_init_data){ 1007 .name = "disp_cc_mdss_non_gdsc_ahb_clk", 1008 .parent_hws = (const struct clk_hw*[]){ 1009 &disp_cc_mdss_ahb_clk_src.clkr.hw, 1010 }, 1011 .num_parents = 1, 1012 .flags = CLK_SET_RATE_PARENT, 1013 .ops = &clk_branch2_ops, 1014 }, 1015 }, 1016 }; 1017 1018 static struct clk_branch disp_cc_mdss_pclk0_clk = { 1019 .halt_reg = 0x2004, 1020 .halt_check = BRANCH_HALT, 1021 .clkr = { 1022 .enable_reg = 0x2004, 1023 .enable_mask = BIT(0), 1024 .hw.init = &(struct clk_init_data){ 1025 .name = "disp_cc_mdss_pclk0_clk", 1026 .parent_hws = (const struct clk_hw*[]){ 1027 &disp_cc_mdss_pclk0_clk_src.clkr.hw, 1028 }, 1029 .num_parents = 1, 1030 .flags = CLK_SET_RATE_PARENT, 1031 .ops = &clk_branch2_ops, 1032 }, 1033 }, 1034 }; 1035 1036 static struct clk_branch disp_cc_mdss_pclk1_clk = { 1037 .halt_reg = 0x2008, 1038 .halt_check = BRANCH_HALT, 1039 .clkr = { 1040 .enable_reg = 0x2008, 1041 .enable_mask = BIT(0), 1042 .hw.init = &(struct clk_init_data){ 1043 .name = "disp_cc_mdss_pclk1_clk", 1044 .parent_hws = (const struct clk_hw*[]){ 1045 &disp_cc_mdss_pclk1_clk_src.clkr.hw, 1046 }, 1047 .num_parents = 1, 1048 .flags = CLK_SET_RATE_PARENT, 1049 .ops = &clk_branch2_ops, 1050 }, 1051 }, 1052 }; 1053 1054 static struct clk_branch disp_cc_mdss_rot_clk = { 1055 .halt_reg = 0x2014, 1056 .halt_check = BRANCH_HALT, 1057 .clkr = { 1058 .enable_reg = 0x2014, 1059 .enable_mask = BIT(0), 1060 .hw.init = &(struct clk_init_data){ 1061 .name = "disp_cc_mdss_rot_clk", 1062 .parent_hws = (const struct clk_hw*[]){ 1063 &disp_cc_mdss_rot_clk_src.clkr.hw, 1064 }, 1065 .num_parents = 1, 1066 .flags = CLK_SET_RATE_PARENT, 1067 .ops = &clk_branch2_ops, 1068 }, 1069 }, 1070 }; 1071 1072 static struct clk_branch disp_cc_mdss_rscc_ahb_clk = { 1073 .halt_reg = 0x400c, 1074 .halt_check = BRANCH_HALT, 1075 .clkr = { 1076 .enable_reg = 0x400c, 1077 .enable_mask = BIT(0), 1078 .hw.init = &(struct clk_init_data){ 1079 .name = "disp_cc_mdss_rscc_ahb_clk", 1080 .parent_hws = (const struct clk_hw*[]){ 1081 &disp_cc_mdss_ahb_clk_src.clkr.hw, 1082 }, 1083 .num_parents = 1, 1084 .flags = CLK_SET_RATE_PARENT, 1085 .ops = &clk_branch2_ops, 1086 }, 1087 }, 1088 }; 1089 1090 static struct clk_branch disp_cc_mdss_rscc_vsync_clk = { 1091 .halt_reg = 0x4008, 1092 .halt_check = BRANCH_HALT, 1093 .clkr = { 1094 .enable_reg = 0x4008, 1095 .enable_mask = BIT(0), 1096 .hw.init = &(struct clk_init_data){ 1097 .name = "disp_cc_mdss_rscc_vsync_clk", 1098 .parent_hws = (const struct clk_hw*[]){ 1099 &disp_cc_mdss_vsync_clk_src.clkr.hw, 1100 }, 1101 .num_parents = 1, 1102 .flags = CLK_SET_RATE_PARENT, 1103 .ops = &clk_branch2_ops, 1104 }, 1105 }, 1106 }; 1107 1108 static struct clk_branch disp_cc_mdss_vsync_clk = { 1109 .halt_reg = 0x2024, 1110 .halt_check = BRANCH_HALT, 1111 .clkr = { 1112 .enable_reg = 0x2024, 1113 .enable_mask = BIT(0), 1114 .hw.init = &(struct clk_init_data){ 1115 .name = "disp_cc_mdss_vsync_clk", 1116 .parent_hws = (const struct clk_hw*[]){ 1117 &disp_cc_mdss_vsync_clk_src.clkr.hw, 1118 }, 1119 .num_parents = 1, 1120 .flags = CLK_SET_RATE_PARENT, 1121 .ops = &clk_branch2_ops, 1122 }, 1123 }, 1124 }; 1125 1126 static struct gdsc mdss_gdsc = { 1127 .gdscr = 0x3000, 1128 .pd = { 1129 .name = "mdss_gdsc", 1130 }, 1131 .pwrsts = PWRSTS_OFF_ON, 1132 .flags = HW_CTRL, 1133 .supply = "mmcx", 1134 }; 1135 1136 static struct clk_regmap *disp_cc_sm8250_clocks[] = { 1137 [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr, 1138 [DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr, 1139 [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr, 1140 [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr, 1141 [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr, 1142 [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr, 1143 [DISP_CC_MDSS_BYTE1_CLK] = &disp_cc_mdss_byte1_clk.clkr, 1144 [DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp_cc_mdss_byte1_clk_src.clkr, 1145 [DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] = &disp_cc_mdss_byte1_div_clk_src.clkr, 1146 [DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp_cc_mdss_byte1_intf_clk.clkr, 1147 [DISP_CC_MDSS_DP_AUX1_CLK] = &disp_cc_mdss_dp_aux1_clk.clkr, 1148 [DISP_CC_MDSS_DP_AUX1_CLK_SRC] = &disp_cc_mdss_dp_aux1_clk_src.clkr, 1149 [DISP_CC_MDSS_DP_AUX_CLK] = &disp_cc_mdss_dp_aux_clk.clkr, 1150 [DISP_CC_MDSS_DP_AUX_CLK_SRC] = &disp_cc_mdss_dp_aux_clk_src.clkr, 1151 [DISP_CC_MDSS_DP_LINK1_CLK] = &disp_cc_mdss_dp_link1_clk.clkr, 1152 [DISP_CC_MDSS_DP_LINK1_CLK_SRC] = &disp_cc_mdss_dp_link1_clk_src.clkr, 1153 [DISP_CC_MDSS_DP_LINK1_DIV_CLK_SRC] = &disp_cc_mdss_dp_link1_div_clk_src.clkr, 1154 [DISP_CC_MDSS_DP_LINK1_INTF_CLK] = &disp_cc_mdss_dp_link1_intf_clk.clkr, 1155 [DISP_CC_MDSS_DP_LINK_CLK] = &disp_cc_mdss_dp_link_clk.clkr, 1156 [DISP_CC_MDSS_DP_LINK_CLK_SRC] = &disp_cc_mdss_dp_link_clk_src.clkr, 1157 [DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dp_link_div_clk_src.clkr, 1158 [DISP_CC_MDSS_DP_LINK_INTF_CLK] = &disp_cc_mdss_dp_link_intf_clk.clkr, 1159 [DISP_CC_MDSS_DP_PIXEL1_CLK] = &disp_cc_mdss_dp_pixel1_clk.clkr, 1160 [DISP_CC_MDSS_DP_PIXEL1_CLK_SRC] = &disp_cc_mdss_dp_pixel1_clk_src.clkr, 1161 [DISP_CC_MDSS_DP_PIXEL2_CLK] = &disp_cc_mdss_dp_pixel2_clk.clkr, 1162 [DISP_CC_MDSS_DP_PIXEL2_CLK_SRC] = &disp_cc_mdss_dp_pixel2_clk_src.clkr, 1163 [DISP_CC_MDSS_DP_PIXEL_CLK] = &disp_cc_mdss_dp_pixel_clk.clkr, 1164 [DISP_CC_MDSS_DP_PIXEL_CLK_SRC] = &disp_cc_mdss_dp_pixel_clk_src.clkr, 1165 [DISP_CC_MDSS_EDP_AUX_CLK] = &disp_cc_mdss_edp_aux_clk.clkr, 1166 [DISP_CC_MDSS_EDP_AUX_CLK_SRC] = &disp_cc_mdss_edp_aux_clk_src.clkr, 1167 [DISP_CC_MDSS_EDP_GTC_CLK] = &disp_cc_mdss_edp_gtc_clk.clkr, 1168 [DISP_CC_MDSS_EDP_GTC_CLK_SRC] = &disp_cc_mdss_edp_gtc_clk_src.clkr, 1169 [DISP_CC_MDSS_EDP_LINK_CLK] = &disp_cc_mdss_edp_link_clk.clkr, 1170 [DISP_CC_MDSS_EDP_LINK_CLK_SRC] = &disp_cc_mdss_edp_link_clk_src.clkr, 1171 [DISP_CC_MDSS_EDP_LINK_INTF_CLK] = &disp_cc_mdss_edp_link_intf_clk.clkr, 1172 [DISP_CC_MDSS_EDP_PIXEL_CLK] = &disp_cc_mdss_edp_pixel_clk.clkr, 1173 [DISP_CC_MDSS_EDP_PIXEL_CLK_SRC] = &disp_cc_mdss_edp_pixel_clk_src.clkr, 1174 [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr, 1175 [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr, 1176 [DISP_CC_MDSS_ESC1_CLK] = &disp_cc_mdss_esc1_clk.clkr, 1177 [DISP_CC_MDSS_ESC1_CLK_SRC] = &disp_cc_mdss_esc1_clk_src.clkr, 1178 [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr, 1179 [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr, 1180 [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr, 1181 [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr, 1182 [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr, 1183 [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr, 1184 [DISP_CC_MDSS_PCLK1_CLK] = &disp_cc_mdss_pclk1_clk.clkr, 1185 [DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp_cc_mdss_pclk1_clk_src.clkr, 1186 [DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr, 1187 [DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr, 1188 [DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr, 1189 [DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr, 1190 [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr, 1191 [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr, 1192 [DISP_CC_PLL0] = &disp_cc_pll0.clkr, 1193 [DISP_CC_PLL1] = &disp_cc_pll1.clkr, 1194 }; 1195 1196 static const struct qcom_reset_map disp_cc_sm8250_resets[] = { 1197 [DISP_CC_MDSS_CORE_BCR] = { 0x2000 }, 1198 [DISP_CC_MDSS_RSCC_BCR] = { 0x4000 }, 1199 }; 1200 1201 static struct gdsc *disp_cc_sm8250_gdscs[] = { 1202 [MDSS_GDSC] = &mdss_gdsc, 1203 }; 1204 1205 static const struct regmap_config disp_cc_sm8250_regmap_config = { 1206 .reg_bits = 32, 1207 .reg_stride = 4, 1208 .val_bits = 32, 1209 .max_register = 0x10000, 1210 .fast_io = true, 1211 }; 1212 1213 static const struct qcom_cc_desc disp_cc_sm8250_desc = { 1214 .config = &disp_cc_sm8250_regmap_config, 1215 .clks = disp_cc_sm8250_clocks, 1216 .num_clks = ARRAY_SIZE(disp_cc_sm8250_clocks), 1217 .resets = disp_cc_sm8250_resets, 1218 .num_resets = ARRAY_SIZE(disp_cc_sm8250_resets), 1219 .gdscs = disp_cc_sm8250_gdscs, 1220 .num_gdscs = ARRAY_SIZE(disp_cc_sm8250_gdscs), 1221 }; 1222 1223 static const struct of_device_id disp_cc_sm8250_match_table[] = { 1224 { .compatible = "qcom,sc8180x-dispcc" }, 1225 { .compatible = "qcom,sm8150-dispcc" }, 1226 { .compatible = "qcom,sm8250-dispcc" }, 1227 { } 1228 }; 1229 MODULE_DEVICE_TABLE(of, disp_cc_sm8250_match_table); 1230 1231 static int disp_cc_sm8250_probe(struct platform_device *pdev) 1232 { 1233 struct regmap *regmap; 1234 1235 regmap = qcom_cc_map(pdev, &disp_cc_sm8250_desc); 1236 if (IS_ERR(regmap)) 1237 return PTR_ERR(regmap); 1238 1239 /* note: trion == lucid, except for the prepare() op */ 1240 BUILD_BUG_ON(CLK_ALPHA_PLL_TYPE_TRION != CLK_ALPHA_PLL_TYPE_LUCID); 1241 if (of_device_is_compatible(pdev->dev.of_node, "qcom,sc8180x-dispcc") || 1242 of_device_is_compatible(pdev->dev.of_node, "qcom,sm8150-dispcc")) { 1243 disp_cc_pll0_config.config_ctl_hi_val = 0x00002267; 1244 disp_cc_pll0_config.config_ctl_hi1_val = 0x00000024; 1245 disp_cc_pll0_config.user_ctl_hi1_val = 0x000000D0; 1246 disp_cc_pll0_init.ops = &clk_alpha_pll_trion_ops; 1247 disp_cc_pll1_config.config_ctl_hi_val = 0x00002267; 1248 disp_cc_pll1_config.config_ctl_hi1_val = 0x00000024; 1249 disp_cc_pll1_config.user_ctl_hi1_val = 0x000000D0; 1250 disp_cc_pll1_init.ops = &clk_alpha_pll_trion_ops; 1251 } 1252 1253 clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); 1254 clk_lucid_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config); 1255 1256 /* Enable clock gating for MDP clocks */ 1257 regmap_update_bits(regmap, 0x8000, 0x10, 0x10); 1258 1259 /* DISP_CC_XO_CLK always-on */ 1260 regmap_update_bits(regmap, 0x605c, BIT(0), BIT(0)); 1261 1262 return qcom_cc_really_probe(pdev, &disp_cc_sm8250_desc, regmap); 1263 } 1264 1265 static struct platform_driver disp_cc_sm8250_driver = { 1266 .probe = disp_cc_sm8250_probe, 1267 .driver = { 1268 .name = "disp_cc-sm8250", 1269 .of_match_table = disp_cc_sm8250_match_table, 1270 }, 1271 }; 1272 1273 static int __init disp_cc_sm8250_init(void) 1274 { 1275 return platform_driver_register(&disp_cc_sm8250_driver); 1276 } 1277 subsys_initcall(disp_cc_sm8250_init); 1278 1279 static void __exit disp_cc_sm8250_exit(void) 1280 { 1281 platform_driver_unregister(&disp_cc_sm8250_driver); 1282 } 1283 module_exit(disp_cc_sm8250_exit); 1284 1285 MODULE_DESCRIPTION("QTI DISPCC SM8250 Driver"); 1286 MODULE_LICENSE("GPL v2"); 1287