1*9b518788SAdam Skladowski // SPDX-License-Identifier: GPL-2.0-only 2*9b518788SAdam Skladowski /* 3*9b518788SAdam Skladowski * Based on dispcc-qcm2290.c 4*9b518788SAdam Skladowski * Copyright (c) 2020, The Linux Foundation. All rights reserved. 5*9b518788SAdam Skladowski * Copyright (c) 2021, Linaro Ltd. 6*9b518788SAdam Skladowski */ 7*9b518788SAdam Skladowski 8*9b518788SAdam Skladowski #include <linux/err.h> 9*9b518788SAdam Skladowski #include <linux/kernel.h> 10*9b518788SAdam Skladowski #include <linux/module.h> 11*9b518788SAdam Skladowski #include <linux/of_device.h> 12*9b518788SAdam Skladowski #include <linux/of.h> 13*9b518788SAdam Skladowski #include <linux/regmap.h> 14*9b518788SAdam Skladowski 15*9b518788SAdam Skladowski #include <dt-bindings/clock/qcom,sm6115-dispcc.h> 16*9b518788SAdam Skladowski 17*9b518788SAdam Skladowski #include "clk-alpha-pll.h" 18*9b518788SAdam Skladowski #include "clk-branch.h" 19*9b518788SAdam Skladowski #include "clk-rcg.h" 20*9b518788SAdam Skladowski #include "clk-regmap.h" 21*9b518788SAdam Skladowski #include "clk-regmap-divider.h" 22*9b518788SAdam Skladowski #include "common.h" 23*9b518788SAdam Skladowski #include "gdsc.h" 24*9b518788SAdam Skladowski 25*9b518788SAdam Skladowski enum { 26*9b518788SAdam Skladowski DT_BI_TCXO, 27*9b518788SAdam Skladowski DT_SLEEP_CLK, 28*9b518788SAdam Skladowski DT_DSI0_PHY_PLL_OUT_BYTECLK, 29*9b518788SAdam Skladowski DT_DSI0_PHY_PLL_OUT_DSICLK, 30*9b518788SAdam Skladowski DT_GPLL0_DISP_DIV, 31*9b518788SAdam Skladowski }; 32*9b518788SAdam Skladowski 33*9b518788SAdam Skladowski enum { 34*9b518788SAdam Skladowski P_BI_TCXO, 35*9b518788SAdam Skladowski P_DISP_CC_PLL0_OUT_MAIN, 36*9b518788SAdam Skladowski P_DSI0_PHY_PLL_OUT_BYTECLK, 37*9b518788SAdam Skladowski P_DSI0_PHY_PLL_OUT_DSICLK, 38*9b518788SAdam Skladowski P_GPLL0_OUT_MAIN, 39*9b518788SAdam Skladowski P_SLEEP_CLK, 40*9b518788SAdam Skladowski }; 41*9b518788SAdam Skladowski 42*9b518788SAdam Skladowski static const struct clk_parent_data parent_data_tcxo = { .index = DT_BI_TCXO }; 43*9b518788SAdam Skladowski 44*9b518788SAdam Skladowski static const struct pll_vco spark_vco[] = { 45*9b518788SAdam Skladowski { 500000000, 1000000000, 2 }, 46*9b518788SAdam Skladowski }; 47*9b518788SAdam Skladowski 48*9b518788SAdam Skladowski /* 768MHz configuration */ 49*9b518788SAdam Skladowski static const struct alpha_pll_config disp_cc_pll0_config = { 50*9b518788SAdam Skladowski .l = 0x28, 51*9b518788SAdam Skladowski .alpha = 0x0, 52*9b518788SAdam Skladowski .alpha_en_mask = BIT(24), 53*9b518788SAdam Skladowski .vco_val = 0x2 << 20, 54*9b518788SAdam Skladowski .vco_mask = GENMASK(21, 20), 55*9b518788SAdam Skladowski .main_output_mask = BIT(0), 56*9b518788SAdam Skladowski .config_ctl_val = 0x4001055B, 57*9b518788SAdam Skladowski }; 58*9b518788SAdam Skladowski 59*9b518788SAdam Skladowski static struct clk_alpha_pll disp_cc_pll0 = { 60*9b518788SAdam Skladowski .offset = 0x0, 61*9b518788SAdam Skladowski .vco_table = spark_vco, 62*9b518788SAdam Skladowski .num_vco = ARRAY_SIZE(spark_vco), 63*9b518788SAdam Skladowski .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 64*9b518788SAdam Skladowski .clkr = { 65*9b518788SAdam Skladowski .hw.init = &(struct clk_init_data){ 66*9b518788SAdam Skladowski .name = "disp_cc_pll0", 67*9b518788SAdam Skladowski .parent_data = &parent_data_tcxo, 68*9b518788SAdam Skladowski .num_parents = 1, 69*9b518788SAdam Skladowski .ops = &clk_alpha_pll_ops, 70*9b518788SAdam Skladowski }, 71*9b518788SAdam Skladowski }, 72*9b518788SAdam Skladowski }; 73*9b518788SAdam Skladowski 74*9b518788SAdam Skladowski static const struct clk_div_table post_div_table_disp_cc_pll0_out_main[] = { 75*9b518788SAdam Skladowski { 0x0, 1 }, 76*9b518788SAdam Skladowski { } 77*9b518788SAdam Skladowski }; 78*9b518788SAdam Skladowski static struct clk_alpha_pll_postdiv disp_cc_pll0_out_main = { 79*9b518788SAdam Skladowski .offset = 0x0, 80*9b518788SAdam Skladowski .post_div_shift = 8, 81*9b518788SAdam Skladowski .post_div_table = post_div_table_disp_cc_pll0_out_main, 82*9b518788SAdam Skladowski .num_post_div = ARRAY_SIZE(post_div_table_disp_cc_pll0_out_main), 83*9b518788SAdam Skladowski .width = 4, 84*9b518788SAdam Skladowski .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 85*9b518788SAdam Skladowski .clkr.hw.init = &(struct clk_init_data){ 86*9b518788SAdam Skladowski .name = "disp_cc_pll0_out_main", 87*9b518788SAdam Skladowski .parent_hws = (const struct clk_hw*[]){ 88*9b518788SAdam Skladowski &disp_cc_pll0.clkr.hw, 89*9b518788SAdam Skladowski }, 90*9b518788SAdam Skladowski .num_parents = 1, 91*9b518788SAdam Skladowski .flags = CLK_SET_RATE_PARENT, 92*9b518788SAdam Skladowski .ops = &clk_alpha_pll_postdiv_ops, 93*9b518788SAdam Skladowski }, 94*9b518788SAdam Skladowski }; 95*9b518788SAdam Skladowski 96*9b518788SAdam Skladowski static const struct parent_map disp_cc_parent_map_0[] = { 97*9b518788SAdam Skladowski { P_BI_TCXO, 0 }, 98*9b518788SAdam Skladowski { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 }, 99*9b518788SAdam Skladowski }; 100*9b518788SAdam Skladowski 101*9b518788SAdam Skladowski static const struct clk_parent_data disp_cc_parent_data_0[] = { 102*9b518788SAdam Skladowski { .index = DT_BI_TCXO }, 103*9b518788SAdam Skladowski { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK }, 104*9b518788SAdam Skladowski }; 105*9b518788SAdam Skladowski 106*9b518788SAdam Skladowski static const struct parent_map disp_cc_parent_map_1[] = { 107*9b518788SAdam Skladowski { P_BI_TCXO, 0 }, 108*9b518788SAdam Skladowski }; 109*9b518788SAdam Skladowski 110*9b518788SAdam Skladowski static const struct clk_parent_data disp_cc_parent_data_1[] = { 111*9b518788SAdam Skladowski { .index = DT_BI_TCXO }, 112*9b518788SAdam Skladowski }; 113*9b518788SAdam Skladowski 114*9b518788SAdam Skladowski static const struct parent_map disp_cc_parent_map_2[] = { 115*9b518788SAdam Skladowski { P_BI_TCXO, 0 }, 116*9b518788SAdam Skladowski { P_GPLL0_OUT_MAIN, 4 }, 117*9b518788SAdam Skladowski }; 118*9b518788SAdam Skladowski 119*9b518788SAdam Skladowski static const struct clk_parent_data disp_cc_parent_data_2[] = { 120*9b518788SAdam Skladowski { .index = DT_BI_TCXO }, 121*9b518788SAdam Skladowski { .index = DT_GPLL0_DISP_DIV }, 122*9b518788SAdam Skladowski }; 123*9b518788SAdam Skladowski 124*9b518788SAdam Skladowski static const struct parent_map disp_cc_parent_map_3[] = { 125*9b518788SAdam Skladowski { P_BI_TCXO, 0 }, 126*9b518788SAdam Skladowski { P_DISP_CC_PLL0_OUT_MAIN, 1 }, 127*9b518788SAdam Skladowski }; 128*9b518788SAdam Skladowski 129*9b518788SAdam Skladowski static const struct clk_parent_data disp_cc_parent_data_3[] = { 130*9b518788SAdam Skladowski { .index = DT_BI_TCXO }, 131*9b518788SAdam Skladowski { .hw = &disp_cc_pll0_out_main.clkr.hw }, 132*9b518788SAdam Skladowski }; 133*9b518788SAdam Skladowski 134*9b518788SAdam Skladowski static const struct parent_map disp_cc_parent_map_4[] = { 135*9b518788SAdam Skladowski { P_BI_TCXO, 0 }, 136*9b518788SAdam Skladowski { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, 137*9b518788SAdam Skladowski }; 138*9b518788SAdam Skladowski 139*9b518788SAdam Skladowski static const struct clk_parent_data disp_cc_parent_data_4[] = { 140*9b518788SAdam Skladowski { .index = DT_BI_TCXO }, 141*9b518788SAdam Skladowski { .index = DT_DSI0_PHY_PLL_OUT_DSICLK }, 142*9b518788SAdam Skladowski }; 143*9b518788SAdam Skladowski 144*9b518788SAdam Skladowski static const struct parent_map disp_cc_parent_map_5[] = { 145*9b518788SAdam Skladowski { P_SLEEP_CLK, 0 }, 146*9b518788SAdam Skladowski }; 147*9b518788SAdam Skladowski 148*9b518788SAdam Skladowski static const struct clk_parent_data disp_cc_parent_data_5[] = { 149*9b518788SAdam Skladowski { .index = DT_SLEEP_CLK, }, 150*9b518788SAdam Skladowski }; 151*9b518788SAdam Skladowski 152*9b518788SAdam Skladowski static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = { 153*9b518788SAdam Skladowski .cmd_rcgr = 0x20bc, 154*9b518788SAdam Skladowski .mnd_width = 0, 155*9b518788SAdam Skladowski .hid_width = 5, 156*9b518788SAdam Skladowski .parent_map = disp_cc_parent_map_0, 157*9b518788SAdam Skladowski .clkr.hw.init = &(struct clk_init_data){ 158*9b518788SAdam Skladowski .name = "disp_cc_mdss_byte0_clk_src", 159*9b518788SAdam Skladowski .parent_data = disp_cc_parent_data_0, 160*9b518788SAdam Skladowski .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 161*9b518788SAdam Skladowski /* For set_rate and set_parent to succeed, parent(s) must be enabled */ 162*9b518788SAdam Skladowski .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE | CLK_GET_RATE_NOCACHE, 163*9b518788SAdam Skladowski .ops = &clk_byte2_ops, 164*9b518788SAdam Skladowski }, 165*9b518788SAdam Skladowski }; 166*9b518788SAdam Skladowski 167*9b518788SAdam Skladowski static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = { 168*9b518788SAdam Skladowski .reg = 0x20d4, 169*9b518788SAdam Skladowski .shift = 0, 170*9b518788SAdam Skladowski .width = 2, 171*9b518788SAdam Skladowski .clkr.hw.init = &(struct clk_init_data) { 172*9b518788SAdam Skladowski .name = "disp_cc_mdss_byte0_div_clk_src", 173*9b518788SAdam Skladowski .parent_hws = (const struct clk_hw*[]){ 174*9b518788SAdam Skladowski &disp_cc_mdss_byte0_clk_src.clkr.hw, 175*9b518788SAdam Skladowski }, 176*9b518788SAdam Skladowski .num_parents = 1, 177*9b518788SAdam Skladowski .ops = &clk_regmap_div_ops, 178*9b518788SAdam Skladowski }, 179*9b518788SAdam Skladowski }; 180*9b518788SAdam Skladowski 181*9b518788SAdam Skladowski static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = { 182*9b518788SAdam Skladowski F(19200000, P_BI_TCXO, 1, 0, 0), 183*9b518788SAdam Skladowski F(37500000, P_GPLL0_OUT_MAIN, 8, 0, 0), 184*9b518788SAdam Skladowski F(75000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 185*9b518788SAdam Skladowski { } 186*9b518788SAdam Skladowski }; 187*9b518788SAdam Skladowski 188*9b518788SAdam Skladowski static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = { 189*9b518788SAdam Skladowski .cmd_rcgr = 0x2154, 190*9b518788SAdam Skladowski .mnd_width = 0, 191*9b518788SAdam Skladowski .hid_width = 5, 192*9b518788SAdam Skladowski .parent_map = disp_cc_parent_map_2, 193*9b518788SAdam Skladowski .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src, 194*9b518788SAdam Skladowski .clkr.hw.init = &(struct clk_init_data){ 195*9b518788SAdam Skladowski .name = "disp_cc_mdss_ahb_clk_src", 196*9b518788SAdam Skladowski .parent_data = disp_cc_parent_data_2, 197*9b518788SAdam Skladowski .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 198*9b518788SAdam Skladowski .ops = &clk_rcg2_shared_ops, 199*9b518788SAdam Skladowski }, 200*9b518788SAdam Skladowski }; 201*9b518788SAdam Skladowski 202*9b518788SAdam Skladowski static const struct freq_tbl ftbl_disp_cc_mdss_esc0_clk_src[] = { 203*9b518788SAdam Skladowski F(19200000, P_BI_TCXO, 1, 0, 0), 204*9b518788SAdam Skladowski { } 205*9b518788SAdam Skladowski }; 206*9b518788SAdam Skladowski 207*9b518788SAdam Skladowski static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = { 208*9b518788SAdam Skladowski .cmd_rcgr = 0x20d8, 209*9b518788SAdam Skladowski .mnd_width = 0, 210*9b518788SAdam Skladowski .hid_width = 5, 211*9b518788SAdam Skladowski .parent_map = disp_cc_parent_map_0, 212*9b518788SAdam Skladowski .freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src, 213*9b518788SAdam Skladowski .clkr.hw.init = &(struct clk_init_data){ 214*9b518788SAdam Skladowski .name = "disp_cc_mdss_esc0_clk_src", 215*9b518788SAdam Skladowski .parent_data = disp_cc_parent_data_0, 216*9b518788SAdam Skladowski .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 217*9b518788SAdam Skladowski .ops = &clk_rcg2_ops, 218*9b518788SAdam Skladowski }, 219*9b518788SAdam Skladowski }; 220*9b518788SAdam Skladowski 221*9b518788SAdam Skladowski static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = { 222*9b518788SAdam Skladowski F(19200000, P_BI_TCXO, 1, 0, 0), 223*9b518788SAdam Skladowski F(192000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0), 224*9b518788SAdam Skladowski F(256000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 225*9b518788SAdam Skladowski F(307200000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0), 226*9b518788SAdam Skladowski F(384000000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0), 227*9b518788SAdam Skladowski { } 228*9b518788SAdam Skladowski }; 229*9b518788SAdam Skladowski 230*9b518788SAdam Skladowski static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = { 231*9b518788SAdam Skladowski .cmd_rcgr = 0x2074, 232*9b518788SAdam Skladowski .mnd_width = 0, 233*9b518788SAdam Skladowski .hid_width = 5, 234*9b518788SAdam Skladowski .parent_map = disp_cc_parent_map_3, 235*9b518788SAdam Skladowski .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src, 236*9b518788SAdam Skladowski .clkr.hw.init = &(struct clk_init_data){ 237*9b518788SAdam Skladowski .name = "disp_cc_mdss_mdp_clk_src", 238*9b518788SAdam Skladowski .parent_data = disp_cc_parent_data_3, 239*9b518788SAdam Skladowski .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 240*9b518788SAdam Skladowski .flags = CLK_SET_RATE_PARENT, 241*9b518788SAdam Skladowski .ops = &clk_rcg2_shared_ops, 242*9b518788SAdam Skladowski }, 243*9b518788SAdam Skladowski }; 244*9b518788SAdam Skladowski 245*9b518788SAdam Skladowski static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = { 246*9b518788SAdam Skladowski .cmd_rcgr = 0x205c, 247*9b518788SAdam Skladowski .mnd_width = 8, 248*9b518788SAdam Skladowski .hid_width = 5, 249*9b518788SAdam Skladowski .parent_map = disp_cc_parent_map_4, 250*9b518788SAdam Skladowski .clkr.hw.init = &(struct clk_init_data){ 251*9b518788SAdam Skladowski .name = "disp_cc_mdss_pclk0_clk_src", 252*9b518788SAdam Skladowski .parent_data = disp_cc_parent_data_4, 253*9b518788SAdam Skladowski .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), 254*9b518788SAdam Skladowski /* For set_rate and set_parent to succeed, parent(s) must be enabled */ 255*9b518788SAdam Skladowski .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE | CLK_GET_RATE_NOCACHE, 256*9b518788SAdam Skladowski .ops = &clk_pixel_ops, 257*9b518788SAdam Skladowski }, 258*9b518788SAdam Skladowski }; 259*9b518788SAdam Skladowski 260*9b518788SAdam Skladowski static const struct freq_tbl ftbl_disp_cc_mdss_rot_clk_src[] = { 261*9b518788SAdam Skladowski F(19200000, P_BI_TCXO, 1, 0, 0), 262*9b518788SAdam Skladowski F(192000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0), 263*9b518788SAdam Skladowski F(256000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 264*9b518788SAdam Skladowski F(307200000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0), 265*9b518788SAdam Skladowski { } 266*9b518788SAdam Skladowski }; 267*9b518788SAdam Skladowski 268*9b518788SAdam Skladowski static struct clk_rcg2 disp_cc_mdss_rot_clk_src = { 269*9b518788SAdam Skladowski .cmd_rcgr = 0x208c, 270*9b518788SAdam Skladowski .mnd_width = 0, 271*9b518788SAdam Skladowski .hid_width = 5, 272*9b518788SAdam Skladowski .parent_map = disp_cc_parent_map_3, 273*9b518788SAdam Skladowski .freq_tbl = ftbl_disp_cc_mdss_rot_clk_src, 274*9b518788SAdam Skladowski .clkr.hw.init = &(struct clk_init_data){ 275*9b518788SAdam Skladowski .name = "disp_cc_mdss_rot_clk_src", 276*9b518788SAdam Skladowski .parent_data = disp_cc_parent_data_3, 277*9b518788SAdam Skladowski .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 278*9b518788SAdam Skladowski .flags = CLK_SET_RATE_PARENT, 279*9b518788SAdam Skladowski .ops = &clk_rcg2_shared_ops, 280*9b518788SAdam Skladowski }, 281*9b518788SAdam Skladowski }; 282*9b518788SAdam Skladowski 283*9b518788SAdam Skladowski static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = { 284*9b518788SAdam Skladowski .cmd_rcgr = 0x20a4, 285*9b518788SAdam Skladowski .mnd_width = 0, 286*9b518788SAdam Skladowski .hid_width = 5, 287*9b518788SAdam Skladowski .parent_map = disp_cc_parent_map_1, 288*9b518788SAdam Skladowski .freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src, 289*9b518788SAdam Skladowski .clkr.hw.init = &(struct clk_init_data){ 290*9b518788SAdam Skladowski .name = "disp_cc_mdss_vsync_clk_src", 291*9b518788SAdam Skladowski .parent_data = disp_cc_parent_data_1, 292*9b518788SAdam Skladowski .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 293*9b518788SAdam Skladowski .flags = CLK_SET_RATE_PARENT, 294*9b518788SAdam Skladowski .ops = &clk_rcg2_shared_ops, 295*9b518788SAdam Skladowski }, 296*9b518788SAdam Skladowski }; 297*9b518788SAdam Skladowski 298*9b518788SAdam Skladowski static const struct freq_tbl ftbl_disp_cc_sleep_clk_src[] = { 299*9b518788SAdam Skladowski F(32764, P_SLEEP_CLK, 1, 0, 0), 300*9b518788SAdam Skladowski { } 301*9b518788SAdam Skladowski }; 302*9b518788SAdam Skladowski 303*9b518788SAdam Skladowski static struct clk_rcg2 disp_cc_sleep_clk_src = { 304*9b518788SAdam Skladowski .cmd_rcgr = 0x6050, 305*9b518788SAdam Skladowski .mnd_width = 0, 306*9b518788SAdam Skladowski .hid_width = 5, 307*9b518788SAdam Skladowski .parent_map = disp_cc_parent_map_5, 308*9b518788SAdam Skladowski .freq_tbl = ftbl_disp_cc_sleep_clk_src, 309*9b518788SAdam Skladowski .clkr.hw.init = &(struct clk_init_data){ 310*9b518788SAdam Skladowski .name = "disp_cc_sleep_clk_src", 311*9b518788SAdam Skladowski .parent_data = disp_cc_parent_data_5, 312*9b518788SAdam Skladowski .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), 313*9b518788SAdam Skladowski .ops = &clk_rcg2_ops, 314*9b518788SAdam Skladowski }, 315*9b518788SAdam Skladowski }; 316*9b518788SAdam Skladowski 317*9b518788SAdam Skladowski static struct clk_branch disp_cc_mdss_ahb_clk = { 318*9b518788SAdam Skladowski .halt_reg = 0x2044, 319*9b518788SAdam Skladowski .halt_check = BRANCH_HALT, 320*9b518788SAdam Skladowski .clkr = { 321*9b518788SAdam Skladowski .enable_reg = 0x2044, 322*9b518788SAdam Skladowski .enable_mask = BIT(0), 323*9b518788SAdam Skladowski .hw.init = &(struct clk_init_data){ 324*9b518788SAdam Skladowski .name = "disp_cc_mdss_ahb_clk", 325*9b518788SAdam Skladowski .parent_hws = (const struct clk_hw*[]){ 326*9b518788SAdam Skladowski &disp_cc_mdss_ahb_clk_src.clkr.hw, 327*9b518788SAdam Skladowski }, 328*9b518788SAdam Skladowski .num_parents = 1, 329*9b518788SAdam Skladowski .flags = CLK_SET_RATE_PARENT, 330*9b518788SAdam Skladowski .ops = &clk_branch2_ops, 331*9b518788SAdam Skladowski }, 332*9b518788SAdam Skladowski }, 333*9b518788SAdam Skladowski }; 334*9b518788SAdam Skladowski 335*9b518788SAdam Skladowski static struct clk_branch disp_cc_mdss_byte0_clk = { 336*9b518788SAdam Skladowski .halt_reg = 0x2024, 337*9b518788SAdam Skladowski .halt_check = BRANCH_HALT, 338*9b518788SAdam Skladowski .clkr = { 339*9b518788SAdam Skladowski .enable_reg = 0x2024, 340*9b518788SAdam Skladowski .enable_mask = BIT(0), 341*9b518788SAdam Skladowski .hw.init = &(struct clk_init_data){ 342*9b518788SAdam Skladowski .name = "disp_cc_mdss_byte0_clk", 343*9b518788SAdam Skladowski .parent_hws = (const struct clk_hw*[]){ 344*9b518788SAdam Skladowski &disp_cc_mdss_byte0_clk_src.clkr.hw, 345*9b518788SAdam Skladowski }, 346*9b518788SAdam Skladowski .num_parents = 1, 347*9b518788SAdam Skladowski .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, 348*9b518788SAdam Skladowski .ops = &clk_branch2_ops, 349*9b518788SAdam Skladowski }, 350*9b518788SAdam Skladowski }, 351*9b518788SAdam Skladowski }; 352*9b518788SAdam Skladowski 353*9b518788SAdam Skladowski static struct clk_branch disp_cc_mdss_byte0_intf_clk = { 354*9b518788SAdam Skladowski .halt_reg = 0x2028, 355*9b518788SAdam Skladowski .halt_check = BRANCH_HALT, 356*9b518788SAdam Skladowski .clkr = { 357*9b518788SAdam Skladowski .enable_reg = 0x2028, 358*9b518788SAdam Skladowski .enable_mask = BIT(0), 359*9b518788SAdam Skladowski .hw.init = &(struct clk_init_data){ 360*9b518788SAdam Skladowski .name = "disp_cc_mdss_byte0_intf_clk", 361*9b518788SAdam Skladowski .parent_hws = (const struct clk_hw*[]){ 362*9b518788SAdam Skladowski &disp_cc_mdss_byte0_div_clk_src.clkr.hw, 363*9b518788SAdam Skladowski }, 364*9b518788SAdam Skladowski .num_parents = 1, 365*9b518788SAdam Skladowski .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, 366*9b518788SAdam Skladowski .ops = &clk_branch2_ops, 367*9b518788SAdam Skladowski }, 368*9b518788SAdam Skladowski }, 369*9b518788SAdam Skladowski }; 370*9b518788SAdam Skladowski 371*9b518788SAdam Skladowski static struct clk_branch disp_cc_mdss_esc0_clk = { 372*9b518788SAdam Skladowski .halt_reg = 0x202c, 373*9b518788SAdam Skladowski .halt_check = BRANCH_HALT, 374*9b518788SAdam Skladowski .clkr = { 375*9b518788SAdam Skladowski .enable_reg = 0x202c, 376*9b518788SAdam Skladowski .enable_mask = BIT(0), 377*9b518788SAdam Skladowski .hw.init = &(struct clk_init_data){ 378*9b518788SAdam Skladowski .name = "disp_cc_mdss_esc0_clk", 379*9b518788SAdam Skladowski .parent_hws = (const struct clk_hw*[]){ 380*9b518788SAdam Skladowski &disp_cc_mdss_esc0_clk_src.clkr.hw, 381*9b518788SAdam Skladowski }, 382*9b518788SAdam Skladowski .num_parents = 1, 383*9b518788SAdam Skladowski .flags = CLK_SET_RATE_PARENT, 384*9b518788SAdam Skladowski .ops = &clk_branch2_ops, 385*9b518788SAdam Skladowski }, 386*9b518788SAdam Skladowski }, 387*9b518788SAdam Skladowski }; 388*9b518788SAdam Skladowski 389*9b518788SAdam Skladowski static struct clk_branch disp_cc_mdss_mdp_clk = { 390*9b518788SAdam Skladowski .halt_reg = 0x2008, 391*9b518788SAdam Skladowski .halt_check = BRANCH_HALT, 392*9b518788SAdam Skladowski .clkr = { 393*9b518788SAdam Skladowski .enable_reg = 0x2008, 394*9b518788SAdam Skladowski .enable_mask = BIT(0), 395*9b518788SAdam Skladowski .hw.init = &(struct clk_init_data){ 396*9b518788SAdam Skladowski .name = "disp_cc_mdss_mdp_clk", 397*9b518788SAdam Skladowski .parent_hws = (const struct clk_hw*[]){ 398*9b518788SAdam Skladowski &disp_cc_mdss_mdp_clk_src.clkr.hw, 399*9b518788SAdam Skladowski }, 400*9b518788SAdam Skladowski .num_parents = 1, 401*9b518788SAdam Skladowski .flags = CLK_SET_RATE_PARENT, 402*9b518788SAdam Skladowski .ops = &clk_branch2_ops, 403*9b518788SAdam Skladowski }, 404*9b518788SAdam Skladowski }, 405*9b518788SAdam Skladowski }; 406*9b518788SAdam Skladowski 407*9b518788SAdam Skladowski static struct clk_branch disp_cc_mdss_mdp_lut_clk = { 408*9b518788SAdam Skladowski .halt_reg = 0x2018, 409*9b518788SAdam Skladowski .halt_check = BRANCH_HALT_VOTED, 410*9b518788SAdam Skladowski .clkr = { 411*9b518788SAdam Skladowski .enable_reg = 0x2018, 412*9b518788SAdam Skladowski .enable_mask = BIT(0), 413*9b518788SAdam Skladowski .hw.init = &(struct clk_init_data){ 414*9b518788SAdam Skladowski .name = "disp_cc_mdss_mdp_lut_clk", 415*9b518788SAdam Skladowski .parent_hws = (const struct clk_hw*[]){ 416*9b518788SAdam Skladowski &disp_cc_mdss_mdp_clk_src.clkr.hw, 417*9b518788SAdam Skladowski }, 418*9b518788SAdam Skladowski .num_parents = 1, 419*9b518788SAdam Skladowski .flags = CLK_SET_RATE_PARENT, 420*9b518788SAdam Skladowski .ops = &clk_branch2_ops, 421*9b518788SAdam Skladowski }, 422*9b518788SAdam Skladowski }, 423*9b518788SAdam Skladowski }; 424*9b518788SAdam Skladowski 425*9b518788SAdam Skladowski static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = { 426*9b518788SAdam Skladowski .halt_reg = 0x4004, 427*9b518788SAdam Skladowski .halt_check = BRANCH_HALT_VOTED, 428*9b518788SAdam Skladowski .clkr = { 429*9b518788SAdam Skladowski .enable_reg = 0x4004, 430*9b518788SAdam Skladowski .enable_mask = BIT(0), 431*9b518788SAdam Skladowski .hw.init = &(struct clk_init_data){ 432*9b518788SAdam Skladowski .name = "disp_cc_mdss_non_gdsc_ahb_clk", 433*9b518788SAdam Skladowski .parent_hws = (const struct clk_hw*[]){ 434*9b518788SAdam Skladowski &disp_cc_mdss_ahb_clk_src.clkr.hw, 435*9b518788SAdam Skladowski }, 436*9b518788SAdam Skladowski .num_parents = 1, 437*9b518788SAdam Skladowski .flags = CLK_SET_RATE_PARENT, 438*9b518788SAdam Skladowski .ops = &clk_branch2_ops, 439*9b518788SAdam Skladowski }, 440*9b518788SAdam Skladowski }, 441*9b518788SAdam Skladowski }; 442*9b518788SAdam Skladowski 443*9b518788SAdam Skladowski static struct clk_branch disp_cc_mdss_pclk0_clk = { 444*9b518788SAdam Skladowski .halt_reg = 0x2004, 445*9b518788SAdam Skladowski .halt_check = BRANCH_HALT, 446*9b518788SAdam Skladowski .clkr = { 447*9b518788SAdam Skladowski .enable_reg = 0x2004, 448*9b518788SAdam Skladowski .enable_mask = BIT(0), 449*9b518788SAdam Skladowski .hw.init = &(struct clk_init_data){ 450*9b518788SAdam Skladowski .name = "disp_cc_mdss_pclk0_clk", 451*9b518788SAdam Skladowski .parent_hws = (const struct clk_hw*[]){ 452*9b518788SAdam Skladowski &disp_cc_mdss_pclk0_clk_src.clkr.hw, 453*9b518788SAdam Skladowski }, 454*9b518788SAdam Skladowski .num_parents = 1, 455*9b518788SAdam Skladowski .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, 456*9b518788SAdam Skladowski .ops = &clk_branch2_ops, 457*9b518788SAdam Skladowski }, 458*9b518788SAdam Skladowski }, 459*9b518788SAdam Skladowski }; 460*9b518788SAdam Skladowski 461*9b518788SAdam Skladowski static struct clk_branch disp_cc_mdss_rot_clk = { 462*9b518788SAdam Skladowski .halt_reg = 0x2010, 463*9b518788SAdam Skladowski .halt_check = BRANCH_HALT, 464*9b518788SAdam Skladowski .clkr = { 465*9b518788SAdam Skladowski .enable_reg = 0x2010, 466*9b518788SAdam Skladowski .enable_mask = BIT(0), 467*9b518788SAdam Skladowski .hw.init = &(struct clk_init_data){ 468*9b518788SAdam Skladowski .name = "disp_cc_mdss_rot_clk", 469*9b518788SAdam Skladowski .parent_names = (const char *[]){ 470*9b518788SAdam Skladowski "disp_cc_mdss_rot_clk_src", 471*9b518788SAdam Skladowski }, 472*9b518788SAdam Skladowski .num_parents = 1, 473*9b518788SAdam Skladowski .flags = CLK_SET_RATE_PARENT, 474*9b518788SAdam Skladowski .ops = &clk_branch2_ops, 475*9b518788SAdam Skladowski }, 476*9b518788SAdam Skladowski }, 477*9b518788SAdam Skladowski }; 478*9b518788SAdam Skladowski 479*9b518788SAdam Skladowski static struct clk_branch disp_cc_mdss_vsync_clk = { 480*9b518788SAdam Skladowski .halt_reg = 0x2020, 481*9b518788SAdam Skladowski .halt_check = BRANCH_HALT, 482*9b518788SAdam Skladowski .clkr = { 483*9b518788SAdam Skladowski .enable_reg = 0x2020, 484*9b518788SAdam Skladowski .enable_mask = BIT(0), 485*9b518788SAdam Skladowski .hw.init = &(struct clk_init_data){ 486*9b518788SAdam Skladowski .name = "disp_cc_mdss_vsync_clk", 487*9b518788SAdam Skladowski .parent_hws = (const struct clk_hw*[]){ 488*9b518788SAdam Skladowski &disp_cc_mdss_vsync_clk_src.clkr.hw, 489*9b518788SAdam Skladowski }, 490*9b518788SAdam Skladowski .num_parents = 1, 491*9b518788SAdam Skladowski .flags = CLK_SET_RATE_PARENT, 492*9b518788SAdam Skladowski .ops = &clk_branch2_ops, 493*9b518788SAdam Skladowski }, 494*9b518788SAdam Skladowski }, 495*9b518788SAdam Skladowski }; 496*9b518788SAdam Skladowski 497*9b518788SAdam Skladowski static struct clk_branch disp_cc_sleep_clk = { 498*9b518788SAdam Skladowski .halt_reg = 0x6068, 499*9b518788SAdam Skladowski .halt_check = BRANCH_HALT, 500*9b518788SAdam Skladowski .clkr = { 501*9b518788SAdam Skladowski .enable_reg = 0x6068, 502*9b518788SAdam Skladowski .enable_mask = BIT(0), 503*9b518788SAdam Skladowski .hw.init = &(struct clk_init_data){ 504*9b518788SAdam Skladowski .name = "disp_cc_sleep_clk", 505*9b518788SAdam Skladowski .parent_hws = (const struct clk_hw*[]){ 506*9b518788SAdam Skladowski &disp_cc_sleep_clk_src.clkr.hw, 507*9b518788SAdam Skladowski }, 508*9b518788SAdam Skladowski .num_parents = 1, 509*9b518788SAdam Skladowski .flags = CLK_SET_RATE_PARENT, 510*9b518788SAdam Skladowski .ops = &clk_branch2_ops, 511*9b518788SAdam Skladowski }, 512*9b518788SAdam Skladowski }, 513*9b518788SAdam Skladowski }; 514*9b518788SAdam Skladowski 515*9b518788SAdam Skladowski static struct gdsc mdss_gdsc = { 516*9b518788SAdam Skladowski .gdscr = 0x3000, 517*9b518788SAdam Skladowski .pd = { 518*9b518788SAdam Skladowski .name = "mdss_gdsc", 519*9b518788SAdam Skladowski }, 520*9b518788SAdam Skladowski .pwrsts = PWRSTS_OFF_ON, 521*9b518788SAdam Skladowski .flags = HW_CTRL, 522*9b518788SAdam Skladowski }; 523*9b518788SAdam Skladowski 524*9b518788SAdam Skladowski static struct gdsc *disp_cc_sm6115_gdscs[] = { 525*9b518788SAdam Skladowski [MDSS_GDSC] = &mdss_gdsc, 526*9b518788SAdam Skladowski }; 527*9b518788SAdam Skladowski 528*9b518788SAdam Skladowski static struct clk_regmap *disp_cc_sm6115_clocks[] = { 529*9b518788SAdam Skladowski [DISP_CC_PLL0] = &disp_cc_pll0.clkr, 530*9b518788SAdam Skladowski [DISP_CC_PLL0_OUT_MAIN] = &disp_cc_pll0_out_main.clkr, 531*9b518788SAdam Skladowski [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr, 532*9b518788SAdam Skladowski [DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr, 533*9b518788SAdam Skladowski [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr, 534*9b518788SAdam Skladowski [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr, 535*9b518788SAdam Skladowski [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr, 536*9b518788SAdam Skladowski [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr, 537*9b518788SAdam Skladowski [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr, 538*9b518788SAdam Skladowski [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr, 539*9b518788SAdam Skladowski [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr, 540*9b518788SAdam Skladowski [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr, 541*9b518788SAdam Skladowski [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr, 542*9b518788SAdam Skladowski [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr, 543*9b518788SAdam Skladowski [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr, 544*9b518788SAdam Skladowski [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr, 545*9b518788SAdam Skladowski [DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr, 546*9b518788SAdam Skladowski [DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr, 547*9b518788SAdam Skladowski [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr, 548*9b518788SAdam Skladowski [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr, 549*9b518788SAdam Skladowski [DISP_CC_SLEEP_CLK] = &disp_cc_sleep_clk.clkr, 550*9b518788SAdam Skladowski [DISP_CC_SLEEP_CLK_SRC] = &disp_cc_sleep_clk_src.clkr, 551*9b518788SAdam Skladowski }; 552*9b518788SAdam Skladowski 553*9b518788SAdam Skladowski static const struct regmap_config disp_cc_sm6115_regmap_config = { 554*9b518788SAdam Skladowski .reg_bits = 32, 555*9b518788SAdam Skladowski .reg_stride = 4, 556*9b518788SAdam Skladowski .val_bits = 32, 557*9b518788SAdam Skladowski .max_register = 0x10000, 558*9b518788SAdam Skladowski .fast_io = true, 559*9b518788SAdam Skladowski }; 560*9b518788SAdam Skladowski 561*9b518788SAdam Skladowski static const struct qcom_cc_desc disp_cc_sm6115_desc = { 562*9b518788SAdam Skladowski .config = &disp_cc_sm6115_regmap_config, 563*9b518788SAdam Skladowski .clks = disp_cc_sm6115_clocks, 564*9b518788SAdam Skladowski .num_clks = ARRAY_SIZE(disp_cc_sm6115_clocks), 565*9b518788SAdam Skladowski .gdscs = disp_cc_sm6115_gdscs, 566*9b518788SAdam Skladowski .num_gdscs = ARRAY_SIZE(disp_cc_sm6115_gdscs), 567*9b518788SAdam Skladowski }; 568*9b518788SAdam Skladowski 569*9b518788SAdam Skladowski static const struct of_device_id disp_cc_sm6115_match_table[] = { 570*9b518788SAdam Skladowski { .compatible = "qcom,sm6115-dispcc" }, 571*9b518788SAdam Skladowski { } 572*9b518788SAdam Skladowski }; 573*9b518788SAdam Skladowski MODULE_DEVICE_TABLE(of, disp_cc_sm6115_match_table); 574*9b518788SAdam Skladowski 575*9b518788SAdam Skladowski static int disp_cc_sm6115_probe(struct platform_device *pdev) 576*9b518788SAdam Skladowski { 577*9b518788SAdam Skladowski struct regmap *regmap; 578*9b518788SAdam Skladowski int ret; 579*9b518788SAdam Skladowski 580*9b518788SAdam Skladowski regmap = qcom_cc_map(pdev, &disp_cc_sm6115_desc); 581*9b518788SAdam Skladowski if (IS_ERR(regmap)) 582*9b518788SAdam Skladowski return PTR_ERR(regmap); 583*9b518788SAdam Skladowski 584*9b518788SAdam Skladowski clk_alpha_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); 585*9b518788SAdam Skladowski 586*9b518788SAdam Skladowski /* Keep DISP_CC_XO_CLK always-ON */ 587*9b518788SAdam Skladowski regmap_update_bits(regmap, 0x604c, BIT(0), BIT(0)); 588*9b518788SAdam Skladowski 589*9b518788SAdam Skladowski ret = qcom_cc_really_probe(pdev, &disp_cc_sm6115_desc, regmap); 590*9b518788SAdam Skladowski if (ret) { 591*9b518788SAdam Skladowski dev_err(&pdev->dev, "Failed to register DISP CC clocks\n"); 592*9b518788SAdam Skladowski return ret; 593*9b518788SAdam Skladowski } 594*9b518788SAdam Skladowski 595*9b518788SAdam Skladowski return ret; 596*9b518788SAdam Skladowski } 597*9b518788SAdam Skladowski 598*9b518788SAdam Skladowski static struct platform_driver disp_cc_sm6115_driver = { 599*9b518788SAdam Skladowski .probe = disp_cc_sm6115_probe, 600*9b518788SAdam Skladowski .driver = { 601*9b518788SAdam Skladowski .name = "dispcc-sm6115", 602*9b518788SAdam Skladowski .of_match_table = disp_cc_sm6115_match_table, 603*9b518788SAdam Skladowski }, 604*9b518788SAdam Skladowski }; 605*9b518788SAdam Skladowski 606*9b518788SAdam Skladowski module_platform_driver(disp_cc_sm6115_driver); 607*9b518788SAdam Skladowski MODULE_DESCRIPTION("Qualcomm SM6115 Display Clock controller"); 608*9b518788SAdam Skladowski MODULE_LICENSE("GPL"); 609