1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/export.h> 7 #include <linux/module.h> 8 #include <linux/regmap.h> 9 #include <linux/platform_device.h> 10 #include <linux/clk-provider.h> 11 #include <linux/reset-controller.h> 12 #include <linux/of.h> 13 14 #include "common.h" 15 #include "clk-rcg.h" 16 #include "clk-regmap.h" 17 #include "reset.h" 18 #include "gdsc.h" 19 20 struct qcom_cc { 21 struct qcom_reset_controller reset; 22 struct clk_regmap **rclks; 23 size_t num_rclks; 24 }; 25 26 const 27 struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, unsigned long rate) 28 { 29 if (!f) 30 return NULL; 31 32 if (!f->freq) 33 return f; 34 35 for (; f->freq; f++) 36 if (rate <= f->freq) 37 return f; 38 39 /* Default to our fastest rate */ 40 return f - 1; 41 } 42 EXPORT_SYMBOL_GPL(qcom_find_freq); 43 44 const struct freq_tbl *qcom_find_freq_floor(const struct freq_tbl *f, 45 unsigned long rate) 46 { 47 const struct freq_tbl *best = NULL; 48 49 for ( ; f->freq; f++) { 50 if (rate >= f->freq) 51 best = f; 52 else 53 break; 54 } 55 56 return best; 57 } 58 EXPORT_SYMBOL_GPL(qcom_find_freq_floor); 59 60 int qcom_find_src_index(struct clk_hw *hw, const struct parent_map *map, u8 src) 61 { 62 int i, num_parents = clk_hw_get_num_parents(hw); 63 64 for (i = 0; i < num_parents; i++) 65 if (src == map[i].src) 66 return i; 67 68 return -ENOENT; 69 } 70 EXPORT_SYMBOL_GPL(qcom_find_src_index); 71 72 int qcom_find_cfg_index(struct clk_hw *hw, const struct parent_map *map, u8 cfg) 73 { 74 int i, num_parents = clk_hw_get_num_parents(hw); 75 76 for (i = 0; i < num_parents; i++) 77 if (cfg == map[i].cfg) 78 return i; 79 80 return -ENOENT; 81 } 82 EXPORT_SYMBOL_GPL(qcom_find_cfg_index); 83 84 struct regmap * 85 qcom_cc_map(struct platform_device *pdev, const struct qcom_cc_desc *desc) 86 { 87 void __iomem *base; 88 struct device *dev = &pdev->dev; 89 90 base = devm_platform_ioremap_resource(pdev, 0); 91 if (IS_ERR(base)) 92 return ERR_CAST(base); 93 94 return devm_regmap_init_mmio(dev, base, desc->config); 95 } 96 EXPORT_SYMBOL_GPL(qcom_cc_map); 97 98 void 99 qcom_pll_set_fsm_mode(struct regmap *map, u32 reg, u8 bias_count, u8 lock_count) 100 { 101 u32 val; 102 u32 mask; 103 104 /* De-assert reset to FSM */ 105 regmap_update_bits(map, reg, PLL_VOTE_FSM_RESET, 0); 106 107 /* Program bias count and lock count */ 108 val = bias_count << PLL_BIAS_COUNT_SHIFT | 109 lock_count << PLL_LOCK_COUNT_SHIFT; 110 mask = PLL_BIAS_COUNT_MASK << PLL_BIAS_COUNT_SHIFT; 111 mask |= PLL_LOCK_COUNT_MASK << PLL_LOCK_COUNT_SHIFT; 112 regmap_update_bits(map, reg, mask, val); 113 114 /* Enable PLL FSM voting */ 115 regmap_update_bits(map, reg, PLL_VOTE_FSM_ENA, PLL_VOTE_FSM_ENA); 116 } 117 EXPORT_SYMBOL_GPL(qcom_pll_set_fsm_mode); 118 119 static void qcom_cc_gdsc_unregister(void *data) 120 { 121 gdsc_unregister(data); 122 } 123 124 /* 125 * Backwards compatibility with old DTs. Register a pass-through factor 1/1 126 * clock to translate 'path' clk into 'name' clk and register the 'path' 127 * clk as a fixed rate clock if it isn't present. 128 */ 129 static int _qcom_cc_register_board_clk(struct device *dev, const char *path, 130 const char *name, unsigned long rate, 131 bool add_factor) 132 { 133 struct device_node *node = NULL; 134 struct device_node *clocks_node; 135 struct clk_fixed_factor *factor; 136 struct clk_fixed_rate *fixed; 137 struct clk_init_data init_data = { }; 138 int ret; 139 140 clocks_node = of_find_node_by_path("/clocks"); 141 if (clocks_node) { 142 node = of_get_child_by_name(clocks_node, path); 143 of_node_put(clocks_node); 144 } 145 146 if (!node) { 147 fixed = devm_kzalloc(dev, sizeof(*fixed), GFP_KERNEL); 148 if (!fixed) 149 return -EINVAL; 150 151 fixed->fixed_rate = rate; 152 fixed->hw.init = &init_data; 153 154 init_data.name = path; 155 init_data.ops = &clk_fixed_rate_ops; 156 157 ret = devm_clk_hw_register(dev, &fixed->hw); 158 if (ret) 159 return ret; 160 } 161 of_node_put(node); 162 163 if (add_factor) { 164 factor = devm_kzalloc(dev, sizeof(*factor), GFP_KERNEL); 165 if (!factor) 166 return -EINVAL; 167 168 factor->mult = factor->div = 1; 169 factor->hw.init = &init_data; 170 171 init_data.name = name; 172 init_data.parent_names = &path; 173 init_data.num_parents = 1; 174 init_data.flags = 0; 175 init_data.ops = &clk_fixed_factor_ops; 176 177 ret = devm_clk_hw_register(dev, &factor->hw); 178 if (ret) 179 return ret; 180 } 181 182 return 0; 183 } 184 185 int qcom_cc_register_board_clk(struct device *dev, const char *path, 186 const char *name, unsigned long rate) 187 { 188 bool add_factor = true; 189 190 /* 191 * TODO: The RPM clock driver currently does not support the xo clock. 192 * When xo is added to the RPM clock driver, we should change this 193 * function to skip registration of xo factor clocks. 194 */ 195 196 return _qcom_cc_register_board_clk(dev, path, name, rate, add_factor); 197 } 198 EXPORT_SYMBOL_GPL(qcom_cc_register_board_clk); 199 200 int qcom_cc_register_sleep_clk(struct device *dev) 201 { 202 return _qcom_cc_register_board_clk(dev, "sleep_clk", "sleep_clk_src", 203 32768, true); 204 } 205 EXPORT_SYMBOL_GPL(qcom_cc_register_sleep_clk); 206 207 /* Drop 'protected-clocks' from the list of clocks to register */ 208 static void qcom_cc_drop_protected(struct device *dev, struct qcom_cc *cc) 209 { 210 struct device_node *np = dev->of_node; 211 u32 i; 212 213 of_property_for_each_u32(np, "protected-clocks", i) { 214 if (i >= cc->num_rclks) 215 continue; 216 217 cc->rclks[i] = NULL; 218 } 219 } 220 221 static struct clk_hw *qcom_cc_clk_hw_get(struct of_phandle_args *clkspec, 222 void *data) 223 { 224 struct qcom_cc *cc = data; 225 unsigned int idx = clkspec->args[0]; 226 227 if (idx >= cc->num_rclks) { 228 pr_err("%s: invalid index %u\n", __func__, idx); 229 return ERR_PTR(-EINVAL); 230 } 231 232 return cc->rclks[idx] ? &cc->rclks[idx]->hw : NULL; 233 } 234 235 int qcom_cc_really_probe(struct platform_device *pdev, 236 const struct qcom_cc_desc *desc, struct regmap *regmap) 237 { 238 int i, ret; 239 struct device *dev = &pdev->dev; 240 struct qcom_reset_controller *reset; 241 struct qcom_cc *cc; 242 struct gdsc_desc *scd; 243 size_t num_clks = desc->num_clks; 244 struct clk_regmap **rclks = desc->clks; 245 size_t num_clk_hws = desc->num_clk_hws; 246 struct clk_hw **clk_hws = desc->clk_hws; 247 248 cc = devm_kzalloc(dev, sizeof(*cc), GFP_KERNEL); 249 if (!cc) 250 return -ENOMEM; 251 252 reset = &cc->reset; 253 reset->rcdev.of_node = dev->of_node; 254 reset->rcdev.ops = &qcom_reset_ops; 255 reset->rcdev.owner = dev->driver->owner; 256 reset->rcdev.nr_resets = desc->num_resets; 257 reset->regmap = regmap; 258 reset->reset_map = desc->resets; 259 260 ret = devm_reset_controller_register(dev, &reset->rcdev); 261 if (ret) 262 return ret; 263 264 if (desc->gdscs && desc->num_gdscs) { 265 scd = devm_kzalloc(dev, sizeof(*scd), GFP_KERNEL); 266 if (!scd) 267 return -ENOMEM; 268 scd->dev = dev; 269 scd->scs = desc->gdscs; 270 scd->num = desc->num_gdscs; 271 ret = gdsc_register(scd, &reset->rcdev, regmap); 272 if (ret) 273 return ret; 274 ret = devm_add_action_or_reset(dev, qcom_cc_gdsc_unregister, 275 scd); 276 if (ret) 277 return ret; 278 } 279 280 cc->rclks = rclks; 281 cc->num_rclks = num_clks; 282 283 qcom_cc_drop_protected(dev, cc); 284 285 for (i = 0; i < num_clk_hws; i++) { 286 ret = devm_clk_hw_register(dev, clk_hws[i]); 287 if (ret) 288 return ret; 289 } 290 291 for (i = 0; i < num_clks; i++) { 292 if (!rclks[i]) 293 continue; 294 295 ret = devm_clk_register_regmap(dev, rclks[i]); 296 if (ret) 297 return ret; 298 } 299 300 ret = devm_of_clk_add_hw_provider(dev, qcom_cc_clk_hw_get, cc); 301 if (ret) 302 return ret; 303 304 return 0; 305 } 306 EXPORT_SYMBOL_GPL(qcom_cc_really_probe); 307 308 int qcom_cc_probe(struct platform_device *pdev, const struct qcom_cc_desc *desc) 309 { 310 struct regmap *regmap; 311 312 regmap = qcom_cc_map(pdev, desc); 313 if (IS_ERR(regmap)) 314 return PTR_ERR(regmap); 315 316 return qcom_cc_really_probe(pdev, desc, regmap); 317 } 318 EXPORT_SYMBOL_GPL(qcom_cc_probe); 319 320 int qcom_cc_probe_by_index(struct platform_device *pdev, int index, 321 const struct qcom_cc_desc *desc) 322 { 323 struct regmap *regmap; 324 void __iomem *base; 325 326 base = devm_platform_ioremap_resource(pdev, index); 327 if (IS_ERR(base)) 328 return -ENOMEM; 329 330 regmap = devm_regmap_init_mmio(&pdev->dev, base, desc->config); 331 if (IS_ERR(regmap)) 332 return PTR_ERR(regmap); 333 334 return qcom_cc_really_probe(pdev, desc, regmap); 335 } 336 EXPORT_SYMBOL_GPL(qcom_cc_probe_by_index); 337 338 MODULE_LICENSE("GPL v2"); 339