1 /* 2 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include <linux/export.h> 15 #include <linux/module.h> 16 #include <linux/regmap.h> 17 #include <linux/platform_device.h> 18 #include <linux/clk-provider.h> 19 #include <linux/reset-controller.h> 20 #include <linux/of.h> 21 22 #include "common.h" 23 #include "clk-rcg.h" 24 #include "clk-regmap.h" 25 #include "reset.h" 26 #include "gdsc.h" 27 28 struct qcom_cc { 29 struct qcom_reset_controller reset; 30 struct clk_regmap **rclks; 31 size_t num_rclks; 32 }; 33 34 const 35 struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, unsigned long rate) 36 { 37 if (!f) 38 return NULL; 39 40 for (; f->freq; f++) 41 if (rate <= f->freq) 42 return f; 43 44 /* Default to our fastest rate */ 45 return f - 1; 46 } 47 EXPORT_SYMBOL_GPL(qcom_find_freq); 48 49 const struct freq_tbl *qcom_find_freq_floor(const struct freq_tbl *f, 50 unsigned long rate) 51 { 52 const struct freq_tbl *best = NULL; 53 54 for ( ; f->freq; f++) { 55 if (rate >= f->freq) 56 best = f; 57 else 58 break; 59 } 60 61 return best; 62 } 63 EXPORT_SYMBOL_GPL(qcom_find_freq_floor); 64 65 int qcom_find_src_index(struct clk_hw *hw, const struct parent_map *map, u8 src) 66 { 67 int i, num_parents = clk_hw_get_num_parents(hw); 68 69 for (i = 0; i < num_parents; i++) 70 if (src == map[i].src) 71 return i; 72 73 return -ENOENT; 74 } 75 EXPORT_SYMBOL_GPL(qcom_find_src_index); 76 77 struct regmap * 78 qcom_cc_map(struct platform_device *pdev, const struct qcom_cc_desc *desc) 79 { 80 void __iomem *base; 81 struct resource *res; 82 struct device *dev = &pdev->dev; 83 84 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 85 base = devm_ioremap_resource(dev, res); 86 if (IS_ERR(base)) 87 return ERR_CAST(base); 88 89 return devm_regmap_init_mmio(dev, base, desc->config); 90 } 91 EXPORT_SYMBOL_GPL(qcom_cc_map); 92 93 void 94 qcom_pll_set_fsm_mode(struct regmap *map, u32 reg, u8 bias_count, u8 lock_count) 95 { 96 u32 val; 97 u32 mask; 98 99 /* De-assert reset to FSM */ 100 regmap_update_bits(map, reg, PLL_VOTE_FSM_RESET, 0); 101 102 /* Program bias count and lock count */ 103 val = bias_count << PLL_BIAS_COUNT_SHIFT | 104 lock_count << PLL_LOCK_COUNT_SHIFT; 105 mask = PLL_BIAS_COUNT_MASK << PLL_BIAS_COUNT_SHIFT; 106 mask |= PLL_LOCK_COUNT_MASK << PLL_LOCK_COUNT_SHIFT; 107 regmap_update_bits(map, reg, mask, val); 108 109 /* Enable PLL FSM voting */ 110 regmap_update_bits(map, reg, PLL_VOTE_FSM_ENA, PLL_VOTE_FSM_ENA); 111 } 112 EXPORT_SYMBOL_GPL(qcom_pll_set_fsm_mode); 113 114 static void qcom_cc_gdsc_unregister(void *data) 115 { 116 gdsc_unregister(data); 117 } 118 119 /* 120 * Backwards compatibility with old DTs. Register a pass-through factor 1/1 121 * clock to translate 'path' clk into 'name' clk and register the 'path' 122 * clk as a fixed rate clock if it isn't present. 123 */ 124 static int _qcom_cc_register_board_clk(struct device *dev, const char *path, 125 const char *name, unsigned long rate, 126 bool add_factor) 127 { 128 struct device_node *node = NULL; 129 struct device_node *clocks_node; 130 struct clk_fixed_factor *factor; 131 struct clk_fixed_rate *fixed; 132 struct clk_init_data init_data = { }; 133 int ret; 134 135 clocks_node = of_find_node_by_path("/clocks"); 136 if (clocks_node) { 137 node = of_get_child_by_name(clocks_node, path); 138 of_node_put(clocks_node); 139 } 140 141 if (!node) { 142 fixed = devm_kzalloc(dev, sizeof(*fixed), GFP_KERNEL); 143 if (!fixed) 144 return -EINVAL; 145 146 fixed->fixed_rate = rate; 147 fixed->hw.init = &init_data; 148 149 init_data.name = path; 150 init_data.ops = &clk_fixed_rate_ops; 151 152 ret = devm_clk_hw_register(dev, &fixed->hw); 153 if (ret) 154 return ret; 155 } 156 of_node_put(node); 157 158 if (add_factor) { 159 factor = devm_kzalloc(dev, sizeof(*factor), GFP_KERNEL); 160 if (!factor) 161 return -EINVAL; 162 163 factor->mult = factor->div = 1; 164 factor->hw.init = &init_data; 165 166 init_data.name = name; 167 init_data.parent_names = &path; 168 init_data.num_parents = 1; 169 init_data.flags = 0; 170 init_data.ops = &clk_fixed_factor_ops; 171 172 ret = devm_clk_hw_register(dev, &factor->hw); 173 if (ret) 174 return ret; 175 } 176 177 return 0; 178 } 179 180 int qcom_cc_register_board_clk(struct device *dev, const char *path, 181 const char *name, unsigned long rate) 182 { 183 bool add_factor = true; 184 185 /* 186 * TODO: The RPM clock driver currently does not support the xo clock. 187 * When xo is added to the RPM clock driver, we should change this 188 * function to skip registration of xo factor clocks. 189 */ 190 191 return _qcom_cc_register_board_clk(dev, path, name, rate, add_factor); 192 } 193 EXPORT_SYMBOL_GPL(qcom_cc_register_board_clk); 194 195 int qcom_cc_register_sleep_clk(struct device *dev) 196 { 197 return _qcom_cc_register_board_clk(dev, "sleep_clk", "sleep_clk_src", 198 32768, true); 199 } 200 EXPORT_SYMBOL_GPL(qcom_cc_register_sleep_clk); 201 202 static struct clk_hw *qcom_cc_clk_hw_get(struct of_phandle_args *clkspec, 203 void *data) 204 { 205 struct qcom_cc *cc = data; 206 unsigned int idx = clkspec->args[0]; 207 208 if (idx >= cc->num_rclks) { 209 pr_err("%s: invalid index %u\n", __func__, idx); 210 return ERR_PTR(-EINVAL); 211 } 212 213 return cc->rclks[idx] ? &cc->rclks[idx]->hw : ERR_PTR(-ENOENT); 214 } 215 216 int qcom_cc_really_probe(struct platform_device *pdev, 217 const struct qcom_cc_desc *desc, struct regmap *regmap) 218 { 219 int i, ret; 220 struct device *dev = &pdev->dev; 221 struct qcom_reset_controller *reset; 222 struct qcom_cc *cc; 223 struct gdsc_desc *scd; 224 size_t num_clks = desc->num_clks; 225 struct clk_regmap **rclks = desc->clks; 226 227 cc = devm_kzalloc(dev, sizeof(*cc), GFP_KERNEL); 228 if (!cc) 229 return -ENOMEM; 230 231 cc->rclks = rclks; 232 cc->num_rclks = num_clks; 233 234 for (i = 0; i < num_clks; i++) { 235 if (!rclks[i]) 236 continue; 237 238 ret = devm_clk_register_regmap(dev, rclks[i]); 239 if (ret) 240 return ret; 241 } 242 243 ret = devm_of_clk_add_hw_provider(dev, qcom_cc_clk_hw_get, cc); 244 if (ret) 245 return ret; 246 247 reset = &cc->reset; 248 reset->rcdev.of_node = dev->of_node; 249 reset->rcdev.ops = &qcom_reset_ops; 250 reset->rcdev.owner = dev->driver->owner; 251 reset->rcdev.nr_resets = desc->num_resets; 252 reset->regmap = regmap; 253 reset->reset_map = desc->resets; 254 255 ret = devm_reset_controller_register(dev, &reset->rcdev); 256 if (ret) 257 return ret; 258 259 if (desc->gdscs && desc->num_gdscs) { 260 scd = devm_kzalloc(dev, sizeof(*scd), GFP_KERNEL); 261 if (!scd) 262 return -ENOMEM; 263 scd->dev = dev; 264 scd->scs = desc->gdscs; 265 scd->num = desc->num_gdscs; 266 ret = gdsc_register(scd, &reset->rcdev, regmap); 267 if (ret) 268 return ret; 269 ret = devm_add_action_or_reset(dev, qcom_cc_gdsc_unregister, 270 scd); 271 if (ret) 272 return ret; 273 } 274 275 return 0; 276 } 277 EXPORT_SYMBOL_GPL(qcom_cc_really_probe); 278 279 int qcom_cc_probe(struct platform_device *pdev, const struct qcom_cc_desc *desc) 280 { 281 struct regmap *regmap; 282 283 regmap = qcom_cc_map(pdev, desc); 284 if (IS_ERR(regmap)) 285 return PTR_ERR(regmap); 286 287 return qcom_cc_really_probe(pdev, desc, regmap); 288 } 289 EXPORT_SYMBOL_GPL(qcom_cc_probe); 290 291 MODULE_LICENSE("GPL v2"); 292