1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2016, Linaro Limited 4 * Copyright (c) 2014, The Linux Foundation. All rights reserved. 5 */ 6 7 #include <linux/clk-provider.h> 8 #include <linux/err.h> 9 #include <linux/export.h> 10 #include <linux/init.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/mutex.h> 14 #include <linux/of.h> 15 #include <linux/of_device.h> 16 #include <linux/platform_device.h> 17 #include <linux/soc/qcom/smd-rpm.h> 18 19 #include <dt-bindings/clock/qcom,rpmcc.h> 20 21 #define QCOM_RPM_KEY_SOFTWARE_ENABLE 0x6e657773 22 #define QCOM_RPM_KEY_PIN_CTRL_CLK_BUFFER_ENABLE_KEY 0x62636370 23 #define QCOM_RPM_SMD_KEY_RATE 0x007a484b 24 #define QCOM_RPM_SMD_KEY_ENABLE 0x62616e45 25 #define QCOM_RPM_SMD_KEY_STATE 0x54415453 26 #define QCOM_RPM_SCALING_ENABLE_ID 0x2 27 28 #define __DEFINE_CLK_SMD_RPM_PREFIX(_prefix, _name, _active, \ 29 type, r_id, key) \ 30 static struct clk_smd_rpm clk_smd_rpm_##_prefix##_active; \ 31 static struct clk_smd_rpm clk_smd_rpm_##_prefix##_name = { \ 32 .rpm_res_type = (type), \ 33 .rpm_clk_id = (r_id), \ 34 .rpm_key = (key), \ 35 .peer = &clk_smd_rpm_##_prefix##_active, \ 36 .rate = INT_MAX, \ 37 .hw.init = &(struct clk_init_data){ \ 38 .ops = &clk_smd_rpm_ops, \ 39 .name = #_name, \ 40 .parent_data = &(const struct clk_parent_data){ \ 41 .fw_name = "xo", \ 42 .name = "xo_board", \ 43 }, \ 44 .num_parents = 1, \ 45 }, \ 46 }; \ 47 static struct clk_smd_rpm clk_smd_rpm_##_prefix##_active = { \ 48 .rpm_res_type = (type), \ 49 .rpm_clk_id = (r_id), \ 50 .active_only = true, \ 51 .rpm_key = (key), \ 52 .peer = &clk_smd_rpm_##_prefix##_name, \ 53 .rate = INT_MAX, \ 54 .hw.init = &(struct clk_init_data){ \ 55 .ops = &clk_smd_rpm_ops, \ 56 .name = #_active, \ 57 .parent_data = &(const struct clk_parent_data){ \ 58 .fw_name = "xo", \ 59 .name = "xo_board", \ 60 }, \ 61 .num_parents = 1, \ 62 }, \ 63 } 64 65 #define __DEFINE_CLK_SMD_RPM(_name, _active, type, r_id, key) \ 66 __DEFINE_CLK_SMD_RPM_PREFIX(/* empty */, _name, _active, \ 67 type, r_id, key) 68 69 #define __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(_prefix, _name, _active,\ 70 type, r_id, r, key) \ 71 static struct clk_smd_rpm clk_smd_rpm_##_prefix##_active; \ 72 static struct clk_smd_rpm clk_smd_rpm_##_prefix##_name = { \ 73 .rpm_res_type = (type), \ 74 .rpm_clk_id = (r_id), \ 75 .rpm_key = (key), \ 76 .branch = true, \ 77 .peer = &clk_smd_rpm_##_prefix##_active, \ 78 .rate = (r), \ 79 .hw.init = &(struct clk_init_data){ \ 80 .ops = &clk_smd_rpm_branch_ops, \ 81 .name = #_name, \ 82 .parent_data = &(const struct clk_parent_data){ \ 83 .fw_name = "xo", \ 84 .name = "xo_board", \ 85 }, \ 86 .num_parents = 1, \ 87 }, \ 88 }; \ 89 static struct clk_smd_rpm clk_smd_rpm_##_prefix##_active = { \ 90 .rpm_res_type = (type), \ 91 .rpm_clk_id = (r_id), \ 92 .active_only = true, \ 93 .rpm_key = (key), \ 94 .branch = true, \ 95 .peer = &clk_smd_rpm_##_prefix##_name, \ 96 .rate = (r), \ 97 .hw.init = &(struct clk_init_data){ \ 98 .ops = &clk_smd_rpm_branch_ops, \ 99 .name = #_active, \ 100 .parent_data = &(const struct clk_parent_data){ \ 101 .fw_name = "xo", \ 102 .name = "xo_board", \ 103 }, \ 104 .num_parents = 1, \ 105 }, \ 106 } 107 108 #define __DEFINE_CLK_SMD_RPM_BRANCH(_name, _active, type, r_id, r, key) \ 109 __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(/* empty */, \ 110 _name, _active, type, r_id, r, key) 111 112 #define DEFINE_CLK_SMD_RPM(_name, type, r_id) \ 113 __DEFINE_CLK_SMD_RPM(_name##_clk, _name##_a_clk, \ 114 type, r_id, QCOM_RPM_SMD_KEY_RATE) 115 116 #define DEFINE_CLK_SMD_RPM_BUS(_name, r_id) \ 117 __DEFINE_CLK_SMD_RPM_PREFIX(bus_##r_id##_, \ 118 _name##_clk, _name##_a_clk, QCOM_SMD_RPM_BUS_CLK, r_id, \ 119 QCOM_RPM_SMD_KEY_RATE) 120 121 #define DEFINE_CLK_SMD_RPM_CLK_SRC(_name, type, r_id) \ 122 __DEFINE_CLK_SMD_RPM( \ 123 _name##_clk_src, _name##_a_clk_src, \ 124 type, r_id, QCOM_RPM_SMD_KEY_RATE) 125 126 #define DEFINE_CLK_SMD_RPM_BRANCH(_name, type, r_id, r) \ 127 __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(branch_, \ 128 _name##_clk, _name##_a_clk, \ 129 type, r_id, r, QCOM_RPM_SMD_KEY_ENABLE) 130 131 #define DEFINE_CLK_SMD_RPM_BRANCH_A(_name, type, r_id, r) \ 132 __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(branch_, \ 133 _name, _name##_a, type, \ 134 r_id, r, QCOM_RPM_SMD_KEY_ENABLE) 135 136 #define DEFINE_CLK_SMD_RPM_QDSS(_name, type, r_id) \ 137 __DEFINE_CLK_SMD_RPM(_name##_clk, _name##_a_clk, \ 138 type, r_id, QCOM_RPM_SMD_KEY_STATE) 139 140 #define DEFINE_CLK_SMD_RPM_XO_BUFFER(_name, r_id, r) \ 141 __DEFINE_CLK_SMD_RPM_BRANCH(_name, _name##_a, \ 142 QCOM_SMD_RPM_CLK_BUF_A, r_id, r, \ 143 QCOM_RPM_KEY_SOFTWARE_ENABLE) 144 145 #define DEFINE_CLK_SMD_RPM_XO_BUFFER_PREFIX(_prefix, _name, r_id, r) \ 146 __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(_prefix, \ 147 _name, _name##_a, \ 148 QCOM_SMD_RPM_CLK_BUF_A, r_id, r, \ 149 QCOM_RPM_KEY_SOFTWARE_ENABLE) 150 151 #define DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(_name, r_id, r) \ 152 DEFINE_CLK_SMD_RPM_XO_BUFFER(_name, r_id, r); \ 153 __DEFINE_CLK_SMD_RPM_BRANCH(_name##_pin, _name##_a##_pin, \ 154 QCOM_SMD_RPM_CLK_BUF_A, r_id, r, \ 155 QCOM_RPM_KEY_PIN_CTRL_CLK_BUFFER_ENABLE_KEY) 156 157 #define to_clk_smd_rpm(_hw) container_of(_hw, struct clk_smd_rpm, hw) 158 159 struct clk_smd_rpm { 160 const int rpm_res_type; 161 const int rpm_key; 162 const int rpm_clk_id; 163 const bool active_only; 164 bool enabled; 165 bool branch; 166 struct clk_smd_rpm *peer; 167 struct clk_hw hw; 168 unsigned long rate; 169 struct qcom_smd_rpm *rpm; 170 }; 171 172 struct clk_smd_rpm_req { 173 __le32 key; 174 __le32 nbytes; 175 __le32 value; 176 }; 177 178 struct rpm_smd_clk_desc { 179 struct clk_smd_rpm **clks; 180 size_t num_clks; 181 }; 182 183 static DEFINE_MUTEX(rpm_smd_clk_lock); 184 185 static int clk_smd_rpm_handoff(struct clk_smd_rpm *r) 186 { 187 int ret; 188 struct clk_smd_rpm_req req = { 189 .key = cpu_to_le32(r->rpm_key), 190 .nbytes = cpu_to_le32(sizeof(u32)), 191 .value = cpu_to_le32(r->branch ? 1 : INT_MAX), 192 }; 193 194 ret = qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_ACTIVE_STATE, 195 r->rpm_res_type, r->rpm_clk_id, &req, 196 sizeof(req)); 197 if (ret) 198 return ret; 199 ret = qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_SLEEP_STATE, 200 r->rpm_res_type, r->rpm_clk_id, &req, 201 sizeof(req)); 202 if (ret) 203 return ret; 204 205 return 0; 206 } 207 208 static int clk_smd_rpm_set_rate_active(struct clk_smd_rpm *r, 209 unsigned long rate) 210 { 211 struct clk_smd_rpm_req req = { 212 .key = cpu_to_le32(r->rpm_key), 213 .nbytes = cpu_to_le32(sizeof(u32)), 214 .value = cpu_to_le32(DIV_ROUND_UP(rate, 1000)), /* to kHz */ 215 }; 216 217 return qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_ACTIVE_STATE, 218 r->rpm_res_type, r->rpm_clk_id, &req, 219 sizeof(req)); 220 } 221 222 static int clk_smd_rpm_set_rate_sleep(struct clk_smd_rpm *r, 223 unsigned long rate) 224 { 225 struct clk_smd_rpm_req req = { 226 .key = cpu_to_le32(r->rpm_key), 227 .nbytes = cpu_to_le32(sizeof(u32)), 228 .value = cpu_to_le32(DIV_ROUND_UP(rate, 1000)), /* to kHz */ 229 }; 230 231 return qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_SLEEP_STATE, 232 r->rpm_res_type, r->rpm_clk_id, &req, 233 sizeof(req)); 234 } 235 236 static void to_active_sleep(struct clk_smd_rpm *r, unsigned long rate, 237 unsigned long *active, unsigned long *sleep) 238 { 239 *active = rate; 240 241 /* 242 * Active-only clocks don't care what the rate is during sleep. So, 243 * they vote for zero. 244 */ 245 if (r->active_only) 246 *sleep = 0; 247 else 248 *sleep = *active; 249 } 250 251 static int clk_smd_rpm_prepare(struct clk_hw *hw) 252 { 253 struct clk_smd_rpm *r = to_clk_smd_rpm(hw); 254 struct clk_smd_rpm *peer = r->peer; 255 unsigned long this_rate = 0, this_sleep_rate = 0; 256 unsigned long peer_rate = 0, peer_sleep_rate = 0; 257 unsigned long active_rate, sleep_rate; 258 int ret = 0; 259 260 mutex_lock(&rpm_smd_clk_lock); 261 262 /* Don't send requests to the RPM if the rate has not been set. */ 263 if (!r->rate) 264 goto out; 265 266 to_active_sleep(r, r->rate, &this_rate, &this_sleep_rate); 267 268 /* Take peer clock's rate into account only if it's enabled. */ 269 if (peer->enabled) 270 to_active_sleep(peer, peer->rate, 271 &peer_rate, &peer_sleep_rate); 272 273 active_rate = max(this_rate, peer_rate); 274 275 if (r->branch) 276 active_rate = !!active_rate; 277 278 ret = clk_smd_rpm_set_rate_active(r, active_rate); 279 if (ret) 280 goto out; 281 282 sleep_rate = max(this_sleep_rate, peer_sleep_rate); 283 if (r->branch) 284 sleep_rate = !!sleep_rate; 285 286 ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate); 287 if (ret) 288 /* Undo the active set vote and restore it */ 289 ret = clk_smd_rpm_set_rate_active(r, peer_rate); 290 291 out: 292 if (!ret) 293 r->enabled = true; 294 295 mutex_unlock(&rpm_smd_clk_lock); 296 297 return ret; 298 } 299 300 static void clk_smd_rpm_unprepare(struct clk_hw *hw) 301 { 302 struct clk_smd_rpm *r = to_clk_smd_rpm(hw); 303 struct clk_smd_rpm *peer = r->peer; 304 unsigned long peer_rate = 0, peer_sleep_rate = 0; 305 unsigned long active_rate, sleep_rate; 306 int ret; 307 308 mutex_lock(&rpm_smd_clk_lock); 309 310 if (!r->rate) 311 goto out; 312 313 /* Take peer clock's rate into account only if it's enabled. */ 314 if (peer->enabled) 315 to_active_sleep(peer, peer->rate, &peer_rate, 316 &peer_sleep_rate); 317 318 active_rate = r->branch ? !!peer_rate : peer_rate; 319 ret = clk_smd_rpm_set_rate_active(r, active_rate); 320 if (ret) 321 goto out; 322 323 sleep_rate = r->branch ? !!peer_sleep_rate : peer_sleep_rate; 324 ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate); 325 if (ret) 326 goto out; 327 328 r->enabled = false; 329 330 out: 331 mutex_unlock(&rpm_smd_clk_lock); 332 } 333 334 static int clk_smd_rpm_set_rate(struct clk_hw *hw, unsigned long rate, 335 unsigned long parent_rate) 336 { 337 struct clk_smd_rpm *r = to_clk_smd_rpm(hw); 338 struct clk_smd_rpm *peer = r->peer; 339 unsigned long active_rate, sleep_rate; 340 unsigned long this_rate = 0, this_sleep_rate = 0; 341 unsigned long peer_rate = 0, peer_sleep_rate = 0; 342 int ret = 0; 343 344 mutex_lock(&rpm_smd_clk_lock); 345 346 if (!r->enabled) 347 goto out; 348 349 to_active_sleep(r, rate, &this_rate, &this_sleep_rate); 350 351 /* Take peer clock's rate into account only if it's enabled. */ 352 if (peer->enabled) 353 to_active_sleep(peer, peer->rate, 354 &peer_rate, &peer_sleep_rate); 355 356 active_rate = max(this_rate, peer_rate); 357 ret = clk_smd_rpm_set_rate_active(r, active_rate); 358 if (ret) 359 goto out; 360 361 sleep_rate = max(this_sleep_rate, peer_sleep_rate); 362 ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate); 363 if (ret) 364 goto out; 365 366 r->rate = rate; 367 368 out: 369 mutex_unlock(&rpm_smd_clk_lock); 370 371 return ret; 372 } 373 374 static long clk_smd_rpm_round_rate(struct clk_hw *hw, unsigned long rate, 375 unsigned long *parent_rate) 376 { 377 /* 378 * RPM handles rate rounding and we don't have a way to 379 * know what the rate will be, so just return whatever 380 * rate is requested. 381 */ 382 return rate; 383 } 384 385 static unsigned long clk_smd_rpm_recalc_rate(struct clk_hw *hw, 386 unsigned long parent_rate) 387 { 388 struct clk_smd_rpm *r = to_clk_smd_rpm(hw); 389 390 /* 391 * RPM handles rate rounding and we don't have a way to 392 * know what the rate will be, so just return whatever 393 * rate was set. 394 */ 395 return r->rate; 396 } 397 398 static int clk_smd_rpm_enable_scaling(struct qcom_smd_rpm *rpm) 399 { 400 int ret; 401 struct clk_smd_rpm_req req = { 402 .key = cpu_to_le32(QCOM_RPM_SMD_KEY_ENABLE), 403 .nbytes = cpu_to_le32(sizeof(u32)), 404 .value = cpu_to_le32(1), 405 }; 406 407 ret = qcom_rpm_smd_write(rpm, QCOM_SMD_RPM_SLEEP_STATE, 408 QCOM_SMD_RPM_MISC_CLK, 409 QCOM_RPM_SCALING_ENABLE_ID, &req, sizeof(req)); 410 if (ret) { 411 pr_err("RPM clock scaling (sleep set) not enabled!\n"); 412 return ret; 413 } 414 415 ret = qcom_rpm_smd_write(rpm, QCOM_SMD_RPM_ACTIVE_STATE, 416 QCOM_SMD_RPM_MISC_CLK, 417 QCOM_RPM_SCALING_ENABLE_ID, &req, sizeof(req)); 418 if (ret) { 419 pr_err("RPM clock scaling (active set) not enabled!\n"); 420 return ret; 421 } 422 423 pr_debug("%s: RPM clock scaling is enabled\n", __func__); 424 return 0; 425 } 426 427 static const struct clk_ops clk_smd_rpm_ops = { 428 .prepare = clk_smd_rpm_prepare, 429 .unprepare = clk_smd_rpm_unprepare, 430 .set_rate = clk_smd_rpm_set_rate, 431 .round_rate = clk_smd_rpm_round_rate, 432 .recalc_rate = clk_smd_rpm_recalc_rate, 433 }; 434 435 static const struct clk_ops clk_smd_rpm_branch_ops = { 436 .prepare = clk_smd_rpm_prepare, 437 .unprepare = clk_smd_rpm_unprepare, 438 .recalc_rate = clk_smd_rpm_recalc_rate, 439 }; 440 441 DEFINE_CLK_SMD_RPM_BRANCH_A(bi_tcxo, QCOM_SMD_RPM_MISC_CLK, 0, 19200000); 442 DEFINE_CLK_SMD_RPM_BRANCH(qdss, QCOM_SMD_RPM_MISC_CLK, 1, 19200000); 443 DEFINE_CLK_SMD_RPM_QDSS(qdss, QCOM_SMD_RPM_MISC_CLK, 1); 444 DEFINE_CLK_SMD_RPM_BRANCH_A(bimc_freq_log, QCOM_SMD_RPM_MISC_CLK, 4, 1); 445 446 DEFINE_CLK_SMD_RPM_BRANCH(mss_cfg_ahb, QCOM_SMD_RPM_MCFG_CLK, 0, 19200000); 447 448 DEFINE_CLK_SMD_RPM_BRANCH(aggre1_noc, QCOM_SMD_RPM_AGGR_CLK, 1, 1000); 449 DEFINE_CLK_SMD_RPM_BRANCH(aggre2_noc, QCOM_SMD_RPM_AGGR_CLK, 2, 1000); 450 DEFINE_CLK_SMD_RPM(aggre1_noc, QCOM_SMD_RPM_AGGR_CLK, 1); 451 DEFINE_CLK_SMD_RPM(aggre2_noc, QCOM_SMD_RPM_AGGR_CLK, 2); 452 453 DEFINE_CLK_SMD_RPM_BUS(pcnoc, 0); 454 DEFINE_CLK_SMD_RPM_BUS(snoc, 1); 455 DEFINE_CLK_SMD_RPM_BUS(sysmmnoc, 2); 456 DEFINE_CLK_SMD_RPM_BUS(cnoc, 2); 457 DEFINE_CLK_SMD_RPM_BUS(mmssnoc_ahb, 3); 458 DEFINE_CLK_SMD_RPM_BUS(snoc_periph, 0); 459 DEFINE_CLK_SMD_RPM_BUS(cnoc, 1); 460 DEFINE_CLK_SMD_RPM_BUS(snoc, 2); 461 DEFINE_CLK_SMD_RPM_BUS(snoc_lpass, 5); 462 463 DEFINE_CLK_SMD_RPM(bimc, QCOM_SMD_RPM_MEM_CLK, 0); 464 DEFINE_CLK_SMD_RPM(cpuss_gnoc, QCOM_SMD_RPM_MEM_CLK, 1); 465 DEFINE_CLK_SMD_RPM_CLK_SRC(gfx3d, QCOM_SMD_RPM_MEM_CLK, 1); 466 DEFINE_CLK_SMD_RPM(ocmemgx, QCOM_SMD_RPM_MEM_CLK, 2); 467 DEFINE_CLK_SMD_RPM(bimc_gpu, QCOM_SMD_RPM_MEM_CLK, 2); 468 469 DEFINE_CLK_SMD_RPM(ce1, QCOM_SMD_RPM_CE_CLK, 0); 470 DEFINE_CLK_SMD_RPM(ce2, QCOM_SMD_RPM_CE_CLK, 1); 471 DEFINE_CLK_SMD_RPM(ce3, QCOM_SMD_RPM_CE_CLK, 2); 472 473 DEFINE_CLK_SMD_RPM(ipa, QCOM_SMD_RPM_IPA_CLK, 0); 474 475 DEFINE_CLK_SMD_RPM(hwkm, QCOM_SMD_RPM_HWKM_CLK, 0); 476 477 DEFINE_CLK_SMD_RPM(mmssnoc_axi_rpm, QCOM_SMD_RPM_MMAXI_CLK, 0); 478 DEFINE_CLK_SMD_RPM(mmnrt, QCOM_SMD_RPM_MMAXI_CLK, 0); 479 DEFINE_CLK_SMD_RPM(mmrt, QCOM_SMD_RPM_MMAXI_CLK, 1); 480 481 DEFINE_CLK_SMD_RPM(pka, QCOM_SMD_RPM_PKA_CLK, 0); 482 483 DEFINE_CLK_SMD_RPM(qpic, QCOM_SMD_RPM_QPIC_CLK, 0); 484 485 DEFINE_CLK_SMD_RPM(qup, QCOM_SMD_RPM_QUP_CLK, 0); 486 487 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(bb_clk1, 1, 19200000); 488 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(bb_clk2, 2, 19200000); 489 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(ln_bb_clk1, 1, 19200000); 490 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(ln_bb_clk2, 2, 19200000); 491 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(ln_bb_clk3, 3, 19200000); 492 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(rf_clk1, 4, 19200000); 493 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(rf_clk2, 5, 19200000); 494 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(rf_clk3, 6, 19200000); 495 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(ln_bb_clk, 8, 19200000); 496 497 DEFINE_CLK_SMD_RPM_XO_BUFFER_PREFIX(38m4_, rf_clk3, 6, 38400000); 498 499 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(cxo_d0, 1, 19200000); 500 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(cxo_d1, 2, 19200000); 501 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(cxo_a0, 4, 19200000); 502 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(cxo_a1, 5, 19200000); 503 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(cxo_a2, 6, 19200000); 504 505 DEFINE_CLK_SMD_RPM_XO_BUFFER(diff_clk, 7, 19200000); 506 DEFINE_CLK_SMD_RPM_XO_BUFFER(div_clk1, 11, 19200000); 507 DEFINE_CLK_SMD_RPM_XO_BUFFER(div_clk2, 12, 19200000); 508 DEFINE_CLK_SMD_RPM_XO_BUFFER(div_clk3, 13, 19200000); 509 510 static struct clk_smd_rpm *msm8909_clks[] = { 511 [RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, 512 [RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, 513 [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, 514 [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, 515 [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, 516 [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, 517 [RPM_SMD_QPIC_CLK] = &clk_smd_rpm_qpic_clk, 518 [RPM_SMD_QPIC_CLK_A] = &clk_smd_rpm_qpic_a_clk, 519 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, 520 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, 521 [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, 522 [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, 523 [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2, 524 [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a, 525 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, 526 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, 527 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, 528 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, 529 [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, 530 [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin, 531 [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin, 532 [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin, 533 [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin, 534 [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin, 535 [RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin, 536 [RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin, 537 }; 538 539 static const struct rpm_smd_clk_desc rpm_clk_msm8909 = { 540 .clks = msm8909_clks, 541 .num_clks = ARRAY_SIZE(msm8909_clks), 542 }; 543 544 static struct clk_smd_rpm *msm8916_clks[] = { 545 [RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, 546 [RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, 547 [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, 548 [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, 549 [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, 550 [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, 551 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, 552 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, 553 [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, 554 [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, 555 [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2, 556 [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a, 557 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, 558 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, 559 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, 560 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, 561 [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, 562 [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin, 563 [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin, 564 [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin, 565 [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin, 566 [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin, 567 [RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin, 568 [RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin, 569 }; 570 571 static const struct rpm_smd_clk_desc rpm_clk_msm8916 = { 572 .clks = msm8916_clks, 573 .num_clks = ARRAY_SIZE(msm8916_clks), 574 }; 575 576 static struct clk_smd_rpm *msm8917_clks[] = { 577 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, 578 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, 579 [RPM_SMD_PNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, 580 [RPM_SMD_PNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, 581 [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, 582 [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, 583 [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, 584 [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, 585 [RPM_SMD_BIMC_GPU_CLK] = &clk_smd_rpm_bimc_gpu_clk, 586 [RPM_SMD_BIMC_GPU_A_CLK] = &clk_smd_rpm_bimc_gpu_a_clk, 587 [RPM_SMD_SYSMMNOC_CLK] = &clk_smd_rpm_bus_2_sysmmnoc_clk, 588 [RPM_SMD_SYSMMNOC_A_CLK] = &clk_smd_rpm_bus_2_sysmmnoc_a_clk, 589 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, 590 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, 591 [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, 592 [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, 593 [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2, 594 [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a, 595 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, 596 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, 597 [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2, 598 [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a, 599 [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, 600 [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin, 601 [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin, 602 [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin, 603 }; 604 605 static const struct rpm_smd_clk_desc rpm_clk_msm8917 = { 606 .clks = msm8917_clks, 607 .num_clks = ARRAY_SIZE(msm8917_clks), 608 }; 609 610 static struct clk_smd_rpm *msm8936_clks[] = { 611 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, 612 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, 613 [RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, 614 [RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, 615 [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, 616 [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, 617 [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, 618 [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, 619 [RPM_SMD_SYSMMNOC_CLK] = &clk_smd_rpm_bus_2_sysmmnoc_clk, 620 [RPM_SMD_SYSMMNOC_A_CLK] = &clk_smd_rpm_bus_2_sysmmnoc_a_clk, 621 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, 622 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, 623 [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, 624 [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, 625 [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2, 626 [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a, 627 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, 628 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, 629 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, 630 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, 631 [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, 632 [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin, 633 [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin, 634 [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin, 635 [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin, 636 [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin, 637 [RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin, 638 [RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin, 639 }; 640 641 static const struct rpm_smd_clk_desc rpm_clk_msm8936 = { 642 .clks = msm8936_clks, 643 .num_clks = ARRAY_SIZE(msm8936_clks), 644 }; 645 646 static struct clk_smd_rpm *msm8974_clks[] = { 647 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, 648 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, 649 [RPM_SMD_PNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, 650 [RPM_SMD_PNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, 651 [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, 652 [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, 653 [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_2_cnoc_clk, 654 [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_2_cnoc_a_clk, 655 [RPM_SMD_MMSSNOC_AHB_CLK] = &clk_smd_rpm_bus_3_mmssnoc_ahb_clk, 656 [RPM_SMD_MMSSNOC_AHB_A_CLK] = &clk_smd_rpm_bus_3_mmssnoc_ahb_a_clk, 657 [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, 658 [RPM_SMD_GFX3D_CLK_SRC] = &clk_smd_rpm_gfx3d_clk_src, 659 [RPM_SMD_GFX3D_A_CLK_SRC] = &clk_smd_rpm_gfx3d_a_clk_src, 660 [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, 661 [RPM_SMD_OCMEMGX_CLK] = &clk_smd_rpm_ocmemgx_clk, 662 [RPM_SMD_OCMEMGX_A_CLK] = &clk_smd_rpm_ocmemgx_a_clk, 663 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, 664 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, 665 [RPM_SMD_CXO_D0] = &clk_smd_rpm_cxo_d0, 666 [RPM_SMD_CXO_D0_A] = &clk_smd_rpm_cxo_d0_a, 667 [RPM_SMD_CXO_D1] = &clk_smd_rpm_cxo_d1, 668 [RPM_SMD_CXO_D1_A] = &clk_smd_rpm_cxo_d1_a, 669 [RPM_SMD_CXO_A0] = &clk_smd_rpm_cxo_a0, 670 [RPM_SMD_CXO_A0_A] = &clk_smd_rpm_cxo_a0_a, 671 [RPM_SMD_CXO_A1] = &clk_smd_rpm_cxo_a1, 672 [RPM_SMD_CXO_A1_A] = &clk_smd_rpm_cxo_a1_a, 673 [RPM_SMD_CXO_A2] = &clk_smd_rpm_cxo_a2, 674 [RPM_SMD_CXO_A2_A] = &clk_smd_rpm_cxo_a2_a, 675 [RPM_SMD_DIFF_CLK] = &clk_smd_rpm_diff_clk, 676 [RPM_SMD_DIFF_A_CLK] = &clk_smd_rpm_diff_clk_a, 677 [RPM_SMD_DIV_CLK1] = &clk_smd_rpm_div_clk1, 678 [RPM_SMD_DIV_A_CLK1] = &clk_smd_rpm_div_clk1_a, 679 [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2, 680 [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a, 681 [RPM_SMD_CXO_D0_PIN] = &clk_smd_rpm_cxo_d0_pin, 682 [RPM_SMD_CXO_D0_A_PIN] = &clk_smd_rpm_cxo_d0_a_pin, 683 [RPM_SMD_CXO_D1_PIN] = &clk_smd_rpm_cxo_d1_pin, 684 [RPM_SMD_CXO_D1_A_PIN] = &clk_smd_rpm_cxo_d1_a_pin, 685 [RPM_SMD_CXO_A0_PIN] = &clk_smd_rpm_cxo_a0_pin, 686 [RPM_SMD_CXO_A0_A_PIN] = &clk_smd_rpm_cxo_a0_a_pin, 687 [RPM_SMD_CXO_A1_PIN] = &clk_smd_rpm_cxo_a1_pin, 688 [RPM_SMD_CXO_A1_A_PIN] = &clk_smd_rpm_cxo_a1_a_pin, 689 [RPM_SMD_CXO_A2_PIN] = &clk_smd_rpm_cxo_a2_pin, 690 [RPM_SMD_CXO_A2_A_PIN] = &clk_smd_rpm_cxo_a2_a_pin, 691 }; 692 693 static const struct rpm_smd_clk_desc rpm_clk_msm8974 = { 694 .clks = msm8974_clks, 695 .num_clks = ARRAY_SIZE(msm8974_clks), 696 }; 697 698 static struct clk_smd_rpm *msm8976_clks[] = { 699 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, 700 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, 701 [RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, 702 [RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, 703 [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, 704 [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, 705 [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, 706 [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, 707 [RPM_SMD_SYSMMNOC_CLK] = &clk_smd_rpm_bus_2_sysmmnoc_clk, 708 [RPM_SMD_SYSMMNOC_A_CLK] = &clk_smd_rpm_bus_2_sysmmnoc_a_clk, 709 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, 710 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, 711 [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, 712 [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, 713 [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2, 714 [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a, 715 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, 716 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, 717 [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, 718 [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin, 719 [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin, 720 [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin, 721 [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2, 722 [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a, 723 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, 724 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, 725 }; 726 727 static const struct rpm_smd_clk_desc rpm_clk_msm8976 = { 728 .clks = msm8976_clks, 729 .num_clks = ARRAY_SIZE(msm8976_clks), 730 }; 731 732 static struct clk_smd_rpm *msm8992_clks[] = { 733 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, 734 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, 735 [RPM_SMD_PNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, 736 [RPM_SMD_PNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, 737 [RPM_SMD_OCMEMGX_CLK] = &clk_smd_rpm_ocmemgx_clk, 738 [RPM_SMD_OCMEMGX_A_CLK] = &clk_smd_rpm_ocmemgx_a_clk, 739 [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, 740 [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, 741 [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_2_cnoc_clk, 742 [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_2_cnoc_a_clk, 743 [RPM_SMD_GFX3D_CLK_SRC] = &clk_smd_rpm_gfx3d_clk_src, 744 [RPM_SMD_GFX3D_A_CLK_SRC] = &clk_smd_rpm_gfx3d_a_clk_src, 745 [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, 746 [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, 747 [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, 748 [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, 749 [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, 750 [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin, 751 [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2, 752 [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a, 753 [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin, 754 [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin, 755 [RPM_SMD_DIV_CLK1] = &clk_smd_rpm_div_clk1, 756 [RPM_SMD_DIV_A_CLK1] = &clk_smd_rpm_div_clk1_a, 757 [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2, 758 [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a, 759 [RPM_SMD_DIV_CLK3] = &clk_smd_rpm_div_clk3, 760 [RPM_SMD_DIV_A_CLK3] = &clk_smd_rpm_div_clk3_a, 761 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, 762 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, 763 [RPM_SMD_LN_BB_CLK] = &clk_smd_rpm_ln_bb_clk, 764 [RPM_SMD_LN_BB_A_CLK] = &clk_smd_rpm_ln_bb_clk_a, 765 [RPM_SMD_MMSSNOC_AHB_CLK] = &clk_smd_rpm_bus_3_mmssnoc_ahb_clk, 766 [RPM_SMD_MMSSNOC_AHB_A_CLK] = &clk_smd_rpm_bus_3_mmssnoc_ahb_a_clk, 767 [RPM_SMD_MSS_CFG_AHB_CLK] = &clk_smd_rpm_branch_mss_cfg_ahb_clk, 768 [RPM_SMD_MSS_CFG_AHB_A_CLK] = &clk_smd_rpm_branch_mss_cfg_ahb_a_clk, 769 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, 770 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, 771 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, 772 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, 773 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, 774 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, 775 [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin, 776 [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin, 777 [RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin, 778 [RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin, 779 [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, 780 [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, 781 [RPM_SMD_CE2_CLK] = &clk_smd_rpm_ce2_clk, 782 [RPM_SMD_CE2_A_CLK] = &clk_smd_rpm_ce2_a_clk, 783 }; 784 785 static const struct rpm_smd_clk_desc rpm_clk_msm8992 = { 786 .clks = msm8992_clks, 787 .num_clks = ARRAY_SIZE(msm8992_clks), 788 }; 789 790 static struct clk_smd_rpm *msm8994_clks[] = { 791 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, 792 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, 793 [RPM_SMD_PNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, 794 [RPM_SMD_PNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, 795 [RPM_SMD_OCMEMGX_CLK] = &clk_smd_rpm_ocmemgx_clk, 796 [RPM_SMD_OCMEMGX_A_CLK] = &clk_smd_rpm_ocmemgx_a_clk, 797 [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, 798 [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, 799 [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_2_cnoc_clk, 800 [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_2_cnoc_a_clk, 801 [RPM_SMD_GFX3D_CLK_SRC] = &clk_smd_rpm_gfx3d_clk_src, 802 [RPM_SMD_GFX3D_A_CLK_SRC] = &clk_smd_rpm_gfx3d_a_clk_src, 803 [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, 804 [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, 805 [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, 806 [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, 807 [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, 808 [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin, 809 [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2, 810 [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a, 811 [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin, 812 [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin, 813 [RPM_SMD_DIV_CLK1] = &clk_smd_rpm_div_clk1, 814 [RPM_SMD_DIV_A_CLK1] = &clk_smd_rpm_div_clk1_a, 815 [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2, 816 [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a, 817 [RPM_SMD_DIV_CLK3] = &clk_smd_rpm_div_clk3, 818 [RPM_SMD_DIV_A_CLK3] = &clk_smd_rpm_div_clk3_a, 819 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, 820 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, 821 [RPM_SMD_LN_BB_CLK] = &clk_smd_rpm_ln_bb_clk, 822 [RPM_SMD_LN_BB_A_CLK] = &clk_smd_rpm_ln_bb_clk_a, 823 [RPM_SMD_MMSSNOC_AHB_CLK] = &clk_smd_rpm_bus_3_mmssnoc_ahb_clk, 824 [RPM_SMD_MMSSNOC_AHB_A_CLK] = &clk_smd_rpm_bus_3_mmssnoc_ahb_a_clk, 825 [RPM_SMD_MSS_CFG_AHB_CLK] = &clk_smd_rpm_branch_mss_cfg_ahb_clk, 826 [RPM_SMD_MSS_CFG_AHB_A_CLK] = &clk_smd_rpm_branch_mss_cfg_ahb_a_clk, 827 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, 828 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, 829 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, 830 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, 831 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, 832 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, 833 [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin, 834 [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin, 835 [RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin, 836 [RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin, 837 [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, 838 [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, 839 [RPM_SMD_CE2_CLK] = &clk_smd_rpm_ce2_clk, 840 [RPM_SMD_CE2_A_CLK] = &clk_smd_rpm_ce2_a_clk, 841 [RPM_SMD_CE3_CLK] = &clk_smd_rpm_ce3_clk, 842 [RPM_SMD_CE3_A_CLK] = &clk_smd_rpm_ce3_a_clk, 843 }; 844 845 static const struct rpm_smd_clk_desc rpm_clk_msm8994 = { 846 .clks = msm8994_clks, 847 .num_clks = ARRAY_SIZE(msm8994_clks), 848 }; 849 850 static struct clk_smd_rpm *msm8996_clks[] = { 851 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, 852 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, 853 [RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, 854 [RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, 855 [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, 856 [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, 857 [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_2_cnoc_clk, 858 [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_2_cnoc_a_clk, 859 [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, 860 [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, 861 [RPM_SMD_MMAXI_CLK] = &clk_smd_rpm_mmssnoc_axi_rpm_clk, 862 [RPM_SMD_MMAXI_A_CLK] = &clk_smd_rpm_mmssnoc_axi_rpm_a_clk, 863 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, 864 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, 865 [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, 866 [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, 867 [RPM_SMD_AGGR1_NOC_CLK] = &clk_smd_rpm_branch_aggre1_noc_clk, 868 [RPM_SMD_AGGR1_NOC_A_CLK] = &clk_smd_rpm_branch_aggre1_noc_a_clk, 869 [RPM_SMD_AGGR2_NOC_CLK] = &clk_smd_rpm_branch_aggre2_noc_clk, 870 [RPM_SMD_AGGR2_NOC_A_CLK] = &clk_smd_rpm_branch_aggre2_noc_a_clk, 871 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, 872 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, 873 [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, 874 [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, 875 [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2, 876 [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a, 877 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, 878 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, 879 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, 880 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, 881 [RPM_SMD_LN_BB_CLK] = &clk_smd_rpm_ln_bb_clk, 882 [RPM_SMD_LN_BB_A_CLK] = &clk_smd_rpm_ln_bb_clk_a, 883 [RPM_SMD_DIV_CLK1] = &clk_smd_rpm_div_clk1, 884 [RPM_SMD_DIV_A_CLK1] = &clk_smd_rpm_div_clk1_a, 885 [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2, 886 [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a, 887 [RPM_SMD_DIV_CLK3] = &clk_smd_rpm_div_clk3, 888 [RPM_SMD_DIV_A_CLK3] = &clk_smd_rpm_div_clk3_a, 889 [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, 890 [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin, 891 [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin, 892 [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin, 893 [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin, 894 [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin, 895 [RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin, 896 [RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin, 897 }; 898 899 static const struct rpm_smd_clk_desc rpm_clk_msm8996 = { 900 .clks = msm8996_clks, 901 .num_clks = ARRAY_SIZE(msm8996_clks), 902 }; 903 904 static struct clk_smd_rpm *qcs404_clks[] = { 905 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, 906 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, 907 [RPM_SMD_PNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, 908 [RPM_SMD_PNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, 909 [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, 910 [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, 911 [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, 912 [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, 913 [RPM_SMD_BIMC_GPU_CLK] = &clk_smd_rpm_bimc_gpu_clk, 914 [RPM_SMD_BIMC_GPU_A_CLK] = &clk_smd_rpm_bimc_gpu_a_clk, 915 [RPM_SMD_QPIC_CLK] = &clk_smd_rpm_qpic_clk, 916 [RPM_SMD_QPIC_CLK_A] = &clk_smd_rpm_qpic_a_clk, 917 [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, 918 [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, 919 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, 920 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, 921 [RPM_SMD_LN_BB_CLK] = &clk_smd_rpm_ln_bb_clk, 922 [RPM_SMD_LN_BB_A_CLK] = &clk_smd_rpm_ln_bb_clk_a, 923 [RPM_SMD_LN_BB_CLK_PIN] = &clk_smd_rpm_ln_bb_clk_pin, 924 [RPM_SMD_LN_BB_A_CLK_PIN] = &clk_smd_rpm_ln_bb_clk_a_pin, 925 }; 926 927 static const struct rpm_smd_clk_desc rpm_clk_qcs404 = { 928 .clks = qcs404_clks, 929 .num_clks = ARRAY_SIZE(qcs404_clks), 930 }; 931 932 static struct clk_smd_rpm *msm8998_clks[] = { 933 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, 934 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, 935 [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, 936 [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, 937 [RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, 938 [RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, 939 [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, 940 [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, 941 [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_2_cnoc_clk, 942 [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_2_cnoc_a_clk, 943 [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, 944 [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, 945 [RPM_SMD_DIV_CLK1] = &clk_smd_rpm_div_clk1, 946 [RPM_SMD_DIV_A_CLK1] = &clk_smd_rpm_div_clk1_a, 947 [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2, 948 [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a, 949 [RPM_SMD_DIV_CLK3] = &clk_smd_rpm_div_clk3, 950 [RPM_SMD_DIV_A_CLK3] = &clk_smd_rpm_div_clk3_a, 951 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, 952 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, 953 [RPM_SMD_LN_BB_CLK1] = &clk_smd_rpm_ln_bb_clk1, 954 [RPM_SMD_LN_BB_CLK1_A] = &clk_smd_rpm_ln_bb_clk1_a, 955 [RPM_SMD_LN_BB_CLK2] = &clk_smd_rpm_ln_bb_clk2, 956 [RPM_SMD_LN_BB_CLK2_A] = &clk_smd_rpm_ln_bb_clk2_a, 957 [RPM_SMD_LN_BB_CLK3] = &clk_smd_rpm_ln_bb_clk3, 958 [RPM_SMD_LN_BB_CLK3_A] = &clk_smd_rpm_ln_bb_clk3_a, 959 [RPM_SMD_LN_BB_CLK1_PIN] = &clk_smd_rpm_ln_bb_clk1_pin, 960 [RPM_SMD_LN_BB_CLK1_A_PIN] = &clk_smd_rpm_ln_bb_clk1_a_pin, 961 [RPM_SMD_LN_BB_CLK2_PIN] = &clk_smd_rpm_ln_bb_clk2_pin, 962 [RPM_SMD_LN_BB_CLK2_A_PIN] = &clk_smd_rpm_ln_bb_clk2_a_pin, 963 [RPM_SMD_LN_BB_CLK3_PIN] = &clk_smd_rpm_ln_bb_clk3_pin, 964 [RPM_SMD_LN_BB_CLK3_A_PIN] = &clk_smd_rpm_ln_bb_clk3_a_pin, 965 [RPM_SMD_MMAXI_CLK] = &clk_smd_rpm_mmssnoc_axi_rpm_clk, 966 [RPM_SMD_MMAXI_A_CLK] = &clk_smd_rpm_mmssnoc_axi_rpm_a_clk, 967 [RPM_SMD_AGGR1_NOC_CLK] = &clk_smd_rpm_aggre1_noc_clk, 968 [RPM_SMD_AGGR1_NOC_A_CLK] = &clk_smd_rpm_aggre1_noc_a_clk, 969 [RPM_SMD_AGGR2_NOC_CLK] = &clk_smd_rpm_aggre2_noc_clk, 970 [RPM_SMD_AGGR2_NOC_A_CLK] = &clk_smd_rpm_aggre2_noc_a_clk, 971 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, 972 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, 973 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, 974 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, 975 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, 976 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, 977 [RPM_SMD_RF_CLK3] = &clk_smd_rpm_rf_clk3, 978 [RPM_SMD_RF_CLK3_A] = &clk_smd_rpm_rf_clk3_a, 979 [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin, 980 [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin, 981 [RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin, 982 [RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin, 983 [RPM_SMD_RF_CLK3_PIN] = &clk_smd_rpm_rf_clk3_pin, 984 [RPM_SMD_RF_CLK3_A_PIN] = &clk_smd_rpm_rf_clk3_a_pin, 985 }; 986 987 static const struct rpm_smd_clk_desc rpm_clk_msm8998 = { 988 .clks = msm8998_clks, 989 .num_clks = ARRAY_SIZE(msm8998_clks), 990 }; 991 992 static struct clk_smd_rpm *sdm660_clks[] = { 993 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, 994 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, 995 [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, 996 [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, 997 [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_2_cnoc_clk, 998 [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_2_cnoc_a_clk, 999 [RPM_SMD_CNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, 1000 [RPM_SMD_CNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, 1001 [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, 1002 [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, 1003 [RPM_SMD_MMSSNOC_AXI_CLK] = &clk_smd_rpm_mmssnoc_axi_rpm_clk, 1004 [RPM_SMD_MMSSNOC_AXI_CLK_A] = &clk_smd_rpm_mmssnoc_axi_rpm_a_clk, 1005 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, 1006 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, 1007 [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, 1008 [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, 1009 [RPM_SMD_AGGR2_NOC_CLK] = &clk_smd_rpm_aggre2_noc_clk, 1010 [RPM_SMD_AGGR2_NOC_A_CLK] = &clk_smd_rpm_aggre2_noc_a_clk, 1011 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, 1012 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, 1013 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, 1014 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, 1015 [RPM_SMD_DIV_CLK1] = &clk_smd_rpm_div_clk1, 1016 [RPM_SMD_DIV_A_CLK1] = &clk_smd_rpm_div_clk1_a, 1017 [RPM_SMD_LN_BB_CLK] = &clk_smd_rpm_ln_bb_clk1, 1018 [RPM_SMD_LN_BB_A_CLK] = &clk_smd_rpm_ln_bb_clk1_a, 1019 [RPM_SMD_LN_BB_CLK2] = &clk_smd_rpm_ln_bb_clk2, 1020 [RPM_SMD_LN_BB_CLK2_A] = &clk_smd_rpm_ln_bb_clk2_a, 1021 [RPM_SMD_LN_BB_CLK3] = &clk_smd_rpm_ln_bb_clk3, 1022 [RPM_SMD_LN_BB_CLK3_A] = &clk_smd_rpm_ln_bb_clk3_a, 1023 [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin, 1024 [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin, 1025 [RPM_SMD_LN_BB_CLK1_PIN] = &clk_smd_rpm_ln_bb_clk1_pin, 1026 [RPM_SMD_LN_BB_CLK1_A_PIN] = &clk_smd_rpm_ln_bb_clk1_a_pin, 1027 [RPM_SMD_LN_BB_CLK2_PIN] = &clk_smd_rpm_ln_bb_clk2_pin, 1028 [RPM_SMD_LN_BB_CLK2_A_PIN] = &clk_smd_rpm_ln_bb_clk2_a_pin, 1029 [RPM_SMD_LN_BB_CLK3_PIN] = &clk_smd_rpm_ln_bb_clk3_pin, 1030 [RPM_SMD_LN_BB_CLK3_A_PIN] = &clk_smd_rpm_ln_bb_clk3_a_pin, 1031 }; 1032 1033 static const struct rpm_smd_clk_desc rpm_clk_sdm660 = { 1034 .clks = sdm660_clks, 1035 .num_clks = ARRAY_SIZE(sdm660_clks), 1036 }; 1037 1038 static struct clk_smd_rpm *mdm9607_clks[] = { 1039 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, 1040 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, 1041 [RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, 1042 [RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, 1043 [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, 1044 [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, 1045 [RPM_SMD_QPIC_CLK] = &clk_smd_rpm_qpic_clk, 1046 [RPM_SMD_QPIC_CLK_A] = &clk_smd_rpm_qpic_a_clk, 1047 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, 1048 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, 1049 [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, 1050 [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, 1051 [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, 1052 [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin, 1053 }; 1054 1055 static const struct rpm_smd_clk_desc rpm_clk_mdm9607 = { 1056 .clks = mdm9607_clks, 1057 .num_clks = ARRAY_SIZE(mdm9607_clks), 1058 }; 1059 1060 static struct clk_smd_rpm *msm8953_clks[] = { 1061 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, 1062 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, 1063 [RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, 1064 [RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, 1065 [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, 1066 [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, 1067 [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, 1068 [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, 1069 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, 1070 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, 1071 [RPM_SMD_SYSMMNOC_CLK] = &clk_smd_rpm_bus_2_sysmmnoc_clk, 1072 [RPM_SMD_SYSMMNOC_A_CLK] = &clk_smd_rpm_bus_2_sysmmnoc_a_clk, 1073 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, 1074 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, 1075 [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, 1076 [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, 1077 [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2, 1078 [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a, 1079 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, 1080 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, 1081 [RPM_SMD_RF_CLK3] = &clk_smd_rpm_ln_bb_clk, 1082 [RPM_SMD_RF_CLK3_A] = &clk_smd_rpm_ln_bb_clk_a, 1083 [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2, 1084 [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a, 1085 [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, 1086 [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin, 1087 [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin, 1088 [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin, 1089 }; 1090 1091 static const struct rpm_smd_clk_desc rpm_clk_msm8953 = { 1092 .clks = msm8953_clks, 1093 .num_clks = ARRAY_SIZE(msm8953_clks), 1094 }; 1095 1096 static struct clk_smd_rpm *sm6125_clks[] = { 1097 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, 1098 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, 1099 [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_2_snoc_clk, 1100 [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_2_snoc_a_clk, 1101 [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, 1102 [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, 1103 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_branch_qdss_clk, 1104 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_branch_qdss_a_clk, 1105 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, 1106 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, 1107 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, 1108 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, 1109 [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_1_cnoc_clk, 1110 [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_1_cnoc_a_clk, 1111 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, 1112 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, 1113 [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, 1114 [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, 1115 [RPM_SMD_LN_BB_CLK1] = &clk_smd_rpm_ln_bb_clk1, 1116 [RPM_SMD_LN_BB_CLK1_A] = &clk_smd_rpm_ln_bb_clk1_a, 1117 [RPM_SMD_LN_BB_CLK2] = &clk_smd_rpm_ln_bb_clk2, 1118 [RPM_SMD_LN_BB_CLK2_A] = &clk_smd_rpm_ln_bb_clk2_a, 1119 [RPM_SMD_LN_BB_CLK3] = &clk_smd_rpm_ln_bb_clk3, 1120 [RPM_SMD_LN_BB_CLK3_A] = &clk_smd_rpm_ln_bb_clk3_a, 1121 [RPM_SMD_QUP_CLK] = &clk_smd_rpm_qup_clk, 1122 [RPM_SMD_QUP_A_CLK] = &clk_smd_rpm_qup_a_clk, 1123 [RPM_SMD_MMRT_CLK] = &clk_smd_rpm_mmrt_clk, 1124 [RPM_SMD_MMRT_A_CLK] = &clk_smd_rpm_mmrt_a_clk, 1125 [RPM_SMD_MMNRT_CLK] = &clk_smd_rpm_mmnrt_clk, 1126 [RPM_SMD_MMNRT_A_CLK] = &clk_smd_rpm_mmnrt_a_clk, 1127 [RPM_SMD_SNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_snoc_periph_clk, 1128 [RPM_SMD_SNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_snoc_periph_a_clk, 1129 [RPM_SMD_SNOC_LPASS_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_clk, 1130 [RPM_SMD_SNOC_LPASS_A_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_a_clk, 1131 }; 1132 1133 static const struct rpm_smd_clk_desc rpm_clk_sm6125 = { 1134 .clks = sm6125_clks, 1135 .num_clks = ARRAY_SIZE(sm6125_clks), 1136 }; 1137 1138 /* SM6115 */ 1139 static struct clk_smd_rpm *sm6115_clks[] = { 1140 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, 1141 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, 1142 [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_2_snoc_clk, 1143 [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_2_snoc_a_clk, 1144 [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, 1145 [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, 1146 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_branch_qdss_clk, 1147 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_branch_qdss_a_clk, 1148 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, 1149 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, 1150 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, 1151 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, 1152 [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_1_cnoc_clk, 1153 [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_1_cnoc_a_clk, 1154 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, 1155 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, 1156 [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, 1157 [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, 1158 [RPM_SMD_QUP_CLK] = &clk_smd_rpm_qup_clk, 1159 [RPM_SMD_QUP_A_CLK] = &clk_smd_rpm_qup_a_clk, 1160 [RPM_SMD_MMRT_CLK] = &clk_smd_rpm_mmrt_clk, 1161 [RPM_SMD_MMRT_A_CLK] = &clk_smd_rpm_mmrt_a_clk, 1162 [RPM_SMD_MMNRT_CLK] = &clk_smd_rpm_mmnrt_clk, 1163 [RPM_SMD_MMNRT_A_CLK] = &clk_smd_rpm_mmnrt_a_clk, 1164 [RPM_SMD_SNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_snoc_periph_clk, 1165 [RPM_SMD_SNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_snoc_periph_a_clk, 1166 [RPM_SMD_SNOC_LPASS_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_clk, 1167 [RPM_SMD_SNOC_LPASS_A_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_a_clk, 1168 [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin, 1169 [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin, 1170 [RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin, 1171 [RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin, 1172 }; 1173 1174 static const struct rpm_smd_clk_desc rpm_clk_sm6115 = { 1175 .clks = sm6115_clks, 1176 .num_clks = ARRAY_SIZE(sm6115_clks), 1177 }; 1178 1179 static struct clk_smd_rpm *sm6375_clks[] = { 1180 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, 1181 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, 1182 [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_2_snoc_clk, 1183 [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_2_snoc_a_clk, 1184 [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, 1185 [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, 1186 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_branch_qdss_clk, 1187 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_branch_qdss_a_clk, 1188 [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_1_cnoc_clk, 1189 [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_1_cnoc_a_clk, 1190 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, 1191 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, 1192 [RPM_SMD_QUP_CLK] = &clk_smd_rpm_qup_clk, 1193 [RPM_SMD_QUP_A_CLK] = &clk_smd_rpm_qup_a_clk, 1194 [RPM_SMD_MMRT_CLK] = &clk_smd_rpm_mmrt_clk, 1195 [RPM_SMD_MMRT_A_CLK] = &clk_smd_rpm_mmrt_a_clk, 1196 [RPM_SMD_MMNRT_CLK] = &clk_smd_rpm_mmnrt_clk, 1197 [RPM_SMD_MMNRT_A_CLK] = &clk_smd_rpm_mmnrt_a_clk, 1198 [RPM_SMD_SNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_snoc_periph_clk, 1199 [RPM_SMD_SNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_snoc_periph_a_clk, 1200 [RPM_SMD_SNOC_LPASS_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_clk, 1201 [RPM_SMD_SNOC_LPASS_A_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_a_clk, 1202 [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, 1203 [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, 1204 [RPM_SMD_HWKM_CLK] = &clk_smd_rpm_hwkm_clk, 1205 [RPM_SMD_HWKM_A_CLK] = &clk_smd_rpm_hwkm_a_clk, 1206 [RPM_SMD_PKA_CLK] = &clk_smd_rpm_pka_clk, 1207 [RPM_SMD_PKA_A_CLK] = &clk_smd_rpm_pka_a_clk, 1208 [RPM_SMD_BIMC_FREQ_LOG] = &clk_smd_rpm_branch_bimc_freq_log, 1209 }; 1210 1211 static const struct rpm_smd_clk_desc rpm_clk_sm6375 = { 1212 .clks = sm6375_clks, 1213 .num_clks = ARRAY_SIZE(sm6375_clks), 1214 }; 1215 1216 static struct clk_smd_rpm *qcm2290_clks[] = { 1217 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, 1218 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, 1219 [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_2_snoc_clk, 1220 [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_2_snoc_a_clk, 1221 [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, 1222 [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, 1223 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_branch_qdss_clk, 1224 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_branch_qdss_a_clk, 1225 [RPM_SMD_LN_BB_CLK2] = &clk_smd_rpm_ln_bb_clk2, 1226 [RPM_SMD_LN_BB_CLK2_A] = &clk_smd_rpm_ln_bb_clk2_a, 1227 [RPM_SMD_RF_CLK3] = &clk_smd_rpm_38m4_rf_clk3, 1228 [RPM_SMD_RF_CLK3_A] = &clk_smd_rpm_38m4_rf_clk3_a, 1229 [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_1_cnoc_clk, 1230 [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_1_cnoc_a_clk, 1231 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, 1232 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, 1233 [RPM_SMD_QUP_CLK] = &clk_smd_rpm_qup_clk, 1234 [RPM_SMD_QUP_A_CLK] = &clk_smd_rpm_qup_a_clk, 1235 [RPM_SMD_MMRT_CLK] = &clk_smd_rpm_mmrt_clk, 1236 [RPM_SMD_MMRT_A_CLK] = &clk_smd_rpm_mmrt_a_clk, 1237 [RPM_SMD_MMNRT_CLK] = &clk_smd_rpm_mmnrt_clk, 1238 [RPM_SMD_MMNRT_A_CLK] = &clk_smd_rpm_mmnrt_a_clk, 1239 [RPM_SMD_SNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_snoc_periph_clk, 1240 [RPM_SMD_SNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_snoc_periph_a_clk, 1241 [RPM_SMD_SNOC_LPASS_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_clk, 1242 [RPM_SMD_SNOC_LPASS_A_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_a_clk, 1243 [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, 1244 [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, 1245 [RPM_SMD_QPIC_CLK] = &clk_smd_rpm_qpic_clk, 1246 [RPM_SMD_QPIC_CLK_A] = &clk_smd_rpm_qpic_a_clk, 1247 [RPM_SMD_HWKM_CLK] = &clk_smd_rpm_hwkm_clk, 1248 [RPM_SMD_HWKM_A_CLK] = &clk_smd_rpm_hwkm_a_clk, 1249 [RPM_SMD_PKA_CLK] = &clk_smd_rpm_pka_clk, 1250 [RPM_SMD_PKA_A_CLK] = &clk_smd_rpm_pka_a_clk, 1251 [RPM_SMD_BIMC_GPU_CLK] = &clk_smd_rpm_bimc_gpu_clk, 1252 [RPM_SMD_BIMC_GPU_A_CLK] = &clk_smd_rpm_bimc_gpu_a_clk, 1253 [RPM_SMD_CPUSS_GNOC_CLK] = &clk_smd_rpm_cpuss_gnoc_clk, 1254 [RPM_SMD_CPUSS_GNOC_A_CLK] = &clk_smd_rpm_cpuss_gnoc_a_clk, 1255 }; 1256 1257 static const struct rpm_smd_clk_desc rpm_clk_qcm2290 = { 1258 .clks = qcm2290_clks, 1259 .num_clks = ARRAY_SIZE(qcm2290_clks), 1260 }; 1261 1262 static const struct of_device_id rpm_smd_clk_match_table[] = { 1263 { .compatible = "qcom,rpmcc-mdm9607", .data = &rpm_clk_mdm9607 }, 1264 { .compatible = "qcom,rpmcc-msm8226", .data = &rpm_clk_msm8974 }, 1265 { .compatible = "qcom,rpmcc-msm8909", .data = &rpm_clk_msm8909 }, 1266 { .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916 }, 1267 { .compatible = "qcom,rpmcc-msm8917", .data = &rpm_clk_msm8917 }, 1268 { .compatible = "qcom,rpmcc-msm8936", .data = &rpm_clk_msm8936 }, 1269 { .compatible = "qcom,rpmcc-msm8953", .data = &rpm_clk_msm8953 }, 1270 { .compatible = "qcom,rpmcc-msm8974", .data = &rpm_clk_msm8974 }, 1271 { .compatible = "qcom,rpmcc-msm8976", .data = &rpm_clk_msm8976 }, 1272 { .compatible = "qcom,rpmcc-msm8992", .data = &rpm_clk_msm8992 }, 1273 { .compatible = "qcom,rpmcc-msm8994", .data = &rpm_clk_msm8994 }, 1274 { .compatible = "qcom,rpmcc-msm8996", .data = &rpm_clk_msm8996 }, 1275 { .compatible = "qcom,rpmcc-msm8998", .data = &rpm_clk_msm8998 }, 1276 { .compatible = "qcom,rpmcc-qcm2290", .data = &rpm_clk_qcm2290 }, 1277 { .compatible = "qcom,rpmcc-qcs404", .data = &rpm_clk_qcs404 }, 1278 { .compatible = "qcom,rpmcc-sdm660", .data = &rpm_clk_sdm660 }, 1279 { .compatible = "qcom,rpmcc-sm6115", .data = &rpm_clk_sm6115 }, 1280 { .compatible = "qcom,rpmcc-sm6125", .data = &rpm_clk_sm6125 }, 1281 { .compatible = "qcom,rpmcc-sm6375", .data = &rpm_clk_sm6375 }, 1282 { } 1283 }; 1284 MODULE_DEVICE_TABLE(of, rpm_smd_clk_match_table); 1285 1286 static struct clk_hw *qcom_smdrpm_clk_hw_get(struct of_phandle_args *clkspec, 1287 void *data) 1288 { 1289 const struct rpm_smd_clk_desc *desc = data; 1290 unsigned int idx = clkspec->args[0]; 1291 1292 if (idx >= desc->num_clks) { 1293 pr_err("%s: invalid index %u\n", __func__, idx); 1294 return ERR_PTR(-EINVAL); 1295 } 1296 1297 return desc->clks[idx] ? &desc->clks[idx]->hw : ERR_PTR(-ENOENT); 1298 } 1299 1300 static int rpm_smd_clk_probe(struct platform_device *pdev) 1301 { 1302 int ret; 1303 size_t num_clks, i; 1304 struct qcom_smd_rpm *rpm; 1305 struct clk_smd_rpm **rpm_smd_clks; 1306 const struct rpm_smd_clk_desc *desc; 1307 1308 rpm = dev_get_drvdata(pdev->dev.parent); 1309 if (!rpm) { 1310 dev_err(&pdev->dev, "Unable to retrieve handle to RPM\n"); 1311 return -ENODEV; 1312 } 1313 1314 desc = of_device_get_match_data(&pdev->dev); 1315 if (!desc) 1316 return -EINVAL; 1317 1318 rpm_smd_clks = desc->clks; 1319 num_clks = desc->num_clks; 1320 1321 for (i = 0; i < num_clks; i++) { 1322 if (!rpm_smd_clks[i]) 1323 continue; 1324 1325 rpm_smd_clks[i]->rpm = rpm; 1326 1327 ret = clk_smd_rpm_handoff(rpm_smd_clks[i]); 1328 if (ret) 1329 goto err; 1330 } 1331 1332 ret = clk_smd_rpm_enable_scaling(rpm); 1333 if (ret) 1334 goto err; 1335 1336 for (i = 0; i < num_clks; i++) { 1337 if (!rpm_smd_clks[i]) 1338 continue; 1339 1340 ret = devm_clk_hw_register(&pdev->dev, &rpm_smd_clks[i]->hw); 1341 if (ret) 1342 goto err; 1343 } 1344 1345 ret = devm_of_clk_add_hw_provider(&pdev->dev, qcom_smdrpm_clk_hw_get, 1346 (void *)desc); 1347 if (ret) 1348 goto err; 1349 1350 return 0; 1351 err: 1352 dev_err(&pdev->dev, "Error registering SMD clock driver (%d)\n", ret); 1353 return ret; 1354 } 1355 1356 static struct platform_driver rpm_smd_clk_driver = { 1357 .driver = { 1358 .name = "qcom-clk-smd-rpm", 1359 .of_match_table = rpm_smd_clk_match_table, 1360 }, 1361 .probe = rpm_smd_clk_probe, 1362 }; 1363 1364 static int __init rpm_smd_clk_init(void) 1365 { 1366 return platform_driver_register(&rpm_smd_clk_driver); 1367 } 1368 core_initcall(rpm_smd_clk_init); 1369 1370 static void __exit rpm_smd_clk_exit(void) 1371 { 1372 platform_driver_unregister(&rpm_smd_clk_driver); 1373 } 1374 module_exit(rpm_smd_clk_exit); 1375 1376 MODULE_DESCRIPTION("Qualcomm RPM over SMD Clock Controller Driver"); 1377 MODULE_LICENSE("GPL v2"); 1378 MODULE_ALIAS("platform:qcom-clk-smd-rpm"); 1379