1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2016, Linaro Limited 4 * Copyright (c) 2014, The Linux Foundation. All rights reserved. 5 */ 6 7 #include <linux/clk-provider.h> 8 #include <linux/err.h> 9 #include <linux/export.h> 10 #include <linux/init.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/mutex.h> 14 #include <linux/of.h> 15 #include <linux/of_device.h> 16 #include <linux/platform_device.h> 17 #include <linux/soc/qcom/smd-rpm.h> 18 19 #include <dt-bindings/clock/qcom,rpmcc.h> 20 21 #define __DEFINE_CLK_SMD_RPM_PREFIX(_prefix, _name, _active, \ 22 type, r_id, key) \ 23 static struct clk_smd_rpm clk_smd_rpm_##_prefix##_active; \ 24 static struct clk_smd_rpm clk_smd_rpm_##_prefix##_name = { \ 25 .rpm_res_type = (type), \ 26 .rpm_clk_id = (r_id), \ 27 .rpm_key = (key), \ 28 .peer = &clk_smd_rpm_##_prefix##_active, \ 29 .rate = INT_MAX, \ 30 .hw.init = &(struct clk_init_data){ \ 31 .ops = &clk_smd_rpm_ops, \ 32 .name = #_name, \ 33 .parent_data = &(const struct clk_parent_data){ \ 34 .fw_name = "xo", \ 35 .name = "xo_board", \ 36 }, \ 37 .num_parents = 1, \ 38 }, \ 39 }; \ 40 static struct clk_smd_rpm clk_smd_rpm_##_prefix##_active = { \ 41 .rpm_res_type = (type), \ 42 .rpm_clk_id = (r_id), \ 43 .active_only = true, \ 44 .rpm_key = (key), \ 45 .peer = &clk_smd_rpm_##_prefix##_name, \ 46 .rate = INT_MAX, \ 47 .hw.init = &(struct clk_init_data){ \ 48 .ops = &clk_smd_rpm_ops, \ 49 .name = #_active, \ 50 .parent_data = &(const struct clk_parent_data){ \ 51 .fw_name = "xo", \ 52 .name = "xo_board", \ 53 }, \ 54 .num_parents = 1, \ 55 }, \ 56 } 57 58 #define __DEFINE_CLK_SMD_RPM(_name, _active, type, r_id, key) \ 59 __DEFINE_CLK_SMD_RPM_PREFIX(/* empty */, _name, _active, \ 60 type, r_id, key) 61 62 #define __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(_prefix, _name, _active,\ 63 type, r_id, r, key, ao_flags) \ 64 static struct clk_smd_rpm clk_smd_rpm_##_prefix##_active; \ 65 static struct clk_smd_rpm clk_smd_rpm_##_prefix##_name = { \ 66 .rpm_res_type = (type), \ 67 .rpm_clk_id = (r_id), \ 68 .rpm_key = (key), \ 69 .branch = true, \ 70 .peer = &clk_smd_rpm_##_prefix##_active, \ 71 .rate = (r), \ 72 .hw.init = &(struct clk_init_data){ \ 73 .ops = &clk_smd_rpm_branch_ops, \ 74 .name = #_name, \ 75 .parent_data = &(const struct clk_parent_data){ \ 76 .fw_name = "xo", \ 77 .name = "xo_board", \ 78 }, \ 79 .num_parents = 1, \ 80 }, \ 81 }; \ 82 static struct clk_smd_rpm clk_smd_rpm_##_prefix##_active = { \ 83 .rpm_res_type = (type), \ 84 .rpm_clk_id = (r_id), \ 85 .active_only = true, \ 86 .rpm_key = (key), \ 87 .branch = true, \ 88 .peer = &clk_smd_rpm_##_prefix##_name, \ 89 .rate = (r), \ 90 .hw.init = &(struct clk_init_data){ \ 91 .ops = &clk_smd_rpm_branch_ops, \ 92 .name = #_active, \ 93 .parent_data = &(const struct clk_parent_data){ \ 94 .fw_name = "xo", \ 95 .name = "xo_board", \ 96 }, \ 97 .num_parents = 1, \ 98 .flags = (ao_flags), \ 99 }, \ 100 } 101 102 #define __DEFINE_CLK_SMD_RPM_BRANCH(_name, _active, type, r_id, r, key) \ 103 __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(/* empty */, \ 104 _name, _active, type, r_id, r, key, 0) 105 106 #define DEFINE_CLK_SMD_RPM(_name, type, r_id) \ 107 __DEFINE_CLK_SMD_RPM(_name##_clk, _name##_a_clk, \ 108 type, r_id, QCOM_RPM_SMD_KEY_RATE) 109 110 #define DEFINE_CLK_SMD_RPM_BUS(_name, r_id) \ 111 __DEFINE_CLK_SMD_RPM_PREFIX(bus_##r_id##_, \ 112 _name##_clk, _name##_a_clk, QCOM_SMD_RPM_BUS_CLK, r_id, \ 113 QCOM_RPM_SMD_KEY_RATE) 114 115 #define DEFINE_CLK_SMD_RPM_CLK_SRC(_name, type, r_id) \ 116 __DEFINE_CLK_SMD_RPM( \ 117 _name##_clk_src, _name##_a_clk_src, \ 118 type, r_id, QCOM_RPM_SMD_KEY_RATE) 119 120 #define DEFINE_CLK_SMD_RPM_BRANCH(_name, type, r_id, r) \ 121 __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(branch_, \ 122 _name##_clk, _name##_a_clk, \ 123 type, r_id, r, QCOM_RPM_SMD_KEY_ENABLE, 0) 124 125 #define DEFINE_CLK_SMD_RPM_BRANCH_A(_name, type, r_id, r, ao_flags) \ 126 __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(branch_, \ 127 _name, _name##_a, type, \ 128 r_id, r, QCOM_RPM_SMD_KEY_ENABLE, ao_flags) 129 130 #define DEFINE_CLK_SMD_RPM_QDSS(_name, type, r_id) \ 131 __DEFINE_CLK_SMD_RPM(_name##_clk, _name##_a_clk, \ 132 type, r_id, QCOM_RPM_SMD_KEY_STATE) 133 134 #define DEFINE_CLK_SMD_RPM_XO_BUFFER(_name, r_id, r) \ 135 __DEFINE_CLK_SMD_RPM_BRANCH(_name, _name##_a, \ 136 QCOM_SMD_RPM_CLK_BUF_A, r_id, r, \ 137 QCOM_RPM_KEY_SOFTWARE_ENABLE) 138 139 #define DEFINE_CLK_SMD_RPM_XO_BUFFER_PREFIX(_prefix, _name, r_id, r) \ 140 __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(_prefix, \ 141 _name, _name##_a, \ 142 QCOM_SMD_RPM_CLK_BUF_A, r_id, r, \ 143 QCOM_RPM_KEY_SOFTWARE_ENABLE, 0) 144 145 #define DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(_name, r_id, r) \ 146 DEFINE_CLK_SMD_RPM_XO_BUFFER(_name, r_id, r); \ 147 __DEFINE_CLK_SMD_RPM_BRANCH(_name##_pin, _name##_a##_pin, \ 148 QCOM_SMD_RPM_CLK_BUF_A, r_id, r, \ 149 QCOM_RPM_KEY_PIN_CTRL_CLK_BUFFER_ENABLE_KEY) 150 151 #define to_clk_smd_rpm(_hw) container_of(_hw, struct clk_smd_rpm, hw) 152 153 static struct qcom_smd_rpm *rpmcc_smd_rpm; 154 155 struct clk_smd_rpm { 156 const int rpm_res_type; 157 const int rpm_key; 158 const int rpm_clk_id; 159 const bool active_only; 160 bool enabled; 161 bool branch; 162 struct clk_smd_rpm *peer; 163 struct clk_hw hw; 164 unsigned long rate; 165 }; 166 167 struct rpm_smd_clk_desc { 168 struct clk_smd_rpm **clks; 169 size_t num_clks; 170 bool scaling_before_handover; 171 }; 172 173 static DEFINE_MUTEX(rpm_smd_clk_lock); 174 175 static int clk_smd_rpm_handoff(struct clk_smd_rpm *r) 176 { 177 int ret; 178 struct clk_smd_rpm_req req = { 179 .key = cpu_to_le32(r->rpm_key), 180 .nbytes = cpu_to_le32(sizeof(u32)), 181 .value = cpu_to_le32(r->branch ? 1 : INT_MAX), 182 }; 183 184 ret = qcom_rpm_smd_write(rpmcc_smd_rpm, QCOM_SMD_RPM_ACTIVE_STATE, 185 r->rpm_res_type, r->rpm_clk_id, &req, 186 sizeof(req)); 187 if (ret) 188 return ret; 189 ret = qcom_rpm_smd_write(rpmcc_smd_rpm, QCOM_SMD_RPM_SLEEP_STATE, 190 r->rpm_res_type, r->rpm_clk_id, &req, 191 sizeof(req)); 192 if (ret) 193 return ret; 194 195 return 0; 196 } 197 198 static int clk_smd_rpm_set_rate_active(struct clk_smd_rpm *r, 199 unsigned long rate) 200 { 201 struct clk_smd_rpm_req req = { 202 .key = cpu_to_le32(r->rpm_key), 203 .nbytes = cpu_to_le32(sizeof(u32)), 204 .value = cpu_to_le32(DIV_ROUND_UP(rate, 1000)), /* to kHz */ 205 }; 206 207 return qcom_rpm_smd_write(rpmcc_smd_rpm, QCOM_SMD_RPM_ACTIVE_STATE, 208 r->rpm_res_type, r->rpm_clk_id, &req, 209 sizeof(req)); 210 } 211 212 static int clk_smd_rpm_set_rate_sleep(struct clk_smd_rpm *r, 213 unsigned long rate) 214 { 215 struct clk_smd_rpm_req req = { 216 .key = cpu_to_le32(r->rpm_key), 217 .nbytes = cpu_to_le32(sizeof(u32)), 218 .value = cpu_to_le32(DIV_ROUND_UP(rate, 1000)), /* to kHz */ 219 }; 220 221 return qcom_rpm_smd_write(rpmcc_smd_rpm, QCOM_SMD_RPM_SLEEP_STATE, 222 r->rpm_res_type, r->rpm_clk_id, &req, 223 sizeof(req)); 224 } 225 226 static void to_active_sleep(struct clk_smd_rpm *r, unsigned long rate, 227 unsigned long *active, unsigned long *sleep) 228 { 229 *active = rate; 230 231 /* 232 * Active-only clocks don't care what the rate is during sleep. So, 233 * they vote for zero. 234 */ 235 if (r->active_only) 236 *sleep = 0; 237 else 238 *sleep = *active; 239 } 240 241 static int clk_smd_rpm_prepare(struct clk_hw *hw) 242 { 243 struct clk_smd_rpm *r = to_clk_smd_rpm(hw); 244 struct clk_smd_rpm *peer = r->peer; 245 unsigned long this_rate = 0, this_sleep_rate = 0; 246 unsigned long peer_rate = 0, peer_sleep_rate = 0; 247 unsigned long active_rate, sleep_rate; 248 int ret = 0; 249 250 mutex_lock(&rpm_smd_clk_lock); 251 252 /* Don't send requests to the RPM if the rate has not been set. */ 253 if (!r->rate) 254 goto out; 255 256 to_active_sleep(r, r->rate, &this_rate, &this_sleep_rate); 257 258 /* Take peer clock's rate into account only if it's enabled. */ 259 if (peer->enabled) 260 to_active_sleep(peer, peer->rate, 261 &peer_rate, &peer_sleep_rate); 262 263 active_rate = max(this_rate, peer_rate); 264 265 if (r->branch) 266 active_rate = !!active_rate; 267 268 ret = clk_smd_rpm_set_rate_active(r, active_rate); 269 if (ret) 270 goto out; 271 272 sleep_rate = max(this_sleep_rate, peer_sleep_rate); 273 if (r->branch) 274 sleep_rate = !!sleep_rate; 275 276 ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate); 277 if (ret) 278 /* Undo the active set vote and restore it */ 279 ret = clk_smd_rpm_set_rate_active(r, peer_rate); 280 281 out: 282 if (!ret) 283 r->enabled = true; 284 285 mutex_unlock(&rpm_smd_clk_lock); 286 287 return ret; 288 } 289 290 static void clk_smd_rpm_unprepare(struct clk_hw *hw) 291 { 292 struct clk_smd_rpm *r = to_clk_smd_rpm(hw); 293 struct clk_smd_rpm *peer = r->peer; 294 unsigned long peer_rate = 0, peer_sleep_rate = 0; 295 unsigned long active_rate, sleep_rate; 296 int ret; 297 298 mutex_lock(&rpm_smd_clk_lock); 299 300 if (!r->rate) 301 goto out; 302 303 /* Take peer clock's rate into account only if it's enabled. */ 304 if (peer->enabled) 305 to_active_sleep(peer, peer->rate, &peer_rate, 306 &peer_sleep_rate); 307 308 active_rate = r->branch ? !!peer_rate : peer_rate; 309 ret = clk_smd_rpm_set_rate_active(r, active_rate); 310 if (ret) 311 goto out; 312 313 sleep_rate = r->branch ? !!peer_sleep_rate : peer_sleep_rate; 314 ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate); 315 if (ret) 316 goto out; 317 318 r->enabled = false; 319 320 out: 321 mutex_unlock(&rpm_smd_clk_lock); 322 } 323 324 static int clk_smd_rpm_set_rate(struct clk_hw *hw, unsigned long rate, 325 unsigned long parent_rate) 326 { 327 struct clk_smd_rpm *r = to_clk_smd_rpm(hw); 328 struct clk_smd_rpm *peer = r->peer; 329 unsigned long active_rate, sleep_rate; 330 unsigned long this_rate = 0, this_sleep_rate = 0; 331 unsigned long peer_rate = 0, peer_sleep_rate = 0; 332 int ret = 0; 333 334 mutex_lock(&rpm_smd_clk_lock); 335 336 if (!r->enabled) 337 goto out; 338 339 to_active_sleep(r, rate, &this_rate, &this_sleep_rate); 340 341 /* Take peer clock's rate into account only if it's enabled. */ 342 if (peer->enabled) 343 to_active_sleep(peer, peer->rate, 344 &peer_rate, &peer_sleep_rate); 345 346 active_rate = max(this_rate, peer_rate); 347 ret = clk_smd_rpm_set_rate_active(r, active_rate); 348 if (ret) 349 goto out; 350 351 sleep_rate = max(this_sleep_rate, peer_sleep_rate); 352 ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate); 353 if (ret) 354 goto out; 355 356 r->rate = rate; 357 358 out: 359 mutex_unlock(&rpm_smd_clk_lock); 360 361 return ret; 362 } 363 364 static long clk_smd_rpm_round_rate(struct clk_hw *hw, unsigned long rate, 365 unsigned long *parent_rate) 366 { 367 /* 368 * RPM handles rate rounding and we don't have a way to 369 * know what the rate will be, so just return whatever 370 * rate is requested. 371 */ 372 return rate; 373 } 374 375 static unsigned long clk_smd_rpm_recalc_rate(struct clk_hw *hw, 376 unsigned long parent_rate) 377 { 378 struct clk_smd_rpm *r = to_clk_smd_rpm(hw); 379 380 /* 381 * RPM handles rate rounding and we don't have a way to 382 * know what the rate will be, so just return whatever 383 * rate was set. 384 */ 385 return r->rate; 386 } 387 388 static int clk_smd_rpm_enable_scaling(void) 389 { 390 int ret; 391 struct clk_smd_rpm_req req = { 392 .key = cpu_to_le32(QCOM_RPM_SMD_KEY_ENABLE), 393 .nbytes = cpu_to_le32(sizeof(u32)), 394 .value = cpu_to_le32(1), 395 }; 396 397 ret = qcom_rpm_smd_write(rpmcc_smd_rpm, QCOM_SMD_RPM_SLEEP_STATE, 398 QCOM_SMD_RPM_MISC_CLK, 399 QCOM_RPM_SCALING_ENABLE_ID, &req, sizeof(req)); 400 if (ret) { 401 pr_err("RPM clock scaling (sleep set) not enabled!\n"); 402 return ret; 403 } 404 405 ret = qcom_rpm_smd_write(rpmcc_smd_rpm, QCOM_SMD_RPM_ACTIVE_STATE, 406 QCOM_SMD_RPM_MISC_CLK, 407 QCOM_RPM_SCALING_ENABLE_ID, &req, sizeof(req)); 408 if (ret) { 409 pr_err("RPM clock scaling (active set) not enabled!\n"); 410 return ret; 411 } 412 413 pr_debug("%s: RPM clock scaling is enabled\n", __func__); 414 return 0; 415 } 416 417 static const struct clk_ops clk_smd_rpm_ops = { 418 .prepare = clk_smd_rpm_prepare, 419 .unprepare = clk_smd_rpm_unprepare, 420 .set_rate = clk_smd_rpm_set_rate, 421 .round_rate = clk_smd_rpm_round_rate, 422 .recalc_rate = clk_smd_rpm_recalc_rate, 423 }; 424 425 static const struct clk_ops clk_smd_rpm_branch_ops = { 426 .prepare = clk_smd_rpm_prepare, 427 .unprepare = clk_smd_rpm_unprepare, 428 .recalc_rate = clk_smd_rpm_recalc_rate, 429 }; 430 431 /* Disabling BI_TCXO_AO could gate the root clock source of the entire system. */ 432 DEFINE_CLK_SMD_RPM_BRANCH_A(bi_tcxo, QCOM_SMD_RPM_MISC_CLK, 0, 19200000, CLK_IS_CRITICAL); 433 DEFINE_CLK_SMD_RPM_BRANCH(qdss, QCOM_SMD_RPM_MISC_CLK, 1, 19200000); 434 DEFINE_CLK_SMD_RPM_QDSS(qdss, QCOM_SMD_RPM_MISC_CLK, 1); 435 DEFINE_CLK_SMD_RPM_BRANCH_A(bimc_freq_log, QCOM_SMD_RPM_MISC_CLK, 4, 1, 0); 436 437 DEFINE_CLK_SMD_RPM_BRANCH(mss_cfg_ahb, QCOM_SMD_RPM_MCFG_CLK, 0, 19200000); 438 439 DEFINE_CLK_SMD_RPM_BRANCH(aggre1_noc, QCOM_SMD_RPM_AGGR_CLK, 1, 1000); 440 DEFINE_CLK_SMD_RPM_BRANCH(aggre2_noc, QCOM_SMD_RPM_AGGR_CLK, 2, 1000); 441 DEFINE_CLK_SMD_RPM(aggre1_noc, QCOM_SMD_RPM_AGGR_CLK, 1); 442 DEFINE_CLK_SMD_RPM(aggre2_noc, QCOM_SMD_RPM_AGGR_CLK, 2); 443 444 DEFINE_CLK_SMD_RPM_BUS(pcnoc, 0); 445 DEFINE_CLK_SMD_RPM_BUS(snoc, 1); 446 DEFINE_CLK_SMD_RPM_BUS(sysmmnoc, 2); 447 DEFINE_CLK_SMD_RPM_BUS(cnoc, 2); 448 DEFINE_CLK_SMD_RPM_BUS(mmssnoc_ahb, 3); 449 DEFINE_CLK_SMD_RPM_BUS(snoc_periph, 0); 450 DEFINE_CLK_SMD_RPM_BUS(cnoc, 1); 451 DEFINE_CLK_SMD_RPM_BUS(snoc, 2); 452 DEFINE_CLK_SMD_RPM_BUS(snoc_lpass, 5); 453 454 DEFINE_CLK_SMD_RPM(bimc, QCOM_SMD_RPM_MEM_CLK, 0); 455 DEFINE_CLK_SMD_RPM(cpuss_gnoc, QCOM_SMD_RPM_MEM_CLK, 1); 456 DEFINE_CLK_SMD_RPM_CLK_SRC(gfx3d, QCOM_SMD_RPM_MEM_CLK, 1); 457 DEFINE_CLK_SMD_RPM(ocmemgx, QCOM_SMD_RPM_MEM_CLK, 2); 458 DEFINE_CLK_SMD_RPM(bimc_gpu, QCOM_SMD_RPM_MEM_CLK, 2); 459 460 DEFINE_CLK_SMD_RPM(ce1, QCOM_SMD_RPM_CE_CLK, 0); 461 DEFINE_CLK_SMD_RPM(ce2, QCOM_SMD_RPM_CE_CLK, 1); 462 DEFINE_CLK_SMD_RPM(ce3, QCOM_SMD_RPM_CE_CLK, 2); 463 464 DEFINE_CLK_SMD_RPM(ipa, QCOM_SMD_RPM_IPA_CLK, 0); 465 466 DEFINE_CLK_SMD_RPM(hwkm, QCOM_SMD_RPM_HWKM_CLK, 0); 467 468 DEFINE_CLK_SMD_RPM(mmssnoc_axi_rpm, QCOM_SMD_RPM_MMAXI_CLK, 0); 469 DEFINE_CLK_SMD_RPM(mmnrt, QCOM_SMD_RPM_MMAXI_CLK, 0); 470 DEFINE_CLK_SMD_RPM(mmrt, QCOM_SMD_RPM_MMAXI_CLK, 1); 471 472 DEFINE_CLK_SMD_RPM(pka, QCOM_SMD_RPM_PKA_CLK, 0); 473 474 DEFINE_CLK_SMD_RPM(qpic, QCOM_SMD_RPM_QPIC_CLK, 0); 475 476 DEFINE_CLK_SMD_RPM(qup, QCOM_SMD_RPM_QUP_CLK, 0); 477 478 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(bb_clk1, 1, 19200000); 479 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(bb_clk2, 2, 19200000); 480 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(ln_bb_clk1, 1, 19200000); 481 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(ln_bb_clk2, 2, 19200000); 482 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(ln_bb_clk3, 3, 19200000); 483 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(rf_clk1, 4, 19200000); 484 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(rf_clk2, 5, 19200000); 485 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(rf_clk3, 6, 19200000); 486 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(ln_bb_clk, 8, 19200000); 487 488 DEFINE_CLK_SMD_RPM_XO_BUFFER_PREFIX(38m4_, rf_clk3, 6, 38400000); 489 490 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(cxo_d0, 1, 19200000); 491 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(cxo_d1, 2, 19200000); 492 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(cxo_a0, 4, 19200000); 493 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(cxo_a1, 5, 19200000); 494 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(cxo_a2, 6, 19200000); 495 496 DEFINE_CLK_SMD_RPM_XO_BUFFER(diff_clk, 7, 19200000); 497 DEFINE_CLK_SMD_RPM_XO_BUFFER(div_clk1, 11, 19200000); 498 DEFINE_CLK_SMD_RPM_XO_BUFFER(div_clk2, 12, 19200000); 499 DEFINE_CLK_SMD_RPM_XO_BUFFER(div_clk3, 13, 19200000); 500 501 static struct clk_smd_rpm *msm8909_clks[] = { 502 [RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, 503 [RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, 504 [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, 505 [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, 506 [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, 507 [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, 508 [RPM_SMD_QPIC_CLK] = &clk_smd_rpm_qpic_clk, 509 [RPM_SMD_QPIC_CLK_A] = &clk_smd_rpm_qpic_a_clk, 510 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, 511 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, 512 [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, 513 [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, 514 [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2, 515 [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a, 516 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, 517 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, 518 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, 519 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, 520 [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, 521 [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin, 522 [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin, 523 [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin, 524 [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin, 525 [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin, 526 [RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin, 527 [RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin, 528 }; 529 530 static const struct rpm_smd_clk_desc rpm_clk_msm8909 = { 531 .clks = msm8909_clks, 532 .num_clks = ARRAY_SIZE(msm8909_clks), 533 }; 534 535 static struct clk_smd_rpm *msm8916_clks[] = { 536 [RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, 537 [RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, 538 [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, 539 [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, 540 [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, 541 [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, 542 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, 543 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, 544 [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, 545 [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, 546 [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2, 547 [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a, 548 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, 549 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, 550 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, 551 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, 552 [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, 553 [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin, 554 [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin, 555 [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin, 556 [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin, 557 [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin, 558 [RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin, 559 [RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin, 560 }; 561 562 static const struct rpm_smd_clk_desc rpm_clk_msm8916 = { 563 .clks = msm8916_clks, 564 .num_clks = ARRAY_SIZE(msm8916_clks), 565 }; 566 567 static struct clk_smd_rpm *msm8917_clks[] = { 568 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, 569 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, 570 [RPM_SMD_PNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, 571 [RPM_SMD_PNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, 572 [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, 573 [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, 574 [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, 575 [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, 576 [RPM_SMD_BIMC_GPU_CLK] = &clk_smd_rpm_bimc_gpu_clk, 577 [RPM_SMD_BIMC_GPU_A_CLK] = &clk_smd_rpm_bimc_gpu_a_clk, 578 [RPM_SMD_SYSMMNOC_CLK] = &clk_smd_rpm_bus_2_sysmmnoc_clk, 579 [RPM_SMD_SYSMMNOC_A_CLK] = &clk_smd_rpm_bus_2_sysmmnoc_a_clk, 580 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, 581 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, 582 [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, 583 [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, 584 [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2, 585 [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a, 586 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, 587 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, 588 [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2, 589 [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a, 590 [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, 591 [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin, 592 [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin, 593 [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin, 594 }; 595 596 static const struct rpm_smd_clk_desc rpm_clk_msm8917 = { 597 .clks = msm8917_clks, 598 .num_clks = ARRAY_SIZE(msm8917_clks), 599 }; 600 601 static struct clk_smd_rpm *msm8936_clks[] = { 602 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, 603 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, 604 [RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, 605 [RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, 606 [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, 607 [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, 608 [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, 609 [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, 610 [RPM_SMD_SYSMMNOC_CLK] = &clk_smd_rpm_bus_2_sysmmnoc_clk, 611 [RPM_SMD_SYSMMNOC_A_CLK] = &clk_smd_rpm_bus_2_sysmmnoc_a_clk, 612 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, 613 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, 614 [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, 615 [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, 616 [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2, 617 [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a, 618 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, 619 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, 620 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, 621 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, 622 [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, 623 [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin, 624 [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin, 625 [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin, 626 [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin, 627 [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin, 628 [RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin, 629 [RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin, 630 }; 631 632 static const struct rpm_smd_clk_desc rpm_clk_msm8936 = { 633 .clks = msm8936_clks, 634 .num_clks = ARRAY_SIZE(msm8936_clks), 635 }; 636 637 static struct clk_smd_rpm *msm8974_clks[] = { 638 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, 639 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, 640 [RPM_SMD_PNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, 641 [RPM_SMD_PNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, 642 [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, 643 [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, 644 [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_2_cnoc_clk, 645 [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_2_cnoc_a_clk, 646 [RPM_SMD_MMSSNOC_AHB_CLK] = &clk_smd_rpm_bus_3_mmssnoc_ahb_clk, 647 [RPM_SMD_MMSSNOC_AHB_A_CLK] = &clk_smd_rpm_bus_3_mmssnoc_ahb_a_clk, 648 [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, 649 [RPM_SMD_GFX3D_CLK_SRC] = &clk_smd_rpm_gfx3d_clk_src, 650 [RPM_SMD_GFX3D_A_CLK_SRC] = &clk_smd_rpm_gfx3d_a_clk_src, 651 [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, 652 [RPM_SMD_OCMEMGX_CLK] = &clk_smd_rpm_ocmemgx_clk, 653 [RPM_SMD_OCMEMGX_A_CLK] = &clk_smd_rpm_ocmemgx_a_clk, 654 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, 655 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, 656 [RPM_SMD_CXO_D0] = &clk_smd_rpm_cxo_d0, 657 [RPM_SMD_CXO_D0_A] = &clk_smd_rpm_cxo_d0_a, 658 [RPM_SMD_CXO_D1] = &clk_smd_rpm_cxo_d1, 659 [RPM_SMD_CXO_D1_A] = &clk_smd_rpm_cxo_d1_a, 660 [RPM_SMD_CXO_A0] = &clk_smd_rpm_cxo_a0, 661 [RPM_SMD_CXO_A0_A] = &clk_smd_rpm_cxo_a0_a, 662 [RPM_SMD_CXO_A1] = &clk_smd_rpm_cxo_a1, 663 [RPM_SMD_CXO_A1_A] = &clk_smd_rpm_cxo_a1_a, 664 [RPM_SMD_CXO_A2] = &clk_smd_rpm_cxo_a2, 665 [RPM_SMD_CXO_A2_A] = &clk_smd_rpm_cxo_a2_a, 666 [RPM_SMD_DIFF_CLK] = &clk_smd_rpm_diff_clk, 667 [RPM_SMD_DIFF_A_CLK] = &clk_smd_rpm_diff_clk_a, 668 [RPM_SMD_DIV_CLK1] = &clk_smd_rpm_div_clk1, 669 [RPM_SMD_DIV_A_CLK1] = &clk_smd_rpm_div_clk1_a, 670 [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2, 671 [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a, 672 [RPM_SMD_CXO_D0_PIN] = &clk_smd_rpm_cxo_d0_pin, 673 [RPM_SMD_CXO_D0_A_PIN] = &clk_smd_rpm_cxo_d0_a_pin, 674 [RPM_SMD_CXO_D1_PIN] = &clk_smd_rpm_cxo_d1_pin, 675 [RPM_SMD_CXO_D1_A_PIN] = &clk_smd_rpm_cxo_d1_a_pin, 676 [RPM_SMD_CXO_A0_PIN] = &clk_smd_rpm_cxo_a0_pin, 677 [RPM_SMD_CXO_A0_A_PIN] = &clk_smd_rpm_cxo_a0_a_pin, 678 [RPM_SMD_CXO_A1_PIN] = &clk_smd_rpm_cxo_a1_pin, 679 [RPM_SMD_CXO_A1_A_PIN] = &clk_smd_rpm_cxo_a1_a_pin, 680 [RPM_SMD_CXO_A2_PIN] = &clk_smd_rpm_cxo_a2_pin, 681 [RPM_SMD_CXO_A2_A_PIN] = &clk_smd_rpm_cxo_a2_a_pin, 682 }; 683 684 static const struct rpm_smd_clk_desc rpm_clk_msm8974 = { 685 .clks = msm8974_clks, 686 .num_clks = ARRAY_SIZE(msm8974_clks), 687 .scaling_before_handover = true, 688 }; 689 690 static struct clk_smd_rpm *msm8976_clks[] = { 691 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, 692 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, 693 [RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, 694 [RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, 695 [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, 696 [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, 697 [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, 698 [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, 699 [RPM_SMD_SYSMMNOC_CLK] = &clk_smd_rpm_bus_2_sysmmnoc_clk, 700 [RPM_SMD_SYSMMNOC_A_CLK] = &clk_smd_rpm_bus_2_sysmmnoc_a_clk, 701 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, 702 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, 703 [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, 704 [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, 705 [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2, 706 [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a, 707 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, 708 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, 709 [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, 710 [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin, 711 [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin, 712 [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin, 713 [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2, 714 [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a, 715 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, 716 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, 717 }; 718 719 static const struct rpm_smd_clk_desc rpm_clk_msm8976 = { 720 .clks = msm8976_clks, 721 .num_clks = ARRAY_SIZE(msm8976_clks), 722 }; 723 724 static struct clk_smd_rpm *msm8992_clks[] = { 725 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, 726 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, 727 [RPM_SMD_PNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, 728 [RPM_SMD_PNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, 729 [RPM_SMD_OCMEMGX_CLK] = &clk_smd_rpm_ocmemgx_clk, 730 [RPM_SMD_OCMEMGX_A_CLK] = &clk_smd_rpm_ocmemgx_a_clk, 731 [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, 732 [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, 733 [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_2_cnoc_clk, 734 [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_2_cnoc_a_clk, 735 [RPM_SMD_GFX3D_CLK_SRC] = &clk_smd_rpm_gfx3d_clk_src, 736 [RPM_SMD_GFX3D_A_CLK_SRC] = &clk_smd_rpm_gfx3d_a_clk_src, 737 [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, 738 [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, 739 [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, 740 [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, 741 [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, 742 [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin, 743 [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2, 744 [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a, 745 [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin, 746 [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin, 747 [RPM_SMD_DIV_CLK1] = &clk_smd_rpm_div_clk1, 748 [RPM_SMD_DIV_A_CLK1] = &clk_smd_rpm_div_clk1_a, 749 [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2, 750 [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a, 751 [RPM_SMD_DIV_CLK3] = &clk_smd_rpm_div_clk3, 752 [RPM_SMD_DIV_A_CLK3] = &clk_smd_rpm_div_clk3_a, 753 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, 754 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, 755 [RPM_SMD_LN_BB_CLK] = &clk_smd_rpm_ln_bb_clk, 756 [RPM_SMD_LN_BB_A_CLK] = &clk_smd_rpm_ln_bb_clk_a, 757 [RPM_SMD_MMSSNOC_AHB_CLK] = &clk_smd_rpm_bus_3_mmssnoc_ahb_clk, 758 [RPM_SMD_MMSSNOC_AHB_A_CLK] = &clk_smd_rpm_bus_3_mmssnoc_ahb_a_clk, 759 [RPM_SMD_MSS_CFG_AHB_CLK] = &clk_smd_rpm_branch_mss_cfg_ahb_clk, 760 [RPM_SMD_MSS_CFG_AHB_A_CLK] = &clk_smd_rpm_branch_mss_cfg_ahb_a_clk, 761 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, 762 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, 763 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, 764 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, 765 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, 766 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, 767 [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin, 768 [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin, 769 [RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin, 770 [RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin, 771 [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, 772 [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, 773 [RPM_SMD_CE2_CLK] = &clk_smd_rpm_ce2_clk, 774 [RPM_SMD_CE2_A_CLK] = &clk_smd_rpm_ce2_a_clk, 775 }; 776 777 static const struct rpm_smd_clk_desc rpm_clk_msm8992 = { 778 .clks = msm8992_clks, 779 .num_clks = ARRAY_SIZE(msm8992_clks), 780 }; 781 782 static struct clk_smd_rpm *msm8994_clks[] = { 783 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, 784 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, 785 [RPM_SMD_PNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, 786 [RPM_SMD_PNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, 787 [RPM_SMD_OCMEMGX_CLK] = &clk_smd_rpm_ocmemgx_clk, 788 [RPM_SMD_OCMEMGX_A_CLK] = &clk_smd_rpm_ocmemgx_a_clk, 789 [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, 790 [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, 791 [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_2_cnoc_clk, 792 [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_2_cnoc_a_clk, 793 [RPM_SMD_GFX3D_CLK_SRC] = &clk_smd_rpm_gfx3d_clk_src, 794 [RPM_SMD_GFX3D_A_CLK_SRC] = &clk_smd_rpm_gfx3d_a_clk_src, 795 [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, 796 [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, 797 [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, 798 [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, 799 [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, 800 [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin, 801 [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2, 802 [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a, 803 [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin, 804 [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin, 805 [RPM_SMD_DIV_CLK1] = &clk_smd_rpm_div_clk1, 806 [RPM_SMD_DIV_A_CLK1] = &clk_smd_rpm_div_clk1_a, 807 [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2, 808 [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a, 809 [RPM_SMD_DIV_CLK3] = &clk_smd_rpm_div_clk3, 810 [RPM_SMD_DIV_A_CLK3] = &clk_smd_rpm_div_clk3_a, 811 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, 812 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, 813 [RPM_SMD_LN_BB_CLK] = &clk_smd_rpm_ln_bb_clk, 814 [RPM_SMD_LN_BB_A_CLK] = &clk_smd_rpm_ln_bb_clk_a, 815 [RPM_SMD_MMSSNOC_AHB_CLK] = &clk_smd_rpm_bus_3_mmssnoc_ahb_clk, 816 [RPM_SMD_MMSSNOC_AHB_A_CLK] = &clk_smd_rpm_bus_3_mmssnoc_ahb_a_clk, 817 [RPM_SMD_MSS_CFG_AHB_CLK] = &clk_smd_rpm_branch_mss_cfg_ahb_clk, 818 [RPM_SMD_MSS_CFG_AHB_A_CLK] = &clk_smd_rpm_branch_mss_cfg_ahb_a_clk, 819 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, 820 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, 821 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, 822 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, 823 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, 824 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, 825 [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin, 826 [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin, 827 [RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin, 828 [RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin, 829 [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, 830 [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, 831 [RPM_SMD_CE2_CLK] = &clk_smd_rpm_ce2_clk, 832 [RPM_SMD_CE2_A_CLK] = &clk_smd_rpm_ce2_a_clk, 833 [RPM_SMD_CE3_CLK] = &clk_smd_rpm_ce3_clk, 834 [RPM_SMD_CE3_A_CLK] = &clk_smd_rpm_ce3_a_clk, 835 }; 836 837 static const struct rpm_smd_clk_desc rpm_clk_msm8994 = { 838 .clks = msm8994_clks, 839 .num_clks = ARRAY_SIZE(msm8994_clks), 840 }; 841 842 static struct clk_smd_rpm *msm8996_clks[] = { 843 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, 844 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, 845 [RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, 846 [RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, 847 [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, 848 [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, 849 [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_2_cnoc_clk, 850 [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_2_cnoc_a_clk, 851 [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, 852 [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, 853 [RPM_SMD_MMAXI_CLK] = &clk_smd_rpm_mmssnoc_axi_rpm_clk, 854 [RPM_SMD_MMAXI_A_CLK] = &clk_smd_rpm_mmssnoc_axi_rpm_a_clk, 855 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, 856 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, 857 [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, 858 [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, 859 [RPM_SMD_AGGR1_NOC_CLK] = &clk_smd_rpm_branch_aggre1_noc_clk, 860 [RPM_SMD_AGGR1_NOC_A_CLK] = &clk_smd_rpm_branch_aggre1_noc_a_clk, 861 [RPM_SMD_AGGR2_NOC_CLK] = &clk_smd_rpm_branch_aggre2_noc_clk, 862 [RPM_SMD_AGGR2_NOC_A_CLK] = &clk_smd_rpm_branch_aggre2_noc_a_clk, 863 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, 864 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, 865 [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, 866 [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, 867 [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2, 868 [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a, 869 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, 870 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, 871 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, 872 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, 873 [RPM_SMD_LN_BB_CLK] = &clk_smd_rpm_ln_bb_clk, 874 [RPM_SMD_LN_BB_A_CLK] = &clk_smd_rpm_ln_bb_clk_a, 875 [RPM_SMD_DIV_CLK1] = &clk_smd_rpm_div_clk1, 876 [RPM_SMD_DIV_A_CLK1] = &clk_smd_rpm_div_clk1_a, 877 [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2, 878 [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a, 879 [RPM_SMD_DIV_CLK3] = &clk_smd_rpm_div_clk3, 880 [RPM_SMD_DIV_A_CLK3] = &clk_smd_rpm_div_clk3_a, 881 [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, 882 [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin, 883 [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin, 884 [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin, 885 [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin, 886 [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin, 887 [RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin, 888 [RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin, 889 }; 890 891 static const struct rpm_smd_clk_desc rpm_clk_msm8996 = { 892 .clks = msm8996_clks, 893 .num_clks = ARRAY_SIZE(msm8996_clks), 894 }; 895 896 static struct clk_smd_rpm *qcs404_clks[] = { 897 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, 898 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, 899 [RPM_SMD_PNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, 900 [RPM_SMD_PNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, 901 [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, 902 [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, 903 [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, 904 [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, 905 [RPM_SMD_BIMC_GPU_CLK] = &clk_smd_rpm_bimc_gpu_clk, 906 [RPM_SMD_BIMC_GPU_A_CLK] = &clk_smd_rpm_bimc_gpu_a_clk, 907 [RPM_SMD_QPIC_CLK] = &clk_smd_rpm_qpic_clk, 908 [RPM_SMD_QPIC_CLK_A] = &clk_smd_rpm_qpic_a_clk, 909 [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, 910 [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, 911 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, 912 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, 913 [RPM_SMD_LN_BB_CLK] = &clk_smd_rpm_ln_bb_clk, 914 [RPM_SMD_LN_BB_A_CLK] = &clk_smd_rpm_ln_bb_clk_a, 915 [RPM_SMD_LN_BB_CLK_PIN] = &clk_smd_rpm_ln_bb_clk_pin, 916 [RPM_SMD_LN_BB_A_CLK_PIN] = &clk_smd_rpm_ln_bb_clk_a_pin, 917 }; 918 919 static const struct rpm_smd_clk_desc rpm_clk_qcs404 = { 920 .clks = qcs404_clks, 921 .num_clks = ARRAY_SIZE(qcs404_clks), 922 }; 923 924 static struct clk_smd_rpm *msm8998_clks[] = { 925 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, 926 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, 927 [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, 928 [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, 929 [RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, 930 [RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, 931 [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, 932 [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, 933 [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_2_cnoc_clk, 934 [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_2_cnoc_a_clk, 935 [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, 936 [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, 937 [RPM_SMD_DIV_CLK1] = &clk_smd_rpm_div_clk1, 938 [RPM_SMD_DIV_A_CLK1] = &clk_smd_rpm_div_clk1_a, 939 [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2, 940 [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a, 941 [RPM_SMD_DIV_CLK3] = &clk_smd_rpm_div_clk3, 942 [RPM_SMD_DIV_A_CLK3] = &clk_smd_rpm_div_clk3_a, 943 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, 944 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, 945 [RPM_SMD_LN_BB_CLK1] = &clk_smd_rpm_ln_bb_clk1, 946 [RPM_SMD_LN_BB_CLK1_A] = &clk_smd_rpm_ln_bb_clk1_a, 947 [RPM_SMD_LN_BB_CLK2] = &clk_smd_rpm_ln_bb_clk2, 948 [RPM_SMD_LN_BB_CLK2_A] = &clk_smd_rpm_ln_bb_clk2_a, 949 [RPM_SMD_LN_BB_CLK3] = &clk_smd_rpm_ln_bb_clk3, 950 [RPM_SMD_LN_BB_CLK3_A] = &clk_smd_rpm_ln_bb_clk3_a, 951 [RPM_SMD_LN_BB_CLK1_PIN] = &clk_smd_rpm_ln_bb_clk1_pin, 952 [RPM_SMD_LN_BB_CLK1_A_PIN] = &clk_smd_rpm_ln_bb_clk1_a_pin, 953 [RPM_SMD_LN_BB_CLK2_PIN] = &clk_smd_rpm_ln_bb_clk2_pin, 954 [RPM_SMD_LN_BB_CLK2_A_PIN] = &clk_smd_rpm_ln_bb_clk2_a_pin, 955 [RPM_SMD_LN_BB_CLK3_PIN] = &clk_smd_rpm_ln_bb_clk3_pin, 956 [RPM_SMD_LN_BB_CLK3_A_PIN] = &clk_smd_rpm_ln_bb_clk3_a_pin, 957 [RPM_SMD_MMAXI_CLK] = &clk_smd_rpm_mmssnoc_axi_rpm_clk, 958 [RPM_SMD_MMAXI_A_CLK] = &clk_smd_rpm_mmssnoc_axi_rpm_a_clk, 959 [RPM_SMD_AGGR1_NOC_CLK] = &clk_smd_rpm_aggre1_noc_clk, 960 [RPM_SMD_AGGR1_NOC_A_CLK] = &clk_smd_rpm_aggre1_noc_a_clk, 961 [RPM_SMD_AGGR2_NOC_CLK] = &clk_smd_rpm_aggre2_noc_clk, 962 [RPM_SMD_AGGR2_NOC_A_CLK] = &clk_smd_rpm_aggre2_noc_a_clk, 963 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, 964 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, 965 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, 966 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, 967 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, 968 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, 969 [RPM_SMD_RF_CLK3] = &clk_smd_rpm_rf_clk3, 970 [RPM_SMD_RF_CLK3_A] = &clk_smd_rpm_rf_clk3_a, 971 [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin, 972 [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin, 973 [RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin, 974 [RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin, 975 [RPM_SMD_RF_CLK3_PIN] = &clk_smd_rpm_rf_clk3_pin, 976 [RPM_SMD_RF_CLK3_A_PIN] = &clk_smd_rpm_rf_clk3_a_pin, 977 }; 978 979 static const struct rpm_smd_clk_desc rpm_clk_msm8998 = { 980 .clks = msm8998_clks, 981 .num_clks = ARRAY_SIZE(msm8998_clks), 982 }; 983 984 static struct clk_smd_rpm *sdm660_clks[] = { 985 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, 986 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, 987 [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, 988 [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, 989 [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_2_cnoc_clk, 990 [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_2_cnoc_a_clk, 991 [RPM_SMD_CNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, 992 [RPM_SMD_CNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, 993 [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, 994 [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, 995 [RPM_SMD_MMSSNOC_AXI_CLK] = &clk_smd_rpm_mmssnoc_axi_rpm_clk, 996 [RPM_SMD_MMSSNOC_AXI_CLK_A] = &clk_smd_rpm_mmssnoc_axi_rpm_a_clk, 997 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, 998 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, 999 [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, 1000 [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, 1001 [RPM_SMD_AGGR2_NOC_CLK] = &clk_smd_rpm_aggre2_noc_clk, 1002 [RPM_SMD_AGGR2_NOC_A_CLK] = &clk_smd_rpm_aggre2_noc_a_clk, 1003 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, 1004 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, 1005 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, 1006 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, 1007 [RPM_SMD_DIV_CLK1] = &clk_smd_rpm_div_clk1, 1008 [RPM_SMD_DIV_A_CLK1] = &clk_smd_rpm_div_clk1_a, 1009 [RPM_SMD_LN_BB_CLK] = &clk_smd_rpm_ln_bb_clk1, 1010 [RPM_SMD_LN_BB_A_CLK] = &clk_smd_rpm_ln_bb_clk1_a, 1011 [RPM_SMD_LN_BB_CLK2] = &clk_smd_rpm_ln_bb_clk2, 1012 [RPM_SMD_LN_BB_CLK2_A] = &clk_smd_rpm_ln_bb_clk2_a, 1013 [RPM_SMD_LN_BB_CLK3] = &clk_smd_rpm_ln_bb_clk3, 1014 [RPM_SMD_LN_BB_CLK3_A] = &clk_smd_rpm_ln_bb_clk3_a, 1015 [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin, 1016 [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin, 1017 [RPM_SMD_LN_BB_CLK1_PIN] = &clk_smd_rpm_ln_bb_clk1_pin, 1018 [RPM_SMD_LN_BB_CLK1_A_PIN] = &clk_smd_rpm_ln_bb_clk1_a_pin, 1019 [RPM_SMD_LN_BB_CLK2_PIN] = &clk_smd_rpm_ln_bb_clk2_pin, 1020 [RPM_SMD_LN_BB_CLK2_A_PIN] = &clk_smd_rpm_ln_bb_clk2_a_pin, 1021 [RPM_SMD_LN_BB_CLK3_PIN] = &clk_smd_rpm_ln_bb_clk3_pin, 1022 [RPM_SMD_LN_BB_CLK3_A_PIN] = &clk_smd_rpm_ln_bb_clk3_a_pin, 1023 }; 1024 1025 static const struct rpm_smd_clk_desc rpm_clk_sdm660 = { 1026 .clks = sdm660_clks, 1027 .num_clks = ARRAY_SIZE(sdm660_clks), 1028 }; 1029 1030 static struct clk_smd_rpm *mdm9607_clks[] = { 1031 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, 1032 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, 1033 [RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, 1034 [RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, 1035 [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, 1036 [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, 1037 [RPM_SMD_QPIC_CLK] = &clk_smd_rpm_qpic_clk, 1038 [RPM_SMD_QPIC_CLK_A] = &clk_smd_rpm_qpic_a_clk, 1039 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, 1040 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, 1041 [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, 1042 [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, 1043 [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, 1044 [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin, 1045 }; 1046 1047 static const struct rpm_smd_clk_desc rpm_clk_mdm9607 = { 1048 .clks = mdm9607_clks, 1049 .num_clks = ARRAY_SIZE(mdm9607_clks), 1050 }; 1051 1052 static struct clk_smd_rpm *msm8953_clks[] = { 1053 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, 1054 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, 1055 [RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, 1056 [RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, 1057 [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, 1058 [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, 1059 [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, 1060 [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, 1061 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, 1062 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, 1063 [RPM_SMD_SYSMMNOC_CLK] = &clk_smd_rpm_bus_2_sysmmnoc_clk, 1064 [RPM_SMD_SYSMMNOC_A_CLK] = &clk_smd_rpm_bus_2_sysmmnoc_a_clk, 1065 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, 1066 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, 1067 [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, 1068 [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, 1069 [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2, 1070 [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a, 1071 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, 1072 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, 1073 [RPM_SMD_RF_CLK3] = &clk_smd_rpm_ln_bb_clk, 1074 [RPM_SMD_RF_CLK3_A] = &clk_smd_rpm_ln_bb_clk_a, 1075 [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2, 1076 [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a, 1077 [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, 1078 [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin, 1079 [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin, 1080 [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin, 1081 }; 1082 1083 static const struct rpm_smd_clk_desc rpm_clk_msm8953 = { 1084 .clks = msm8953_clks, 1085 .num_clks = ARRAY_SIZE(msm8953_clks), 1086 }; 1087 1088 static struct clk_smd_rpm *sm6125_clks[] = { 1089 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, 1090 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, 1091 [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_2_snoc_clk, 1092 [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_2_snoc_a_clk, 1093 [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, 1094 [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, 1095 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_branch_qdss_clk, 1096 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_branch_qdss_a_clk, 1097 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, 1098 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, 1099 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, 1100 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, 1101 [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_1_cnoc_clk, 1102 [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_1_cnoc_a_clk, 1103 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, 1104 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, 1105 [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, 1106 [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, 1107 [RPM_SMD_LN_BB_CLK1] = &clk_smd_rpm_ln_bb_clk1, 1108 [RPM_SMD_LN_BB_CLK1_A] = &clk_smd_rpm_ln_bb_clk1_a, 1109 [RPM_SMD_LN_BB_CLK2] = &clk_smd_rpm_ln_bb_clk2, 1110 [RPM_SMD_LN_BB_CLK2_A] = &clk_smd_rpm_ln_bb_clk2_a, 1111 [RPM_SMD_LN_BB_CLK3] = &clk_smd_rpm_ln_bb_clk3, 1112 [RPM_SMD_LN_BB_CLK3_A] = &clk_smd_rpm_ln_bb_clk3_a, 1113 [RPM_SMD_QUP_CLK] = &clk_smd_rpm_qup_clk, 1114 [RPM_SMD_QUP_A_CLK] = &clk_smd_rpm_qup_a_clk, 1115 [RPM_SMD_MMRT_CLK] = &clk_smd_rpm_mmrt_clk, 1116 [RPM_SMD_MMRT_A_CLK] = &clk_smd_rpm_mmrt_a_clk, 1117 [RPM_SMD_MMNRT_CLK] = &clk_smd_rpm_mmnrt_clk, 1118 [RPM_SMD_MMNRT_A_CLK] = &clk_smd_rpm_mmnrt_a_clk, 1119 [RPM_SMD_SNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_snoc_periph_clk, 1120 [RPM_SMD_SNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_snoc_periph_a_clk, 1121 [RPM_SMD_SNOC_LPASS_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_clk, 1122 [RPM_SMD_SNOC_LPASS_A_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_a_clk, 1123 }; 1124 1125 static const struct rpm_smd_clk_desc rpm_clk_sm6125 = { 1126 .clks = sm6125_clks, 1127 .num_clks = ARRAY_SIZE(sm6125_clks), 1128 }; 1129 1130 /* SM6115 */ 1131 static struct clk_smd_rpm *sm6115_clks[] = { 1132 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, 1133 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, 1134 [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_2_snoc_clk, 1135 [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_2_snoc_a_clk, 1136 [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, 1137 [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, 1138 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_branch_qdss_clk, 1139 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_branch_qdss_a_clk, 1140 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, 1141 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, 1142 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, 1143 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, 1144 [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_1_cnoc_clk, 1145 [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_1_cnoc_a_clk, 1146 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, 1147 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, 1148 [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, 1149 [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, 1150 [RPM_SMD_QUP_CLK] = &clk_smd_rpm_qup_clk, 1151 [RPM_SMD_QUP_A_CLK] = &clk_smd_rpm_qup_a_clk, 1152 [RPM_SMD_MMRT_CLK] = &clk_smd_rpm_mmrt_clk, 1153 [RPM_SMD_MMRT_A_CLK] = &clk_smd_rpm_mmrt_a_clk, 1154 [RPM_SMD_MMNRT_CLK] = &clk_smd_rpm_mmnrt_clk, 1155 [RPM_SMD_MMNRT_A_CLK] = &clk_smd_rpm_mmnrt_a_clk, 1156 [RPM_SMD_SNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_snoc_periph_clk, 1157 [RPM_SMD_SNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_snoc_periph_a_clk, 1158 [RPM_SMD_SNOC_LPASS_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_clk, 1159 [RPM_SMD_SNOC_LPASS_A_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_a_clk, 1160 [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin, 1161 [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin, 1162 [RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin, 1163 [RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin, 1164 }; 1165 1166 static const struct rpm_smd_clk_desc rpm_clk_sm6115 = { 1167 .clks = sm6115_clks, 1168 .num_clks = ARRAY_SIZE(sm6115_clks), 1169 }; 1170 1171 static struct clk_smd_rpm *sm6375_clks[] = { 1172 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, 1173 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, 1174 [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_2_snoc_clk, 1175 [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_2_snoc_a_clk, 1176 [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, 1177 [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, 1178 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_branch_qdss_clk, 1179 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_branch_qdss_a_clk, 1180 [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_1_cnoc_clk, 1181 [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_1_cnoc_a_clk, 1182 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, 1183 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, 1184 [RPM_SMD_QUP_CLK] = &clk_smd_rpm_qup_clk, 1185 [RPM_SMD_QUP_A_CLK] = &clk_smd_rpm_qup_a_clk, 1186 [RPM_SMD_MMRT_CLK] = &clk_smd_rpm_mmrt_clk, 1187 [RPM_SMD_MMRT_A_CLK] = &clk_smd_rpm_mmrt_a_clk, 1188 [RPM_SMD_MMNRT_CLK] = &clk_smd_rpm_mmnrt_clk, 1189 [RPM_SMD_MMNRT_A_CLK] = &clk_smd_rpm_mmnrt_a_clk, 1190 [RPM_SMD_SNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_snoc_periph_clk, 1191 [RPM_SMD_SNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_snoc_periph_a_clk, 1192 [RPM_SMD_SNOC_LPASS_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_clk, 1193 [RPM_SMD_SNOC_LPASS_A_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_a_clk, 1194 [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, 1195 [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, 1196 [RPM_SMD_HWKM_CLK] = &clk_smd_rpm_hwkm_clk, 1197 [RPM_SMD_HWKM_A_CLK] = &clk_smd_rpm_hwkm_a_clk, 1198 [RPM_SMD_PKA_CLK] = &clk_smd_rpm_pka_clk, 1199 [RPM_SMD_PKA_A_CLK] = &clk_smd_rpm_pka_a_clk, 1200 [RPM_SMD_BIMC_FREQ_LOG] = &clk_smd_rpm_branch_bimc_freq_log, 1201 }; 1202 1203 static const struct rpm_smd_clk_desc rpm_clk_sm6375 = { 1204 .clks = sm6375_clks, 1205 .num_clks = ARRAY_SIZE(sm6375_clks), 1206 }; 1207 1208 static struct clk_smd_rpm *qcm2290_clks[] = { 1209 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, 1210 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, 1211 [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_2_snoc_clk, 1212 [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_2_snoc_a_clk, 1213 [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, 1214 [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, 1215 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_branch_qdss_clk, 1216 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_branch_qdss_a_clk, 1217 [RPM_SMD_LN_BB_CLK2] = &clk_smd_rpm_ln_bb_clk2, 1218 [RPM_SMD_LN_BB_CLK2_A] = &clk_smd_rpm_ln_bb_clk2_a, 1219 [RPM_SMD_RF_CLK3] = &clk_smd_rpm_38m4_rf_clk3, 1220 [RPM_SMD_RF_CLK3_A] = &clk_smd_rpm_38m4_rf_clk3_a, 1221 [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_1_cnoc_clk, 1222 [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_1_cnoc_a_clk, 1223 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, 1224 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, 1225 [RPM_SMD_QUP_CLK] = &clk_smd_rpm_qup_clk, 1226 [RPM_SMD_QUP_A_CLK] = &clk_smd_rpm_qup_a_clk, 1227 [RPM_SMD_MMRT_CLK] = &clk_smd_rpm_mmrt_clk, 1228 [RPM_SMD_MMRT_A_CLK] = &clk_smd_rpm_mmrt_a_clk, 1229 [RPM_SMD_MMNRT_CLK] = &clk_smd_rpm_mmnrt_clk, 1230 [RPM_SMD_MMNRT_A_CLK] = &clk_smd_rpm_mmnrt_a_clk, 1231 [RPM_SMD_SNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_snoc_periph_clk, 1232 [RPM_SMD_SNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_snoc_periph_a_clk, 1233 [RPM_SMD_SNOC_LPASS_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_clk, 1234 [RPM_SMD_SNOC_LPASS_A_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_a_clk, 1235 [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, 1236 [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, 1237 [RPM_SMD_QPIC_CLK] = &clk_smd_rpm_qpic_clk, 1238 [RPM_SMD_QPIC_CLK_A] = &clk_smd_rpm_qpic_a_clk, 1239 [RPM_SMD_HWKM_CLK] = &clk_smd_rpm_hwkm_clk, 1240 [RPM_SMD_HWKM_A_CLK] = &clk_smd_rpm_hwkm_a_clk, 1241 [RPM_SMD_PKA_CLK] = &clk_smd_rpm_pka_clk, 1242 [RPM_SMD_PKA_A_CLK] = &clk_smd_rpm_pka_a_clk, 1243 [RPM_SMD_BIMC_GPU_CLK] = &clk_smd_rpm_bimc_gpu_clk, 1244 [RPM_SMD_BIMC_GPU_A_CLK] = &clk_smd_rpm_bimc_gpu_a_clk, 1245 [RPM_SMD_CPUSS_GNOC_CLK] = &clk_smd_rpm_cpuss_gnoc_clk, 1246 [RPM_SMD_CPUSS_GNOC_A_CLK] = &clk_smd_rpm_cpuss_gnoc_a_clk, 1247 }; 1248 1249 static const struct rpm_smd_clk_desc rpm_clk_qcm2290 = { 1250 .clks = qcm2290_clks, 1251 .num_clks = ARRAY_SIZE(qcm2290_clks), 1252 }; 1253 1254 static const struct of_device_id rpm_smd_clk_match_table[] = { 1255 { .compatible = "qcom,rpmcc-mdm9607", .data = &rpm_clk_mdm9607 }, 1256 { .compatible = "qcom,rpmcc-msm8226", .data = &rpm_clk_msm8974 }, 1257 { .compatible = "qcom,rpmcc-msm8909", .data = &rpm_clk_msm8909 }, 1258 { .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916 }, 1259 { .compatible = "qcom,rpmcc-msm8917", .data = &rpm_clk_msm8917 }, 1260 { .compatible = "qcom,rpmcc-msm8936", .data = &rpm_clk_msm8936 }, 1261 { .compatible = "qcom,rpmcc-msm8953", .data = &rpm_clk_msm8953 }, 1262 { .compatible = "qcom,rpmcc-msm8974", .data = &rpm_clk_msm8974 }, 1263 { .compatible = "qcom,rpmcc-msm8976", .data = &rpm_clk_msm8976 }, 1264 { .compatible = "qcom,rpmcc-msm8992", .data = &rpm_clk_msm8992 }, 1265 { .compatible = "qcom,rpmcc-msm8994", .data = &rpm_clk_msm8994 }, 1266 { .compatible = "qcom,rpmcc-msm8996", .data = &rpm_clk_msm8996 }, 1267 { .compatible = "qcom,rpmcc-msm8998", .data = &rpm_clk_msm8998 }, 1268 { .compatible = "qcom,rpmcc-qcm2290", .data = &rpm_clk_qcm2290 }, 1269 { .compatible = "qcom,rpmcc-qcs404", .data = &rpm_clk_qcs404 }, 1270 { .compatible = "qcom,rpmcc-sdm660", .data = &rpm_clk_sdm660 }, 1271 { .compatible = "qcom,rpmcc-sm6115", .data = &rpm_clk_sm6115 }, 1272 { .compatible = "qcom,rpmcc-sm6125", .data = &rpm_clk_sm6125 }, 1273 { .compatible = "qcom,rpmcc-sm6375", .data = &rpm_clk_sm6375 }, 1274 { } 1275 }; 1276 MODULE_DEVICE_TABLE(of, rpm_smd_clk_match_table); 1277 1278 static struct clk_hw *qcom_smdrpm_clk_hw_get(struct of_phandle_args *clkspec, 1279 void *data) 1280 { 1281 const struct rpm_smd_clk_desc *desc = data; 1282 unsigned int idx = clkspec->args[0]; 1283 1284 if (idx >= desc->num_clks) { 1285 pr_err("%s: invalid index %u\n", __func__, idx); 1286 return ERR_PTR(-EINVAL); 1287 } 1288 1289 return desc->clks[idx] ? &desc->clks[idx]->hw : ERR_PTR(-ENOENT); 1290 } 1291 1292 static int rpm_smd_clk_probe(struct platform_device *pdev) 1293 { 1294 int ret; 1295 size_t num_clks, i; 1296 struct clk_smd_rpm **rpm_smd_clks; 1297 const struct rpm_smd_clk_desc *desc; 1298 1299 rpmcc_smd_rpm = dev_get_drvdata(pdev->dev.parent); 1300 if (!rpmcc_smd_rpm) { 1301 dev_err(&pdev->dev, "Unable to retrieve handle to RPM\n"); 1302 return -ENODEV; 1303 } 1304 1305 desc = of_device_get_match_data(&pdev->dev); 1306 if (!desc) 1307 return -EINVAL; 1308 1309 rpm_smd_clks = desc->clks; 1310 num_clks = desc->num_clks; 1311 1312 if (desc->scaling_before_handover) { 1313 ret = clk_smd_rpm_enable_scaling(); 1314 if (ret) 1315 goto err; 1316 } 1317 1318 for (i = 0; i < num_clks; i++) { 1319 if (!rpm_smd_clks[i]) 1320 continue; 1321 1322 ret = clk_smd_rpm_handoff(rpm_smd_clks[i]); 1323 if (ret) 1324 goto err; 1325 } 1326 1327 if (!desc->scaling_before_handover) { 1328 ret = clk_smd_rpm_enable_scaling(); 1329 if (ret) 1330 goto err; 1331 } 1332 1333 for (i = 0; i < num_clks; i++) { 1334 if (!rpm_smd_clks[i]) 1335 continue; 1336 1337 ret = devm_clk_hw_register(&pdev->dev, &rpm_smd_clks[i]->hw); 1338 if (ret) 1339 goto err; 1340 } 1341 1342 ret = devm_of_clk_add_hw_provider(&pdev->dev, qcom_smdrpm_clk_hw_get, 1343 (void *)desc); 1344 if (ret) 1345 goto err; 1346 1347 return 0; 1348 err: 1349 dev_err(&pdev->dev, "Error registering SMD clock driver (%d)\n", ret); 1350 return ret; 1351 } 1352 1353 static struct platform_driver rpm_smd_clk_driver = { 1354 .driver = { 1355 .name = "qcom-clk-smd-rpm", 1356 .of_match_table = rpm_smd_clk_match_table, 1357 }, 1358 .probe = rpm_smd_clk_probe, 1359 }; 1360 1361 static int __init rpm_smd_clk_init(void) 1362 { 1363 return platform_driver_register(&rpm_smd_clk_driver); 1364 } 1365 core_initcall(rpm_smd_clk_init); 1366 1367 static void __exit rpm_smd_clk_exit(void) 1368 { 1369 platform_driver_unregister(&rpm_smd_clk_driver); 1370 } 1371 module_exit(rpm_smd_clk_exit); 1372 1373 MODULE_DESCRIPTION("Qualcomm RPM over SMD Clock Controller Driver"); 1374 MODULE_LICENSE("GPL v2"); 1375 MODULE_ALIAS("platform:qcom-clk-smd-rpm"); 1376