1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2016, Linaro Limited 4 * Copyright (c) 2014, The Linux Foundation. All rights reserved. 5 */ 6 7 #include <linux/clk-provider.h> 8 #include <linux/err.h> 9 #include <linux/export.h> 10 #include <linux/init.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/mutex.h> 14 #include <linux/of.h> 15 #include <linux/of_device.h> 16 #include <linux/platform_device.h> 17 #include <linux/soc/qcom/smd-rpm.h> 18 19 #include <dt-bindings/clock/qcom,rpmcc.h> 20 #include <dt-bindings/mfd/qcom-rpm.h> 21 22 #define QCOM_RPM_KEY_SOFTWARE_ENABLE 0x6e657773 23 #define QCOM_RPM_KEY_PIN_CTRL_CLK_BUFFER_ENABLE_KEY 0x62636370 24 #define QCOM_RPM_SMD_KEY_RATE 0x007a484b 25 #define QCOM_RPM_SMD_KEY_ENABLE 0x62616e45 26 #define QCOM_RPM_SMD_KEY_STATE 0x54415453 27 #define QCOM_RPM_SCALING_ENABLE_ID 0x2 28 29 #define __DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id, stat_id, \ 30 key) \ 31 static struct clk_smd_rpm _platform##_##_active; \ 32 static struct clk_smd_rpm _platform##_##_name = { \ 33 .rpm_res_type = (type), \ 34 .rpm_clk_id = (r_id), \ 35 .rpm_status_id = (stat_id), \ 36 .rpm_key = (key), \ 37 .peer = &_platform##_##_active, \ 38 .rate = INT_MAX, \ 39 .hw.init = &(struct clk_init_data){ \ 40 .ops = &clk_smd_rpm_ops, \ 41 .name = #_name, \ 42 .parent_names = (const char *[]){ "xo_board" }, \ 43 .num_parents = 1, \ 44 }, \ 45 }; \ 46 static struct clk_smd_rpm _platform##_##_active = { \ 47 .rpm_res_type = (type), \ 48 .rpm_clk_id = (r_id), \ 49 .rpm_status_id = (stat_id), \ 50 .active_only = true, \ 51 .rpm_key = (key), \ 52 .peer = &_platform##_##_name, \ 53 .rate = INT_MAX, \ 54 .hw.init = &(struct clk_init_data){ \ 55 .ops = &clk_smd_rpm_ops, \ 56 .name = #_active, \ 57 .parent_names = (const char *[]){ "xo_board" }, \ 58 .num_parents = 1, \ 59 }, \ 60 } 61 62 #define __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, type, r_id, \ 63 stat_id, r, key) \ 64 static struct clk_smd_rpm _platform##_##_active; \ 65 static struct clk_smd_rpm _platform##_##_name = { \ 66 .rpm_res_type = (type), \ 67 .rpm_clk_id = (r_id), \ 68 .rpm_status_id = (stat_id), \ 69 .rpm_key = (key), \ 70 .branch = true, \ 71 .peer = &_platform##_##_active, \ 72 .rate = (r), \ 73 .hw.init = &(struct clk_init_data){ \ 74 .ops = &clk_smd_rpm_branch_ops, \ 75 .name = #_name, \ 76 .parent_names = (const char *[]){ "xo_board" }, \ 77 .num_parents = 1, \ 78 }, \ 79 }; \ 80 static struct clk_smd_rpm _platform##_##_active = { \ 81 .rpm_res_type = (type), \ 82 .rpm_clk_id = (r_id), \ 83 .rpm_status_id = (stat_id), \ 84 .active_only = true, \ 85 .rpm_key = (key), \ 86 .branch = true, \ 87 .peer = &_platform##_##_name, \ 88 .rate = (r), \ 89 .hw.init = &(struct clk_init_data){ \ 90 .ops = &clk_smd_rpm_branch_ops, \ 91 .name = #_active, \ 92 .parent_names = (const char *[]){ "xo_board" }, \ 93 .num_parents = 1, \ 94 }, \ 95 } 96 97 #define DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id) \ 98 __DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id, \ 99 0, QCOM_RPM_SMD_KEY_RATE) 100 101 #define DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, type, r_id, r) \ 102 __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, type, \ 103 r_id, 0, r, QCOM_RPM_SMD_KEY_ENABLE) 104 105 #define DEFINE_CLK_SMD_RPM_QDSS(_platform, _name, _active, type, r_id) \ 106 __DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id, \ 107 0, QCOM_RPM_SMD_KEY_STATE) 108 109 #define DEFINE_CLK_SMD_RPM_XO_BUFFER(_platform, _name, _active, r_id) \ 110 __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, \ 111 QCOM_SMD_RPM_CLK_BUF_A, r_id, 0, 1000, \ 112 QCOM_RPM_KEY_SOFTWARE_ENABLE) 113 114 #define DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(_platform, _name, _active, r_id) \ 115 __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, \ 116 QCOM_SMD_RPM_CLK_BUF_A, r_id, 0, 1000, \ 117 QCOM_RPM_KEY_PIN_CTRL_CLK_BUFFER_ENABLE_KEY) 118 119 #define to_clk_smd_rpm(_hw) container_of(_hw, struct clk_smd_rpm, hw) 120 121 struct clk_smd_rpm { 122 const int rpm_res_type; 123 const int rpm_key; 124 const int rpm_clk_id; 125 const int rpm_status_id; 126 const bool active_only; 127 bool enabled; 128 bool branch; 129 struct clk_smd_rpm *peer; 130 struct clk_hw hw; 131 unsigned long rate; 132 struct qcom_smd_rpm *rpm; 133 }; 134 135 struct clk_smd_rpm_req { 136 __le32 key; 137 __le32 nbytes; 138 __le32 value; 139 }; 140 141 struct rpm_cc { 142 struct qcom_rpm *rpm; 143 struct clk_smd_rpm **clks; 144 size_t num_clks; 145 }; 146 147 struct rpm_smd_clk_desc { 148 struct clk_smd_rpm **clks; 149 size_t num_clks; 150 }; 151 152 static DEFINE_MUTEX(rpm_smd_clk_lock); 153 154 static int clk_smd_rpm_handoff(struct clk_smd_rpm *r) 155 { 156 int ret; 157 struct clk_smd_rpm_req req = { 158 .key = cpu_to_le32(r->rpm_key), 159 .nbytes = cpu_to_le32(sizeof(u32)), 160 .value = cpu_to_le32(r->branch ? 1 : INT_MAX), 161 }; 162 163 ret = qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_ACTIVE_STATE, 164 r->rpm_res_type, r->rpm_clk_id, &req, 165 sizeof(req)); 166 if (ret) 167 return ret; 168 ret = qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_SLEEP_STATE, 169 r->rpm_res_type, r->rpm_clk_id, &req, 170 sizeof(req)); 171 if (ret) 172 return ret; 173 174 return 0; 175 } 176 177 static int clk_smd_rpm_set_rate_active(struct clk_smd_rpm *r, 178 unsigned long rate) 179 { 180 struct clk_smd_rpm_req req = { 181 .key = cpu_to_le32(r->rpm_key), 182 .nbytes = cpu_to_le32(sizeof(u32)), 183 .value = cpu_to_le32(DIV_ROUND_UP(rate, 1000)), /* to kHz */ 184 }; 185 186 return qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_ACTIVE_STATE, 187 r->rpm_res_type, r->rpm_clk_id, &req, 188 sizeof(req)); 189 } 190 191 static int clk_smd_rpm_set_rate_sleep(struct clk_smd_rpm *r, 192 unsigned long rate) 193 { 194 struct clk_smd_rpm_req req = { 195 .key = cpu_to_le32(r->rpm_key), 196 .nbytes = cpu_to_le32(sizeof(u32)), 197 .value = cpu_to_le32(DIV_ROUND_UP(rate, 1000)), /* to kHz */ 198 }; 199 200 return qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_SLEEP_STATE, 201 r->rpm_res_type, r->rpm_clk_id, &req, 202 sizeof(req)); 203 } 204 205 static void to_active_sleep(struct clk_smd_rpm *r, unsigned long rate, 206 unsigned long *active, unsigned long *sleep) 207 { 208 *active = rate; 209 210 /* 211 * Active-only clocks don't care what the rate is during sleep. So, 212 * they vote for zero. 213 */ 214 if (r->active_only) 215 *sleep = 0; 216 else 217 *sleep = *active; 218 } 219 220 static int clk_smd_rpm_prepare(struct clk_hw *hw) 221 { 222 struct clk_smd_rpm *r = to_clk_smd_rpm(hw); 223 struct clk_smd_rpm *peer = r->peer; 224 unsigned long this_rate = 0, this_sleep_rate = 0; 225 unsigned long peer_rate = 0, peer_sleep_rate = 0; 226 unsigned long active_rate, sleep_rate; 227 int ret = 0; 228 229 mutex_lock(&rpm_smd_clk_lock); 230 231 /* Don't send requests to the RPM if the rate has not been set. */ 232 if (!r->rate) 233 goto out; 234 235 to_active_sleep(r, r->rate, &this_rate, &this_sleep_rate); 236 237 /* Take peer clock's rate into account only if it's enabled. */ 238 if (peer->enabled) 239 to_active_sleep(peer, peer->rate, 240 &peer_rate, &peer_sleep_rate); 241 242 active_rate = max(this_rate, peer_rate); 243 244 if (r->branch) 245 active_rate = !!active_rate; 246 247 ret = clk_smd_rpm_set_rate_active(r, active_rate); 248 if (ret) 249 goto out; 250 251 sleep_rate = max(this_sleep_rate, peer_sleep_rate); 252 if (r->branch) 253 sleep_rate = !!sleep_rate; 254 255 ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate); 256 if (ret) 257 /* Undo the active set vote and restore it */ 258 ret = clk_smd_rpm_set_rate_active(r, peer_rate); 259 260 out: 261 if (!ret) 262 r->enabled = true; 263 264 mutex_unlock(&rpm_smd_clk_lock); 265 266 return ret; 267 } 268 269 static void clk_smd_rpm_unprepare(struct clk_hw *hw) 270 { 271 struct clk_smd_rpm *r = to_clk_smd_rpm(hw); 272 struct clk_smd_rpm *peer = r->peer; 273 unsigned long peer_rate = 0, peer_sleep_rate = 0; 274 unsigned long active_rate, sleep_rate; 275 int ret; 276 277 mutex_lock(&rpm_smd_clk_lock); 278 279 if (!r->rate) 280 goto out; 281 282 /* Take peer clock's rate into account only if it's enabled. */ 283 if (peer->enabled) 284 to_active_sleep(peer, peer->rate, &peer_rate, 285 &peer_sleep_rate); 286 287 active_rate = r->branch ? !!peer_rate : peer_rate; 288 ret = clk_smd_rpm_set_rate_active(r, active_rate); 289 if (ret) 290 goto out; 291 292 sleep_rate = r->branch ? !!peer_sleep_rate : peer_sleep_rate; 293 ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate); 294 if (ret) 295 goto out; 296 297 r->enabled = false; 298 299 out: 300 mutex_unlock(&rpm_smd_clk_lock); 301 } 302 303 static int clk_smd_rpm_set_rate(struct clk_hw *hw, unsigned long rate, 304 unsigned long parent_rate) 305 { 306 struct clk_smd_rpm *r = to_clk_smd_rpm(hw); 307 struct clk_smd_rpm *peer = r->peer; 308 unsigned long active_rate, sleep_rate; 309 unsigned long this_rate = 0, this_sleep_rate = 0; 310 unsigned long peer_rate = 0, peer_sleep_rate = 0; 311 int ret = 0; 312 313 mutex_lock(&rpm_smd_clk_lock); 314 315 if (!r->enabled) 316 goto out; 317 318 to_active_sleep(r, rate, &this_rate, &this_sleep_rate); 319 320 /* Take peer clock's rate into account only if it's enabled. */ 321 if (peer->enabled) 322 to_active_sleep(peer, peer->rate, 323 &peer_rate, &peer_sleep_rate); 324 325 active_rate = max(this_rate, peer_rate); 326 ret = clk_smd_rpm_set_rate_active(r, active_rate); 327 if (ret) 328 goto out; 329 330 sleep_rate = max(this_sleep_rate, peer_sleep_rate); 331 ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate); 332 if (ret) 333 goto out; 334 335 r->rate = rate; 336 337 out: 338 mutex_unlock(&rpm_smd_clk_lock); 339 340 return ret; 341 } 342 343 static long clk_smd_rpm_round_rate(struct clk_hw *hw, unsigned long rate, 344 unsigned long *parent_rate) 345 { 346 /* 347 * RPM handles rate rounding and we don't have a way to 348 * know what the rate will be, so just return whatever 349 * rate is requested. 350 */ 351 return rate; 352 } 353 354 static unsigned long clk_smd_rpm_recalc_rate(struct clk_hw *hw, 355 unsigned long parent_rate) 356 { 357 struct clk_smd_rpm *r = to_clk_smd_rpm(hw); 358 359 /* 360 * RPM handles rate rounding and we don't have a way to 361 * know what the rate will be, so just return whatever 362 * rate was set. 363 */ 364 return r->rate; 365 } 366 367 static int clk_smd_rpm_enable_scaling(struct qcom_smd_rpm *rpm) 368 { 369 int ret; 370 struct clk_smd_rpm_req req = { 371 .key = cpu_to_le32(QCOM_RPM_SMD_KEY_ENABLE), 372 .nbytes = cpu_to_le32(sizeof(u32)), 373 .value = cpu_to_le32(1), 374 }; 375 376 ret = qcom_rpm_smd_write(rpm, QCOM_SMD_RPM_SLEEP_STATE, 377 QCOM_SMD_RPM_MISC_CLK, 378 QCOM_RPM_SCALING_ENABLE_ID, &req, sizeof(req)); 379 if (ret) { 380 pr_err("RPM clock scaling (sleep set) not enabled!\n"); 381 return ret; 382 } 383 384 ret = qcom_rpm_smd_write(rpm, QCOM_SMD_RPM_ACTIVE_STATE, 385 QCOM_SMD_RPM_MISC_CLK, 386 QCOM_RPM_SCALING_ENABLE_ID, &req, sizeof(req)); 387 if (ret) { 388 pr_err("RPM clock scaling (active set) not enabled!\n"); 389 return ret; 390 } 391 392 pr_debug("%s: RPM clock scaling is enabled\n", __func__); 393 return 0; 394 } 395 396 static const struct clk_ops clk_smd_rpm_ops = { 397 .prepare = clk_smd_rpm_prepare, 398 .unprepare = clk_smd_rpm_unprepare, 399 .set_rate = clk_smd_rpm_set_rate, 400 .round_rate = clk_smd_rpm_round_rate, 401 .recalc_rate = clk_smd_rpm_recalc_rate, 402 }; 403 404 static const struct clk_ops clk_smd_rpm_branch_ops = { 405 .prepare = clk_smd_rpm_prepare, 406 .unprepare = clk_smd_rpm_unprepare, 407 }; 408 409 /* msm8916 */ 410 DEFINE_CLK_SMD_RPM(msm8916, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0); 411 DEFINE_CLK_SMD_RPM(msm8916, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1); 412 DEFINE_CLK_SMD_RPM(msm8916, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0); 413 DEFINE_CLK_SMD_RPM_QDSS(msm8916, qdss_clk, qdss_a_clk, QCOM_SMD_RPM_MISC_CLK, 1); 414 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, bb_clk1, bb_clk1_a, 1); 415 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, bb_clk2, bb_clk2_a, 2); 416 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, rf_clk1, rf_clk1_a, 4); 417 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, rf_clk2, rf_clk2_a, 5); 418 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, bb_clk1_pin, bb_clk1_a_pin, 1); 419 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, bb_clk2_pin, bb_clk2_a_pin, 2); 420 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, rf_clk1_pin, rf_clk1_a_pin, 4); 421 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, rf_clk2_pin, rf_clk2_a_pin, 5); 422 423 static struct clk_smd_rpm *msm8916_clks[] = { 424 [RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk, 425 [RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk, 426 [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk, 427 [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk, 428 [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, 429 [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, 430 [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk, 431 [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk, 432 [RPM_SMD_BB_CLK1] = &msm8916_bb_clk1, 433 [RPM_SMD_BB_CLK1_A] = &msm8916_bb_clk1_a, 434 [RPM_SMD_BB_CLK2] = &msm8916_bb_clk2, 435 [RPM_SMD_BB_CLK2_A] = &msm8916_bb_clk2_a, 436 [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1, 437 [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a, 438 [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2, 439 [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a, 440 [RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin, 441 [RPM_SMD_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin, 442 [RPM_SMD_BB_CLK2_PIN] = &msm8916_bb_clk2_pin, 443 [RPM_SMD_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin, 444 [RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin, 445 [RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin, 446 [RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin, 447 [RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin, 448 }; 449 450 static const struct rpm_smd_clk_desc rpm_clk_msm8916 = { 451 .clks = msm8916_clks, 452 .num_clks = ARRAY_SIZE(msm8916_clks), 453 }; 454 455 /* msm8936 */ 456 DEFINE_CLK_SMD_RPM(msm8936, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0); 457 DEFINE_CLK_SMD_RPM(msm8936, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1); 458 DEFINE_CLK_SMD_RPM(msm8936, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0); 459 DEFINE_CLK_SMD_RPM(msm8936, sysmmnoc_clk, sysmmnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2); 460 DEFINE_CLK_SMD_RPM_QDSS(msm8936, qdss_clk, qdss_a_clk, QCOM_SMD_RPM_MISC_CLK, 1); 461 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8936, bb_clk1, bb_clk1_a, 1); 462 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8936, bb_clk2, bb_clk2_a, 2); 463 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8936, rf_clk1, rf_clk1_a, 4); 464 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8936, rf_clk2, rf_clk2_a, 5); 465 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8936, bb_clk1_pin, bb_clk1_a_pin, 1); 466 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8936, bb_clk2_pin, bb_clk2_a_pin, 2); 467 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8936, rf_clk1_pin, rf_clk1_a_pin, 4); 468 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8936, rf_clk2_pin, rf_clk2_a_pin, 5); 469 470 static struct clk_smd_rpm *msm8936_clks[] = { 471 [RPM_SMD_PCNOC_CLK] = &msm8936_pcnoc_clk, 472 [RPM_SMD_PCNOC_A_CLK] = &msm8936_pcnoc_a_clk, 473 [RPM_SMD_SNOC_CLK] = &msm8936_snoc_clk, 474 [RPM_SMD_SNOC_A_CLK] = &msm8936_snoc_a_clk, 475 [RPM_SMD_BIMC_CLK] = &msm8936_bimc_clk, 476 [RPM_SMD_BIMC_A_CLK] = &msm8936_bimc_a_clk, 477 [RPM_SMD_SYSMMNOC_CLK] = &msm8936_sysmmnoc_clk, 478 [RPM_SMD_SYSMMNOC_A_CLK] = &msm8936_sysmmnoc_a_clk, 479 [RPM_SMD_QDSS_CLK] = &msm8936_qdss_clk, 480 [RPM_SMD_QDSS_A_CLK] = &msm8936_qdss_a_clk, 481 [RPM_SMD_BB_CLK1] = &msm8936_bb_clk1, 482 [RPM_SMD_BB_CLK1_A] = &msm8936_bb_clk1_a, 483 [RPM_SMD_BB_CLK2] = &msm8936_bb_clk2, 484 [RPM_SMD_BB_CLK2_A] = &msm8936_bb_clk2_a, 485 [RPM_SMD_RF_CLK1] = &msm8936_rf_clk1, 486 [RPM_SMD_RF_CLK1_A] = &msm8936_rf_clk1_a, 487 [RPM_SMD_RF_CLK2] = &msm8936_rf_clk2, 488 [RPM_SMD_RF_CLK2_A] = &msm8936_rf_clk2_a, 489 [RPM_SMD_BB_CLK1_PIN] = &msm8936_bb_clk1_pin, 490 [RPM_SMD_BB_CLK1_A_PIN] = &msm8936_bb_clk1_a_pin, 491 [RPM_SMD_BB_CLK2_PIN] = &msm8936_bb_clk2_pin, 492 [RPM_SMD_BB_CLK2_A_PIN] = &msm8936_bb_clk2_a_pin, 493 [RPM_SMD_RF_CLK1_PIN] = &msm8936_rf_clk1_pin, 494 [RPM_SMD_RF_CLK1_A_PIN] = &msm8936_rf_clk1_a_pin, 495 [RPM_SMD_RF_CLK2_PIN] = &msm8936_rf_clk2_pin, 496 [RPM_SMD_RF_CLK2_A_PIN] = &msm8936_rf_clk2_a_pin, 497 }; 498 499 static const struct rpm_smd_clk_desc rpm_clk_msm8936 = { 500 .clks = msm8936_clks, 501 .num_clks = ARRAY_SIZE(msm8936_clks), 502 }; 503 504 /* msm8974 */ 505 DEFINE_CLK_SMD_RPM(msm8974, pnoc_clk, pnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0); 506 DEFINE_CLK_SMD_RPM(msm8974, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1); 507 DEFINE_CLK_SMD_RPM(msm8974, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2); 508 DEFINE_CLK_SMD_RPM(msm8974, mmssnoc_ahb_clk, mmssnoc_ahb_a_clk, QCOM_SMD_RPM_BUS_CLK, 3); 509 DEFINE_CLK_SMD_RPM(msm8974, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0); 510 DEFINE_CLK_SMD_RPM(msm8974, gfx3d_clk_src, gfx3d_a_clk_src, QCOM_SMD_RPM_MEM_CLK, 1); 511 DEFINE_CLK_SMD_RPM(msm8974, ocmemgx_clk, ocmemgx_a_clk, QCOM_SMD_RPM_MEM_CLK, 2); 512 DEFINE_CLK_SMD_RPM_QDSS(msm8974, qdss_clk, qdss_a_clk, QCOM_SMD_RPM_MISC_CLK, 1); 513 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_d0, cxo_d0_a, 1); 514 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_d1, cxo_d1_a, 2); 515 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_a0, cxo_a0_a, 4); 516 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_a1, cxo_a1_a, 5); 517 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_a2, cxo_a2_a, 6); 518 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, diff_clk, diff_a_clk, 7); 519 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, div_clk1, div_a_clk1, 11); 520 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, div_clk2, div_a_clk2, 12); 521 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_d0_pin, cxo_d0_a_pin, 1); 522 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_d1_pin, cxo_d1_a_pin, 2); 523 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a0_pin, cxo_a0_a_pin, 4); 524 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a1_pin, cxo_a1_a_pin, 5); 525 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a2_pin, cxo_a2_a_pin, 6); 526 527 static struct clk_smd_rpm *msm8974_clks[] = { 528 [RPM_SMD_PNOC_CLK] = &msm8974_pnoc_clk, 529 [RPM_SMD_PNOC_A_CLK] = &msm8974_pnoc_a_clk, 530 [RPM_SMD_SNOC_CLK] = &msm8974_snoc_clk, 531 [RPM_SMD_SNOC_A_CLK] = &msm8974_snoc_a_clk, 532 [RPM_SMD_CNOC_CLK] = &msm8974_cnoc_clk, 533 [RPM_SMD_CNOC_A_CLK] = &msm8974_cnoc_a_clk, 534 [RPM_SMD_MMSSNOC_AHB_CLK] = &msm8974_mmssnoc_ahb_clk, 535 [RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8974_mmssnoc_ahb_a_clk, 536 [RPM_SMD_BIMC_CLK] = &msm8974_bimc_clk, 537 [RPM_SMD_GFX3D_CLK_SRC] = &msm8974_gfx3d_clk_src, 538 [RPM_SMD_GFX3D_A_CLK_SRC] = &msm8974_gfx3d_a_clk_src, 539 [RPM_SMD_BIMC_A_CLK] = &msm8974_bimc_a_clk, 540 [RPM_SMD_OCMEMGX_CLK] = &msm8974_ocmemgx_clk, 541 [RPM_SMD_OCMEMGX_A_CLK] = &msm8974_ocmemgx_a_clk, 542 [RPM_SMD_QDSS_CLK] = &msm8974_qdss_clk, 543 [RPM_SMD_QDSS_A_CLK] = &msm8974_qdss_a_clk, 544 [RPM_SMD_CXO_D0] = &msm8974_cxo_d0, 545 [RPM_SMD_CXO_D0_A] = &msm8974_cxo_d0_a, 546 [RPM_SMD_CXO_D1] = &msm8974_cxo_d1, 547 [RPM_SMD_CXO_D1_A] = &msm8974_cxo_d1_a, 548 [RPM_SMD_CXO_A0] = &msm8974_cxo_a0, 549 [RPM_SMD_CXO_A0_A] = &msm8974_cxo_a0_a, 550 [RPM_SMD_CXO_A1] = &msm8974_cxo_a1, 551 [RPM_SMD_CXO_A1_A] = &msm8974_cxo_a1_a, 552 [RPM_SMD_CXO_A2] = &msm8974_cxo_a2, 553 [RPM_SMD_CXO_A2_A] = &msm8974_cxo_a2_a, 554 [RPM_SMD_DIFF_CLK] = &msm8974_diff_clk, 555 [RPM_SMD_DIFF_A_CLK] = &msm8974_diff_a_clk, 556 [RPM_SMD_DIV_CLK1] = &msm8974_div_clk1, 557 [RPM_SMD_DIV_A_CLK1] = &msm8974_div_a_clk1, 558 [RPM_SMD_DIV_CLK2] = &msm8974_div_clk2, 559 [RPM_SMD_DIV_A_CLK2] = &msm8974_div_a_clk2, 560 [RPM_SMD_CXO_D0_PIN] = &msm8974_cxo_d0_pin, 561 [RPM_SMD_CXO_D0_A_PIN] = &msm8974_cxo_d0_a_pin, 562 [RPM_SMD_CXO_D1_PIN] = &msm8974_cxo_d1_pin, 563 [RPM_SMD_CXO_D1_A_PIN] = &msm8974_cxo_d1_a_pin, 564 [RPM_SMD_CXO_A0_PIN] = &msm8974_cxo_a0_pin, 565 [RPM_SMD_CXO_A0_A_PIN] = &msm8974_cxo_a0_a_pin, 566 [RPM_SMD_CXO_A1_PIN] = &msm8974_cxo_a1_pin, 567 [RPM_SMD_CXO_A1_A_PIN] = &msm8974_cxo_a1_a_pin, 568 [RPM_SMD_CXO_A2_PIN] = &msm8974_cxo_a2_pin, 569 [RPM_SMD_CXO_A2_A_PIN] = &msm8974_cxo_a2_a_pin, 570 }; 571 572 static const struct rpm_smd_clk_desc rpm_clk_msm8974 = { 573 .clks = msm8974_clks, 574 .num_clks = ARRAY_SIZE(msm8974_clks), 575 }; 576 577 578 /* msm8976 */ 579 DEFINE_CLK_SMD_RPM(msm8976, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0); 580 DEFINE_CLK_SMD_RPM(msm8976, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1); 581 DEFINE_CLK_SMD_RPM(msm8976, mmssnoc_ahb_clk, mmssnoc_ahb_a_clk, 582 QCOM_SMD_RPM_BUS_CLK, 2); 583 DEFINE_CLK_SMD_RPM(msm8976, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0); 584 DEFINE_CLK_SMD_RPM(msm8976, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0); 585 DEFINE_CLK_SMD_RPM_QDSS(msm8976, qdss_clk, qdss_a_clk, 586 QCOM_SMD_RPM_MISC_CLK, 1); 587 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8976, bb_clk1, bb_clk1_a, 1); 588 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8976, bb_clk2, bb_clk2_a, 2); 589 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8976, rf_clk2, rf_clk2_a, 5); 590 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8976, div_clk2, div_clk2_a, 12); 591 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8976, bb_clk1_pin, bb_clk1_a_pin, 1); 592 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8976, bb_clk2_pin, bb_clk2_a_pin, 2); 593 594 static struct clk_smd_rpm *msm8976_clks[] = { 595 [RPM_SMD_PCNOC_CLK] = &msm8976_pcnoc_clk, 596 [RPM_SMD_PCNOC_A_CLK] = &msm8976_pcnoc_a_clk, 597 [RPM_SMD_SNOC_CLK] = &msm8976_snoc_clk, 598 [RPM_SMD_SNOC_A_CLK] = &msm8976_snoc_a_clk, 599 [RPM_SMD_BIMC_CLK] = &msm8976_bimc_clk, 600 [RPM_SMD_BIMC_A_CLK] = &msm8976_bimc_a_clk, 601 [RPM_SMD_QDSS_CLK] = &msm8976_qdss_clk, 602 [RPM_SMD_QDSS_A_CLK] = &msm8976_qdss_a_clk, 603 [RPM_SMD_BB_CLK1] = &msm8976_bb_clk1, 604 [RPM_SMD_BB_CLK1_A] = &msm8976_bb_clk1_a, 605 [RPM_SMD_BB_CLK2] = &msm8976_bb_clk2, 606 [RPM_SMD_BB_CLK2_A] = &msm8976_bb_clk2_a, 607 [RPM_SMD_RF_CLK2] = &msm8976_rf_clk2, 608 [RPM_SMD_RF_CLK2_A] = &msm8976_rf_clk2_a, 609 [RPM_SMD_BB_CLK1_PIN] = &msm8976_bb_clk1_pin, 610 [RPM_SMD_BB_CLK1_A_PIN] = &msm8976_bb_clk1_a_pin, 611 [RPM_SMD_BB_CLK2_PIN] = &msm8976_bb_clk2_pin, 612 [RPM_SMD_BB_CLK2_A_PIN] = &msm8976_bb_clk2_a_pin, 613 [RPM_SMD_MMSSNOC_AHB_CLK] = &msm8976_mmssnoc_ahb_clk, 614 [RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8976_mmssnoc_ahb_a_clk, 615 [RPM_SMD_DIV_CLK2] = &msm8976_div_clk2, 616 [RPM_SMD_DIV_A_CLK2] = &msm8976_div_clk2_a, 617 [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk, 618 [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk, 619 }; 620 621 static const struct rpm_smd_clk_desc rpm_clk_msm8976 = { 622 .clks = msm8976_clks, 623 .num_clks = ARRAY_SIZE(msm8976_clks), 624 }; 625 626 /* msm8992 */ 627 DEFINE_CLK_SMD_RPM(msm8992, pnoc_clk, pnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0); 628 DEFINE_CLK_SMD_RPM(msm8992, ocmemgx_clk, ocmemgx_a_clk, QCOM_SMD_RPM_MEM_CLK, 2); 629 DEFINE_CLK_SMD_RPM(msm8992, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0); 630 DEFINE_CLK_SMD_RPM(msm8992, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2); 631 DEFINE_CLK_SMD_RPM(msm8992, gfx3d_clk_src, gfx3d_a_clk_src, QCOM_SMD_RPM_MEM_CLK, 1); 632 DEFINE_CLK_SMD_RPM(msm8992, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1); 633 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, bb_clk1, bb_clk1_a, 1); 634 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8992, bb_clk1_pin, bb_clk1_a_pin, 1); 635 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, bb_clk2, bb_clk2_a, 2); 636 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8992, bb_clk2_pin, bb_clk2_a_pin, 2); 637 638 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, div_clk1, div_clk1_a, 11); 639 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, div_clk2, div_clk2_a, 12); 640 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, div_clk3, div_clk3_a, 13); 641 DEFINE_CLK_SMD_RPM(msm8992, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0); 642 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, ln_bb_clk, ln_bb_a_clk, 8); 643 DEFINE_CLK_SMD_RPM(msm8992, mmssnoc_ahb_clk, mmssnoc_ahb_a_clk, 644 QCOM_SMD_RPM_BUS_CLK, 3); 645 DEFINE_CLK_SMD_RPM_QDSS(msm8992, qdss_clk, qdss_a_clk, 646 QCOM_SMD_RPM_MISC_CLK, 1); 647 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, rf_clk1, rf_clk1_a, 4); 648 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, rf_clk2, rf_clk2_a, 5); 649 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8992, rf_clk1_pin, rf_clk1_a_pin, 4); 650 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8992, rf_clk2_pin, rf_clk2_a_pin, 5); 651 652 DEFINE_CLK_SMD_RPM(msm8992, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0); 653 DEFINE_CLK_SMD_RPM(msm8992, ce2_clk, ce2_a_clk, QCOM_SMD_RPM_CE_CLK, 1); 654 655 static struct clk_smd_rpm *msm8992_clks[] = { 656 [RPM_SMD_PNOC_CLK] = &msm8992_pnoc_clk, 657 [RPM_SMD_PNOC_A_CLK] = &msm8992_pnoc_a_clk, 658 [RPM_SMD_OCMEMGX_CLK] = &msm8992_ocmemgx_clk, 659 [RPM_SMD_OCMEMGX_A_CLK] = &msm8992_ocmemgx_a_clk, 660 [RPM_SMD_BIMC_CLK] = &msm8992_bimc_clk, 661 [RPM_SMD_BIMC_A_CLK] = &msm8992_bimc_a_clk, 662 [RPM_SMD_CNOC_CLK] = &msm8992_cnoc_clk, 663 [RPM_SMD_CNOC_A_CLK] = &msm8992_cnoc_a_clk, 664 [RPM_SMD_GFX3D_CLK_SRC] = &msm8992_gfx3d_clk_src, 665 [RPM_SMD_GFX3D_A_CLK_SRC] = &msm8992_gfx3d_a_clk_src, 666 [RPM_SMD_SNOC_CLK] = &msm8992_snoc_clk, 667 [RPM_SMD_SNOC_A_CLK] = &msm8992_snoc_a_clk, 668 [RPM_SMD_BB_CLK1] = &msm8992_bb_clk1, 669 [RPM_SMD_BB_CLK1_A] = &msm8992_bb_clk1_a, 670 [RPM_SMD_BB_CLK1_PIN] = &msm8992_bb_clk1_pin, 671 [RPM_SMD_BB_CLK1_A_PIN] = &msm8992_bb_clk1_a_pin, 672 [RPM_SMD_BB_CLK2] = &msm8992_bb_clk2, 673 [RPM_SMD_BB_CLK2_A] = &msm8992_bb_clk2_a, 674 [RPM_SMD_BB_CLK2_PIN] = &msm8992_bb_clk2_pin, 675 [RPM_SMD_BB_CLK2_A_PIN] = &msm8992_bb_clk2_a_pin, 676 [RPM_SMD_DIV_CLK1] = &msm8992_div_clk1, 677 [RPM_SMD_DIV_A_CLK1] = &msm8992_div_clk1_a, 678 [RPM_SMD_DIV_CLK2] = &msm8992_div_clk2, 679 [RPM_SMD_DIV_A_CLK2] = &msm8992_div_clk2_a, 680 [RPM_SMD_DIV_CLK3] = &msm8992_div_clk3, 681 [RPM_SMD_DIV_A_CLK3] = &msm8992_div_clk3_a, 682 [RPM_SMD_IPA_CLK] = &msm8992_ipa_clk, 683 [RPM_SMD_IPA_A_CLK] = &msm8992_ipa_a_clk, 684 [RPM_SMD_LN_BB_CLK] = &msm8992_ln_bb_clk, 685 [RPM_SMD_LN_BB_A_CLK] = &msm8992_ln_bb_a_clk, 686 [RPM_SMD_MMSSNOC_AHB_CLK] = &msm8992_mmssnoc_ahb_clk, 687 [RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8992_mmssnoc_ahb_a_clk, 688 [RPM_SMD_QDSS_CLK] = &msm8992_qdss_clk, 689 [RPM_SMD_QDSS_A_CLK] = &msm8992_qdss_a_clk, 690 [RPM_SMD_RF_CLK1] = &msm8992_rf_clk1, 691 [RPM_SMD_RF_CLK1_A] = &msm8992_rf_clk1_a, 692 [RPM_SMD_RF_CLK2] = &msm8992_rf_clk2, 693 [RPM_SMD_RF_CLK2_A] = &msm8992_rf_clk2_a, 694 [RPM_SMD_RF_CLK1_PIN] = &msm8992_rf_clk1_pin, 695 [RPM_SMD_RF_CLK1_A_PIN] = &msm8992_rf_clk1_a_pin, 696 [RPM_SMD_RF_CLK2_PIN] = &msm8992_rf_clk2_pin, 697 [RPM_SMD_RF_CLK2_A_PIN] = &msm8992_rf_clk2_a_pin, 698 [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk, 699 [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk, 700 [RPM_SMD_CE2_CLK] = &msm8992_ce2_clk, 701 [RPM_SMD_CE2_A_CLK] = &msm8992_ce2_a_clk, 702 }; 703 704 static const struct rpm_smd_clk_desc rpm_clk_msm8992 = { 705 .clks = msm8992_clks, 706 .num_clks = ARRAY_SIZE(msm8992_clks), 707 }; 708 709 /* msm8994 */ 710 DEFINE_CLK_SMD_RPM(msm8994, pnoc_clk, pnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0); 711 DEFINE_CLK_SMD_RPM(msm8994, ocmemgx_clk, ocmemgx_a_clk, QCOM_SMD_RPM_MEM_CLK, 2); 712 DEFINE_CLK_SMD_RPM(msm8994, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0); 713 DEFINE_CLK_SMD_RPM(msm8994, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2); 714 DEFINE_CLK_SMD_RPM(msm8994, gfx3d_clk_src, gfx3d_a_clk_src, QCOM_SMD_RPM_MEM_CLK, 1); 715 DEFINE_CLK_SMD_RPM(msm8994, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1); 716 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8994, bb_clk1, bb_clk1_a, 1); 717 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8994, bb_clk1_pin, bb_clk1_a_pin, 1); 718 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8994, bb_clk2, bb_clk2_a, 2); 719 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8994, bb_clk2_pin, bb_clk2_a_pin, 2); 720 721 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8994, div_clk1, div_clk1_a, 11); 722 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8994, div_clk2, div_clk2_a, 12); 723 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8994, div_clk3, div_clk3_a, 13); 724 DEFINE_CLK_SMD_RPM(msm8994, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0); 725 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8994, ln_bb_clk, ln_bb_a_clk, 8); 726 DEFINE_CLK_SMD_RPM(msm8994, mmssnoc_ahb_clk, mmssnoc_ahb_a_clk, 727 QCOM_SMD_RPM_BUS_CLK, 3); 728 DEFINE_CLK_SMD_RPM_QDSS(msm8994, qdss_clk, qdss_a_clk, 729 QCOM_SMD_RPM_MISC_CLK, 1); 730 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8994, rf_clk1, rf_clk1_a, 4); 731 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8994, rf_clk2, rf_clk2_a, 5); 732 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8994, rf_clk1_pin, rf_clk1_a_pin, 4); 733 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8994, rf_clk2_pin, rf_clk2_a_pin, 5); 734 735 DEFINE_CLK_SMD_RPM(msm8994, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0); 736 DEFINE_CLK_SMD_RPM(msm8994, ce2_clk, ce2_a_clk, QCOM_SMD_RPM_CE_CLK, 1); 737 DEFINE_CLK_SMD_RPM(msm8994, ce3_clk, ce3_a_clk, QCOM_SMD_RPM_CE_CLK, 2); 738 739 static struct clk_smd_rpm *msm8994_clks[] = { 740 [RPM_SMD_PNOC_CLK] = &msm8994_pnoc_clk, 741 [RPM_SMD_PNOC_A_CLK] = &msm8994_pnoc_a_clk, 742 [RPM_SMD_OCMEMGX_CLK] = &msm8994_ocmemgx_clk, 743 [RPM_SMD_OCMEMGX_A_CLK] = &msm8994_ocmemgx_a_clk, 744 [RPM_SMD_BIMC_CLK] = &msm8994_bimc_clk, 745 [RPM_SMD_BIMC_A_CLK] = &msm8994_bimc_a_clk, 746 [RPM_SMD_CNOC_CLK] = &msm8994_cnoc_clk, 747 [RPM_SMD_CNOC_A_CLK] = &msm8994_cnoc_a_clk, 748 [RPM_SMD_GFX3D_CLK_SRC] = &msm8994_gfx3d_clk_src, 749 [RPM_SMD_GFX3D_A_CLK_SRC] = &msm8994_gfx3d_a_clk_src, 750 [RPM_SMD_SNOC_CLK] = &msm8994_snoc_clk, 751 [RPM_SMD_SNOC_A_CLK] = &msm8994_snoc_a_clk, 752 [RPM_SMD_BB_CLK1] = &msm8994_bb_clk1, 753 [RPM_SMD_BB_CLK1_A] = &msm8994_bb_clk1_a, 754 [RPM_SMD_BB_CLK1_PIN] = &msm8994_bb_clk1_pin, 755 [RPM_SMD_BB_CLK1_A_PIN] = &msm8994_bb_clk1_a_pin, 756 [RPM_SMD_BB_CLK2] = &msm8994_bb_clk2, 757 [RPM_SMD_BB_CLK2_A] = &msm8994_bb_clk2_a, 758 [RPM_SMD_BB_CLK2_PIN] = &msm8994_bb_clk2_pin, 759 [RPM_SMD_BB_CLK2_A_PIN] = &msm8994_bb_clk2_a_pin, 760 [RPM_SMD_DIV_CLK1] = &msm8994_div_clk1, 761 [RPM_SMD_DIV_A_CLK1] = &msm8994_div_clk1_a, 762 [RPM_SMD_DIV_CLK2] = &msm8994_div_clk2, 763 [RPM_SMD_DIV_A_CLK2] = &msm8994_div_clk2_a, 764 [RPM_SMD_DIV_CLK3] = &msm8994_div_clk3, 765 [RPM_SMD_DIV_A_CLK3] = &msm8994_div_clk3_a, 766 [RPM_SMD_IPA_CLK] = &msm8994_ipa_clk, 767 [RPM_SMD_IPA_A_CLK] = &msm8994_ipa_a_clk, 768 [RPM_SMD_LN_BB_CLK] = &msm8994_ln_bb_clk, 769 [RPM_SMD_LN_BB_A_CLK] = &msm8994_ln_bb_a_clk, 770 [RPM_SMD_MMSSNOC_AHB_CLK] = &msm8994_mmssnoc_ahb_clk, 771 [RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8994_mmssnoc_ahb_a_clk, 772 [RPM_SMD_QDSS_CLK] = &msm8994_qdss_clk, 773 [RPM_SMD_QDSS_A_CLK] = &msm8994_qdss_a_clk, 774 [RPM_SMD_RF_CLK1] = &msm8994_rf_clk1, 775 [RPM_SMD_RF_CLK1_A] = &msm8994_rf_clk1_a, 776 [RPM_SMD_RF_CLK2] = &msm8994_rf_clk2, 777 [RPM_SMD_RF_CLK2_A] = &msm8994_rf_clk2_a, 778 [RPM_SMD_RF_CLK1_PIN] = &msm8994_rf_clk1_pin, 779 [RPM_SMD_RF_CLK1_A_PIN] = &msm8994_rf_clk1_a_pin, 780 [RPM_SMD_RF_CLK2_PIN] = &msm8994_rf_clk2_pin, 781 [RPM_SMD_RF_CLK2_A_PIN] = &msm8994_rf_clk2_a_pin, 782 [RPM_SMD_CE1_CLK] = &msm8994_ce1_clk, 783 [RPM_SMD_CE1_A_CLK] = &msm8994_ce1_a_clk, 784 [RPM_SMD_CE2_CLK] = &msm8994_ce2_clk, 785 [RPM_SMD_CE2_A_CLK] = &msm8994_ce2_a_clk, 786 [RPM_SMD_CE3_CLK] = &msm8994_ce3_clk, 787 [RPM_SMD_CE3_A_CLK] = &msm8994_ce3_a_clk, 788 }; 789 790 static const struct rpm_smd_clk_desc rpm_clk_msm8994 = { 791 .clks = msm8994_clks, 792 .num_clks = ARRAY_SIZE(msm8994_clks), 793 }; 794 795 /* msm8996 */ 796 DEFINE_CLK_SMD_RPM(msm8996, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0); 797 DEFINE_CLK_SMD_RPM(msm8996, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1); 798 DEFINE_CLK_SMD_RPM(msm8996, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2); 799 DEFINE_CLK_SMD_RPM(msm8996, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0); 800 DEFINE_CLK_SMD_RPM(msm8996, mmssnoc_axi_rpm_clk, mmssnoc_axi_rpm_a_clk, 801 QCOM_SMD_RPM_MMAXI_CLK, 0); 802 DEFINE_CLK_SMD_RPM(msm8996, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0); 803 DEFINE_CLK_SMD_RPM(msm8996, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0); 804 DEFINE_CLK_SMD_RPM_BRANCH(msm8996, aggre1_noc_clk, aggre1_noc_a_clk, 805 QCOM_SMD_RPM_AGGR_CLK, 1, 1000); 806 DEFINE_CLK_SMD_RPM_BRANCH(msm8996, aggre2_noc_clk, aggre2_noc_a_clk, 807 QCOM_SMD_RPM_AGGR_CLK, 2, 1000); 808 DEFINE_CLK_SMD_RPM_QDSS(msm8996, qdss_clk, qdss_a_clk, 809 QCOM_SMD_RPM_MISC_CLK, 1); 810 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, bb_clk1, bb_clk1_a, 1); 811 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, bb_clk2, bb_clk2_a, 2); 812 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, rf_clk1, rf_clk1_a, 4); 813 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, rf_clk2, rf_clk2_a, 5); 814 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, ln_bb_clk, ln_bb_a_clk, 8); 815 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, div_clk1, div_clk1_a, 0xb); 816 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, div_clk2, div_clk2_a, 0xc); 817 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, div_clk3, div_clk3_a, 0xd); 818 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8996, bb_clk1_pin, bb_clk1_a_pin, 1); 819 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8996, bb_clk2_pin, bb_clk2_a_pin, 2); 820 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8996, rf_clk1_pin, rf_clk1_a_pin, 4); 821 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8996, rf_clk2_pin, rf_clk2_a_pin, 5); 822 823 static struct clk_smd_rpm *msm8996_clks[] = { 824 [RPM_SMD_PCNOC_CLK] = &msm8996_pcnoc_clk, 825 [RPM_SMD_PCNOC_A_CLK] = &msm8996_pcnoc_a_clk, 826 [RPM_SMD_SNOC_CLK] = &msm8996_snoc_clk, 827 [RPM_SMD_SNOC_A_CLK] = &msm8996_snoc_a_clk, 828 [RPM_SMD_CNOC_CLK] = &msm8996_cnoc_clk, 829 [RPM_SMD_CNOC_A_CLK] = &msm8996_cnoc_a_clk, 830 [RPM_SMD_BIMC_CLK] = &msm8996_bimc_clk, 831 [RPM_SMD_BIMC_A_CLK] = &msm8996_bimc_a_clk, 832 [RPM_SMD_MMAXI_CLK] = &msm8996_mmssnoc_axi_rpm_clk, 833 [RPM_SMD_MMAXI_A_CLK] = &msm8996_mmssnoc_axi_rpm_a_clk, 834 [RPM_SMD_IPA_CLK] = &msm8996_ipa_clk, 835 [RPM_SMD_IPA_A_CLK] = &msm8996_ipa_a_clk, 836 [RPM_SMD_CE1_CLK] = &msm8996_ce1_clk, 837 [RPM_SMD_CE1_A_CLK] = &msm8996_ce1_a_clk, 838 [RPM_SMD_AGGR1_NOC_CLK] = &msm8996_aggre1_noc_clk, 839 [RPM_SMD_AGGR1_NOC_A_CLK] = &msm8996_aggre1_noc_a_clk, 840 [RPM_SMD_AGGR2_NOC_CLK] = &msm8996_aggre2_noc_clk, 841 [RPM_SMD_AGGR2_NOC_A_CLK] = &msm8996_aggre2_noc_a_clk, 842 [RPM_SMD_QDSS_CLK] = &msm8996_qdss_clk, 843 [RPM_SMD_QDSS_A_CLK] = &msm8996_qdss_a_clk, 844 [RPM_SMD_BB_CLK1] = &msm8996_bb_clk1, 845 [RPM_SMD_BB_CLK1_A] = &msm8996_bb_clk1_a, 846 [RPM_SMD_BB_CLK2] = &msm8996_bb_clk2, 847 [RPM_SMD_BB_CLK2_A] = &msm8996_bb_clk2_a, 848 [RPM_SMD_RF_CLK1] = &msm8996_rf_clk1, 849 [RPM_SMD_RF_CLK1_A] = &msm8996_rf_clk1_a, 850 [RPM_SMD_RF_CLK2] = &msm8996_rf_clk2, 851 [RPM_SMD_RF_CLK2_A] = &msm8996_rf_clk2_a, 852 [RPM_SMD_LN_BB_CLK] = &msm8996_ln_bb_clk, 853 [RPM_SMD_LN_BB_A_CLK] = &msm8996_ln_bb_a_clk, 854 [RPM_SMD_DIV_CLK1] = &msm8996_div_clk1, 855 [RPM_SMD_DIV_A_CLK1] = &msm8996_div_clk1_a, 856 [RPM_SMD_DIV_CLK2] = &msm8996_div_clk2, 857 [RPM_SMD_DIV_A_CLK2] = &msm8996_div_clk2_a, 858 [RPM_SMD_DIV_CLK3] = &msm8996_div_clk3, 859 [RPM_SMD_DIV_A_CLK3] = &msm8996_div_clk3_a, 860 [RPM_SMD_BB_CLK1_PIN] = &msm8996_bb_clk1_pin, 861 [RPM_SMD_BB_CLK1_A_PIN] = &msm8996_bb_clk1_a_pin, 862 [RPM_SMD_BB_CLK2_PIN] = &msm8996_bb_clk2_pin, 863 [RPM_SMD_BB_CLK2_A_PIN] = &msm8996_bb_clk2_a_pin, 864 [RPM_SMD_RF_CLK1_PIN] = &msm8996_rf_clk1_pin, 865 [RPM_SMD_RF_CLK1_A_PIN] = &msm8996_rf_clk1_a_pin, 866 [RPM_SMD_RF_CLK2_PIN] = &msm8996_rf_clk2_pin, 867 [RPM_SMD_RF_CLK2_A_PIN] = &msm8996_rf_clk2_a_pin, 868 }; 869 870 static const struct rpm_smd_clk_desc rpm_clk_msm8996 = { 871 .clks = msm8996_clks, 872 .num_clks = ARRAY_SIZE(msm8996_clks), 873 }; 874 875 /* QCS404 */ 876 DEFINE_CLK_SMD_RPM_QDSS(qcs404, qdss_clk, qdss_a_clk, QCOM_SMD_RPM_MISC_CLK, 1); 877 878 DEFINE_CLK_SMD_RPM(qcs404, pnoc_clk, pnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0); 879 DEFINE_CLK_SMD_RPM(qcs404, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1); 880 881 DEFINE_CLK_SMD_RPM(qcs404, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0); 882 DEFINE_CLK_SMD_RPM(qcs404, bimc_gpu_clk, bimc_gpu_a_clk, QCOM_SMD_RPM_MEM_CLK, 2); 883 884 DEFINE_CLK_SMD_RPM(qcs404, qpic_clk, qpic_a_clk, QCOM_SMD_RPM_QPIC_CLK, 0); 885 DEFINE_CLK_SMD_RPM(qcs404, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0); 886 887 DEFINE_CLK_SMD_RPM_XO_BUFFER(qcs404, rf_clk1, rf_clk1_a, 4); 888 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(qcs404, rf_clk1_pin, rf_clk1_a_pin, 4); 889 890 DEFINE_CLK_SMD_RPM_XO_BUFFER(qcs404, ln_bb_clk, ln_bb_a_clk, 8); 891 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(qcs404, ln_bb_clk_pin, ln_bb_clk_a_pin, 8); 892 893 static struct clk_smd_rpm *qcs404_clks[] = { 894 [RPM_SMD_QDSS_CLK] = &qcs404_qdss_clk, 895 [RPM_SMD_QDSS_A_CLK] = &qcs404_qdss_a_clk, 896 [RPM_SMD_PNOC_CLK] = &qcs404_pnoc_clk, 897 [RPM_SMD_PNOC_A_CLK] = &qcs404_pnoc_a_clk, 898 [RPM_SMD_SNOC_CLK] = &qcs404_snoc_clk, 899 [RPM_SMD_SNOC_A_CLK] = &qcs404_snoc_a_clk, 900 [RPM_SMD_BIMC_CLK] = &qcs404_bimc_clk, 901 [RPM_SMD_BIMC_A_CLK] = &qcs404_bimc_a_clk, 902 [RPM_SMD_BIMC_GPU_CLK] = &qcs404_bimc_gpu_clk, 903 [RPM_SMD_BIMC_GPU_A_CLK] = &qcs404_bimc_gpu_a_clk, 904 [RPM_SMD_QPIC_CLK] = &qcs404_qpic_clk, 905 [RPM_SMD_QPIC_CLK_A] = &qcs404_qpic_a_clk, 906 [RPM_SMD_CE1_CLK] = &qcs404_ce1_clk, 907 [RPM_SMD_CE1_A_CLK] = &qcs404_ce1_a_clk, 908 [RPM_SMD_RF_CLK1] = &qcs404_rf_clk1, 909 [RPM_SMD_RF_CLK1_A] = &qcs404_rf_clk1_a, 910 [RPM_SMD_LN_BB_CLK] = &qcs404_ln_bb_clk, 911 [RPM_SMD_LN_BB_A_CLK] = &qcs404_ln_bb_a_clk, 912 }; 913 914 static const struct rpm_smd_clk_desc rpm_clk_qcs404 = { 915 .clks = qcs404_clks, 916 .num_clks = ARRAY_SIZE(qcs404_clks), 917 }; 918 919 /* msm8998 */ 920 DEFINE_CLK_SMD_RPM(msm8998, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0); 921 DEFINE_CLK_SMD_RPM(msm8998, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0); 922 DEFINE_CLK_SMD_RPM(msm8998, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1); 923 DEFINE_CLK_SMD_RPM(msm8998, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2); 924 DEFINE_CLK_SMD_RPM(msm8998, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0); 925 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, div_clk1, div_clk1_a, 0xb); 926 DEFINE_CLK_SMD_RPM(msm8998, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0); 927 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, ln_bb_clk1, ln_bb_clk1_a, 1); 928 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, ln_bb_clk2, ln_bb_clk2_a, 2); 929 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, ln_bb_clk3_pin, ln_bb_clk3_a_pin, 930 3); 931 DEFINE_CLK_SMD_RPM(msm8998, mmssnoc_axi_rpm_clk, mmssnoc_axi_rpm_a_clk, 932 QCOM_SMD_RPM_MMAXI_CLK, 0); 933 DEFINE_CLK_SMD_RPM(msm8998, aggre1_noc_clk, aggre1_noc_a_clk, 934 QCOM_SMD_RPM_AGGR_CLK, 1); 935 DEFINE_CLK_SMD_RPM(msm8998, aggre2_noc_clk, aggre2_noc_a_clk, 936 QCOM_SMD_RPM_AGGR_CLK, 2); 937 DEFINE_CLK_SMD_RPM_QDSS(msm8998, qdss_clk, qdss_a_clk, 938 QCOM_SMD_RPM_MISC_CLK, 1); 939 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, rf_clk1, rf_clk1_a, 4); 940 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, rf_clk2_pin, rf_clk2_a_pin, 5); 941 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, rf_clk3, rf_clk3_a, 6); 942 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, rf_clk3_pin, rf_clk3_a_pin, 6); 943 static struct clk_smd_rpm *msm8998_clks[] = { 944 [RPM_SMD_BIMC_CLK] = &msm8998_bimc_clk, 945 [RPM_SMD_BIMC_A_CLK] = &msm8998_bimc_a_clk, 946 [RPM_SMD_PCNOC_CLK] = &msm8998_pcnoc_clk, 947 [RPM_SMD_PCNOC_A_CLK] = &msm8998_pcnoc_a_clk, 948 [RPM_SMD_SNOC_CLK] = &msm8998_snoc_clk, 949 [RPM_SMD_SNOC_A_CLK] = &msm8998_snoc_a_clk, 950 [RPM_SMD_CNOC_CLK] = &msm8998_cnoc_clk, 951 [RPM_SMD_CNOC_A_CLK] = &msm8998_cnoc_a_clk, 952 [RPM_SMD_CE1_CLK] = &msm8998_ce1_clk, 953 [RPM_SMD_CE1_A_CLK] = &msm8998_ce1_a_clk, 954 [RPM_SMD_DIV_CLK1] = &msm8998_div_clk1, 955 [RPM_SMD_DIV_A_CLK1] = &msm8998_div_clk1_a, 956 [RPM_SMD_IPA_CLK] = &msm8998_ipa_clk, 957 [RPM_SMD_IPA_A_CLK] = &msm8998_ipa_a_clk, 958 [RPM_SMD_LN_BB_CLK1] = &msm8998_ln_bb_clk1, 959 [RPM_SMD_LN_BB_CLK1_A] = &msm8998_ln_bb_clk1_a, 960 [RPM_SMD_LN_BB_CLK2] = &msm8998_ln_bb_clk2, 961 [RPM_SMD_LN_BB_CLK2_A] = &msm8998_ln_bb_clk2_a, 962 [RPM_SMD_LN_BB_CLK3_PIN] = &msm8998_ln_bb_clk3_pin, 963 [RPM_SMD_LN_BB_CLK3_A_PIN] = &msm8998_ln_bb_clk3_a_pin, 964 [RPM_SMD_MMAXI_CLK] = &msm8998_mmssnoc_axi_rpm_clk, 965 [RPM_SMD_MMAXI_A_CLK] = &msm8998_mmssnoc_axi_rpm_a_clk, 966 [RPM_SMD_AGGR1_NOC_CLK] = &msm8998_aggre1_noc_clk, 967 [RPM_SMD_AGGR1_NOC_A_CLK] = &msm8998_aggre1_noc_a_clk, 968 [RPM_SMD_AGGR2_NOC_CLK] = &msm8998_aggre2_noc_clk, 969 [RPM_SMD_AGGR2_NOC_A_CLK] = &msm8998_aggre2_noc_a_clk, 970 [RPM_SMD_QDSS_CLK] = &msm8998_qdss_clk, 971 [RPM_SMD_QDSS_A_CLK] = &msm8998_qdss_a_clk, 972 [RPM_SMD_RF_CLK1] = &msm8998_rf_clk1, 973 [RPM_SMD_RF_CLK1_A] = &msm8998_rf_clk1_a, 974 [RPM_SMD_RF_CLK2_PIN] = &msm8998_rf_clk2_pin, 975 [RPM_SMD_RF_CLK2_A_PIN] = &msm8998_rf_clk2_a_pin, 976 [RPM_SMD_RF_CLK3] = &msm8998_rf_clk3, 977 [RPM_SMD_RF_CLK3_A] = &msm8998_rf_clk3_a, 978 [RPM_SMD_RF_CLK3_PIN] = &msm8998_rf_clk3_pin, 979 [RPM_SMD_RF_CLK3_A_PIN] = &msm8998_rf_clk3_a_pin, 980 }; 981 982 static const struct rpm_smd_clk_desc rpm_clk_msm8998 = { 983 .clks = msm8998_clks, 984 .num_clks = ARRAY_SIZE(msm8998_clks), 985 }; 986 987 /* sdm660 */ 988 DEFINE_CLK_SMD_RPM_BRANCH(sdm660, bi_tcxo, bi_tcxo_a, QCOM_SMD_RPM_MISC_CLK, 0, 989 19200000); 990 DEFINE_CLK_SMD_RPM(sdm660, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1); 991 DEFINE_CLK_SMD_RPM(sdm660, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2); 992 DEFINE_CLK_SMD_RPM(sdm660, cnoc_periph_clk, cnoc_periph_a_clk, 993 QCOM_SMD_RPM_BUS_CLK, 0); 994 DEFINE_CLK_SMD_RPM(sdm660, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0); 995 DEFINE_CLK_SMD_RPM(sdm660, mmssnoc_axi_clk, mmssnoc_axi_a_clk, 996 QCOM_SMD_RPM_MMAXI_CLK, 0); 997 DEFINE_CLK_SMD_RPM(sdm660, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0); 998 DEFINE_CLK_SMD_RPM(sdm660, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0); 999 DEFINE_CLK_SMD_RPM(sdm660, aggre2_noc_clk, aggre2_noc_a_clk, 1000 QCOM_SMD_RPM_AGGR_CLK, 2); 1001 DEFINE_CLK_SMD_RPM_QDSS(sdm660, qdss_clk, qdss_a_clk, 1002 QCOM_SMD_RPM_MISC_CLK, 1); 1003 DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, rf_clk1, rf_clk1_a, 4); 1004 DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, div_clk1, div_clk1_a, 11); 1005 DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, ln_bb_clk1, ln_bb_clk1_a, 1); 1006 DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, ln_bb_clk2, ln_bb_clk2_a, 2); 1007 DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, ln_bb_clk3, ln_bb_clk3_a, 3); 1008 1009 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, rf_clk1_pin, rf_clk1_a_pin, 4); 1010 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, ln_bb_clk1_pin, 1011 ln_bb_clk1_pin_a, 1); 1012 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, ln_bb_clk2_pin, 1013 ln_bb_clk2_pin_a, 2); 1014 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, ln_bb_clk3_pin, 1015 ln_bb_clk3_pin_a, 3); 1016 static struct clk_smd_rpm *sdm660_clks[] = { 1017 [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo, 1018 [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a, 1019 [RPM_SMD_SNOC_CLK] = &sdm660_snoc_clk, 1020 [RPM_SMD_SNOC_A_CLK] = &sdm660_snoc_a_clk, 1021 [RPM_SMD_CNOC_CLK] = &sdm660_cnoc_clk, 1022 [RPM_SMD_CNOC_A_CLK] = &sdm660_cnoc_a_clk, 1023 [RPM_SMD_CNOC_PERIPH_CLK] = &sdm660_cnoc_periph_clk, 1024 [RPM_SMD_CNOC_PERIPH_A_CLK] = &sdm660_cnoc_periph_a_clk, 1025 [RPM_SMD_BIMC_CLK] = &sdm660_bimc_clk, 1026 [RPM_SMD_BIMC_A_CLK] = &sdm660_bimc_a_clk, 1027 [RPM_SMD_MMSSNOC_AXI_CLK] = &sdm660_mmssnoc_axi_clk, 1028 [RPM_SMD_MMSSNOC_AXI_CLK_A] = &sdm660_mmssnoc_axi_a_clk, 1029 [RPM_SMD_IPA_CLK] = &sdm660_ipa_clk, 1030 [RPM_SMD_IPA_A_CLK] = &sdm660_ipa_a_clk, 1031 [RPM_SMD_CE1_CLK] = &sdm660_ce1_clk, 1032 [RPM_SMD_CE1_A_CLK] = &sdm660_ce1_a_clk, 1033 [RPM_SMD_AGGR2_NOC_CLK] = &sdm660_aggre2_noc_clk, 1034 [RPM_SMD_AGGR2_NOC_A_CLK] = &sdm660_aggre2_noc_a_clk, 1035 [RPM_SMD_QDSS_CLK] = &sdm660_qdss_clk, 1036 [RPM_SMD_QDSS_A_CLK] = &sdm660_qdss_a_clk, 1037 [RPM_SMD_RF_CLK1] = &sdm660_rf_clk1, 1038 [RPM_SMD_RF_CLK1_A] = &sdm660_rf_clk1_a, 1039 [RPM_SMD_DIV_CLK1] = &sdm660_div_clk1, 1040 [RPM_SMD_DIV_A_CLK1] = &sdm660_div_clk1_a, 1041 [RPM_SMD_LN_BB_CLK] = &sdm660_ln_bb_clk1, 1042 [RPM_SMD_LN_BB_A_CLK] = &sdm660_ln_bb_clk1_a, 1043 [RPM_SMD_LN_BB_CLK2] = &sdm660_ln_bb_clk2, 1044 [RPM_SMD_LN_BB_CLK2_A] = &sdm660_ln_bb_clk2_a, 1045 [RPM_SMD_LN_BB_CLK3] = &sdm660_ln_bb_clk3, 1046 [RPM_SMD_LN_BB_CLK3_A] = &sdm660_ln_bb_clk3_a, 1047 [RPM_SMD_RF_CLK1_PIN] = &sdm660_rf_clk1_pin, 1048 [RPM_SMD_RF_CLK1_A_PIN] = &sdm660_rf_clk1_a_pin, 1049 [RPM_SMD_LN_BB_CLK1_PIN] = &sdm660_ln_bb_clk1_pin, 1050 [RPM_SMD_LN_BB_CLK1_A_PIN] = &sdm660_ln_bb_clk1_pin_a, 1051 [RPM_SMD_LN_BB_CLK2_PIN] = &sdm660_ln_bb_clk2_pin, 1052 [RPM_SMD_LN_BB_CLK2_A_PIN] = &sdm660_ln_bb_clk2_pin_a, 1053 [RPM_SMD_LN_BB_CLK3_PIN] = &sdm660_ln_bb_clk3_pin, 1054 [RPM_SMD_LN_BB_CLK3_A_PIN] = &sdm660_ln_bb_clk3_pin_a, 1055 }; 1056 1057 static const struct rpm_smd_clk_desc rpm_clk_sdm660 = { 1058 .clks = sdm660_clks, 1059 .num_clks = ARRAY_SIZE(sdm660_clks), 1060 }; 1061 1062 static const struct of_device_id rpm_smd_clk_match_table[] = { 1063 { .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916 }, 1064 { .compatible = "qcom,rpmcc-msm8936", .data = &rpm_clk_msm8936 }, 1065 { .compatible = "qcom,rpmcc-msm8974", .data = &rpm_clk_msm8974 }, 1066 { .compatible = "qcom,rpmcc-msm8976", .data = &rpm_clk_msm8976 }, 1067 { .compatible = "qcom,rpmcc-msm8992", .data = &rpm_clk_msm8992 }, 1068 { .compatible = "qcom,rpmcc-msm8994", .data = &rpm_clk_msm8994 }, 1069 { .compatible = "qcom,rpmcc-msm8996", .data = &rpm_clk_msm8996 }, 1070 { .compatible = "qcom,rpmcc-msm8998", .data = &rpm_clk_msm8998 }, 1071 { .compatible = "qcom,rpmcc-qcs404", .data = &rpm_clk_qcs404 }, 1072 { .compatible = "qcom,rpmcc-sdm660", .data = &rpm_clk_sdm660 }, 1073 { } 1074 }; 1075 MODULE_DEVICE_TABLE(of, rpm_smd_clk_match_table); 1076 1077 static struct clk_hw *qcom_smdrpm_clk_hw_get(struct of_phandle_args *clkspec, 1078 void *data) 1079 { 1080 struct rpm_cc *rcc = data; 1081 unsigned int idx = clkspec->args[0]; 1082 1083 if (idx >= rcc->num_clks) { 1084 pr_err("%s: invalid index %u\n", __func__, idx); 1085 return ERR_PTR(-EINVAL); 1086 } 1087 1088 return rcc->clks[idx] ? &rcc->clks[idx]->hw : ERR_PTR(-ENOENT); 1089 } 1090 1091 static int rpm_smd_clk_probe(struct platform_device *pdev) 1092 { 1093 struct rpm_cc *rcc; 1094 int ret; 1095 size_t num_clks, i; 1096 struct qcom_smd_rpm *rpm; 1097 struct clk_smd_rpm **rpm_smd_clks; 1098 const struct rpm_smd_clk_desc *desc; 1099 1100 rpm = dev_get_drvdata(pdev->dev.parent); 1101 if (!rpm) { 1102 dev_err(&pdev->dev, "Unable to retrieve handle to RPM\n"); 1103 return -ENODEV; 1104 } 1105 1106 desc = of_device_get_match_data(&pdev->dev); 1107 if (!desc) 1108 return -EINVAL; 1109 1110 rpm_smd_clks = desc->clks; 1111 num_clks = desc->num_clks; 1112 1113 rcc = devm_kzalloc(&pdev->dev, sizeof(*rcc), GFP_KERNEL); 1114 if (!rcc) 1115 return -ENOMEM; 1116 1117 rcc->clks = rpm_smd_clks; 1118 rcc->num_clks = num_clks; 1119 1120 for (i = 0; i < num_clks; i++) { 1121 if (!rpm_smd_clks[i]) 1122 continue; 1123 1124 rpm_smd_clks[i]->rpm = rpm; 1125 1126 ret = clk_smd_rpm_handoff(rpm_smd_clks[i]); 1127 if (ret) 1128 goto err; 1129 } 1130 1131 ret = clk_smd_rpm_enable_scaling(rpm); 1132 if (ret) 1133 goto err; 1134 1135 for (i = 0; i < num_clks; i++) { 1136 if (!rpm_smd_clks[i]) 1137 continue; 1138 1139 ret = devm_clk_hw_register(&pdev->dev, &rpm_smd_clks[i]->hw); 1140 if (ret) 1141 goto err; 1142 } 1143 1144 ret = devm_of_clk_add_hw_provider(&pdev->dev, qcom_smdrpm_clk_hw_get, 1145 rcc); 1146 if (ret) 1147 goto err; 1148 1149 return 0; 1150 err: 1151 dev_err(&pdev->dev, "Error registering SMD clock driver (%d)\n", ret); 1152 return ret; 1153 } 1154 1155 static struct platform_driver rpm_smd_clk_driver = { 1156 .driver = { 1157 .name = "qcom-clk-smd-rpm", 1158 .of_match_table = rpm_smd_clk_match_table, 1159 }, 1160 .probe = rpm_smd_clk_probe, 1161 }; 1162 1163 static int __init rpm_smd_clk_init(void) 1164 { 1165 return platform_driver_register(&rpm_smd_clk_driver); 1166 } 1167 core_initcall(rpm_smd_clk_init); 1168 1169 static void __exit rpm_smd_clk_exit(void) 1170 { 1171 platform_driver_unregister(&rpm_smd_clk_driver); 1172 } 1173 module_exit(rpm_smd_clk_exit); 1174 1175 MODULE_DESCRIPTION("Qualcomm RPM over SMD Clock Controller Driver"); 1176 MODULE_LICENSE("GPL v2"); 1177 MODULE_ALIAS("platform:qcom-clk-smd-rpm"); 1178