1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2016, Linaro Limited 4 * Copyright (c) 2014, The Linux Foundation. All rights reserved. 5 */ 6 7 #include <linux/clk-provider.h> 8 #include <linux/err.h> 9 #include <linux/export.h> 10 #include <linux/init.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/mutex.h> 14 #include <linux/of.h> 15 #include <linux/of_device.h> 16 #include <linux/platform_device.h> 17 #include <linux/soc/qcom/smd-rpm.h> 18 19 #include <dt-bindings/clock/qcom,rpmcc.h> 20 #include <dt-bindings/mfd/qcom-rpm.h> 21 22 #define QCOM_RPM_KEY_SOFTWARE_ENABLE 0x6e657773 23 #define QCOM_RPM_KEY_PIN_CTRL_CLK_BUFFER_ENABLE_KEY 0x62636370 24 #define QCOM_RPM_SMD_KEY_RATE 0x007a484b 25 #define QCOM_RPM_SMD_KEY_ENABLE 0x62616e45 26 #define QCOM_RPM_SMD_KEY_STATE 0x54415453 27 #define QCOM_RPM_SCALING_ENABLE_ID 0x2 28 29 #define __DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id, stat_id, \ 30 key) \ 31 static struct clk_smd_rpm _platform##_##_active; \ 32 static struct clk_smd_rpm _platform##_##_name = { \ 33 .rpm_res_type = (type), \ 34 .rpm_clk_id = (r_id), \ 35 .rpm_status_id = (stat_id), \ 36 .rpm_key = (key), \ 37 .peer = &_platform##_##_active, \ 38 .rate = INT_MAX, \ 39 .hw.init = &(struct clk_init_data){ \ 40 .ops = &clk_smd_rpm_ops, \ 41 .name = #_name, \ 42 .parent_data = &(const struct clk_parent_data){ \ 43 .fw_name = "xo", \ 44 .name = "xo_board", \ 45 }, \ 46 .num_parents = 1, \ 47 }, \ 48 }; \ 49 static struct clk_smd_rpm _platform##_##_active = { \ 50 .rpm_res_type = (type), \ 51 .rpm_clk_id = (r_id), \ 52 .rpm_status_id = (stat_id), \ 53 .active_only = true, \ 54 .rpm_key = (key), \ 55 .peer = &_platform##_##_name, \ 56 .rate = INT_MAX, \ 57 .hw.init = &(struct clk_init_data){ \ 58 .ops = &clk_smd_rpm_ops, \ 59 .name = #_active, \ 60 .parent_data = &(const struct clk_parent_data){ \ 61 .fw_name = "xo", \ 62 .name = "xo_board", \ 63 }, \ 64 .num_parents = 1, \ 65 }, \ 66 } 67 68 #define __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, type, r_id, \ 69 stat_id, r, key) \ 70 static struct clk_smd_rpm _platform##_##_active; \ 71 static struct clk_smd_rpm _platform##_##_name = { \ 72 .rpm_res_type = (type), \ 73 .rpm_clk_id = (r_id), \ 74 .rpm_status_id = (stat_id), \ 75 .rpm_key = (key), \ 76 .branch = true, \ 77 .peer = &_platform##_##_active, \ 78 .rate = (r), \ 79 .hw.init = &(struct clk_init_data){ \ 80 .ops = &clk_smd_rpm_branch_ops, \ 81 .name = #_name, \ 82 .parent_data = &(const struct clk_parent_data){ \ 83 .fw_name = "xo", \ 84 .name = "xo_board", \ 85 }, \ 86 .num_parents = 1, \ 87 }, \ 88 }; \ 89 static struct clk_smd_rpm _platform##_##_active = { \ 90 .rpm_res_type = (type), \ 91 .rpm_clk_id = (r_id), \ 92 .rpm_status_id = (stat_id), \ 93 .active_only = true, \ 94 .rpm_key = (key), \ 95 .branch = true, \ 96 .peer = &_platform##_##_name, \ 97 .rate = (r), \ 98 .hw.init = &(struct clk_init_data){ \ 99 .ops = &clk_smd_rpm_branch_ops, \ 100 .name = #_active, \ 101 .parent_data = &(const struct clk_parent_data){ \ 102 .fw_name = "xo", \ 103 .name = "xo_board", \ 104 }, \ 105 .num_parents = 1, \ 106 }, \ 107 } 108 109 #define DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id) \ 110 __DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id, \ 111 0, QCOM_RPM_SMD_KEY_RATE) 112 113 #define DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, type, r_id, r) \ 114 __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, type, \ 115 r_id, 0, r, QCOM_RPM_SMD_KEY_ENABLE) 116 117 #define DEFINE_CLK_SMD_RPM_QDSS(_platform, _name, _active, type, r_id) \ 118 __DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id, \ 119 0, QCOM_RPM_SMD_KEY_STATE) 120 121 #define DEFINE_CLK_SMD_RPM_XO_BUFFER(_platform, _name, _active, r_id, r) \ 122 __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, \ 123 QCOM_SMD_RPM_CLK_BUF_A, r_id, 0, r, \ 124 QCOM_RPM_KEY_SOFTWARE_ENABLE) 125 126 #define DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(_platform, _name, _active, \ 127 r_id, r) \ 128 __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, \ 129 QCOM_SMD_RPM_CLK_BUF_A, r_id, 0, r, \ 130 QCOM_RPM_KEY_PIN_CTRL_CLK_BUFFER_ENABLE_KEY) 131 132 #define to_clk_smd_rpm(_hw) container_of(_hw, struct clk_smd_rpm, hw) 133 134 struct clk_smd_rpm { 135 const int rpm_res_type; 136 const int rpm_key; 137 const int rpm_clk_id; 138 const int rpm_status_id; 139 const bool active_only; 140 bool enabled; 141 bool branch; 142 struct clk_smd_rpm *peer; 143 struct clk_hw hw; 144 unsigned long rate; 145 struct qcom_smd_rpm *rpm; 146 }; 147 148 struct clk_smd_rpm_req { 149 __le32 key; 150 __le32 nbytes; 151 __le32 value; 152 }; 153 154 struct rpm_cc { 155 struct qcom_rpm *rpm; 156 struct clk_smd_rpm **clks; 157 size_t num_clks; 158 }; 159 160 struct rpm_smd_clk_desc { 161 struct clk_smd_rpm **clks; 162 size_t num_clks; 163 }; 164 165 static DEFINE_MUTEX(rpm_smd_clk_lock); 166 167 static int clk_smd_rpm_handoff(struct clk_smd_rpm *r) 168 { 169 int ret; 170 struct clk_smd_rpm_req req = { 171 .key = cpu_to_le32(r->rpm_key), 172 .nbytes = cpu_to_le32(sizeof(u32)), 173 .value = cpu_to_le32(r->branch ? 1 : INT_MAX), 174 }; 175 176 ret = qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_ACTIVE_STATE, 177 r->rpm_res_type, r->rpm_clk_id, &req, 178 sizeof(req)); 179 if (ret) 180 return ret; 181 ret = qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_SLEEP_STATE, 182 r->rpm_res_type, r->rpm_clk_id, &req, 183 sizeof(req)); 184 if (ret) 185 return ret; 186 187 return 0; 188 } 189 190 static int clk_smd_rpm_set_rate_active(struct clk_smd_rpm *r, 191 unsigned long rate) 192 { 193 struct clk_smd_rpm_req req = { 194 .key = cpu_to_le32(r->rpm_key), 195 .nbytes = cpu_to_le32(sizeof(u32)), 196 .value = cpu_to_le32(DIV_ROUND_UP(rate, 1000)), /* to kHz */ 197 }; 198 199 /* Buffered clock needs a binary value */ 200 if (r->rpm_res_type == QCOM_SMD_RPM_CLK_BUF_A) 201 req.value = cpu_to_le32(!!req.value); 202 203 return qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_ACTIVE_STATE, 204 r->rpm_res_type, r->rpm_clk_id, &req, 205 sizeof(req)); 206 } 207 208 static int clk_smd_rpm_set_rate_sleep(struct clk_smd_rpm *r, 209 unsigned long rate) 210 { 211 struct clk_smd_rpm_req req = { 212 .key = cpu_to_le32(r->rpm_key), 213 .nbytes = cpu_to_le32(sizeof(u32)), 214 .value = cpu_to_le32(DIV_ROUND_UP(rate, 1000)), /* to kHz */ 215 }; 216 217 /* Buffered clock needs a binary value */ 218 if (r->rpm_res_type == QCOM_SMD_RPM_CLK_BUF_A) 219 req.value = cpu_to_le32(!!req.value); 220 221 return qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_SLEEP_STATE, 222 r->rpm_res_type, r->rpm_clk_id, &req, 223 sizeof(req)); 224 } 225 226 static void to_active_sleep(struct clk_smd_rpm *r, unsigned long rate, 227 unsigned long *active, unsigned long *sleep) 228 { 229 *active = rate; 230 231 /* 232 * Active-only clocks don't care what the rate is during sleep. So, 233 * they vote for zero. 234 */ 235 if (r->active_only) 236 *sleep = 0; 237 else 238 *sleep = *active; 239 } 240 241 static int clk_smd_rpm_prepare(struct clk_hw *hw) 242 { 243 struct clk_smd_rpm *r = to_clk_smd_rpm(hw); 244 struct clk_smd_rpm *peer = r->peer; 245 unsigned long this_rate = 0, this_sleep_rate = 0; 246 unsigned long peer_rate = 0, peer_sleep_rate = 0; 247 unsigned long active_rate, sleep_rate; 248 int ret = 0; 249 250 mutex_lock(&rpm_smd_clk_lock); 251 252 /* Don't send requests to the RPM if the rate has not been set. */ 253 if (!r->rate) 254 goto out; 255 256 to_active_sleep(r, r->rate, &this_rate, &this_sleep_rate); 257 258 /* Take peer clock's rate into account only if it's enabled. */ 259 if (peer->enabled) 260 to_active_sleep(peer, peer->rate, 261 &peer_rate, &peer_sleep_rate); 262 263 active_rate = max(this_rate, peer_rate); 264 265 if (r->branch) 266 active_rate = !!active_rate; 267 268 ret = clk_smd_rpm_set_rate_active(r, active_rate); 269 if (ret) 270 goto out; 271 272 sleep_rate = max(this_sleep_rate, peer_sleep_rate); 273 if (r->branch) 274 sleep_rate = !!sleep_rate; 275 276 ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate); 277 if (ret) 278 /* Undo the active set vote and restore it */ 279 ret = clk_smd_rpm_set_rate_active(r, peer_rate); 280 281 out: 282 if (!ret) 283 r->enabled = true; 284 285 mutex_unlock(&rpm_smd_clk_lock); 286 287 return ret; 288 } 289 290 static void clk_smd_rpm_unprepare(struct clk_hw *hw) 291 { 292 struct clk_smd_rpm *r = to_clk_smd_rpm(hw); 293 struct clk_smd_rpm *peer = r->peer; 294 unsigned long peer_rate = 0, peer_sleep_rate = 0; 295 unsigned long active_rate, sleep_rate; 296 int ret; 297 298 mutex_lock(&rpm_smd_clk_lock); 299 300 if (!r->rate) 301 goto out; 302 303 /* Take peer clock's rate into account only if it's enabled. */ 304 if (peer->enabled) 305 to_active_sleep(peer, peer->rate, &peer_rate, 306 &peer_sleep_rate); 307 308 active_rate = r->branch ? !!peer_rate : peer_rate; 309 ret = clk_smd_rpm_set_rate_active(r, active_rate); 310 if (ret) 311 goto out; 312 313 sleep_rate = r->branch ? !!peer_sleep_rate : peer_sleep_rate; 314 ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate); 315 if (ret) 316 goto out; 317 318 r->enabled = false; 319 320 out: 321 mutex_unlock(&rpm_smd_clk_lock); 322 } 323 324 static int clk_smd_rpm_set_rate(struct clk_hw *hw, unsigned long rate, 325 unsigned long parent_rate) 326 { 327 struct clk_smd_rpm *r = to_clk_smd_rpm(hw); 328 struct clk_smd_rpm *peer = r->peer; 329 unsigned long active_rate, sleep_rate; 330 unsigned long this_rate = 0, this_sleep_rate = 0; 331 unsigned long peer_rate = 0, peer_sleep_rate = 0; 332 int ret = 0; 333 334 mutex_lock(&rpm_smd_clk_lock); 335 336 if (!r->enabled) 337 goto out; 338 339 to_active_sleep(r, rate, &this_rate, &this_sleep_rate); 340 341 /* Take peer clock's rate into account only if it's enabled. */ 342 if (peer->enabled) 343 to_active_sleep(peer, peer->rate, 344 &peer_rate, &peer_sleep_rate); 345 346 active_rate = max(this_rate, peer_rate); 347 ret = clk_smd_rpm_set_rate_active(r, active_rate); 348 if (ret) 349 goto out; 350 351 sleep_rate = max(this_sleep_rate, peer_sleep_rate); 352 ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate); 353 if (ret) 354 goto out; 355 356 r->rate = rate; 357 358 out: 359 mutex_unlock(&rpm_smd_clk_lock); 360 361 return ret; 362 } 363 364 static long clk_smd_rpm_round_rate(struct clk_hw *hw, unsigned long rate, 365 unsigned long *parent_rate) 366 { 367 /* 368 * RPM handles rate rounding and we don't have a way to 369 * know what the rate will be, so just return whatever 370 * rate is requested. 371 */ 372 return rate; 373 } 374 375 static unsigned long clk_smd_rpm_recalc_rate(struct clk_hw *hw, 376 unsigned long parent_rate) 377 { 378 struct clk_smd_rpm *r = to_clk_smd_rpm(hw); 379 380 /* 381 * RPM handles rate rounding and we don't have a way to 382 * know what the rate will be, so just return whatever 383 * rate was set. 384 */ 385 return r->rate; 386 } 387 388 static int clk_smd_rpm_enable_scaling(struct qcom_smd_rpm *rpm) 389 { 390 int ret; 391 struct clk_smd_rpm_req req = { 392 .key = cpu_to_le32(QCOM_RPM_SMD_KEY_ENABLE), 393 .nbytes = cpu_to_le32(sizeof(u32)), 394 .value = cpu_to_le32(1), 395 }; 396 397 ret = qcom_rpm_smd_write(rpm, QCOM_SMD_RPM_SLEEP_STATE, 398 QCOM_SMD_RPM_MISC_CLK, 399 QCOM_RPM_SCALING_ENABLE_ID, &req, sizeof(req)); 400 if (ret) { 401 pr_err("RPM clock scaling (sleep set) not enabled!\n"); 402 return ret; 403 } 404 405 ret = qcom_rpm_smd_write(rpm, QCOM_SMD_RPM_ACTIVE_STATE, 406 QCOM_SMD_RPM_MISC_CLK, 407 QCOM_RPM_SCALING_ENABLE_ID, &req, sizeof(req)); 408 if (ret) { 409 pr_err("RPM clock scaling (active set) not enabled!\n"); 410 return ret; 411 } 412 413 pr_debug("%s: RPM clock scaling is enabled\n", __func__); 414 return 0; 415 } 416 417 static const struct clk_ops clk_smd_rpm_ops = { 418 .prepare = clk_smd_rpm_prepare, 419 .unprepare = clk_smd_rpm_unprepare, 420 .set_rate = clk_smd_rpm_set_rate, 421 .round_rate = clk_smd_rpm_round_rate, 422 .recalc_rate = clk_smd_rpm_recalc_rate, 423 }; 424 425 static const struct clk_ops clk_smd_rpm_branch_ops = { 426 .prepare = clk_smd_rpm_prepare, 427 .unprepare = clk_smd_rpm_unprepare, 428 .recalc_rate = clk_smd_rpm_recalc_rate, 429 }; 430 431 DEFINE_CLK_SMD_RPM(msm8916, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0); 432 DEFINE_CLK_SMD_RPM(msm8916, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1); 433 DEFINE_CLK_SMD_RPM(msm8916, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0); 434 DEFINE_CLK_SMD_RPM_QDSS(msm8916, qdss_clk, qdss_a_clk, QCOM_SMD_RPM_MISC_CLK, 1); 435 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, bb_clk1, bb_clk1_a, 1, 19200000); 436 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, bb_clk2, bb_clk2_a, 2, 19200000); 437 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, rf_clk1, rf_clk1_a, 4, 19200000); 438 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, rf_clk2, rf_clk2_a, 5, 19200000); 439 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, bb_clk1_pin, bb_clk1_a_pin, 1, 19200000); 440 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, bb_clk2_pin, bb_clk2_a_pin, 2, 19200000); 441 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, rf_clk1_pin, rf_clk1_a_pin, 4, 19200000); 442 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, rf_clk2_pin, rf_clk2_a_pin, 5, 19200000); 443 444 static struct clk_smd_rpm *msm8916_clks[] = { 445 [RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk, 446 [RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk, 447 [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk, 448 [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk, 449 [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, 450 [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, 451 [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk, 452 [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk, 453 [RPM_SMD_BB_CLK1] = &msm8916_bb_clk1, 454 [RPM_SMD_BB_CLK1_A] = &msm8916_bb_clk1_a, 455 [RPM_SMD_BB_CLK2] = &msm8916_bb_clk2, 456 [RPM_SMD_BB_CLK2_A] = &msm8916_bb_clk2_a, 457 [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1, 458 [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a, 459 [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2, 460 [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a, 461 [RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin, 462 [RPM_SMD_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin, 463 [RPM_SMD_BB_CLK2_PIN] = &msm8916_bb_clk2_pin, 464 [RPM_SMD_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin, 465 [RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin, 466 [RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin, 467 [RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin, 468 [RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin, 469 }; 470 471 static const struct rpm_smd_clk_desc rpm_clk_msm8916 = { 472 .clks = msm8916_clks, 473 .num_clks = ARRAY_SIZE(msm8916_clks), 474 }; 475 476 DEFINE_CLK_SMD_RPM(msm8936, sysmmnoc_clk, sysmmnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2); 477 478 static struct clk_smd_rpm *msm8936_clks[] = { 479 [RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk, 480 [RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk, 481 [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk, 482 [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk, 483 [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, 484 [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, 485 [RPM_SMD_SYSMMNOC_CLK] = &msm8936_sysmmnoc_clk, 486 [RPM_SMD_SYSMMNOC_A_CLK] = &msm8936_sysmmnoc_a_clk, 487 [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk, 488 [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk, 489 [RPM_SMD_BB_CLK1] = &msm8916_bb_clk1, 490 [RPM_SMD_BB_CLK1_A] = &msm8916_bb_clk1_a, 491 [RPM_SMD_BB_CLK2] = &msm8916_bb_clk2, 492 [RPM_SMD_BB_CLK2_A] = &msm8916_bb_clk2_a, 493 [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1, 494 [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a, 495 [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2, 496 [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a, 497 [RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin, 498 [RPM_SMD_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin, 499 [RPM_SMD_BB_CLK2_PIN] = &msm8916_bb_clk2_pin, 500 [RPM_SMD_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin, 501 [RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin, 502 [RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin, 503 [RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin, 504 [RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin, 505 }; 506 507 static const struct rpm_smd_clk_desc rpm_clk_msm8936 = { 508 .clks = msm8936_clks, 509 .num_clks = ARRAY_SIZE(msm8936_clks), 510 }; 511 512 DEFINE_CLK_SMD_RPM(msm8974, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2); 513 DEFINE_CLK_SMD_RPM(msm8974, mmssnoc_ahb_clk, mmssnoc_ahb_a_clk, QCOM_SMD_RPM_BUS_CLK, 3); 514 DEFINE_CLK_SMD_RPM(msm8974, gfx3d_clk_src, gfx3d_a_clk_src, QCOM_SMD_RPM_MEM_CLK, 1); 515 DEFINE_CLK_SMD_RPM(msm8974, ocmemgx_clk, ocmemgx_a_clk, QCOM_SMD_RPM_MEM_CLK, 2); 516 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_d0, cxo_d0_a, 1, 19200000); 517 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_d1, cxo_d1_a, 2, 19200000); 518 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_a0, cxo_a0_a, 4, 19200000); 519 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_a1, cxo_a1_a, 5, 19200000); 520 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_a2, cxo_a2_a, 6, 19200000); 521 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, diff_clk, diff_a_clk, 7, 19200000); 522 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, div_clk1, div_a_clk1, 11, 19200000); 523 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, div_clk2, div_a_clk2, 12, 19200000); 524 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_d0_pin, cxo_d0_a_pin, 1, 19200000); 525 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_d1_pin, cxo_d1_a_pin, 2, 19200000); 526 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a0_pin, cxo_a0_a_pin, 4, 19200000); 527 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a1_pin, cxo_a1_a_pin, 5, 19200000); 528 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a2_pin, cxo_a2_a_pin, 6, 19200000); 529 530 static struct clk_smd_rpm *msm8974_clks[] = { 531 [RPM_SMD_PNOC_CLK] = &msm8916_pcnoc_clk, 532 [RPM_SMD_PNOC_A_CLK] = &msm8916_pcnoc_a_clk, 533 [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk, 534 [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk, 535 [RPM_SMD_CNOC_CLK] = &msm8974_cnoc_clk, 536 [RPM_SMD_CNOC_A_CLK] = &msm8974_cnoc_a_clk, 537 [RPM_SMD_MMSSNOC_AHB_CLK] = &msm8974_mmssnoc_ahb_clk, 538 [RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8974_mmssnoc_ahb_a_clk, 539 [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, 540 [RPM_SMD_GFX3D_CLK_SRC] = &msm8974_gfx3d_clk_src, 541 [RPM_SMD_GFX3D_A_CLK_SRC] = &msm8974_gfx3d_a_clk_src, 542 [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, 543 [RPM_SMD_OCMEMGX_CLK] = &msm8974_ocmemgx_clk, 544 [RPM_SMD_OCMEMGX_A_CLK] = &msm8974_ocmemgx_a_clk, 545 [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk, 546 [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk, 547 [RPM_SMD_CXO_D0] = &msm8974_cxo_d0, 548 [RPM_SMD_CXO_D0_A] = &msm8974_cxo_d0_a, 549 [RPM_SMD_CXO_D1] = &msm8974_cxo_d1, 550 [RPM_SMD_CXO_D1_A] = &msm8974_cxo_d1_a, 551 [RPM_SMD_CXO_A0] = &msm8974_cxo_a0, 552 [RPM_SMD_CXO_A0_A] = &msm8974_cxo_a0_a, 553 [RPM_SMD_CXO_A1] = &msm8974_cxo_a1, 554 [RPM_SMD_CXO_A1_A] = &msm8974_cxo_a1_a, 555 [RPM_SMD_CXO_A2] = &msm8974_cxo_a2, 556 [RPM_SMD_CXO_A2_A] = &msm8974_cxo_a2_a, 557 [RPM_SMD_DIFF_CLK] = &msm8974_diff_clk, 558 [RPM_SMD_DIFF_A_CLK] = &msm8974_diff_a_clk, 559 [RPM_SMD_DIV_CLK1] = &msm8974_div_clk1, 560 [RPM_SMD_DIV_A_CLK1] = &msm8974_div_a_clk1, 561 [RPM_SMD_DIV_CLK2] = &msm8974_div_clk2, 562 [RPM_SMD_DIV_A_CLK2] = &msm8974_div_a_clk2, 563 [RPM_SMD_CXO_D0_PIN] = &msm8974_cxo_d0_pin, 564 [RPM_SMD_CXO_D0_A_PIN] = &msm8974_cxo_d0_a_pin, 565 [RPM_SMD_CXO_D1_PIN] = &msm8974_cxo_d1_pin, 566 [RPM_SMD_CXO_D1_A_PIN] = &msm8974_cxo_d1_a_pin, 567 [RPM_SMD_CXO_A0_PIN] = &msm8974_cxo_a0_pin, 568 [RPM_SMD_CXO_A0_A_PIN] = &msm8974_cxo_a0_a_pin, 569 [RPM_SMD_CXO_A1_PIN] = &msm8974_cxo_a1_pin, 570 [RPM_SMD_CXO_A1_A_PIN] = &msm8974_cxo_a1_a_pin, 571 [RPM_SMD_CXO_A2_PIN] = &msm8974_cxo_a2_pin, 572 [RPM_SMD_CXO_A2_A_PIN] = &msm8974_cxo_a2_a_pin, 573 }; 574 575 static const struct rpm_smd_clk_desc rpm_clk_msm8974 = { 576 .clks = msm8974_clks, 577 .num_clks = ARRAY_SIZE(msm8974_clks), 578 }; 579 580 DEFINE_CLK_SMD_RPM(msm8976, mmssnoc_ahb_clk, mmssnoc_ahb_a_clk, 581 QCOM_SMD_RPM_BUS_CLK, 2); 582 DEFINE_CLK_SMD_RPM(msm8976, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0); 583 584 static struct clk_smd_rpm *msm8976_clks[] = { 585 [RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk, 586 [RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk, 587 [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk, 588 [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk, 589 [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, 590 [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, 591 [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk, 592 [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk, 593 [RPM_SMD_BB_CLK1] = &msm8916_bb_clk1, 594 [RPM_SMD_BB_CLK1_A] = &msm8916_bb_clk1_a, 595 [RPM_SMD_BB_CLK2] = &msm8916_bb_clk2, 596 [RPM_SMD_BB_CLK2_A] = &msm8916_bb_clk2_a, 597 [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2, 598 [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a, 599 [RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin, 600 [RPM_SMD_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin, 601 [RPM_SMD_BB_CLK2_PIN] = &msm8916_bb_clk2_pin, 602 [RPM_SMD_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin, 603 [RPM_SMD_MMSSNOC_AHB_CLK] = &msm8976_mmssnoc_ahb_clk, 604 [RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8976_mmssnoc_ahb_a_clk, 605 [RPM_SMD_DIV_CLK2] = &msm8974_div_clk2, 606 [RPM_SMD_DIV_A_CLK2] = &msm8974_div_a_clk2, 607 [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk, 608 [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk, 609 }; 610 611 static const struct rpm_smd_clk_desc rpm_clk_msm8976 = { 612 .clks = msm8976_clks, 613 .num_clks = ARRAY_SIZE(msm8976_clks), 614 }; 615 616 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, div_clk3, div_clk3_a, 13, 19200000); 617 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, ln_bb_clk, ln_bb_a_clk, 8, 19200000); 618 619 DEFINE_CLK_SMD_RPM(msm8992, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0); 620 DEFINE_CLK_SMD_RPM(msm8992, ce2_clk, ce2_a_clk, QCOM_SMD_RPM_CE_CLK, 1); 621 622 static struct clk_smd_rpm *msm8992_clks[] = { 623 [RPM_SMD_PNOC_CLK] = &msm8916_pcnoc_clk, 624 [RPM_SMD_PNOC_A_CLK] = &msm8916_pcnoc_a_clk, 625 [RPM_SMD_OCMEMGX_CLK] = &msm8974_ocmemgx_clk, 626 [RPM_SMD_OCMEMGX_A_CLK] = &msm8974_ocmemgx_a_clk, 627 [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, 628 [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, 629 [RPM_SMD_CNOC_CLK] = &msm8974_cnoc_clk, 630 [RPM_SMD_CNOC_A_CLK] = &msm8974_cnoc_a_clk, 631 [RPM_SMD_GFX3D_CLK_SRC] = &msm8974_gfx3d_clk_src, 632 [RPM_SMD_GFX3D_A_CLK_SRC] = &msm8974_gfx3d_a_clk_src, 633 [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk, 634 [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk, 635 [RPM_SMD_BB_CLK1] = &msm8916_bb_clk1, 636 [RPM_SMD_BB_CLK1_A] = &msm8916_bb_clk1_a, 637 [RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin, 638 [RPM_SMD_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin, 639 [RPM_SMD_BB_CLK2] = &msm8916_bb_clk2, 640 [RPM_SMD_BB_CLK2_A] = &msm8916_bb_clk2_a, 641 [RPM_SMD_BB_CLK2_PIN] = &msm8916_bb_clk2_pin, 642 [RPM_SMD_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin, 643 [RPM_SMD_DIV_CLK1] = &msm8974_div_clk1, 644 [RPM_SMD_DIV_A_CLK1] = &msm8974_div_a_clk1, 645 [RPM_SMD_DIV_CLK2] = &msm8974_div_clk2, 646 [RPM_SMD_DIV_A_CLK2] = &msm8974_div_a_clk2, 647 [RPM_SMD_DIV_CLK3] = &msm8992_div_clk3, 648 [RPM_SMD_DIV_A_CLK3] = &msm8992_div_clk3_a, 649 [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk, 650 [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk, 651 [RPM_SMD_LN_BB_CLK] = &msm8992_ln_bb_clk, 652 [RPM_SMD_LN_BB_A_CLK] = &msm8992_ln_bb_a_clk, 653 [RPM_SMD_MMSSNOC_AHB_CLK] = &msm8974_mmssnoc_ahb_clk, 654 [RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8974_mmssnoc_ahb_a_clk, 655 [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk, 656 [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk, 657 [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1, 658 [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a, 659 [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2, 660 [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a, 661 [RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin, 662 [RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin, 663 [RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin, 664 [RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin, 665 [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk, 666 [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk, 667 [RPM_SMD_CE2_CLK] = &msm8992_ce2_clk, 668 [RPM_SMD_CE2_A_CLK] = &msm8992_ce2_a_clk, 669 }; 670 671 static const struct rpm_smd_clk_desc rpm_clk_msm8992 = { 672 .clks = msm8992_clks, 673 .num_clks = ARRAY_SIZE(msm8992_clks), 674 }; 675 676 DEFINE_CLK_SMD_RPM(msm8994, ce3_clk, ce3_a_clk, QCOM_SMD_RPM_CE_CLK, 2); 677 678 static struct clk_smd_rpm *msm8994_clks[] = { 679 [RPM_SMD_PNOC_CLK] = &msm8916_pcnoc_clk, 680 [RPM_SMD_PNOC_A_CLK] = &msm8916_pcnoc_a_clk, 681 [RPM_SMD_OCMEMGX_CLK] = &msm8974_ocmemgx_clk, 682 [RPM_SMD_OCMEMGX_A_CLK] = &msm8974_ocmemgx_a_clk, 683 [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, 684 [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, 685 [RPM_SMD_CNOC_CLK] = &msm8974_cnoc_clk, 686 [RPM_SMD_CNOC_A_CLK] = &msm8974_cnoc_a_clk, 687 [RPM_SMD_GFX3D_CLK_SRC] = &msm8974_gfx3d_clk_src, 688 [RPM_SMD_GFX3D_A_CLK_SRC] = &msm8974_gfx3d_a_clk_src, 689 [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk, 690 [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk, 691 [RPM_SMD_BB_CLK1] = &msm8916_bb_clk1, 692 [RPM_SMD_BB_CLK1_A] = &msm8916_bb_clk1_a, 693 [RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin, 694 [RPM_SMD_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin, 695 [RPM_SMD_BB_CLK2] = &msm8916_bb_clk2, 696 [RPM_SMD_BB_CLK2_A] = &msm8916_bb_clk2_a, 697 [RPM_SMD_BB_CLK2_PIN] = &msm8916_bb_clk2_pin, 698 [RPM_SMD_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin, 699 [RPM_SMD_DIV_CLK1] = &msm8974_div_clk1, 700 [RPM_SMD_DIV_A_CLK1] = &msm8974_div_a_clk1, 701 [RPM_SMD_DIV_CLK2] = &msm8974_div_clk2, 702 [RPM_SMD_DIV_A_CLK2] = &msm8974_div_a_clk2, 703 [RPM_SMD_DIV_CLK3] = &msm8992_div_clk3, 704 [RPM_SMD_DIV_A_CLK3] = &msm8992_div_clk3_a, 705 [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk, 706 [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk, 707 [RPM_SMD_LN_BB_CLK] = &msm8992_ln_bb_clk, 708 [RPM_SMD_LN_BB_A_CLK] = &msm8992_ln_bb_a_clk, 709 [RPM_SMD_MMSSNOC_AHB_CLK] = &msm8974_mmssnoc_ahb_clk, 710 [RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8974_mmssnoc_ahb_a_clk, 711 [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk, 712 [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk, 713 [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1, 714 [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a, 715 [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2, 716 [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a, 717 [RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin, 718 [RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin, 719 [RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin, 720 [RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin, 721 [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk, 722 [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk, 723 [RPM_SMD_CE2_CLK] = &msm8992_ce2_clk, 724 [RPM_SMD_CE2_A_CLK] = &msm8992_ce2_a_clk, 725 [RPM_SMD_CE3_CLK] = &msm8994_ce3_clk, 726 [RPM_SMD_CE3_A_CLK] = &msm8994_ce3_a_clk, 727 }; 728 729 static const struct rpm_smd_clk_desc rpm_clk_msm8994 = { 730 .clks = msm8994_clks, 731 .num_clks = ARRAY_SIZE(msm8994_clks), 732 }; 733 734 DEFINE_CLK_SMD_RPM(msm8996, mmssnoc_axi_rpm_clk, mmssnoc_axi_rpm_a_clk, 735 QCOM_SMD_RPM_MMAXI_CLK, 0); 736 DEFINE_CLK_SMD_RPM_BRANCH(msm8996, aggre1_noc_clk, aggre1_noc_a_clk, 737 QCOM_SMD_RPM_AGGR_CLK, 1, 1000); 738 DEFINE_CLK_SMD_RPM_BRANCH(msm8996, aggre2_noc_clk, aggre2_noc_a_clk, 739 QCOM_SMD_RPM_AGGR_CLK, 2, 1000); 740 741 static struct clk_smd_rpm *msm8996_clks[] = { 742 [RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk, 743 [RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk, 744 [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk, 745 [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk, 746 [RPM_SMD_CNOC_CLK] = &msm8974_cnoc_clk, 747 [RPM_SMD_CNOC_A_CLK] = &msm8974_cnoc_a_clk, 748 [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, 749 [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, 750 [RPM_SMD_MMAXI_CLK] = &msm8996_mmssnoc_axi_rpm_clk, 751 [RPM_SMD_MMAXI_A_CLK] = &msm8996_mmssnoc_axi_rpm_a_clk, 752 [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk, 753 [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk, 754 [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk, 755 [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk, 756 [RPM_SMD_AGGR1_NOC_CLK] = &msm8996_aggre1_noc_clk, 757 [RPM_SMD_AGGR1_NOC_A_CLK] = &msm8996_aggre1_noc_a_clk, 758 [RPM_SMD_AGGR2_NOC_CLK] = &msm8996_aggre2_noc_clk, 759 [RPM_SMD_AGGR2_NOC_A_CLK] = &msm8996_aggre2_noc_a_clk, 760 [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk, 761 [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk, 762 [RPM_SMD_BB_CLK1] = &msm8916_bb_clk1, 763 [RPM_SMD_BB_CLK1_A] = &msm8916_bb_clk1_a, 764 [RPM_SMD_BB_CLK2] = &msm8916_bb_clk2, 765 [RPM_SMD_BB_CLK2_A] = &msm8916_bb_clk2_a, 766 [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1, 767 [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a, 768 [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2, 769 [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a, 770 [RPM_SMD_LN_BB_CLK] = &msm8992_ln_bb_clk, 771 [RPM_SMD_LN_BB_A_CLK] = &msm8992_ln_bb_a_clk, 772 [RPM_SMD_DIV_CLK1] = &msm8974_div_clk1, 773 [RPM_SMD_DIV_A_CLK1] = &msm8974_div_a_clk1, 774 [RPM_SMD_DIV_CLK2] = &msm8974_div_clk2, 775 [RPM_SMD_DIV_A_CLK2] = &msm8974_div_a_clk2, 776 [RPM_SMD_DIV_CLK3] = &msm8992_div_clk3, 777 [RPM_SMD_DIV_A_CLK3] = &msm8992_div_clk3_a, 778 [RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin, 779 [RPM_SMD_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin, 780 [RPM_SMD_BB_CLK2_PIN] = &msm8916_bb_clk2_pin, 781 [RPM_SMD_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin, 782 [RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin, 783 [RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin, 784 [RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin, 785 [RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin, 786 }; 787 788 static const struct rpm_smd_clk_desc rpm_clk_msm8996 = { 789 .clks = msm8996_clks, 790 .num_clks = ARRAY_SIZE(msm8996_clks), 791 }; 792 793 DEFINE_CLK_SMD_RPM(qcs404, bimc_gpu_clk, bimc_gpu_a_clk, QCOM_SMD_RPM_MEM_CLK, 2); 794 DEFINE_CLK_SMD_RPM(qcs404, qpic_clk, qpic_a_clk, QCOM_SMD_RPM_QPIC_CLK, 0); 795 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(qcs404, ln_bb_clk_pin, ln_bb_clk_a_pin, 8, 19200000); 796 797 static struct clk_smd_rpm *qcs404_clks[] = { 798 [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk, 799 [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk, 800 [RPM_SMD_PNOC_CLK] = &msm8916_pcnoc_clk, 801 [RPM_SMD_PNOC_A_CLK] = &msm8916_pcnoc_a_clk, 802 [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk, 803 [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk, 804 [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, 805 [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, 806 [RPM_SMD_BIMC_GPU_CLK] = &qcs404_bimc_gpu_clk, 807 [RPM_SMD_BIMC_GPU_A_CLK] = &qcs404_bimc_gpu_a_clk, 808 [RPM_SMD_QPIC_CLK] = &qcs404_qpic_clk, 809 [RPM_SMD_QPIC_CLK_A] = &qcs404_qpic_a_clk, 810 [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk, 811 [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk, 812 [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1, 813 [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a, 814 [RPM_SMD_LN_BB_CLK] = &msm8992_ln_bb_clk, 815 [RPM_SMD_LN_BB_A_CLK] = &msm8992_ln_bb_a_clk, 816 }; 817 818 static const struct rpm_smd_clk_desc rpm_clk_qcs404 = { 819 .clks = qcs404_clks, 820 .num_clks = ARRAY_SIZE(qcs404_clks), 821 }; 822 823 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, ln_bb_clk3_pin, ln_bb_clk3_a_pin, 824 3, 19200000); 825 DEFINE_CLK_SMD_RPM(msm8998, aggre1_noc_clk, aggre1_noc_a_clk, 826 QCOM_SMD_RPM_AGGR_CLK, 1); 827 DEFINE_CLK_SMD_RPM(msm8998, aggre2_noc_clk, aggre2_noc_a_clk, 828 QCOM_SMD_RPM_AGGR_CLK, 2); 829 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, rf_clk3, rf_clk3_a, 6, 19200000); 830 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, rf_clk3_pin, rf_clk3_a_pin, 6, 19200000); 831 static struct clk_smd_rpm *msm8998_clks[] = { 832 [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, 833 [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, 834 [RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk, 835 [RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk, 836 [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk, 837 [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk, 838 [RPM_SMD_CNOC_CLK] = &msm8974_cnoc_clk, 839 [RPM_SMD_CNOC_A_CLK] = &msm8974_cnoc_a_clk, 840 [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk, 841 [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk, 842 [RPM_SMD_DIV_CLK1] = &msm8974_div_clk1, 843 [RPM_SMD_DIV_A_CLK1] = &msm8974_div_a_clk1, 844 [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk, 845 [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk, 846 [RPM_SMD_LN_BB_CLK1] = &msm8916_bb_clk1, 847 [RPM_SMD_LN_BB_CLK1_A] = &msm8916_bb_clk1_a, 848 [RPM_SMD_LN_BB_CLK2] = &msm8916_bb_clk2, 849 [RPM_SMD_LN_BB_CLK2_A] = &msm8916_bb_clk2_a, 850 [RPM_SMD_LN_BB_CLK3_PIN] = &msm8998_ln_bb_clk3_pin, 851 [RPM_SMD_LN_BB_CLK3_A_PIN] = &msm8998_ln_bb_clk3_a_pin, 852 [RPM_SMD_MMAXI_CLK] = &msm8996_mmssnoc_axi_rpm_clk, 853 [RPM_SMD_MMAXI_A_CLK] = &msm8996_mmssnoc_axi_rpm_a_clk, 854 [RPM_SMD_AGGR1_NOC_CLK] = &msm8998_aggre1_noc_clk, 855 [RPM_SMD_AGGR1_NOC_A_CLK] = &msm8998_aggre1_noc_a_clk, 856 [RPM_SMD_AGGR2_NOC_CLK] = &msm8998_aggre2_noc_clk, 857 [RPM_SMD_AGGR2_NOC_A_CLK] = &msm8998_aggre2_noc_a_clk, 858 [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk, 859 [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk, 860 [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1, 861 [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a, 862 [RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin, 863 [RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin, 864 [RPM_SMD_RF_CLK3] = &msm8998_rf_clk3, 865 [RPM_SMD_RF_CLK3_A] = &msm8998_rf_clk3_a, 866 [RPM_SMD_RF_CLK3_PIN] = &msm8998_rf_clk3_pin, 867 [RPM_SMD_RF_CLK3_A_PIN] = &msm8998_rf_clk3_a_pin, 868 }; 869 870 static const struct rpm_smd_clk_desc rpm_clk_msm8998 = { 871 .clks = msm8998_clks, 872 .num_clks = ARRAY_SIZE(msm8998_clks), 873 }; 874 875 DEFINE_CLK_SMD_RPM_BRANCH(sdm660, bi_tcxo, bi_tcxo_a, QCOM_SMD_RPM_MISC_CLK, 0, 876 19200000); 877 DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, ln_bb_clk3, ln_bb_clk3_a, 3, 19200000); 878 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, ln_bb_clk3_pin, ln_bb_clk3_pin_a, 3, 19200000); 879 880 static struct clk_smd_rpm *sdm660_clks[] = { 881 [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo, 882 [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a, 883 [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk, 884 [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk, 885 [RPM_SMD_CNOC_CLK] = &msm8974_cnoc_clk, 886 [RPM_SMD_CNOC_A_CLK] = &msm8974_cnoc_a_clk, 887 [RPM_SMD_CNOC_PERIPH_CLK] = &msm8916_pcnoc_clk, 888 [RPM_SMD_CNOC_PERIPH_A_CLK] = &msm8916_pcnoc_a_clk, 889 [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, 890 [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, 891 [RPM_SMD_MMSSNOC_AXI_CLK] = &msm8996_mmssnoc_axi_rpm_clk, 892 [RPM_SMD_MMSSNOC_AXI_CLK_A] = &msm8996_mmssnoc_axi_rpm_a_clk, 893 [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk, 894 [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk, 895 [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk, 896 [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk, 897 [RPM_SMD_AGGR2_NOC_CLK] = &msm8998_aggre2_noc_clk, 898 [RPM_SMD_AGGR2_NOC_A_CLK] = &msm8998_aggre2_noc_a_clk, 899 [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk, 900 [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk, 901 [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1, 902 [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a, 903 [RPM_SMD_DIV_CLK1] = &msm8974_div_clk1, 904 [RPM_SMD_DIV_A_CLK1] = &msm8974_div_a_clk1, 905 [RPM_SMD_LN_BB_CLK] = &msm8916_bb_clk1, 906 [RPM_SMD_LN_BB_A_CLK] = &msm8916_bb_clk1_a, 907 [RPM_SMD_LN_BB_CLK2] = &msm8916_bb_clk2, 908 [RPM_SMD_LN_BB_CLK2_A] = &msm8916_bb_clk2_a, 909 [RPM_SMD_LN_BB_CLK3] = &sdm660_ln_bb_clk3, 910 [RPM_SMD_LN_BB_CLK3_A] = &sdm660_ln_bb_clk3_a, 911 [RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin, 912 [RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin, 913 [RPM_SMD_LN_BB_CLK1_PIN] = &msm8916_bb_clk1_pin, 914 [RPM_SMD_LN_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin, 915 [RPM_SMD_LN_BB_CLK2_PIN] = &msm8916_bb_clk2_pin, 916 [RPM_SMD_LN_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin, 917 [RPM_SMD_LN_BB_CLK3_PIN] = &sdm660_ln_bb_clk3_pin, 918 [RPM_SMD_LN_BB_CLK3_A_PIN] = &sdm660_ln_bb_clk3_pin_a, 919 }; 920 921 static const struct rpm_smd_clk_desc rpm_clk_sdm660 = { 922 .clks = sdm660_clks, 923 .num_clks = ARRAY_SIZE(sdm660_clks), 924 }; 925 926 static struct clk_smd_rpm *mdm9607_clks[] = { 927 [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo, 928 [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a, 929 [RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk, 930 [RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk, 931 [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, 932 [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, 933 [RPM_SMD_QPIC_CLK] = &qcs404_qpic_clk, 934 [RPM_SMD_QPIC_CLK_A] = &qcs404_qpic_a_clk, 935 [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk, 936 [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk, 937 [RPM_SMD_BB_CLK1] = &msm8916_bb_clk1, 938 [RPM_SMD_BB_CLK1_A] = &msm8916_bb_clk1_a, 939 [RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin, 940 [RPM_SMD_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin, 941 }; 942 943 static const struct rpm_smd_clk_desc rpm_clk_mdm9607 = { 944 .clks = mdm9607_clks, 945 .num_clks = ARRAY_SIZE(mdm9607_clks), 946 }; 947 948 static struct clk_smd_rpm *msm8953_clks[] = { 949 [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo, 950 [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a, 951 [RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk, 952 [RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk, 953 [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk, 954 [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk, 955 [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, 956 [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, 957 [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk, 958 [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk, 959 [RPM_SMD_SYSMMNOC_CLK] = &msm8936_sysmmnoc_clk, 960 [RPM_SMD_SYSMMNOC_A_CLK] = &msm8936_sysmmnoc_a_clk, 961 [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk, 962 [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk, 963 [RPM_SMD_BB_CLK1] = &msm8916_bb_clk1, 964 [RPM_SMD_BB_CLK1_A] = &msm8916_bb_clk1_a, 965 [RPM_SMD_BB_CLK2] = &msm8916_bb_clk2, 966 [RPM_SMD_BB_CLK2_A] = &msm8916_bb_clk2_a, 967 [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2, 968 [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a, 969 [RPM_SMD_RF_CLK3] = &msm8992_ln_bb_clk, 970 [RPM_SMD_RF_CLK3_A] = &msm8992_ln_bb_a_clk, 971 [RPM_SMD_DIV_CLK2] = &msm8974_div_clk2, 972 [RPM_SMD_DIV_A_CLK2] = &msm8974_div_a_clk2, 973 [RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin, 974 [RPM_SMD_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin, 975 [RPM_SMD_BB_CLK2_PIN] = &msm8916_bb_clk2_pin, 976 [RPM_SMD_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin, 977 }; 978 979 static const struct rpm_smd_clk_desc rpm_clk_msm8953 = { 980 .clks = msm8953_clks, 981 .num_clks = ARRAY_SIZE(msm8953_clks), 982 }; 983 984 /* SM6125 */ 985 DEFINE_CLK_SMD_RPM(sm6125, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1); 986 DEFINE_CLK_SMD_RPM(sm6125, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2); 987 DEFINE_CLK_SMD_RPM_BRANCH(sm6125, qdss_clk, qdss_a_clk, 988 QCOM_SMD_RPM_MISC_CLK, 1, 19200000); 989 DEFINE_CLK_SMD_RPM(sm6125, qup_clk, qup_a_clk, QCOM_SMD_RPM_QUP_CLK, 0); 990 DEFINE_CLK_SMD_RPM(sm6125, mmnrt_clk, mmnrt_a_clk, QCOM_SMD_RPM_MMAXI_CLK, 0); 991 DEFINE_CLK_SMD_RPM(sm6125, mmrt_clk, mmrt_a_clk, QCOM_SMD_RPM_MMAXI_CLK, 1); 992 DEFINE_CLK_SMD_RPM(sm6125, snoc_periph_clk, snoc_periph_a_clk, 993 QCOM_SMD_RPM_BUS_CLK, 0); 994 DEFINE_CLK_SMD_RPM(sm6125, snoc_lpass_clk, snoc_lpass_a_clk, 995 QCOM_SMD_RPM_BUS_CLK, 5); 996 997 static struct clk_smd_rpm *sm6125_clks[] = { 998 [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo, 999 [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a, 1000 [RPM_SMD_SNOC_CLK] = &sm6125_snoc_clk, 1001 [RPM_SMD_SNOC_A_CLK] = &sm6125_snoc_a_clk, 1002 [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, 1003 [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, 1004 [RPM_SMD_QDSS_CLK] = &sm6125_qdss_clk, 1005 [RPM_SMD_QDSS_A_CLK] = &sm6125_qdss_a_clk, 1006 [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1, 1007 [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a, 1008 [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2, 1009 [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a, 1010 [RPM_SMD_CNOC_CLK] = &sm6125_cnoc_clk, 1011 [RPM_SMD_CNOC_A_CLK] = &sm6125_cnoc_a_clk, 1012 [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk, 1013 [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk, 1014 [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk, 1015 [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk, 1016 [RPM_SMD_LN_BB_CLK1] = &msm8916_bb_clk1, 1017 [RPM_SMD_LN_BB_CLK1_A] = &msm8916_bb_clk1_a, 1018 [RPM_SMD_LN_BB_CLK2] = &msm8916_bb_clk2, 1019 [RPM_SMD_LN_BB_CLK2_A] = &msm8916_bb_clk2_a, 1020 [RPM_SMD_LN_BB_CLK3] = &sdm660_ln_bb_clk3, 1021 [RPM_SMD_LN_BB_CLK3_A] = &sdm660_ln_bb_clk3_a, 1022 [RPM_SMD_QUP_CLK] = &sm6125_qup_clk, 1023 [RPM_SMD_QUP_A_CLK] = &sm6125_qup_a_clk, 1024 [RPM_SMD_MMRT_CLK] = &sm6125_mmrt_clk, 1025 [RPM_SMD_MMRT_A_CLK] = &sm6125_mmrt_a_clk, 1026 [RPM_SMD_MMNRT_CLK] = &sm6125_mmnrt_clk, 1027 [RPM_SMD_MMNRT_A_CLK] = &sm6125_mmnrt_a_clk, 1028 [RPM_SMD_SNOC_PERIPH_CLK] = &sm6125_snoc_periph_clk, 1029 [RPM_SMD_SNOC_PERIPH_A_CLK] = &sm6125_snoc_periph_a_clk, 1030 [RPM_SMD_SNOC_LPASS_CLK] = &sm6125_snoc_lpass_clk, 1031 [RPM_SMD_SNOC_LPASS_A_CLK] = &sm6125_snoc_lpass_a_clk, 1032 }; 1033 1034 static const struct rpm_smd_clk_desc rpm_clk_sm6125 = { 1035 .clks = sm6125_clks, 1036 .num_clks = ARRAY_SIZE(sm6125_clks), 1037 }; 1038 1039 /* SM6115 */ 1040 static struct clk_smd_rpm *sm6115_clks[] = { 1041 [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo, 1042 [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a, 1043 [RPM_SMD_SNOC_CLK] = &sm6125_snoc_clk, 1044 [RPM_SMD_SNOC_A_CLK] = &sm6125_snoc_a_clk, 1045 [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, 1046 [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, 1047 [RPM_SMD_QDSS_CLK] = &sm6125_qdss_clk, 1048 [RPM_SMD_QDSS_A_CLK] = &sm6125_qdss_a_clk, 1049 [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1, 1050 [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a, 1051 [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2, 1052 [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a, 1053 [RPM_SMD_CNOC_CLK] = &sm6125_cnoc_clk, 1054 [RPM_SMD_CNOC_A_CLK] = &sm6125_cnoc_a_clk, 1055 [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk, 1056 [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk, 1057 [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk, 1058 [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk, 1059 [RPM_SMD_QUP_CLK] = &sm6125_qup_clk, 1060 [RPM_SMD_QUP_A_CLK] = &sm6125_qup_a_clk, 1061 [RPM_SMD_MMRT_CLK] = &sm6125_mmrt_clk, 1062 [RPM_SMD_MMRT_A_CLK] = &sm6125_mmrt_a_clk, 1063 [RPM_SMD_MMNRT_CLK] = &sm6125_mmnrt_clk, 1064 [RPM_SMD_MMNRT_A_CLK] = &sm6125_mmnrt_a_clk, 1065 [RPM_SMD_SNOC_PERIPH_CLK] = &sm6125_snoc_periph_clk, 1066 [RPM_SMD_SNOC_PERIPH_A_CLK] = &sm6125_snoc_periph_a_clk, 1067 [RPM_SMD_SNOC_LPASS_CLK] = &sm6125_snoc_lpass_clk, 1068 [RPM_SMD_SNOC_LPASS_A_CLK] = &sm6125_snoc_lpass_a_clk, 1069 [RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin, 1070 [RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin, 1071 [RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin, 1072 [RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin, 1073 }; 1074 1075 static const struct rpm_smd_clk_desc rpm_clk_sm6115 = { 1076 .clks = sm6115_clks, 1077 .num_clks = ARRAY_SIZE(sm6115_clks), 1078 }; 1079 1080 /* QCM2290 */ 1081 DEFINE_CLK_SMD_RPM_XO_BUFFER(qcm2290, ln_bb_clk2, ln_bb_clk2_a, 0x2, 19200000); 1082 DEFINE_CLK_SMD_RPM_XO_BUFFER(qcm2290, rf_clk3, rf_clk3_a, 6, 38400000); 1083 1084 DEFINE_CLK_SMD_RPM(qcm2290, qpic_clk, qpic_a_clk, QCOM_SMD_RPM_QPIC_CLK, 0); 1085 DEFINE_CLK_SMD_RPM(qcm2290, hwkm_clk, hwkm_a_clk, QCOM_SMD_RPM_HWKM_CLK, 0); 1086 DEFINE_CLK_SMD_RPM(qcm2290, pka_clk, pka_a_clk, QCOM_SMD_RPM_PKA_CLK, 0); 1087 DEFINE_CLK_SMD_RPM(qcm2290, cpuss_gnoc_clk, cpuss_gnoc_a_clk, 1088 QCOM_SMD_RPM_MEM_CLK, 1); 1089 DEFINE_CLK_SMD_RPM(qcm2290, bimc_gpu_clk, bimc_gpu_a_clk, 1090 QCOM_SMD_RPM_MEM_CLK, 2); 1091 1092 static struct clk_smd_rpm *qcm2290_clks[] = { 1093 [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo, 1094 [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a, 1095 [RPM_SMD_SNOC_CLK] = &sm6125_snoc_clk, 1096 [RPM_SMD_SNOC_A_CLK] = &sm6125_snoc_a_clk, 1097 [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, 1098 [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, 1099 [RPM_SMD_QDSS_CLK] = &sm6125_qdss_clk, 1100 [RPM_SMD_QDSS_A_CLK] = &sm6125_qdss_a_clk, 1101 [RPM_SMD_LN_BB_CLK2] = &qcm2290_ln_bb_clk2, 1102 [RPM_SMD_LN_BB_CLK2_A] = &qcm2290_ln_bb_clk2_a, 1103 [RPM_SMD_RF_CLK3] = &qcm2290_rf_clk3, 1104 [RPM_SMD_RF_CLK3_A] = &qcm2290_rf_clk3_a, 1105 [RPM_SMD_CNOC_CLK] = &sm6125_cnoc_clk, 1106 [RPM_SMD_CNOC_A_CLK] = &sm6125_cnoc_a_clk, 1107 [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk, 1108 [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk, 1109 [RPM_SMD_QUP_CLK] = &sm6125_qup_clk, 1110 [RPM_SMD_QUP_A_CLK] = &sm6125_qup_a_clk, 1111 [RPM_SMD_MMRT_CLK] = &sm6125_mmrt_clk, 1112 [RPM_SMD_MMRT_A_CLK] = &sm6125_mmrt_a_clk, 1113 [RPM_SMD_MMNRT_CLK] = &sm6125_mmnrt_clk, 1114 [RPM_SMD_MMNRT_A_CLK] = &sm6125_mmnrt_a_clk, 1115 [RPM_SMD_SNOC_PERIPH_CLK] = &sm6125_snoc_periph_clk, 1116 [RPM_SMD_SNOC_PERIPH_A_CLK] = &sm6125_snoc_periph_a_clk, 1117 [RPM_SMD_SNOC_LPASS_CLK] = &sm6125_snoc_lpass_clk, 1118 [RPM_SMD_SNOC_LPASS_A_CLK] = &sm6125_snoc_lpass_a_clk, 1119 [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk, 1120 [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk, 1121 [RPM_SMD_QPIC_CLK] = &qcm2290_qpic_clk, 1122 [RPM_SMD_QPIC_CLK_A] = &qcm2290_qpic_a_clk, 1123 [RPM_SMD_HWKM_CLK] = &qcm2290_hwkm_clk, 1124 [RPM_SMD_HWKM_A_CLK] = &qcm2290_hwkm_a_clk, 1125 [RPM_SMD_PKA_CLK] = &qcm2290_pka_clk, 1126 [RPM_SMD_PKA_A_CLK] = &qcm2290_pka_a_clk, 1127 [RPM_SMD_BIMC_GPU_CLK] = &qcm2290_bimc_gpu_clk, 1128 [RPM_SMD_BIMC_GPU_A_CLK] = &qcm2290_bimc_gpu_a_clk, 1129 [RPM_SMD_CPUSS_GNOC_CLK] = &qcm2290_cpuss_gnoc_clk, 1130 [RPM_SMD_CPUSS_GNOC_A_CLK] = &qcm2290_cpuss_gnoc_a_clk, 1131 }; 1132 1133 static const struct rpm_smd_clk_desc rpm_clk_qcm2290 = { 1134 .clks = qcm2290_clks, 1135 .num_clks = ARRAY_SIZE(qcm2290_clks), 1136 }; 1137 1138 static const struct of_device_id rpm_smd_clk_match_table[] = { 1139 { .compatible = "qcom,rpmcc-mdm9607", .data = &rpm_clk_mdm9607 }, 1140 { .compatible = "qcom,rpmcc-msm8226", .data = &rpm_clk_msm8974 }, 1141 { .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916 }, 1142 { .compatible = "qcom,rpmcc-msm8936", .data = &rpm_clk_msm8936 }, 1143 { .compatible = "qcom,rpmcc-msm8953", .data = &rpm_clk_msm8953 }, 1144 { .compatible = "qcom,rpmcc-msm8974", .data = &rpm_clk_msm8974 }, 1145 { .compatible = "qcom,rpmcc-msm8976", .data = &rpm_clk_msm8976 }, 1146 { .compatible = "qcom,rpmcc-msm8992", .data = &rpm_clk_msm8992 }, 1147 { .compatible = "qcom,rpmcc-msm8994", .data = &rpm_clk_msm8994 }, 1148 { .compatible = "qcom,rpmcc-msm8996", .data = &rpm_clk_msm8996 }, 1149 { .compatible = "qcom,rpmcc-msm8998", .data = &rpm_clk_msm8998 }, 1150 { .compatible = "qcom,rpmcc-qcm2290", .data = &rpm_clk_qcm2290 }, 1151 { .compatible = "qcom,rpmcc-qcs404", .data = &rpm_clk_qcs404 }, 1152 { .compatible = "qcom,rpmcc-sdm660", .data = &rpm_clk_sdm660 }, 1153 { .compatible = "qcom,rpmcc-sm6115", .data = &rpm_clk_sm6115 }, 1154 { .compatible = "qcom,rpmcc-sm6125", .data = &rpm_clk_sm6125 }, 1155 { } 1156 }; 1157 MODULE_DEVICE_TABLE(of, rpm_smd_clk_match_table); 1158 1159 static struct clk_hw *qcom_smdrpm_clk_hw_get(struct of_phandle_args *clkspec, 1160 void *data) 1161 { 1162 struct rpm_cc *rcc = data; 1163 unsigned int idx = clkspec->args[0]; 1164 1165 if (idx >= rcc->num_clks) { 1166 pr_err("%s: invalid index %u\n", __func__, idx); 1167 return ERR_PTR(-EINVAL); 1168 } 1169 1170 return rcc->clks[idx] ? &rcc->clks[idx]->hw : ERR_PTR(-ENOENT); 1171 } 1172 1173 static int rpm_smd_clk_probe(struct platform_device *pdev) 1174 { 1175 struct rpm_cc *rcc; 1176 int ret; 1177 size_t num_clks, i; 1178 struct qcom_smd_rpm *rpm; 1179 struct clk_smd_rpm **rpm_smd_clks; 1180 const struct rpm_smd_clk_desc *desc; 1181 1182 rpm = dev_get_drvdata(pdev->dev.parent); 1183 if (!rpm) { 1184 dev_err(&pdev->dev, "Unable to retrieve handle to RPM\n"); 1185 return -ENODEV; 1186 } 1187 1188 desc = of_device_get_match_data(&pdev->dev); 1189 if (!desc) 1190 return -EINVAL; 1191 1192 rpm_smd_clks = desc->clks; 1193 num_clks = desc->num_clks; 1194 1195 rcc = devm_kzalloc(&pdev->dev, sizeof(*rcc), GFP_KERNEL); 1196 if (!rcc) 1197 return -ENOMEM; 1198 1199 rcc->clks = rpm_smd_clks; 1200 rcc->num_clks = num_clks; 1201 1202 for (i = 0; i < num_clks; i++) { 1203 if (!rpm_smd_clks[i]) 1204 continue; 1205 1206 rpm_smd_clks[i]->rpm = rpm; 1207 1208 ret = clk_smd_rpm_handoff(rpm_smd_clks[i]); 1209 if (ret) 1210 goto err; 1211 } 1212 1213 ret = clk_smd_rpm_enable_scaling(rpm); 1214 if (ret) 1215 goto err; 1216 1217 for (i = 0; i < num_clks; i++) { 1218 if (!rpm_smd_clks[i]) 1219 continue; 1220 1221 ret = devm_clk_hw_register(&pdev->dev, &rpm_smd_clks[i]->hw); 1222 if (ret) 1223 goto err; 1224 } 1225 1226 ret = devm_of_clk_add_hw_provider(&pdev->dev, qcom_smdrpm_clk_hw_get, 1227 rcc); 1228 if (ret) 1229 goto err; 1230 1231 return 0; 1232 err: 1233 dev_err(&pdev->dev, "Error registering SMD clock driver (%d)\n", ret); 1234 return ret; 1235 } 1236 1237 static struct platform_driver rpm_smd_clk_driver = { 1238 .driver = { 1239 .name = "qcom-clk-smd-rpm", 1240 .of_match_table = rpm_smd_clk_match_table, 1241 }, 1242 .probe = rpm_smd_clk_probe, 1243 }; 1244 1245 static int __init rpm_smd_clk_init(void) 1246 { 1247 return platform_driver_register(&rpm_smd_clk_driver); 1248 } 1249 core_initcall(rpm_smd_clk_init); 1250 1251 static void __exit rpm_smd_clk_exit(void) 1252 { 1253 platform_driver_unregister(&rpm_smd_clk_driver); 1254 } 1255 module_exit(rpm_smd_clk_exit); 1256 1257 MODULE_DESCRIPTION("Qualcomm RPM over SMD Clock Controller Driver"); 1258 MODULE_LICENSE("GPL v2"); 1259 MODULE_ALIAS("platform:qcom-clk-smd-rpm"); 1260