1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/err.h> 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/of.h> 11 #include <linux/of_device.h> 12 #include <linux/platform_device.h> 13 #include <soc/qcom/cmd-db.h> 14 #include <soc/qcom/rpmh.h> 15 #include <soc/qcom/tcs.h> 16 17 #include <dt-bindings/clock/qcom,rpmh.h> 18 19 #define CLK_RPMH_ARC_EN_OFFSET 0 20 #define CLK_RPMH_VRM_EN_OFFSET 4 21 22 /** 23 * struct bcm_db - Auxiliary data pertaining to each Bus Clock Manager(BCM) 24 * @unit: divisor used to convert Hz value to an RPMh msg 25 * @width: multiplier used to convert Hz value to an RPMh msg 26 * @vcd: virtual clock domain that this bcm belongs to 27 * @reserved: reserved to pad the struct 28 */ 29 struct bcm_db { 30 __le32 unit; 31 __le16 width; 32 u8 vcd; 33 u8 reserved; 34 }; 35 36 /** 37 * struct clk_rpmh - individual rpmh clock data structure 38 * @hw: handle between common and hardware-specific interfaces 39 * @res_name: resource name for the rpmh clock 40 * @div: clock divider to compute the clock rate 41 * @res_addr: base address of the rpmh resource within the RPMh 42 * @res_on_val: rpmh clock enable value 43 * @state: rpmh clock requested state 44 * @aggr_state: rpmh clock aggregated state 45 * @last_sent_aggr_state: rpmh clock last aggr state sent to RPMh 46 * @valid_state_mask: mask to determine the state of the rpmh clock 47 * @unit: divisor to convert rate to rpmh msg in magnitudes of Khz 48 * @dev: device to which it is attached 49 * @peer: pointer to the clock rpmh sibling 50 */ 51 struct clk_rpmh { 52 struct clk_hw hw; 53 const char *res_name; 54 u8 div; 55 u32 res_addr; 56 u32 res_on_val; 57 u32 state; 58 u32 aggr_state; 59 u32 last_sent_aggr_state; 60 u32 valid_state_mask; 61 u32 unit; 62 struct device *dev; 63 struct clk_rpmh *peer; 64 }; 65 66 struct clk_rpmh_desc { 67 struct clk_hw **clks; 68 size_t num_clks; 69 }; 70 71 static DEFINE_MUTEX(rpmh_clk_lock); 72 73 #define __DEFINE_CLK_RPMH(_name, _clk_name, _res_name, \ 74 _res_en_offset, _res_on, _div) \ 75 static struct clk_rpmh clk_rpmh_##_clk_name##_ao; \ 76 static struct clk_rpmh clk_rpmh_##_clk_name = { \ 77 .res_name = _res_name, \ 78 .res_addr = _res_en_offset, \ 79 .res_on_val = _res_on, \ 80 .div = _div, \ 81 .peer = &clk_rpmh_##_clk_name##_ao, \ 82 .valid_state_mask = (BIT(RPMH_WAKE_ONLY_STATE) | \ 83 BIT(RPMH_ACTIVE_ONLY_STATE) | \ 84 BIT(RPMH_SLEEP_STATE)), \ 85 .hw.init = &(struct clk_init_data){ \ 86 .ops = &clk_rpmh_ops, \ 87 .name = #_name, \ 88 .parent_data = &(const struct clk_parent_data){ \ 89 .fw_name = "xo", \ 90 .name = "xo_board", \ 91 }, \ 92 .num_parents = 1, \ 93 }, \ 94 }; \ 95 static struct clk_rpmh clk_rpmh_##_clk_name##_ao= { \ 96 .res_name = _res_name, \ 97 .res_addr = _res_en_offset, \ 98 .res_on_val = _res_on, \ 99 .div = _div, \ 100 .peer = &clk_rpmh_##_clk_name, \ 101 .valid_state_mask = (BIT(RPMH_WAKE_ONLY_STATE) | \ 102 BIT(RPMH_ACTIVE_ONLY_STATE)), \ 103 .hw.init = &(struct clk_init_data){ \ 104 .ops = &clk_rpmh_ops, \ 105 .name = #_name "_ao", \ 106 .parent_data = &(const struct clk_parent_data){ \ 107 .fw_name = "xo", \ 108 .name = "xo_board", \ 109 }, \ 110 .num_parents = 1, \ 111 }, \ 112 } 113 114 #define DEFINE_CLK_RPMH_ARC(_name, _res_name, _res_on, _div) \ 115 __DEFINE_CLK_RPMH(_name, _name##_##div##_div, _res_name, \ 116 CLK_RPMH_ARC_EN_OFFSET, _res_on, _div) 117 118 #define DEFINE_CLK_RPMH_VRM(_name, _suffix, _res_name, _div) \ 119 __DEFINE_CLK_RPMH(_name, _name##_suffix, _res_name, \ 120 CLK_RPMH_VRM_EN_OFFSET, 1, _div) 121 122 #define DEFINE_CLK_RPMH_BCM(_name, _res_name) \ 123 static struct clk_rpmh clk_rpmh_##_name = { \ 124 .res_name = _res_name, \ 125 .valid_state_mask = BIT(RPMH_ACTIVE_ONLY_STATE), \ 126 .div = 1, \ 127 .hw.init = &(struct clk_init_data){ \ 128 .ops = &clk_rpmh_bcm_ops, \ 129 .name = #_name, \ 130 }, \ 131 } 132 133 static inline struct clk_rpmh *to_clk_rpmh(struct clk_hw *_hw) 134 { 135 return container_of(_hw, struct clk_rpmh, hw); 136 } 137 138 static inline bool has_state_changed(struct clk_rpmh *c, u32 state) 139 { 140 return (c->last_sent_aggr_state & BIT(state)) 141 != (c->aggr_state & BIT(state)); 142 } 143 144 static int clk_rpmh_send(struct clk_rpmh *c, enum rpmh_state state, 145 struct tcs_cmd *cmd, bool wait) 146 { 147 if (wait) 148 return rpmh_write(c->dev, state, cmd, 1); 149 150 return rpmh_write_async(c->dev, state, cmd, 1); 151 } 152 153 static int clk_rpmh_send_aggregate_command(struct clk_rpmh *c) 154 { 155 struct tcs_cmd cmd = { 0 }; 156 u32 cmd_state, on_val; 157 enum rpmh_state state = RPMH_SLEEP_STATE; 158 int ret; 159 bool wait; 160 161 cmd.addr = c->res_addr; 162 cmd_state = c->aggr_state; 163 on_val = c->res_on_val; 164 165 for (; state <= RPMH_ACTIVE_ONLY_STATE; state++) { 166 if (has_state_changed(c, state)) { 167 if (cmd_state & BIT(state)) 168 cmd.data = on_val; 169 170 wait = cmd_state && state == RPMH_ACTIVE_ONLY_STATE; 171 ret = clk_rpmh_send(c, state, &cmd, wait); 172 if (ret) { 173 dev_err(c->dev, "set %s state of %s failed: (%d)\n", 174 !state ? "sleep" : 175 state == RPMH_WAKE_ONLY_STATE ? 176 "wake" : "active", c->res_name, ret); 177 return ret; 178 } 179 } 180 } 181 182 c->last_sent_aggr_state = c->aggr_state; 183 c->peer->last_sent_aggr_state = c->last_sent_aggr_state; 184 185 return 0; 186 } 187 188 /* 189 * Update state and aggregate state values based on enable value. 190 */ 191 static int clk_rpmh_aggregate_state_send_command(struct clk_rpmh *c, 192 bool enable) 193 { 194 int ret; 195 196 c->state = enable ? c->valid_state_mask : 0; 197 c->aggr_state = c->state | c->peer->state; 198 c->peer->aggr_state = c->aggr_state; 199 200 ret = clk_rpmh_send_aggregate_command(c); 201 if (!ret) 202 return 0; 203 204 if (ret && enable) 205 c->state = 0; 206 else if (ret) 207 c->state = c->valid_state_mask; 208 209 WARN(1, "clk: %s failed to %s\n", c->res_name, 210 enable ? "enable" : "disable"); 211 return ret; 212 } 213 214 static int clk_rpmh_prepare(struct clk_hw *hw) 215 { 216 struct clk_rpmh *c = to_clk_rpmh(hw); 217 int ret = 0; 218 219 mutex_lock(&rpmh_clk_lock); 220 ret = clk_rpmh_aggregate_state_send_command(c, true); 221 mutex_unlock(&rpmh_clk_lock); 222 223 return ret; 224 } 225 226 static void clk_rpmh_unprepare(struct clk_hw *hw) 227 { 228 struct clk_rpmh *c = to_clk_rpmh(hw); 229 230 mutex_lock(&rpmh_clk_lock); 231 clk_rpmh_aggregate_state_send_command(c, false); 232 mutex_unlock(&rpmh_clk_lock); 233 }; 234 235 static unsigned long clk_rpmh_recalc_rate(struct clk_hw *hw, 236 unsigned long prate) 237 { 238 struct clk_rpmh *r = to_clk_rpmh(hw); 239 240 /* 241 * RPMh clocks have a fixed rate. Return static rate. 242 */ 243 return prate / r->div; 244 } 245 246 static const struct clk_ops clk_rpmh_ops = { 247 .prepare = clk_rpmh_prepare, 248 .unprepare = clk_rpmh_unprepare, 249 .recalc_rate = clk_rpmh_recalc_rate, 250 }; 251 252 static int clk_rpmh_bcm_send_cmd(struct clk_rpmh *c, bool enable) 253 { 254 struct tcs_cmd cmd = { 0 }; 255 u32 cmd_state; 256 int ret = 0; 257 258 mutex_lock(&rpmh_clk_lock); 259 if (enable) { 260 cmd_state = 1; 261 if (c->aggr_state) 262 cmd_state = c->aggr_state; 263 } else { 264 cmd_state = 0; 265 } 266 267 if (c->last_sent_aggr_state != cmd_state) { 268 cmd.addr = c->res_addr; 269 cmd.data = BCM_TCS_CMD(1, enable, 0, cmd_state); 270 271 /* 272 * Send only an active only state request. RPMh continues to 273 * use the active state when we're in sleep/wake state as long 274 * as the sleep/wake state has never been set. 275 */ 276 ret = clk_rpmh_send(c, RPMH_ACTIVE_ONLY_STATE, &cmd, enable); 277 if (ret) { 278 dev_err(c->dev, "set active state of %s failed: (%d)\n", 279 c->res_name, ret); 280 } else { 281 c->last_sent_aggr_state = cmd_state; 282 } 283 } 284 285 mutex_unlock(&rpmh_clk_lock); 286 287 return ret; 288 } 289 290 static int clk_rpmh_bcm_prepare(struct clk_hw *hw) 291 { 292 struct clk_rpmh *c = to_clk_rpmh(hw); 293 294 return clk_rpmh_bcm_send_cmd(c, true); 295 } 296 297 static void clk_rpmh_bcm_unprepare(struct clk_hw *hw) 298 { 299 struct clk_rpmh *c = to_clk_rpmh(hw); 300 301 clk_rpmh_bcm_send_cmd(c, false); 302 } 303 304 static int clk_rpmh_bcm_set_rate(struct clk_hw *hw, unsigned long rate, 305 unsigned long parent_rate) 306 { 307 struct clk_rpmh *c = to_clk_rpmh(hw); 308 309 c->aggr_state = rate / c->unit; 310 /* 311 * Since any non-zero value sent to hw would result in enabling the 312 * clock, only send the value if the clock has already been prepared. 313 */ 314 if (clk_hw_is_prepared(hw)) 315 clk_rpmh_bcm_send_cmd(c, true); 316 317 return 0; 318 } 319 320 static long clk_rpmh_round_rate(struct clk_hw *hw, unsigned long rate, 321 unsigned long *parent_rate) 322 { 323 return rate; 324 } 325 326 static unsigned long clk_rpmh_bcm_recalc_rate(struct clk_hw *hw, 327 unsigned long prate) 328 { 329 struct clk_rpmh *c = to_clk_rpmh(hw); 330 331 return c->aggr_state * c->unit; 332 } 333 334 static const struct clk_ops clk_rpmh_bcm_ops = { 335 .prepare = clk_rpmh_bcm_prepare, 336 .unprepare = clk_rpmh_bcm_unprepare, 337 .set_rate = clk_rpmh_bcm_set_rate, 338 .round_rate = clk_rpmh_round_rate, 339 .recalc_rate = clk_rpmh_bcm_recalc_rate, 340 }; 341 342 /* Resource name must match resource id present in cmd-db */ 343 DEFINE_CLK_RPMH_ARC(bi_tcxo, "xo.lvl", 0x3, 1); 344 DEFINE_CLK_RPMH_ARC(bi_tcxo, "xo.lvl", 0x3, 2); 345 DEFINE_CLK_RPMH_ARC(bi_tcxo, "xo.lvl", 0x3, 4); 346 DEFINE_CLK_RPMH_ARC(qlink, "qphy.lvl", 0x1, 4); 347 348 DEFINE_CLK_RPMH_VRM(ln_bb_clk1, _a2, "lnbclka1", 2); 349 DEFINE_CLK_RPMH_VRM(ln_bb_clk2, _a2, "lnbclka2", 2); 350 DEFINE_CLK_RPMH_VRM(ln_bb_clk3, _a2, "lnbclka3", 2); 351 352 DEFINE_CLK_RPMH_VRM(ln_bb_clk1, _a4, "lnbclka1", 4); 353 DEFINE_CLK_RPMH_VRM(ln_bb_clk2, _a4, "lnbclka2", 4); 354 355 DEFINE_CLK_RPMH_VRM(ln_bb_clk2, _g4, "lnbclkg2", 4); 356 DEFINE_CLK_RPMH_VRM(ln_bb_clk3, _g4, "lnbclkg3", 4); 357 358 DEFINE_CLK_RPMH_VRM(rf_clk1, _a, "rfclka1", 1); 359 DEFINE_CLK_RPMH_VRM(rf_clk2, _a, "rfclka2", 1); 360 DEFINE_CLK_RPMH_VRM(rf_clk3, _a, "rfclka3", 1); 361 DEFINE_CLK_RPMH_VRM(rf_clk4, _a, "rfclka4", 1); 362 DEFINE_CLK_RPMH_VRM(rf_clk5, _a, "rfclka5", 1); 363 364 DEFINE_CLK_RPMH_VRM(rf_clk1, _d, "rfclkd1", 1); 365 DEFINE_CLK_RPMH_VRM(rf_clk2, _d, "rfclkd2", 1); 366 DEFINE_CLK_RPMH_VRM(rf_clk3, _d, "rfclkd3", 1); 367 DEFINE_CLK_RPMH_VRM(rf_clk4, _d, "rfclkd4", 1); 368 369 DEFINE_CLK_RPMH_VRM(clk1, _a1, "clka1", 1); 370 DEFINE_CLK_RPMH_VRM(clk2, _a1, "clka2", 1); 371 DEFINE_CLK_RPMH_VRM(clk3, _a1, "clka3", 1); 372 DEFINE_CLK_RPMH_VRM(clk4, _a1, "clka4", 1); 373 DEFINE_CLK_RPMH_VRM(clk5, _a1, "clka5", 1); 374 375 DEFINE_CLK_RPMH_VRM(clk6, _a2, "clka6", 2); 376 DEFINE_CLK_RPMH_VRM(clk7, _a2, "clka7", 2); 377 DEFINE_CLK_RPMH_VRM(clk8, _a2, "clka8", 2); 378 379 DEFINE_CLK_RPMH_VRM(div_clk1, _div2, "divclka1", 2); 380 381 DEFINE_CLK_RPMH_BCM(ce, "CE0"); 382 DEFINE_CLK_RPMH_BCM(hwkm, "HK0"); 383 DEFINE_CLK_RPMH_BCM(ipa, "IP0"); 384 DEFINE_CLK_RPMH_BCM(pka, "PKA0"); 385 DEFINE_CLK_RPMH_BCM(qpic_clk, "QP0"); 386 387 static struct clk_hw *sdm845_rpmh_clocks[] = { 388 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, 389 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, 390 [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw, 391 [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw, 392 [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw, 393 [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw, 394 [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, 395 [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, 396 [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw, 397 [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw, 398 [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw, 399 [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw, 400 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 401 [RPMH_CE_CLK] = &clk_rpmh_ce.hw, 402 }; 403 404 static const struct clk_rpmh_desc clk_rpmh_sdm845 = { 405 .clks = sdm845_rpmh_clocks, 406 .num_clks = ARRAY_SIZE(sdm845_rpmh_clocks), 407 }; 408 409 static struct clk_hw *sa8775p_rpmh_clocks[] = { 410 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, 411 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, 412 [RPMH_LN_BB_CLK1] = &clk_rpmh_ln_bb_clk1_a2.hw, 413 [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw, 414 [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a4_ao.hw, 415 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 416 [RPMH_PKA_CLK] = &clk_rpmh_pka.hw, 417 [RPMH_HWKM_CLK] = &clk_rpmh_hwkm.hw, 418 }; 419 420 static const struct clk_rpmh_desc clk_rpmh_sa8775p = { 421 .clks = sa8775p_rpmh_clocks, 422 .num_clks = ARRAY_SIZE(sa8775p_rpmh_clocks), 423 }; 424 425 static struct clk_hw *sdm670_rpmh_clocks[] = { 426 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, 427 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, 428 [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw, 429 [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw, 430 [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw, 431 [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw, 432 [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, 433 [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, 434 [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw, 435 [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw, 436 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 437 [RPMH_CE_CLK] = &clk_rpmh_ce.hw, 438 }; 439 440 static const struct clk_rpmh_desc clk_rpmh_sdm670 = { 441 .clks = sdm670_rpmh_clocks, 442 .num_clks = ARRAY_SIZE(sdm670_rpmh_clocks), 443 }; 444 445 static struct clk_hw *sdx55_rpmh_clocks[] = { 446 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, 447 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, 448 [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_d.hw, 449 [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_d_ao.hw, 450 [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_d.hw, 451 [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_d_ao.hw, 452 [RPMH_QPIC_CLK] = &clk_rpmh_qpic_clk.hw, 453 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 454 }; 455 456 static const struct clk_rpmh_desc clk_rpmh_sdx55 = { 457 .clks = sdx55_rpmh_clocks, 458 .num_clks = ARRAY_SIZE(sdx55_rpmh_clocks), 459 }; 460 461 static struct clk_hw *sm8150_rpmh_clocks[] = { 462 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, 463 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, 464 [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw, 465 [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw, 466 [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw, 467 [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw, 468 [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, 469 [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, 470 [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw, 471 [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw, 472 [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw, 473 [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw, 474 }; 475 476 static const struct clk_rpmh_desc clk_rpmh_sm8150 = { 477 .clks = sm8150_rpmh_clocks, 478 .num_clks = ARRAY_SIZE(sm8150_rpmh_clocks), 479 }; 480 481 static struct clk_hw *sc7180_rpmh_clocks[] = { 482 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, 483 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, 484 [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw, 485 [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw, 486 [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw, 487 [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw, 488 [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, 489 [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, 490 [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw, 491 [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw, 492 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 493 }; 494 495 static const struct clk_rpmh_desc clk_rpmh_sc7180 = { 496 .clks = sc7180_rpmh_clocks, 497 .num_clks = ARRAY_SIZE(sc7180_rpmh_clocks), 498 }; 499 500 static struct clk_hw *sc8180x_rpmh_clocks[] = { 501 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, 502 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, 503 [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw, 504 [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw, 505 [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw, 506 [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw, 507 [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_d.hw, 508 [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_d_ao.hw, 509 [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_d.hw, 510 [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_d_ao.hw, 511 [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_d.hw, 512 [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_d_ao.hw, 513 }; 514 515 static const struct clk_rpmh_desc clk_rpmh_sc8180x = { 516 .clks = sc8180x_rpmh_clocks, 517 .num_clks = ARRAY_SIZE(sc8180x_rpmh_clocks), 518 }; 519 520 static struct clk_hw *sm8250_rpmh_clocks[] = { 521 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, 522 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, 523 [RPMH_LN_BB_CLK1] = &clk_rpmh_ln_bb_clk1_a2.hw, 524 [RPMH_LN_BB_CLK1_A] = &clk_rpmh_ln_bb_clk1_a2_ao.hw, 525 [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw, 526 [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw, 527 [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw, 528 [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw, 529 [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, 530 [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, 531 [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw, 532 [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw, 533 }; 534 535 static const struct clk_rpmh_desc clk_rpmh_sm8250 = { 536 .clks = sm8250_rpmh_clocks, 537 .num_clks = ARRAY_SIZE(sm8250_rpmh_clocks), 538 }; 539 540 static struct clk_hw *sm8350_rpmh_clocks[] = { 541 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, 542 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, 543 [RPMH_DIV_CLK1] = &clk_rpmh_div_clk1_div2.hw, 544 [RPMH_DIV_CLK1_A] = &clk_rpmh_div_clk1_div2_ao.hw, 545 [RPMH_LN_BB_CLK1] = &clk_rpmh_ln_bb_clk1_a2.hw, 546 [RPMH_LN_BB_CLK1_A] = &clk_rpmh_ln_bb_clk1_a2_ao.hw, 547 [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw, 548 [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw, 549 [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, 550 [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, 551 [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw, 552 [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw, 553 [RPMH_RF_CLK4] = &clk_rpmh_rf_clk4_a.hw, 554 [RPMH_RF_CLK4_A] = &clk_rpmh_rf_clk4_a_ao.hw, 555 [RPMH_RF_CLK5] = &clk_rpmh_rf_clk5_a.hw, 556 [RPMH_RF_CLK5_A] = &clk_rpmh_rf_clk5_a_ao.hw, 557 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 558 [RPMH_PKA_CLK] = &clk_rpmh_pka.hw, 559 [RPMH_HWKM_CLK] = &clk_rpmh_hwkm.hw, 560 }; 561 562 static const struct clk_rpmh_desc clk_rpmh_sm8350 = { 563 .clks = sm8350_rpmh_clocks, 564 .num_clks = ARRAY_SIZE(sm8350_rpmh_clocks), 565 }; 566 567 static struct clk_hw *sc8280xp_rpmh_clocks[] = { 568 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, 569 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, 570 [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw, 571 [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw, 572 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 573 [RPMH_PKA_CLK] = &clk_rpmh_pka.hw, 574 [RPMH_HWKM_CLK] = &clk_rpmh_hwkm.hw, 575 }; 576 577 static const struct clk_rpmh_desc clk_rpmh_sc8280xp = { 578 .clks = sc8280xp_rpmh_clocks, 579 .num_clks = ARRAY_SIZE(sc8280xp_rpmh_clocks), 580 }; 581 582 static struct clk_hw *sm8450_rpmh_clocks[] = { 583 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div4.hw, 584 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div4_ao.hw, 585 [RPMH_LN_BB_CLK1] = &clk_rpmh_ln_bb_clk1_a4.hw, 586 [RPMH_LN_BB_CLK1_A] = &clk_rpmh_ln_bb_clk1_a4_ao.hw, 587 [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a4.hw, 588 [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a4_ao.hw, 589 [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, 590 [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, 591 [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw, 592 [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw, 593 [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw, 594 [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw, 595 [RPMH_RF_CLK4] = &clk_rpmh_rf_clk4_a.hw, 596 [RPMH_RF_CLK4_A] = &clk_rpmh_rf_clk4_a_ao.hw, 597 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 598 }; 599 600 static const struct clk_rpmh_desc clk_rpmh_sm8450 = { 601 .clks = sm8450_rpmh_clocks, 602 .num_clks = ARRAY_SIZE(sm8450_rpmh_clocks), 603 }; 604 605 static struct clk_hw *sm8550_rpmh_clocks[] = { 606 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, 607 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, 608 [RPMH_LN_BB_CLK1] = &clk_rpmh_clk6_a2.hw, 609 [RPMH_LN_BB_CLK1_A] = &clk_rpmh_clk6_a2_ao.hw, 610 [RPMH_LN_BB_CLK2] = &clk_rpmh_clk7_a2.hw, 611 [RPMH_LN_BB_CLK2_A] = &clk_rpmh_clk7_a2_ao.hw, 612 [RPMH_LN_BB_CLK3] = &clk_rpmh_clk8_a2.hw, 613 [RPMH_LN_BB_CLK3_A] = &clk_rpmh_clk8_a2_ao.hw, 614 [RPMH_RF_CLK1] = &clk_rpmh_clk1_a1.hw, 615 [RPMH_RF_CLK1_A] = &clk_rpmh_clk1_a1_ao.hw, 616 [RPMH_RF_CLK2] = &clk_rpmh_clk2_a1.hw, 617 [RPMH_RF_CLK2_A] = &clk_rpmh_clk2_a1_ao.hw, 618 [RPMH_RF_CLK3] = &clk_rpmh_clk3_a1.hw, 619 [RPMH_RF_CLK3_A] = &clk_rpmh_clk3_a1_ao.hw, 620 [RPMH_RF_CLK4] = &clk_rpmh_clk4_a1.hw, 621 [RPMH_RF_CLK4_A] = &clk_rpmh_clk4_a1_ao.hw, 622 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 623 }; 624 625 static const struct clk_rpmh_desc clk_rpmh_sm8550 = { 626 .clks = sm8550_rpmh_clocks, 627 .num_clks = ARRAY_SIZE(sm8550_rpmh_clocks), 628 }; 629 630 static struct clk_hw *sc7280_rpmh_clocks[] = { 631 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div4.hw, 632 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div4_ao.hw, 633 [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw, 634 [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw, 635 [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, 636 [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, 637 [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw, 638 [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw, 639 [RPMH_RF_CLK4] = &clk_rpmh_rf_clk4_a.hw, 640 [RPMH_RF_CLK4_A] = &clk_rpmh_rf_clk4_a_ao.hw, 641 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 642 [RPMH_PKA_CLK] = &clk_rpmh_pka.hw, 643 [RPMH_HWKM_CLK] = &clk_rpmh_hwkm.hw, 644 }; 645 646 static const struct clk_rpmh_desc clk_rpmh_sc7280 = { 647 .clks = sc7280_rpmh_clocks, 648 .num_clks = ARRAY_SIZE(sc7280_rpmh_clocks), 649 }; 650 651 static struct clk_hw *sm6350_rpmh_clocks[] = { 652 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div4.hw, 653 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div4_ao.hw, 654 [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_g4.hw, 655 [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_g4_ao.hw, 656 [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_g4.hw, 657 [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_g4_ao.hw, 658 [RPMH_QLINK_CLK] = &clk_rpmh_qlink_div4.hw, 659 [RPMH_QLINK_CLK_A] = &clk_rpmh_qlink_div4_ao.hw, 660 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 661 }; 662 663 static const struct clk_rpmh_desc clk_rpmh_sm6350 = { 664 .clks = sm6350_rpmh_clocks, 665 .num_clks = ARRAY_SIZE(sm6350_rpmh_clocks), 666 }; 667 668 static struct clk_hw *sdx65_rpmh_clocks[] = { 669 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div4.hw, 670 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div4_ao.hw, 671 [RPMH_LN_BB_CLK1] = &clk_rpmh_ln_bb_clk1_a4.hw, 672 [RPMH_LN_BB_CLK1_A] = &clk_rpmh_ln_bb_clk1_a4_ao.hw, 673 [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, 674 [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, 675 [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw, 676 [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw, 677 [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw, 678 [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw, 679 [RPMH_RF_CLK4] = &clk_rpmh_rf_clk4_a.hw, 680 [RPMH_RF_CLK4_A] = &clk_rpmh_rf_clk4_a_ao.hw, 681 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 682 [RPMH_QPIC_CLK] = &clk_rpmh_qpic_clk.hw, 683 }; 684 685 static const struct clk_rpmh_desc clk_rpmh_sdx65 = { 686 .clks = sdx65_rpmh_clocks, 687 .num_clks = ARRAY_SIZE(sdx65_rpmh_clocks), 688 }; 689 690 static struct clk_hw *qdu1000_rpmh_clocks[] = { 691 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div1.hw, 692 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div1_ao.hw, 693 }; 694 695 static const struct clk_rpmh_desc clk_rpmh_qdu1000 = { 696 .clks = qdu1000_rpmh_clocks, 697 .num_clks = ARRAY_SIZE(qdu1000_rpmh_clocks), 698 }; 699 700 static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec, 701 void *data) 702 { 703 struct clk_rpmh_desc *rpmh = data; 704 unsigned int idx = clkspec->args[0]; 705 706 if (idx >= rpmh->num_clks) { 707 pr_err("%s: invalid index %u\n", __func__, idx); 708 return ERR_PTR(-EINVAL); 709 } 710 711 return rpmh->clks[idx]; 712 } 713 714 static int clk_rpmh_probe(struct platform_device *pdev) 715 { 716 struct clk_hw **hw_clks; 717 struct clk_rpmh *rpmh_clk; 718 const struct clk_rpmh_desc *desc; 719 int ret, i; 720 721 desc = of_device_get_match_data(&pdev->dev); 722 if (!desc) 723 return -ENODEV; 724 725 hw_clks = desc->clks; 726 727 for (i = 0; i < desc->num_clks; i++) { 728 const char *name; 729 u32 res_addr; 730 size_t aux_data_len; 731 const struct bcm_db *data; 732 733 if (!hw_clks[i]) 734 continue; 735 736 name = hw_clks[i]->init->name; 737 738 rpmh_clk = to_clk_rpmh(hw_clks[i]); 739 res_addr = cmd_db_read_addr(rpmh_clk->res_name); 740 if (!res_addr) { 741 dev_err(&pdev->dev, "missing RPMh resource address for %s\n", 742 rpmh_clk->res_name); 743 return -ENODEV; 744 } 745 746 data = cmd_db_read_aux_data(rpmh_clk->res_name, &aux_data_len); 747 if (IS_ERR(data)) { 748 ret = PTR_ERR(data); 749 dev_err(&pdev->dev, 750 "error reading RPMh aux data for %s (%d)\n", 751 rpmh_clk->res_name, ret); 752 return ret; 753 } 754 755 /* Convert unit from Khz to Hz */ 756 if (aux_data_len == sizeof(*data)) 757 rpmh_clk->unit = le32_to_cpu(data->unit) * 1000ULL; 758 759 rpmh_clk->res_addr += res_addr; 760 rpmh_clk->dev = &pdev->dev; 761 762 ret = devm_clk_hw_register(&pdev->dev, hw_clks[i]); 763 if (ret) { 764 dev_err(&pdev->dev, "failed to register %s\n", name); 765 return ret; 766 } 767 } 768 769 /* typecast to silence compiler warning */ 770 ret = devm_of_clk_add_hw_provider(&pdev->dev, of_clk_rpmh_hw_get, 771 (void *)desc); 772 if (ret) { 773 dev_err(&pdev->dev, "Failed to add clock provider\n"); 774 return ret; 775 } 776 777 dev_dbg(&pdev->dev, "Registered RPMh clocks\n"); 778 779 return 0; 780 } 781 782 static const struct of_device_id clk_rpmh_match_table[] = { 783 { .compatible = "qcom,qdu1000-rpmh-clk", .data = &clk_rpmh_qdu1000}, 784 { .compatible = "qcom,sa8775p-rpmh-clk", .data = &clk_rpmh_sa8775p}, 785 { .compatible = "qcom,sc7180-rpmh-clk", .data = &clk_rpmh_sc7180}, 786 { .compatible = "qcom,sc8180x-rpmh-clk", .data = &clk_rpmh_sc8180x}, 787 { .compatible = "qcom,sc8280xp-rpmh-clk", .data = &clk_rpmh_sc8280xp}, 788 { .compatible = "qcom,sdm845-rpmh-clk", .data = &clk_rpmh_sdm845}, 789 { .compatible = "qcom,sdm670-rpmh-clk", .data = &clk_rpmh_sdm670}, 790 { .compatible = "qcom,sdx55-rpmh-clk", .data = &clk_rpmh_sdx55}, 791 { .compatible = "qcom,sdx65-rpmh-clk", .data = &clk_rpmh_sdx65}, 792 { .compatible = "qcom,sm6350-rpmh-clk", .data = &clk_rpmh_sm6350}, 793 { .compatible = "qcom,sm8150-rpmh-clk", .data = &clk_rpmh_sm8150}, 794 { .compatible = "qcom,sm8250-rpmh-clk", .data = &clk_rpmh_sm8250}, 795 { .compatible = "qcom,sm8350-rpmh-clk", .data = &clk_rpmh_sm8350}, 796 { .compatible = "qcom,sm8450-rpmh-clk", .data = &clk_rpmh_sm8450}, 797 { .compatible = "qcom,sm8550-rpmh-clk", .data = &clk_rpmh_sm8550}, 798 { .compatible = "qcom,sc7280-rpmh-clk", .data = &clk_rpmh_sc7280}, 799 { } 800 }; 801 MODULE_DEVICE_TABLE(of, clk_rpmh_match_table); 802 803 static struct platform_driver clk_rpmh_driver = { 804 .probe = clk_rpmh_probe, 805 .driver = { 806 .name = "clk-rpmh", 807 .of_match_table = clk_rpmh_match_table, 808 }, 809 }; 810 811 static int __init clk_rpmh_init(void) 812 { 813 return platform_driver_register(&clk_rpmh_driver); 814 } 815 core_initcall(clk_rpmh_init); 816 817 static void __exit clk_rpmh_exit(void) 818 { 819 platform_driver_unregister(&clk_rpmh_driver); 820 } 821 module_exit(clk_rpmh_exit); 822 823 MODULE_DESCRIPTION("QCOM RPMh Clock Driver"); 824 MODULE_LICENSE("GPL v2"); 825