1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/err.h> 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/of.h> 11 #include <linux/of_device.h> 12 #include <linux/platform_device.h> 13 #include <soc/qcom/cmd-db.h> 14 #include <soc/qcom/rpmh.h> 15 #include <soc/qcom/tcs.h> 16 17 #include <dt-bindings/clock/qcom,rpmh.h> 18 19 #define CLK_RPMH_ARC_EN_OFFSET 0 20 #define CLK_RPMH_VRM_EN_OFFSET 4 21 22 /** 23 * struct bcm_db - Auxiliary data pertaining to each Bus Clock Manager(BCM) 24 * @unit: divisor used to convert Hz value to an RPMh msg 25 * @width: multiplier used to convert Hz value to an RPMh msg 26 * @vcd: virtual clock domain that this bcm belongs to 27 * @reserved: reserved to pad the struct 28 */ 29 struct bcm_db { 30 __le32 unit; 31 __le16 width; 32 u8 vcd; 33 u8 reserved; 34 }; 35 36 /** 37 * struct clk_rpmh - individual rpmh clock data structure 38 * @hw: handle between common and hardware-specific interfaces 39 * @res_name: resource name for the rpmh clock 40 * @div: clock divider to compute the clock rate 41 * @res_addr: base address of the rpmh resource within the RPMh 42 * @res_on_val: rpmh clock enable value 43 * @state: rpmh clock requested state 44 * @aggr_state: rpmh clock aggregated state 45 * @last_sent_aggr_state: rpmh clock last aggr state sent to RPMh 46 * @valid_state_mask: mask to determine the state of the rpmh clock 47 * @unit: divisor to convert rate to rpmh msg in magnitudes of Khz 48 * @dev: device to which it is attached 49 * @peer: pointer to the clock rpmh sibling 50 */ 51 struct clk_rpmh { 52 struct clk_hw hw; 53 const char *res_name; 54 u8 div; 55 u32 res_addr; 56 u32 res_on_val; 57 u32 state; 58 u32 aggr_state; 59 u32 last_sent_aggr_state; 60 u32 valid_state_mask; 61 u32 unit; 62 struct device *dev; 63 struct clk_rpmh *peer; 64 }; 65 66 struct clk_rpmh_desc { 67 struct clk_hw **clks; 68 size_t num_clks; 69 }; 70 71 static DEFINE_MUTEX(rpmh_clk_lock); 72 73 #define __DEFINE_CLK_RPMH(_platform, _name, _name_active, _res_name, \ 74 _res_en_offset, _res_on, _div) \ 75 static struct clk_rpmh _platform##_##_name_active; \ 76 static struct clk_rpmh _platform##_##_name = { \ 77 .res_name = _res_name, \ 78 .res_addr = _res_en_offset, \ 79 .res_on_val = _res_on, \ 80 .div = _div, \ 81 .peer = &_platform##_##_name_active, \ 82 .valid_state_mask = (BIT(RPMH_WAKE_ONLY_STATE) | \ 83 BIT(RPMH_ACTIVE_ONLY_STATE) | \ 84 BIT(RPMH_SLEEP_STATE)), \ 85 .hw.init = &(struct clk_init_data){ \ 86 .ops = &clk_rpmh_ops, \ 87 .name = #_name, \ 88 .parent_names = (const char *[]){ "xo_board" }, \ 89 .num_parents = 1, \ 90 }, \ 91 }; \ 92 static struct clk_rpmh _platform##_##_name_active = { \ 93 .res_name = _res_name, \ 94 .res_addr = _res_en_offset, \ 95 .res_on_val = _res_on, \ 96 .div = _div, \ 97 .peer = &_platform##_##_name, \ 98 .valid_state_mask = (BIT(RPMH_WAKE_ONLY_STATE) | \ 99 BIT(RPMH_ACTIVE_ONLY_STATE)), \ 100 .hw.init = &(struct clk_init_data){ \ 101 .ops = &clk_rpmh_ops, \ 102 .name = #_name_active, \ 103 .parent_names = (const char *[]){ "xo_board" }, \ 104 .num_parents = 1, \ 105 }, \ 106 } 107 108 #define DEFINE_CLK_RPMH_ARC(_platform, _name, _name_active, _res_name, \ 109 _res_on, _div) \ 110 __DEFINE_CLK_RPMH(_platform, _name, _name_active, _res_name, \ 111 CLK_RPMH_ARC_EN_OFFSET, _res_on, _div) 112 113 #define DEFINE_CLK_RPMH_VRM(_platform, _name, _name_active, _res_name, \ 114 _div) \ 115 __DEFINE_CLK_RPMH(_platform, _name, _name_active, _res_name, \ 116 CLK_RPMH_VRM_EN_OFFSET, 1, _div) 117 118 #define DEFINE_CLK_RPMH_BCM(_platform, _name, _res_name) \ 119 static struct clk_rpmh _platform##_##_name = { \ 120 .res_name = _res_name, \ 121 .valid_state_mask = BIT(RPMH_ACTIVE_ONLY_STATE), \ 122 .div = 1, \ 123 .hw.init = &(struct clk_init_data){ \ 124 .ops = &clk_rpmh_bcm_ops, \ 125 .name = #_name, \ 126 }, \ 127 } 128 129 static inline struct clk_rpmh *to_clk_rpmh(struct clk_hw *_hw) 130 { 131 return container_of(_hw, struct clk_rpmh, hw); 132 } 133 134 static inline bool has_state_changed(struct clk_rpmh *c, u32 state) 135 { 136 return (c->last_sent_aggr_state & BIT(state)) 137 != (c->aggr_state & BIT(state)); 138 } 139 140 static int clk_rpmh_send_aggregate_command(struct clk_rpmh *c) 141 { 142 struct tcs_cmd cmd = { 0 }; 143 u32 cmd_state, on_val; 144 enum rpmh_state state = RPMH_SLEEP_STATE; 145 int ret; 146 147 cmd.addr = c->res_addr; 148 cmd_state = c->aggr_state; 149 on_val = c->res_on_val; 150 151 for (; state <= RPMH_ACTIVE_ONLY_STATE; state++) { 152 if (has_state_changed(c, state)) { 153 if (cmd_state & BIT(state)) 154 cmd.data = on_val; 155 156 ret = rpmh_write_async(c->dev, state, &cmd, 1); 157 if (ret) { 158 dev_err(c->dev, "set %s state of %s failed: (%d)\n", 159 !state ? "sleep" : 160 state == RPMH_WAKE_ONLY_STATE ? 161 "wake" : "active", c->res_name, ret); 162 return ret; 163 } 164 } 165 } 166 167 c->last_sent_aggr_state = c->aggr_state; 168 c->peer->last_sent_aggr_state = c->last_sent_aggr_state; 169 170 return 0; 171 } 172 173 /* 174 * Update state and aggregate state values based on enable value. 175 */ 176 static int clk_rpmh_aggregate_state_send_command(struct clk_rpmh *c, 177 bool enable) 178 { 179 int ret; 180 181 /* Nothing required to be done if already off or on */ 182 if (enable == c->state) 183 return 0; 184 185 c->state = enable ? c->valid_state_mask : 0; 186 c->aggr_state = c->state | c->peer->state; 187 c->peer->aggr_state = c->aggr_state; 188 189 ret = clk_rpmh_send_aggregate_command(c); 190 if (!ret) 191 return 0; 192 193 if (ret && enable) 194 c->state = 0; 195 else if (ret) 196 c->state = c->valid_state_mask; 197 198 WARN(1, "clk: %s failed to %s\n", c->res_name, 199 enable ? "enable" : "disable"); 200 return ret; 201 } 202 203 static int clk_rpmh_prepare(struct clk_hw *hw) 204 { 205 struct clk_rpmh *c = to_clk_rpmh(hw); 206 int ret = 0; 207 208 mutex_lock(&rpmh_clk_lock); 209 ret = clk_rpmh_aggregate_state_send_command(c, true); 210 mutex_unlock(&rpmh_clk_lock); 211 212 return ret; 213 }; 214 215 static void clk_rpmh_unprepare(struct clk_hw *hw) 216 { 217 struct clk_rpmh *c = to_clk_rpmh(hw); 218 219 mutex_lock(&rpmh_clk_lock); 220 clk_rpmh_aggregate_state_send_command(c, false); 221 mutex_unlock(&rpmh_clk_lock); 222 }; 223 224 static unsigned long clk_rpmh_recalc_rate(struct clk_hw *hw, 225 unsigned long prate) 226 { 227 struct clk_rpmh *r = to_clk_rpmh(hw); 228 229 /* 230 * RPMh clocks have a fixed rate. Return static rate. 231 */ 232 return prate / r->div; 233 } 234 235 static const struct clk_ops clk_rpmh_ops = { 236 .prepare = clk_rpmh_prepare, 237 .unprepare = clk_rpmh_unprepare, 238 .recalc_rate = clk_rpmh_recalc_rate, 239 }; 240 241 static int clk_rpmh_bcm_send_cmd(struct clk_rpmh *c, bool enable) 242 { 243 struct tcs_cmd cmd = { 0 }; 244 u32 cmd_state; 245 int ret; 246 247 mutex_lock(&rpmh_clk_lock); 248 249 cmd_state = 0; 250 if (enable) { 251 cmd_state = 1; 252 if (c->aggr_state) 253 cmd_state = c->aggr_state; 254 } 255 256 if (c->last_sent_aggr_state == cmd_state) { 257 mutex_unlock(&rpmh_clk_lock); 258 return 0; 259 } 260 261 cmd.addr = c->res_addr; 262 cmd.data = BCM_TCS_CMD(1, enable, 0, cmd_state); 263 264 ret = rpmh_write_async(c->dev, RPMH_ACTIVE_ONLY_STATE, &cmd, 1); 265 if (ret) { 266 dev_err(c->dev, "set active state of %s failed: (%d)\n", 267 c->res_name, ret); 268 mutex_unlock(&rpmh_clk_lock); 269 return ret; 270 } 271 272 c->last_sent_aggr_state = cmd_state; 273 274 mutex_unlock(&rpmh_clk_lock); 275 276 return 0; 277 } 278 279 static int clk_rpmh_bcm_prepare(struct clk_hw *hw) 280 { 281 struct clk_rpmh *c = to_clk_rpmh(hw); 282 283 return clk_rpmh_bcm_send_cmd(c, true); 284 }; 285 286 static void clk_rpmh_bcm_unprepare(struct clk_hw *hw) 287 { 288 struct clk_rpmh *c = to_clk_rpmh(hw); 289 290 clk_rpmh_bcm_send_cmd(c, false); 291 }; 292 293 static int clk_rpmh_bcm_set_rate(struct clk_hw *hw, unsigned long rate, 294 unsigned long parent_rate) 295 { 296 struct clk_rpmh *c = to_clk_rpmh(hw); 297 298 c->aggr_state = rate / c->unit; 299 /* 300 * Since any non-zero value sent to hw would result in enabling the 301 * clock, only send the value if the clock has already been prepared. 302 */ 303 if (clk_hw_is_prepared(hw)) 304 clk_rpmh_bcm_send_cmd(c, true); 305 306 return 0; 307 }; 308 309 static long clk_rpmh_round_rate(struct clk_hw *hw, unsigned long rate, 310 unsigned long *parent_rate) 311 { 312 return rate; 313 } 314 315 static unsigned long clk_rpmh_bcm_recalc_rate(struct clk_hw *hw, 316 unsigned long prate) 317 { 318 struct clk_rpmh *c = to_clk_rpmh(hw); 319 320 return c->aggr_state * c->unit; 321 } 322 323 static const struct clk_ops clk_rpmh_bcm_ops = { 324 .prepare = clk_rpmh_bcm_prepare, 325 .unprepare = clk_rpmh_bcm_unprepare, 326 .set_rate = clk_rpmh_bcm_set_rate, 327 .round_rate = clk_rpmh_round_rate, 328 .recalc_rate = clk_rpmh_bcm_recalc_rate, 329 }; 330 331 /* Resource name must match resource id present in cmd-db. */ 332 DEFINE_CLK_RPMH_ARC(sdm845, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 2); 333 DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk2, ln_bb_clk2_ao, "lnbclka2", 2); 334 DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk3, ln_bb_clk3_ao, "lnbclka3", 2); 335 DEFINE_CLK_RPMH_VRM(sdm845, rf_clk1, rf_clk1_ao, "rfclka1", 1); 336 DEFINE_CLK_RPMH_VRM(sdm845, rf_clk2, rf_clk2_ao, "rfclka2", 1); 337 DEFINE_CLK_RPMH_VRM(sdm845, rf_clk3, rf_clk3_ao, "rfclka3", 1); 338 DEFINE_CLK_RPMH_BCM(sdm845, ipa, "IP0"); 339 340 static struct clk_hw *sdm845_rpmh_clocks[] = { 341 [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw, 342 [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw, 343 [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw, 344 [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw, 345 [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw, 346 [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_ao.hw, 347 [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw, 348 [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw, 349 [RPMH_RF_CLK2] = &sdm845_rf_clk2.hw, 350 [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_ao.hw, 351 [RPMH_RF_CLK3] = &sdm845_rf_clk3.hw, 352 [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw, 353 [RPMH_IPA_CLK] = &sdm845_ipa.hw, 354 }; 355 356 static const struct clk_rpmh_desc clk_rpmh_sdm845 = { 357 .clks = sdm845_rpmh_clocks, 358 .num_clks = ARRAY_SIZE(sdm845_rpmh_clocks), 359 }; 360 361 static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec, 362 void *data) 363 { 364 struct clk_rpmh_desc *rpmh = data; 365 unsigned int idx = clkspec->args[0]; 366 367 if (idx >= rpmh->num_clks) { 368 pr_err("%s: invalid index %u\n", __func__, idx); 369 return ERR_PTR(-EINVAL); 370 } 371 372 return rpmh->clks[idx]; 373 } 374 375 static int clk_rpmh_probe(struct platform_device *pdev) 376 { 377 struct clk_hw **hw_clks; 378 struct clk_rpmh *rpmh_clk; 379 const struct clk_rpmh_desc *desc; 380 int ret, i; 381 382 desc = of_device_get_match_data(&pdev->dev); 383 if (!desc) 384 return -ENODEV; 385 386 hw_clks = desc->clks; 387 388 for (i = 0; i < desc->num_clks; i++) { 389 u32 res_addr; 390 size_t aux_data_len; 391 const struct bcm_db *data; 392 393 rpmh_clk = to_clk_rpmh(hw_clks[i]); 394 res_addr = cmd_db_read_addr(rpmh_clk->res_name); 395 if (!res_addr) { 396 dev_err(&pdev->dev, "missing RPMh resource address for %s\n", 397 rpmh_clk->res_name); 398 return -ENODEV; 399 } 400 401 data = cmd_db_read_aux_data(rpmh_clk->res_name, &aux_data_len); 402 if (IS_ERR(data)) { 403 ret = PTR_ERR(data); 404 dev_err(&pdev->dev, 405 "error reading RPMh aux data for %s (%d)\n", 406 rpmh_clk->res_name, ret); 407 return ret; 408 } 409 410 /* Convert unit from Khz to Hz */ 411 if (aux_data_len == sizeof(*data)) 412 rpmh_clk->unit = le32_to_cpu(data->unit) * 1000ULL; 413 414 rpmh_clk->res_addr += res_addr; 415 rpmh_clk->dev = &pdev->dev; 416 417 ret = devm_clk_hw_register(&pdev->dev, hw_clks[i]); 418 if (ret) { 419 dev_err(&pdev->dev, "failed to register %s\n", 420 hw_clks[i]->init->name); 421 return ret; 422 } 423 } 424 425 /* typecast to silence compiler warning */ 426 ret = devm_of_clk_add_hw_provider(&pdev->dev, of_clk_rpmh_hw_get, 427 (void *)desc); 428 if (ret) { 429 dev_err(&pdev->dev, "Failed to add clock provider\n"); 430 return ret; 431 } 432 433 dev_dbg(&pdev->dev, "Registered RPMh clocks\n"); 434 435 return 0; 436 } 437 438 static const struct of_device_id clk_rpmh_match_table[] = { 439 { .compatible = "qcom,sdm845-rpmh-clk", .data = &clk_rpmh_sdm845}, 440 { } 441 }; 442 MODULE_DEVICE_TABLE(of, clk_rpmh_match_table); 443 444 static struct platform_driver clk_rpmh_driver = { 445 .probe = clk_rpmh_probe, 446 .driver = { 447 .name = "clk-rpmh", 448 .of_match_table = clk_rpmh_match_table, 449 }, 450 }; 451 452 static int __init clk_rpmh_init(void) 453 { 454 return platform_driver_register(&clk_rpmh_driver); 455 } 456 subsys_initcall(clk_rpmh_init); 457 458 static void __exit clk_rpmh_exit(void) 459 { 460 platform_driver_unregister(&clk_rpmh_driver); 461 } 462 module_exit(clk_rpmh_exit); 463 464 MODULE_DESCRIPTION("QCOM RPMh Clock Driver"); 465 MODULE_LICENSE("GPL v2"); 466