1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/err.h> 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/of.h> 11 #include <linux/of_device.h> 12 #include <linux/platform_device.h> 13 #include <soc/qcom/cmd-db.h> 14 #include <soc/qcom/rpmh.h> 15 #include <soc/qcom/tcs.h> 16 17 #include <dt-bindings/clock/qcom,rpmh.h> 18 19 #define CLK_RPMH_ARC_EN_OFFSET 0 20 #define CLK_RPMH_VRM_EN_OFFSET 4 21 22 /** 23 * struct bcm_db - Auxiliary data pertaining to each Bus Clock Manager(BCM) 24 * @unit: divisor used to convert Hz value to an RPMh msg 25 * @width: multiplier used to convert Hz value to an RPMh msg 26 * @vcd: virtual clock domain that this bcm belongs to 27 * @reserved: reserved to pad the struct 28 */ 29 struct bcm_db { 30 __le32 unit; 31 __le16 width; 32 u8 vcd; 33 u8 reserved; 34 }; 35 36 /** 37 * struct clk_rpmh - individual rpmh clock data structure 38 * @hw: handle between common and hardware-specific interfaces 39 * @res_name: resource name for the rpmh clock 40 * @div: clock divider to compute the clock rate 41 * @res_addr: base address of the rpmh resource within the RPMh 42 * @res_on_val: rpmh clock enable value 43 * @state: rpmh clock requested state 44 * @aggr_state: rpmh clock aggregated state 45 * @last_sent_aggr_state: rpmh clock last aggr state sent to RPMh 46 * @valid_state_mask: mask to determine the state of the rpmh clock 47 * @unit: divisor to convert rate to rpmh msg in magnitudes of Khz 48 * @dev: device to which it is attached 49 * @peer: pointer to the clock rpmh sibling 50 */ 51 struct clk_rpmh { 52 struct clk_hw hw; 53 const char *res_name; 54 u8 div; 55 u32 res_addr; 56 u32 res_on_val; 57 u32 state; 58 u32 aggr_state; 59 u32 last_sent_aggr_state; 60 u32 valid_state_mask; 61 u32 unit; 62 struct device *dev; 63 struct clk_rpmh *peer; 64 }; 65 66 struct clk_rpmh_desc { 67 struct clk_hw **clks; 68 size_t num_clks; 69 }; 70 71 static DEFINE_MUTEX(rpmh_clk_lock); 72 73 #define __DEFINE_CLK_RPMH(_platform, _name, _name_active, _res_name, \ 74 _res_en_offset, _res_on, _div) \ 75 static struct clk_rpmh _platform##_##_name_active; \ 76 static struct clk_rpmh _platform##_##_name = { \ 77 .res_name = _res_name, \ 78 .res_addr = _res_en_offset, \ 79 .res_on_val = _res_on, \ 80 .div = _div, \ 81 .peer = &_platform##_##_name_active, \ 82 .valid_state_mask = (BIT(RPMH_WAKE_ONLY_STATE) | \ 83 BIT(RPMH_ACTIVE_ONLY_STATE) | \ 84 BIT(RPMH_SLEEP_STATE)), \ 85 .hw.init = &(struct clk_init_data){ \ 86 .ops = &clk_rpmh_ops, \ 87 .name = #_name, \ 88 .parent_data = &(const struct clk_parent_data){ \ 89 .fw_name = "xo", \ 90 .name = "xo_board", \ 91 }, \ 92 .num_parents = 1, \ 93 }, \ 94 }; \ 95 static struct clk_rpmh _platform##_##_name_active = { \ 96 .res_name = _res_name, \ 97 .res_addr = _res_en_offset, \ 98 .res_on_val = _res_on, \ 99 .div = _div, \ 100 .peer = &_platform##_##_name, \ 101 .valid_state_mask = (BIT(RPMH_WAKE_ONLY_STATE) | \ 102 BIT(RPMH_ACTIVE_ONLY_STATE)), \ 103 .hw.init = &(struct clk_init_data){ \ 104 .ops = &clk_rpmh_ops, \ 105 .name = #_name_active, \ 106 .parent_data = &(const struct clk_parent_data){ \ 107 .fw_name = "xo", \ 108 .name = "xo_board", \ 109 }, \ 110 .num_parents = 1, \ 111 }, \ 112 } 113 114 #define DEFINE_CLK_RPMH_ARC(_platform, _name, _name_active, _res_name, \ 115 _res_on, _div) \ 116 __DEFINE_CLK_RPMH(_platform, _name, _name_active, _res_name, \ 117 CLK_RPMH_ARC_EN_OFFSET, _res_on, _div) 118 119 #define DEFINE_CLK_RPMH_VRM(_platform, _name, _name_active, _res_name, \ 120 _div) \ 121 __DEFINE_CLK_RPMH(_platform, _name, _name_active, _res_name, \ 122 CLK_RPMH_VRM_EN_OFFSET, 1, _div) 123 124 #define DEFINE_CLK_RPMH_BCM(_platform, _name, _res_name) \ 125 static struct clk_rpmh _platform##_##_name = { \ 126 .res_name = _res_name, \ 127 .valid_state_mask = BIT(RPMH_ACTIVE_ONLY_STATE), \ 128 .div = 1, \ 129 .hw.init = &(struct clk_init_data){ \ 130 .ops = &clk_rpmh_bcm_ops, \ 131 .name = #_name, \ 132 }, \ 133 } 134 135 static inline struct clk_rpmh *to_clk_rpmh(struct clk_hw *_hw) 136 { 137 return container_of(_hw, struct clk_rpmh, hw); 138 } 139 140 static inline bool has_state_changed(struct clk_rpmh *c, u32 state) 141 { 142 return (c->last_sent_aggr_state & BIT(state)) 143 != (c->aggr_state & BIT(state)); 144 } 145 146 static int clk_rpmh_send(struct clk_rpmh *c, enum rpmh_state state, 147 struct tcs_cmd *cmd, bool wait) 148 { 149 if (wait) 150 return rpmh_write(c->dev, state, cmd, 1); 151 152 return rpmh_write_async(c->dev, state, cmd, 1); 153 } 154 155 static int clk_rpmh_send_aggregate_command(struct clk_rpmh *c) 156 { 157 struct tcs_cmd cmd = { 0 }; 158 u32 cmd_state, on_val; 159 enum rpmh_state state = RPMH_SLEEP_STATE; 160 int ret; 161 bool wait; 162 163 cmd.addr = c->res_addr; 164 cmd_state = c->aggr_state; 165 on_val = c->res_on_val; 166 167 for (; state <= RPMH_ACTIVE_ONLY_STATE; state++) { 168 if (has_state_changed(c, state)) { 169 if (cmd_state & BIT(state)) 170 cmd.data = on_val; 171 172 wait = cmd_state && state == RPMH_ACTIVE_ONLY_STATE; 173 ret = clk_rpmh_send(c, state, &cmd, wait); 174 if (ret) { 175 dev_err(c->dev, "set %s state of %s failed: (%d)\n", 176 !state ? "sleep" : 177 state == RPMH_WAKE_ONLY_STATE ? 178 "wake" : "active", c->res_name, ret); 179 return ret; 180 } 181 } 182 } 183 184 c->last_sent_aggr_state = c->aggr_state; 185 c->peer->last_sent_aggr_state = c->last_sent_aggr_state; 186 187 return 0; 188 } 189 190 /* 191 * Update state and aggregate state values based on enable value. 192 */ 193 static int clk_rpmh_aggregate_state_send_command(struct clk_rpmh *c, 194 bool enable) 195 { 196 int ret; 197 198 c->state = enable ? c->valid_state_mask : 0; 199 c->aggr_state = c->state | c->peer->state; 200 c->peer->aggr_state = c->aggr_state; 201 202 ret = clk_rpmh_send_aggregate_command(c); 203 if (!ret) 204 return 0; 205 206 if (ret && enable) 207 c->state = 0; 208 else if (ret) 209 c->state = c->valid_state_mask; 210 211 WARN(1, "clk: %s failed to %s\n", c->res_name, 212 enable ? "enable" : "disable"); 213 return ret; 214 } 215 216 static int clk_rpmh_prepare(struct clk_hw *hw) 217 { 218 struct clk_rpmh *c = to_clk_rpmh(hw); 219 int ret = 0; 220 221 mutex_lock(&rpmh_clk_lock); 222 ret = clk_rpmh_aggregate_state_send_command(c, true); 223 mutex_unlock(&rpmh_clk_lock); 224 225 return ret; 226 } 227 228 static void clk_rpmh_unprepare(struct clk_hw *hw) 229 { 230 struct clk_rpmh *c = to_clk_rpmh(hw); 231 232 mutex_lock(&rpmh_clk_lock); 233 clk_rpmh_aggregate_state_send_command(c, false); 234 mutex_unlock(&rpmh_clk_lock); 235 }; 236 237 static unsigned long clk_rpmh_recalc_rate(struct clk_hw *hw, 238 unsigned long prate) 239 { 240 struct clk_rpmh *r = to_clk_rpmh(hw); 241 242 /* 243 * RPMh clocks have a fixed rate. Return static rate. 244 */ 245 return prate / r->div; 246 } 247 248 static const struct clk_ops clk_rpmh_ops = { 249 .prepare = clk_rpmh_prepare, 250 .unprepare = clk_rpmh_unprepare, 251 .recalc_rate = clk_rpmh_recalc_rate, 252 }; 253 254 static int clk_rpmh_bcm_send_cmd(struct clk_rpmh *c, bool enable) 255 { 256 struct tcs_cmd cmd = { 0 }; 257 u32 cmd_state; 258 int ret = 0; 259 260 mutex_lock(&rpmh_clk_lock); 261 if (enable) { 262 cmd_state = 1; 263 if (c->aggr_state) 264 cmd_state = c->aggr_state; 265 } else { 266 cmd_state = 0; 267 } 268 269 if (c->last_sent_aggr_state != cmd_state) { 270 cmd.addr = c->res_addr; 271 cmd.data = BCM_TCS_CMD(1, enable, 0, cmd_state); 272 273 /* 274 * Send only an active only state request. RPMh continues to 275 * use the active state when we're in sleep/wake state as long 276 * as the sleep/wake state has never been set. 277 */ 278 ret = clk_rpmh_send(c, RPMH_ACTIVE_ONLY_STATE, &cmd, enable); 279 if (ret) { 280 dev_err(c->dev, "set active state of %s failed: (%d)\n", 281 c->res_name, ret); 282 } else { 283 c->last_sent_aggr_state = cmd_state; 284 } 285 } 286 287 mutex_unlock(&rpmh_clk_lock); 288 289 return ret; 290 } 291 292 static int clk_rpmh_bcm_prepare(struct clk_hw *hw) 293 { 294 struct clk_rpmh *c = to_clk_rpmh(hw); 295 296 return clk_rpmh_bcm_send_cmd(c, true); 297 } 298 299 static void clk_rpmh_bcm_unprepare(struct clk_hw *hw) 300 { 301 struct clk_rpmh *c = to_clk_rpmh(hw); 302 303 clk_rpmh_bcm_send_cmd(c, false); 304 } 305 306 static int clk_rpmh_bcm_set_rate(struct clk_hw *hw, unsigned long rate, 307 unsigned long parent_rate) 308 { 309 struct clk_rpmh *c = to_clk_rpmh(hw); 310 311 c->aggr_state = rate / c->unit; 312 /* 313 * Since any non-zero value sent to hw would result in enabling the 314 * clock, only send the value if the clock has already been prepared. 315 */ 316 if (clk_hw_is_prepared(hw)) 317 clk_rpmh_bcm_send_cmd(c, true); 318 319 return 0; 320 } 321 322 static long clk_rpmh_round_rate(struct clk_hw *hw, unsigned long rate, 323 unsigned long *parent_rate) 324 { 325 return rate; 326 } 327 328 static unsigned long clk_rpmh_bcm_recalc_rate(struct clk_hw *hw, 329 unsigned long prate) 330 { 331 struct clk_rpmh *c = to_clk_rpmh(hw); 332 333 return c->aggr_state * c->unit; 334 } 335 336 static const struct clk_ops clk_rpmh_bcm_ops = { 337 .prepare = clk_rpmh_bcm_prepare, 338 .unprepare = clk_rpmh_bcm_unprepare, 339 .set_rate = clk_rpmh_bcm_set_rate, 340 .round_rate = clk_rpmh_round_rate, 341 .recalc_rate = clk_rpmh_bcm_recalc_rate, 342 }; 343 344 /* Resource name must match resource id present in cmd-db */ 345 DEFINE_CLK_RPMH_ARC(sdm845, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 2); 346 DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk2, ln_bb_clk2_ao, "lnbclka2", 2); 347 DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk3, ln_bb_clk3_ao, "lnbclka3", 2); 348 DEFINE_CLK_RPMH_VRM(sdm845, rf_clk1, rf_clk1_ao, "rfclka1", 1); 349 DEFINE_CLK_RPMH_VRM(sdm845, rf_clk2, rf_clk2_ao, "rfclka2", 1); 350 DEFINE_CLK_RPMH_VRM(sdm845, rf_clk3, rf_clk3_ao, "rfclka3", 1); 351 DEFINE_CLK_RPMH_VRM(sm8150, rf_clk3, rf_clk3_ao, "rfclka3", 1); 352 DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk1, rf_clk1_ao, "rfclkd1", 1); 353 DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk2, rf_clk2_ao, "rfclkd2", 1); 354 DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk3, rf_clk3_ao, "rfclkd3", 1); 355 DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk4, rf_clk4_ao, "rfclkd4", 1); 356 DEFINE_CLK_RPMH_BCM(sdm845, ipa, "IP0"); 357 DEFINE_CLK_RPMH_BCM(sdm845, ce, "CE0"); 358 359 static struct clk_hw *sdm845_rpmh_clocks[] = { 360 [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw, 361 [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw, 362 [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw, 363 [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw, 364 [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw, 365 [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_ao.hw, 366 [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw, 367 [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw, 368 [RPMH_RF_CLK2] = &sdm845_rf_clk2.hw, 369 [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_ao.hw, 370 [RPMH_RF_CLK3] = &sdm845_rf_clk3.hw, 371 [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw, 372 [RPMH_IPA_CLK] = &sdm845_ipa.hw, 373 [RPMH_CE_CLK] = &sdm845_ce.hw, 374 }; 375 376 static const struct clk_rpmh_desc clk_rpmh_sdm845 = { 377 .clks = sdm845_rpmh_clocks, 378 .num_clks = ARRAY_SIZE(sdm845_rpmh_clocks), 379 }; 380 381 DEFINE_CLK_RPMH_VRM(sdx55, rf_clk1, rf_clk1_ao, "rfclkd1", 1); 382 DEFINE_CLK_RPMH_VRM(sdx55, rf_clk2, rf_clk2_ao, "rfclkd2", 1); 383 DEFINE_CLK_RPMH_BCM(sdx55, qpic_clk, "QP0"); 384 DEFINE_CLK_RPMH_BCM(sdx55, ipa, "IP0"); 385 386 static struct clk_hw *sdx55_rpmh_clocks[] = { 387 [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw, 388 [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw, 389 [RPMH_RF_CLK1] = &sdx55_rf_clk1.hw, 390 [RPMH_RF_CLK1_A] = &sdx55_rf_clk1_ao.hw, 391 [RPMH_RF_CLK2] = &sdx55_rf_clk2.hw, 392 [RPMH_RF_CLK2_A] = &sdx55_rf_clk2_ao.hw, 393 [RPMH_QPIC_CLK] = &sdx55_qpic_clk.hw, 394 [RPMH_IPA_CLK] = &sdx55_ipa.hw, 395 }; 396 397 static const struct clk_rpmh_desc clk_rpmh_sdx55 = { 398 .clks = sdx55_rpmh_clocks, 399 .num_clks = ARRAY_SIZE(sdx55_rpmh_clocks), 400 }; 401 402 static struct clk_hw *sm8150_rpmh_clocks[] = { 403 [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw, 404 [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw, 405 [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw, 406 [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw, 407 [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw, 408 [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_ao.hw, 409 [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw, 410 [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw, 411 [RPMH_RF_CLK2] = &sdm845_rf_clk2.hw, 412 [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_ao.hw, 413 [RPMH_RF_CLK3] = &sdm845_rf_clk3.hw, 414 [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw, 415 }; 416 417 static const struct clk_rpmh_desc clk_rpmh_sm8150 = { 418 .clks = sm8150_rpmh_clocks, 419 .num_clks = ARRAY_SIZE(sm8150_rpmh_clocks), 420 }; 421 422 static struct clk_hw *sc7180_rpmh_clocks[] = { 423 [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw, 424 [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw, 425 [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw, 426 [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw, 427 [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw, 428 [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_ao.hw, 429 [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw, 430 [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw, 431 [RPMH_RF_CLK2] = &sdm845_rf_clk2.hw, 432 [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_ao.hw, 433 [RPMH_IPA_CLK] = &sdm845_ipa.hw, 434 }; 435 436 static const struct clk_rpmh_desc clk_rpmh_sc7180 = { 437 .clks = sc7180_rpmh_clocks, 438 .num_clks = ARRAY_SIZE(sc7180_rpmh_clocks), 439 }; 440 441 static struct clk_hw *sc8180x_rpmh_clocks[] = { 442 [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw, 443 [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw, 444 [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw, 445 [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw, 446 [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw, 447 [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_ao.hw, 448 [RPMH_RF_CLK1] = &sc8180x_rf_clk1.hw, 449 [RPMH_RF_CLK1_A] = &sc8180x_rf_clk1_ao.hw, 450 [RPMH_RF_CLK2] = &sc8180x_rf_clk2.hw, 451 [RPMH_RF_CLK2_A] = &sc8180x_rf_clk2_ao.hw, 452 [RPMH_RF_CLK3] = &sc8180x_rf_clk3.hw, 453 [RPMH_RF_CLK3_A] = &sc8180x_rf_clk3_ao.hw, 454 }; 455 456 static const struct clk_rpmh_desc clk_rpmh_sc8180x = { 457 .clks = sc8180x_rpmh_clocks, 458 .num_clks = ARRAY_SIZE(sc8180x_rpmh_clocks), 459 }; 460 461 DEFINE_CLK_RPMH_VRM(sm8250, ln_bb_clk1, ln_bb_clk1_ao, "lnbclka1", 2); 462 463 static struct clk_hw *sm8250_rpmh_clocks[] = { 464 [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw, 465 [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw, 466 [RPMH_LN_BB_CLK1] = &sm8250_ln_bb_clk1.hw, 467 [RPMH_LN_BB_CLK1_A] = &sm8250_ln_bb_clk1_ao.hw, 468 [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw, 469 [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw, 470 [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw, 471 [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_ao.hw, 472 [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw, 473 [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw, 474 [RPMH_RF_CLK3] = &sdm845_rf_clk3.hw, 475 [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw, 476 }; 477 478 static const struct clk_rpmh_desc clk_rpmh_sm8250 = { 479 .clks = sm8250_rpmh_clocks, 480 .num_clks = ARRAY_SIZE(sm8250_rpmh_clocks), 481 }; 482 483 DEFINE_CLK_RPMH_VRM(sm8350, div_clk1, div_clk1_ao, "divclka1", 2); 484 DEFINE_CLK_RPMH_VRM(sm8350, rf_clk4, rf_clk4_ao, "rfclka4", 1); 485 DEFINE_CLK_RPMH_VRM(sm8350, rf_clk5, rf_clk5_ao, "rfclka5", 1); 486 DEFINE_CLK_RPMH_BCM(sm8350, pka, "PKA0"); 487 DEFINE_CLK_RPMH_BCM(sm8350, hwkm, "HK0"); 488 489 static struct clk_hw *sm8350_rpmh_clocks[] = { 490 [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw, 491 [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw, 492 [RPMH_DIV_CLK1] = &sm8350_div_clk1.hw, 493 [RPMH_DIV_CLK1_A] = &sm8350_div_clk1_ao.hw, 494 [RPMH_LN_BB_CLK1] = &sm8250_ln_bb_clk1.hw, 495 [RPMH_LN_BB_CLK1_A] = &sm8250_ln_bb_clk1_ao.hw, 496 [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw, 497 [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw, 498 [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw, 499 [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw, 500 [RPMH_RF_CLK3] = &sdm845_rf_clk3.hw, 501 [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw, 502 [RPMH_RF_CLK4] = &sm8350_rf_clk4.hw, 503 [RPMH_RF_CLK4_A] = &sm8350_rf_clk4_ao.hw, 504 [RPMH_RF_CLK5] = &sm8350_rf_clk5.hw, 505 [RPMH_RF_CLK5_A] = &sm8350_rf_clk5_ao.hw, 506 [RPMH_IPA_CLK] = &sdm845_ipa.hw, 507 [RPMH_PKA_CLK] = &sm8350_pka.hw, 508 [RPMH_HWKM_CLK] = &sm8350_hwkm.hw, 509 }; 510 511 static const struct clk_rpmh_desc clk_rpmh_sm8350 = { 512 .clks = sm8350_rpmh_clocks, 513 .num_clks = ARRAY_SIZE(sm8350_rpmh_clocks), 514 }; 515 516 DEFINE_CLK_RPMH_VRM(sc8280xp, ln_bb_clk3, ln_bb_clk3_ao, "lnbclka3", 2); 517 518 static struct clk_hw *sc8280xp_rpmh_clocks[] = { 519 [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw, 520 [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw, 521 [RPMH_LN_BB_CLK3] = &sc8280xp_ln_bb_clk3.hw, 522 [RPMH_LN_BB_CLK3_A] = &sc8280xp_ln_bb_clk3_ao.hw, 523 [RPMH_IPA_CLK] = &sdm845_ipa.hw, 524 [RPMH_PKA_CLK] = &sm8350_pka.hw, 525 [RPMH_HWKM_CLK] = &sm8350_hwkm.hw, 526 }; 527 528 static const struct clk_rpmh_desc clk_rpmh_sc8280xp = { 529 .clks = sc8280xp_rpmh_clocks, 530 .num_clks = ARRAY_SIZE(sc8280xp_rpmh_clocks), 531 }; 532 533 /* Resource name must match resource id present in cmd-db */ 534 DEFINE_CLK_RPMH_ARC(sc7280, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 4); 535 536 DEFINE_CLK_RPMH_VRM(sm8450, ln_bb_clk1, ln_bb_clk1_ao, "lnbclka1", 4); 537 DEFINE_CLK_RPMH_VRM(sm8450, ln_bb_clk2, ln_bb_clk2_ao, "lnbclka2", 4); 538 539 static struct clk_hw *sm8450_rpmh_clocks[] = { 540 [RPMH_CXO_CLK] = &sc7280_bi_tcxo.hw, 541 [RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_ao.hw, 542 [RPMH_LN_BB_CLK1] = &sm8450_ln_bb_clk1.hw, 543 [RPMH_LN_BB_CLK1_A] = &sm8450_ln_bb_clk1_ao.hw, 544 [RPMH_LN_BB_CLK2] = &sm8450_ln_bb_clk2.hw, 545 [RPMH_LN_BB_CLK2_A] = &sm8450_ln_bb_clk2_ao.hw, 546 [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw, 547 [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw, 548 [RPMH_RF_CLK2] = &sdm845_rf_clk2.hw, 549 [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_ao.hw, 550 [RPMH_RF_CLK3] = &sdm845_rf_clk3.hw, 551 [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw, 552 [RPMH_RF_CLK4] = &sm8350_rf_clk4.hw, 553 [RPMH_RF_CLK4_A] = &sm8350_rf_clk4_ao.hw, 554 [RPMH_IPA_CLK] = &sdm845_ipa.hw, 555 }; 556 557 static const struct clk_rpmh_desc clk_rpmh_sm8450 = { 558 .clks = sm8450_rpmh_clocks, 559 .num_clks = ARRAY_SIZE(sm8450_rpmh_clocks), 560 }; 561 562 static struct clk_hw *sc7280_rpmh_clocks[] = { 563 [RPMH_CXO_CLK] = &sc7280_bi_tcxo.hw, 564 [RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_ao.hw, 565 [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw, 566 [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw, 567 [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw, 568 [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw, 569 [RPMH_RF_CLK3] = &sdm845_rf_clk3.hw, 570 [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw, 571 [RPMH_RF_CLK4] = &sm8350_rf_clk4.hw, 572 [RPMH_RF_CLK4_A] = &sm8350_rf_clk4_ao.hw, 573 [RPMH_IPA_CLK] = &sdm845_ipa.hw, 574 [RPMH_PKA_CLK] = &sm8350_pka.hw, 575 [RPMH_HWKM_CLK] = &sm8350_hwkm.hw, 576 }; 577 578 static const struct clk_rpmh_desc clk_rpmh_sc7280 = { 579 .clks = sc7280_rpmh_clocks, 580 .num_clks = ARRAY_SIZE(sc7280_rpmh_clocks), 581 }; 582 583 DEFINE_CLK_RPMH_VRM(sm6350, ln_bb_clk2, ln_bb_clk2_ao, "lnbclkg2", 4); 584 DEFINE_CLK_RPMH_VRM(sm6350, ln_bb_clk3, ln_bb_clk3_ao, "lnbclkg3", 4); 585 DEFINE_CLK_RPMH_ARC(sm6350, qlink, qlink_ao, "qphy.lvl", 0x1, 4); 586 587 static struct clk_hw *sm6350_rpmh_clocks[] = { 588 [RPMH_CXO_CLK] = &sc7280_bi_tcxo.hw, 589 [RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_ao.hw, 590 [RPMH_LN_BB_CLK2] = &sm6350_ln_bb_clk2.hw, 591 [RPMH_LN_BB_CLK2_A] = &sm6350_ln_bb_clk2_ao.hw, 592 [RPMH_LN_BB_CLK3] = &sm6350_ln_bb_clk3.hw, 593 [RPMH_LN_BB_CLK3_A] = &sm6350_ln_bb_clk3_ao.hw, 594 [RPMH_QLINK_CLK] = &sm6350_qlink.hw, 595 [RPMH_QLINK_CLK_A] = &sm6350_qlink_ao.hw, 596 }; 597 598 static const struct clk_rpmh_desc clk_rpmh_sm6350 = { 599 .clks = sm6350_rpmh_clocks, 600 .num_clks = ARRAY_SIZE(sm6350_rpmh_clocks), 601 }; 602 603 DEFINE_CLK_RPMH_VRM(sdx65, ln_bb_clk1, ln_bb_clk1_ao, "lnbclka1", 4); 604 605 static struct clk_hw *sdx65_rpmh_clocks[] = { 606 [RPMH_CXO_CLK] = &sc7280_bi_tcxo.hw, 607 [RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_ao.hw, 608 [RPMH_LN_BB_CLK1] = &sdx65_ln_bb_clk1.hw, 609 [RPMH_LN_BB_CLK1_A] = &sdx65_ln_bb_clk1_ao.hw, 610 [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw, 611 [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw, 612 [RPMH_RF_CLK2] = &sdm845_rf_clk2.hw, 613 [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_ao.hw, 614 [RPMH_RF_CLK3] = &sdm845_rf_clk3.hw, 615 [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw, 616 [RPMH_RF_CLK4] = &sm8350_rf_clk4.hw, 617 [RPMH_RF_CLK4_A] = &sm8350_rf_clk4_ao.hw, 618 [RPMH_IPA_CLK] = &sdm845_ipa.hw, 619 [RPMH_QPIC_CLK] = &sdx55_qpic_clk.hw, 620 }; 621 622 static const struct clk_rpmh_desc clk_rpmh_sdx65 = { 623 .clks = sdx65_rpmh_clocks, 624 .num_clks = ARRAY_SIZE(sdx65_rpmh_clocks), 625 }; 626 627 static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec, 628 void *data) 629 { 630 struct clk_rpmh_desc *rpmh = data; 631 unsigned int idx = clkspec->args[0]; 632 633 if (idx >= rpmh->num_clks) { 634 pr_err("%s: invalid index %u\n", __func__, idx); 635 return ERR_PTR(-EINVAL); 636 } 637 638 return rpmh->clks[idx]; 639 } 640 641 static int clk_rpmh_probe(struct platform_device *pdev) 642 { 643 struct clk_hw **hw_clks; 644 struct clk_rpmh *rpmh_clk; 645 const struct clk_rpmh_desc *desc; 646 int ret, i; 647 648 desc = of_device_get_match_data(&pdev->dev); 649 if (!desc) 650 return -ENODEV; 651 652 hw_clks = desc->clks; 653 654 for (i = 0; i < desc->num_clks; i++) { 655 const char *name; 656 u32 res_addr; 657 size_t aux_data_len; 658 const struct bcm_db *data; 659 660 if (!hw_clks[i]) 661 continue; 662 663 name = hw_clks[i]->init->name; 664 665 rpmh_clk = to_clk_rpmh(hw_clks[i]); 666 res_addr = cmd_db_read_addr(rpmh_clk->res_name); 667 if (!res_addr) { 668 dev_err(&pdev->dev, "missing RPMh resource address for %s\n", 669 rpmh_clk->res_name); 670 return -ENODEV; 671 } 672 673 data = cmd_db_read_aux_data(rpmh_clk->res_name, &aux_data_len); 674 if (IS_ERR(data)) { 675 ret = PTR_ERR(data); 676 dev_err(&pdev->dev, 677 "error reading RPMh aux data for %s (%d)\n", 678 rpmh_clk->res_name, ret); 679 return ret; 680 } 681 682 /* Convert unit from Khz to Hz */ 683 if (aux_data_len == sizeof(*data)) 684 rpmh_clk->unit = le32_to_cpu(data->unit) * 1000ULL; 685 686 rpmh_clk->res_addr += res_addr; 687 rpmh_clk->dev = &pdev->dev; 688 689 ret = devm_clk_hw_register(&pdev->dev, hw_clks[i]); 690 if (ret) { 691 dev_err(&pdev->dev, "failed to register %s\n", name); 692 return ret; 693 } 694 } 695 696 /* typecast to silence compiler warning */ 697 ret = devm_of_clk_add_hw_provider(&pdev->dev, of_clk_rpmh_hw_get, 698 (void *)desc); 699 if (ret) { 700 dev_err(&pdev->dev, "Failed to add clock provider\n"); 701 return ret; 702 } 703 704 dev_dbg(&pdev->dev, "Registered RPMh clocks\n"); 705 706 return 0; 707 } 708 709 static const struct of_device_id clk_rpmh_match_table[] = { 710 { .compatible = "qcom,sc7180-rpmh-clk", .data = &clk_rpmh_sc7180}, 711 { .compatible = "qcom,sc8180x-rpmh-clk", .data = &clk_rpmh_sc8180x}, 712 { .compatible = "qcom,sc8280xp-rpmh-clk", .data = &clk_rpmh_sc8280xp}, 713 { .compatible = "qcom,sdm845-rpmh-clk", .data = &clk_rpmh_sdm845}, 714 { .compatible = "qcom,sdx55-rpmh-clk", .data = &clk_rpmh_sdx55}, 715 { .compatible = "qcom,sdx65-rpmh-clk", .data = &clk_rpmh_sdx65}, 716 { .compatible = "qcom,sm6350-rpmh-clk", .data = &clk_rpmh_sm6350}, 717 { .compatible = "qcom,sm8150-rpmh-clk", .data = &clk_rpmh_sm8150}, 718 { .compatible = "qcom,sm8250-rpmh-clk", .data = &clk_rpmh_sm8250}, 719 { .compatible = "qcom,sm8350-rpmh-clk", .data = &clk_rpmh_sm8350}, 720 { .compatible = "qcom,sm8450-rpmh-clk", .data = &clk_rpmh_sm8450}, 721 { .compatible = "qcom,sc7280-rpmh-clk", .data = &clk_rpmh_sc7280}, 722 { } 723 }; 724 MODULE_DEVICE_TABLE(of, clk_rpmh_match_table); 725 726 static struct platform_driver clk_rpmh_driver = { 727 .probe = clk_rpmh_probe, 728 .driver = { 729 .name = "clk-rpmh", 730 .of_match_table = clk_rpmh_match_table, 731 }, 732 }; 733 734 static int __init clk_rpmh_init(void) 735 { 736 return platform_driver_register(&clk_rpmh_driver); 737 } 738 core_initcall(clk_rpmh_init); 739 740 static void __exit clk_rpmh_exit(void) 741 { 742 platform_driver_unregister(&clk_rpmh_driver); 743 } 744 module_exit(clk_rpmh_exit); 745 746 MODULE_DESCRIPTION("QCOM RPMh Clock Driver"); 747 MODULE_LICENSE("GPL v2"); 748