1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2016, Linaro Limited 4 * Copyright (c) 2014, The Linux Foundation. All rights reserved. 5 */ 6 7 #include <linux/clk-provider.h> 8 #include <linux/err.h> 9 #include <linux/export.h> 10 #include <linux/init.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/mutex.h> 14 #include <linux/mfd/qcom_rpm.h> 15 #include <linux/of.h> 16 #include <linux/of_device.h> 17 #include <linux/platform_device.h> 18 19 #include <dt-bindings/mfd/qcom-rpm.h> 20 #include <dt-bindings/clock/qcom,rpmcc.h> 21 22 #define QCOM_RPM_MISC_CLK_TYPE 0x306b6c63 23 #define QCOM_RPM_SCALING_ENABLE_ID 0x2 24 #define QCOM_RPM_XO_MODE_ON 0x2 25 26 #define DEFINE_CLK_RPM(_platform, _name, _active, r_id) \ 27 static struct clk_rpm _platform##_##_active; \ 28 static struct clk_rpm _platform##_##_name = { \ 29 .rpm_clk_id = (r_id), \ 30 .peer = &_platform##_##_active, \ 31 .rate = INT_MAX, \ 32 .hw.init = &(struct clk_init_data){ \ 33 .ops = &clk_rpm_ops, \ 34 .name = #_name, \ 35 .parent_names = (const char *[]){ "pxo_board" }, \ 36 .num_parents = 1, \ 37 }, \ 38 }; \ 39 static struct clk_rpm _platform##_##_active = { \ 40 .rpm_clk_id = (r_id), \ 41 .peer = &_platform##_##_name, \ 42 .active_only = true, \ 43 .rate = INT_MAX, \ 44 .hw.init = &(struct clk_init_data){ \ 45 .ops = &clk_rpm_ops, \ 46 .name = #_active, \ 47 .parent_names = (const char *[]){ "pxo_board" }, \ 48 .num_parents = 1, \ 49 }, \ 50 } 51 52 #define DEFINE_CLK_RPM_XO_BUFFER(_platform, _name, _active, offset) \ 53 static struct clk_rpm _platform##_##_name = { \ 54 .rpm_clk_id = QCOM_RPM_CXO_BUFFERS, \ 55 .xo_offset = (offset), \ 56 .hw.init = &(struct clk_init_data){ \ 57 .ops = &clk_rpm_xo_ops, \ 58 .name = #_name, \ 59 .parent_names = (const char *[]){ "cxo_board" }, \ 60 .num_parents = 1, \ 61 }, \ 62 } 63 64 #define DEFINE_CLK_RPM_FIXED(_platform, _name, _active, r_id, r) \ 65 static struct clk_rpm _platform##_##_name = { \ 66 .rpm_clk_id = (r_id), \ 67 .rate = (r), \ 68 .hw.init = &(struct clk_init_data){ \ 69 .ops = &clk_rpm_fixed_ops, \ 70 .name = #_name, \ 71 .parent_names = (const char *[]){ "pxo" }, \ 72 .num_parents = 1, \ 73 }, \ 74 } 75 76 #define DEFINE_CLK_RPM_PXO_BRANCH(_platform, _name, _active, r_id, r) \ 77 static struct clk_rpm _platform##_##_active; \ 78 static struct clk_rpm _platform##_##_name = { \ 79 .rpm_clk_id = (r_id), \ 80 .active_only = true, \ 81 .peer = &_platform##_##_active, \ 82 .rate = (r), \ 83 .branch = true, \ 84 .hw.init = &(struct clk_init_data){ \ 85 .ops = &clk_rpm_branch_ops, \ 86 .name = #_name, \ 87 .parent_names = (const char *[]){ "pxo_board" }, \ 88 .num_parents = 1, \ 89 }, \ 90 }; \ 91 static struct clk_rpm _platform##_##_active = { \ 92 .rpm_clk_id = (r_id), \ 93 .peer = &_platform##_##_name, \ 94 .rate = (r), \ 95 .branch = true, \ 96 .hw.init = &(struct clk_init_data){ \ 97 .ops = &clk_rpm_branch_ops, \ 98 .name = #_active, \ 99 .parent_names = (const char *[]){ "pxo_board" }, \ 100 .num_parents = 1, \ 101 }, \ 102 } 103 104 #define DEFINE_CLK_RPM_CXO_BRANCH(_platform, _name, _active, r_id, r) \ 105 static struct clk_rpm _platform##_##_active; \ 106 static struct clk_rpm _platform##_##_name = { \ 107 .rpm_clk_id = (r_id), \ 108 .peer = &_platform##_##_active, \ 109 .rate = (r), \ 110 .branch = true, \ 111 .hw.init = &(struct clk_init_data){ \ 112 .ops = &clk_rpm_branch_ops, \ 113 .name = #_name, \ 114 .parent_names = (const char *[]){ "cxo_board" }, \ 115 .num_parents = 1, \ 116 }, \ 117 }; \ 118 static struct clk_rpm _platform##_##_active = { \ 119 .rpm_clk_id = (r_id), \ 120 .active_only = true, \ 121 .peer = &_platform##_##_name, \ 122 .rate = (r), \ 123 .branch = true, \ 124 .hw.init = &(struct clk_init_data){ \ 125 .ops = &clk_rpm_branch_ops, \ 126 .name = #_active, \ 127 .parent_names = (const char *[]){ "cxo_board" }, \ 128 .num_parents = 1, \ 129 }, \ 130 } 131 132 #define to_clk_rpm(_hw) container_of(_hw, struct clk_rpm, hw) 133 134 struct rpm_cc; 135 136 struct clk_rpm { 137 const int rpm_clk_id; 138 const int xo_offset; 139 const bool active_only; 140 unsigned long rate; 141 bool enabled; 142 bool branch; 143 struct clk_rpm *peer; 144 struct clk_hw hw; 145 struct qcom_rpm *rpm; 146 struct rpm_cc *rpm_cc; 147 }; 148 149 struct rpm_cc { 150 struct qcom_rpm *rpm; 151 struct clk_rpm **clks; 152 size_t num_clks; 153 u32 xo_buffer_value; 154 struct mutex xo_lock; 155 }; 156 157 struct rpm_clk_desc { 158 struct clk_rpm **clks; 159 size_t num_clks; 160 }; 161 162 static DEFINE_MUTEX(rpm_clk_lock); 163 164 static int clk_rpm_handoff(struct clk_rpm *r) 165 { 166 int ret; 167 u32 value = INT_MAX; 168 169 /* 170 * The vendor tree simply reads the status for this 171 * RPM clock. 172 */ 173 if (r->rpm_clk_id == QCOM_RPM_PLL_4 || 174 r->rpm_clk_id == QCOM_RPM_CXO_BUFFERS) 175 return 0; 176 177 ret = qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE, 178 r->rpm_clk_id, &value, 1); 179 if (ret) 180 return ret; 181 ret = qcom_rpm_write(r->rpm, QCOM_RPM_SLEEP_STATE, 182 r->rpm_clk_id, &value, 1); 183 if (ret) 184 return ret; 185 186 return 0; 187 } 188 189 static int clk_rpm_set_rate_active(struct clk_rpm *r, unsigned long rate) 190 { 191 u32 value = DIV_ROUND_UP(rate, 1000); /* to kHz */ 192 193 return qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE, 194 r->rpm_clk_id, &value, 1); 195 } 196 197 static int clk_rpm_set_rate_sleep(struct clk_rpm *r, unsigned long rate) 198 { 199 u32 value = DIV_ROUND_UP(rate, 1000); /* to kHz */ 200 201 return qcom_rpm_write(r->rpm, QCOM_RPM_SLEEP_STATE, 202 r->rpm_clk_id, &value, 1); 203 } 204 205 static void to_active_sleep(struct clk_rpm *r, unsigned long rate, 206 unsigned long *active, unsigned long *sleep) 207 { 208 *active = rate; 209 210 /* 211 * Active-only clocks don't care what the rate is during sleep. So, 212 * they vote for zero. 213 */ 214 if (r->active_only) 215 *sleep = 0; 216 else 217 *sleep = *active; 218 } 219 220 static int clk_rpm_prepare(struct clk_hw *hw) 221 { 222 struct clk_rpm *r = to_clk_rpm(hw); 223 struct clk_rpm *peer = r->peer; 224 unsigned long this_rate = 0, this_sleep_rate = 0; 225 unsigned long peer_rate = 0, peer_sleep_rate = 0; 226 unsigned long active_rate, sleep_rate; 227 int ret = 0; 228 229 mutex_lock(&rpm_clk_lock); 230 231 /* Don't send requests to the RPM if the rate has not been set. */ 232 if (!r->rate) 233 goto out; 234 235 to_active_sleep(r, r->rate, &this_rate, &this_sleep_rate); 236 237 /* Take peer clock's rate into account only if it's enabled. */ 238 if (peer->enabled) 239 to_active_sleep(peer, peer->rate, 240 &peer_rate, &peer_sleep_rate); 241 242 active_rate = max(this_rate, peer_rate); 243 244 if (r->branch) 245 active_rate = !!active_rate; 246 247 ret = clk_rpm_set_rate_active(r, active_rate); 248 if (ret) 249 goto out; 250 251 sleep_rate = max(this_sleep_rate, peer_sleep_rate); 252 if (r->branch) 253 sleep_rate = !!sleep_rate; 254 255 ret = clk_rpm_set_rate_sleep(r, sleep_rate); 256 if (ret) 257 /* Undo the active set vote and restore it */ 258 ret = clk_rpm_set_rate_active(r, peer_rate); 259 260 out: 261 if (!ret) 262 r->enabled = true; 263 264 mutex_unlock(&rpm_clk_lock); 265 266 return ret; 267 } 268 269 static void clk_rpm_unprepare(struct clk_hw *hw) 270 { 271 struct clk_rpm *r = to_clk_rpm(hw); 272 struct clk_rpm *peer = r->peer; 273 unsigned long peer_rate = 0, peer_sleep_rate = 0; 274 unsigned long active_rate, sleep_rate; 275 int ret; 276 277 mutex_lock(&rpm_clk_lock); 278 279 if (!r->rate) 280 goto out; 281 282 /* Take peer clock's rate into account only if it's enabled. */ 283 if (peer->enabled) 284 to_active_sleep(peer, peer->rate, &peer_rate, 285 &peer_sleep_rate); 286 287 active_rate = r->branch ? !!peer_rate : peer_rate; 288 ret = clk_rpm_set_rate_active(r, active_rate); 289 if (ret) 290 goto out; 291 292 sleep_rate = r->branch ? !!peer_sleep_rate : peer_sleep_rate; 293 ret = clk_rpm_set_rate_sleep(r, sleep_rate); 294 if (ret) 295 goto out; 296 297 r->enabled = false; 298 299 out: 300 mutex_unlock(&rpm_clk_lock); 301 } 302 303 static int clk_rpm_xo_prepare(struct clk_hw *hw) 304 { 305 struct clk_rpm *r = to_clk_rpm(hw); 306 struct rpm_cc *rcc = r->rpm_cc; 307 int ret, clk_id = r->rpm_clk_id; 308 u32 value; 309 310 mutex_lock(&rcc->xo_lock); 311 312 value = rcc->xo_buffer_value | (QCOM_RPM_XO_MODE_ON << r->xo_offset); 313 ret = qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE, clk_id, &value, 1); 314 if (!ret) { 315 r->enabled = true; 316 rcc->xo_buffer_value = value; 317 } 318 319 mutex_unlock(&rcc->xo_lock); 320 321 return ret; 322 } 323 324 static void clk_rpm_xo_unprepare(struct clk_hw *hw) 325 { 326 struct clk_rpm *r = to_clk_rpm(hw); 327 struct rpm_cc *rcc = r->rpm_cc; 328 int ret, clk_id = r->rpm_clk_id; 329 u32 value; 330 331 mutex_lock(&rcc->xo_lock); 332 333 value = rcc->xo_buffer_value & ~(QCOM_RPM_XO_MODE_ON << r->xo_offset); 334 ret = qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE, clk_id, &value, 1); 335 if (!ret) { 336 r->enabled = false; 337 rcc->xo_buffer_value = value; 338 } 339 340 mutex_unlock(&rcc->xo_lock); 341 } 342 343 static int clk_rpm_fixed_prepare(struct clk_hw *hw) 344 { 345 struct clk_rpm *r = to_clk_rpm(hw); 346 u32 value = 1; 347 int ret; 348 349 ret = qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE, 350 r->rpm_clk_id, &value, 1); 351 if (!ret) 352 r->enabled = true; 353 354 return ret; 355 } 356 357 static void clk_rpm_fixed_unprepare(struct clk_hw *hw) 358 { 359 struct clk_rpm *r = to_clk_rpm(hw); 360 u32 value = 0; 361 int ret; 362 363 ret = qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE, 364 r->rpm_clk_id, &value, 1); 365 if (!ret) 366 r->enabled = false; 367 } 368 369 static int clk_rpm_set_rate(struct clk_hw *hw, 370 unsigned long rate, unsigned long parent_rate) 371 { 372 struct clk_rpm *r = to_clk_rpm(hw); 373 struct clk_rpm *peer = r->peer; 374 unsigned long active_rate, sleep_rate; 375 unsigned long this_rate = 0, this_sleep_rate = 0; 376 unsigned long peer_rate = 0, peer_sleep_rate = 0; 377 int ret = 0; 378 379 mutex_lock(&rpm_clk_lock); 380 381 if (!r->enabled) 382 goto out; 383 384 to_active_sleep(r, rate, &this_rate, &this_sleep_rate); 385 386 /* Take peer clock's rate into account only if it's enabled. */ 387 if (peer->enabled) 388 to_active_sleep(peer, peer->rate, 389 &peer_rate, &peer_sleep_rate); 390 391 active_rate = max(this_rate, peer_rate); 392 ret = clk_rpm_set_rate_active(r, active_rate); 393 if (ret) 394 goto out; 395 396 sleep_rate = max(this_sleep_rate, peer_sleep_rate); 397 ret = clk_rpm_set_rate_sleep(r, sleep_rate); 398 if (ret) 399 goto out; 400 401 r->rate = rate; 402 403 out: 404 mutex_unlock(&rpm_clk_lock); 405 406 return ret; 407 } 408 409 static long clk_rpm_round_rate(struct clk_hw *hw, unsigned long rate, 410 unsigned long *parent_rate) 411 { 412 /* 413 * RPM handles rate rounding and we don't have a way to 414 * know what the rate will be, so just return whatever 415 * rate is requested. 416 */ 417 return rate; 418 } 419 420 static unsigned long clk_rpm_recalc_rate(struct clk_hw *hw, 421 unsigned long parent_rate) 422 { 423 struct clk_rpm *r = to_clk_rpm(hw); 424 425 /* 426 * RPM handles rate rounding and we don't have a way to 427 * know what the rate will be, so just return whatever 428 * rate was set. 429 */ 430 return r->rate; 431 } 432 433 static const struct clk_ops clk_rpm_xo_ops = { 434 .prepare = clk_rpm_xo_prepare, 435 .unprepare = clk_rpm_xo_unprepare, 436 }; 437 438 static const struct clk_ops clk_rpm_fixed_ops = { 439 .prepare = clk_rpm_fixed_prepare, 440 .unprepare = clk_rpm_fixed_unprepare, 441 .round_rate = clk_rpm_round_rate, 442 .recalc_rate = clk_rpm_recalc_rate, 443 }; 444 445 static const struct clk_ops clk_rpm_ops = { 446 .prepare = clk_rpm_prepare, 447 .unprepare = clk_rpm_unprepare, 448 .set_rate = clk_rpm_set_rate, 449 .round_rate = clk_rpm_round_rate, 450 .recalc_rate = clk_rpm_recalc_rate, 451 }; 452 453 static const struct clk_ops clk_rpm_branch_ops = { 454 .prepare = clk_rpm_prepare, 455 .unprepare = clk_rpm_unprepare, 456 .round_rate = clk_rpm_round_rate, 457 .recalc_rate = clk_rpm_recalc_rate, 458 }; 459 460 /* MSM8660/APQ8060 */ 461 DEFINE_CLK_RPM(msm8660, afab_clk, afab_a_clk, QCOM_RPM_APPS_FABRIC_CLK); 462 DEFINE_CLK_RPM(msm8660, sfab_clk, sfab_a_clk, QCOM_RPM_SYS_FABRIC_CLK); 463 DEFINE_CLK_RPM(msm8660, mmfab_clk, mmfab_a_clk, QCOM_RPM_MM_FABRIC_CLK); 464 DEFINE_CLK_RPM(msm8660, daytona_clk, daytona_a_clk, QCOM_RPM_DAYTONA_FABRIC_CLK); 465 DEFINE_CLK_RPM(msm8660, sfpb_clk, sfpb_a_clk, QCOM_RPM_SFPB_CLK); 466 DEFINE_CLK_RPM(msm8660, cfpb_clk, cfpb_a_clk, QCOM_RPM_CFPB_CLK); 467 DEFINE_CLK_RPM(msm8660, mmfpb_clk, mmfpb_a_clk, QCOM_RPM_MMFPB_CLK); 468 DEFINE_CLK_RPM(msm8660, smi_clk, smi_a_clk, QCOM_RPM_SMI_CLK); 469 DEFINE_CLK_RPM(msm8660, ebi1_clk, ebi1_a_clk, QCOM_RPM_EBI1_CLK); 470 DEFINE_CLK_RPM_FIXED(msm8660, pll4_clk, pll4_a_clk, QCOM_RPM_PLL_4, 540672000); 471 472 static struct clk_rpm *msm8660_clks[] = { 473 [RPM_APPS_FABRIC_CLK] = &msm8660_afab_clk, 474 [RPM_APPS_FABRIC_A_CLK] = &msm8660_afab_a_clk, 475 [RPM_SYS_FABRIC_CLK] = &msm8660_sfab_clk, 476 [RPM_SYS_FABRIC_A_CLK] = &msm8660_sfab_a_clk, 477 [RPM_MM_FABRIC_CLK] = &msm8660_mmfab_clk, 478 [RPM_MM_FABRIC_A_CLK] = &msm8660_mmfab_a_clk, 479 [RPM_DAYTONA_FABRIC_CLK] = &msm8660_daytona_clk, 480 [RPM_DAYTONA_FABRIC_A_CLK] = &msm8660_daytona_a_clk, 481 [RPM_SFPB_CLK] = &msm8660_sfpb_clk, 482 [RPM_SFPB_A_CLK] = &msm8660_sfpb_a_clk, 483 [RPM_CFPB_CLK] = &msm8660_cfpb_clk, 484 [RPM_CFPB_A_CLK] = &msm8660_cfpb_a_clk, 485 [RPM_MMFPB_CLK] = &msm8660_mmfpb_clk, 486 [RPM_MMFPB_A_CLK] = &msm8660_mmfpb_a_clk, 487 [RPM_SMI_CLK] = &msm8660_smi_clk, 488 [RPM_SMI_A_CLK] = &msm8660_smi_a_clk, 489 [RPM_EBI1_CLK] = &msm8660_ebi1_clk, 490 [RPM_EBI1_A_CLK] = &msm8660_ebi1_a_clk, 491 [RPM_PLL4_CLK] = &msm8660_pll4_clk, 492 }; 493 494 static const struct rpm_clk_desc rpm_clk_msm8660 = { 495 .clks = msm8660_clks, 496 .num_clks = ARRAY_SIZE(msm8660_clks), 497 }; 498 499 /* apq8064 */ 500 DEFINE_CLK_RPM(apq8064, afab_clk, afab_a_clk, QCOM_RPM_APPS_FABRIC_CLK); 501 DEFINE_CLK_RPM(apq8064, cfpb_clk, cfpb_a_clk, QCOM_RPM_CFPB_CLK); 502 DEFINE_CLK_RPM(apq8064, daytona_clk, daytona_a_clk, QCOM_RPM_DAYTONA_FABRIC_CLK); 503 DEFINE_CLK_RPM(apq8064, ebi1_clk, ebi1_a_clk, QCOM_RPM_EBI1_CLK); 504 DEFINE_CLK_RPM(apq8064, mmfab_clk, mmfab_a_clk, QCOM_RPM_MM_FABRIC_CLK); 505 DEFINE_CLK_RPM(apq8064, mmfpb_clk, mmfpb_a_clk, QCOM_RPM_MMFPB_CLK); 506 DEFINE_CLK_RPM(apq8064, sfab_clk, sfab_a_clk, QCOM_RPM_SYS_FABRIC_CLK); 507 DEFINE_CLK_RPM(apq8064, sfpb_clk, sfpb_a_clk, QCOM_RPM_SFPB_CLK); 508 DEFINE_CLK_RPM(apq8064, qdss_clk, qdss_a_clk, QCOM_RPM_QDSS_CLK); 509 DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_d0_clk, xo_d0_a_clk, 0); 510 DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_d1_clk, xo_d1_a_clk, 8); 511 DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_a0_clk, xo_a0_a_clk, 16); 512 DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_a1_clk, xo_a1_a_clk, 24); 513 DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_a2_clk, xo_a2_a_clk, 28); 514 515 static struct clk_rpm *apq8064_clks[] = { 516 [RPM_APPS_FABRIC_CLK] = &apq8064_afab_clk, 517 [RPM_APPS_FABRIC_A_CLK] = &apq8064_afab_a_clk, 518 [RPM_CFPB_CLK] = &apq8064_cfpb_clk, 519 [RPM_CFPB_A_CLK] = &apq8064_cfpb_a_clk, 520 [RPM_DAYTONA_FABRIC_CLK] = &apq8064_daytona_clk, 521 [RPM_DAYTONA_FABRIC_A_CLK] = &apq8064_daytona_a_clk, 522 [RPM_EBI1_CLK] = &apq8064_ebi1_clk, 523 [RPM_EBI1_A_CLK] = &apq8064_ebi1_a_clk, 524 [RPM_MM_FABRIC_CLK] = &apq8064_mmfab_clk, 525 [RPM_MM_FABRIC_A_CLK] = &apq8064_mmfab_a_clk, 526 [RPM_MMFPB_CLK] = &apq8064_mmfpb_clk, 527 [RPM_MMFPB_A_CLK] = &apq8064_mmfpb_a_clk, 528 [RPM_SYS_FABRIC_CLK] = &apq8064_sfab_clk, 529 [RPM_SYS_FABRIC_A_CLK] = &apq8064_sfab_a_clk, 530 [RPM_SFPB_CLK] = &apq8064_sfpb_clk, 531 [RPM_SFPB_A_CLK] = &apq8064_sfpb_a_clk, 532 [RPM_QDSS_CLK] = &apq8064_qdss_clk, 533 [RPM_QDSS_A_CLK] = &apq8064_qdss_a_clk, 534 [RPM_XO_D0] = &apq8064_xo_d0_clk, 535 [RPM_XO_D1] = &apq8064_xo_d1_clk, 536 [RPM_XO_A0] = &apq8064_xo_a0_clk, 537 [RPM_XO_A1] = &apq8064_xo_a1_clk, 538 [RPM_XO_A2] = &apq8064_xo_a2_clk, 539 }; 540 541 static const struct rpm_clk_desc rpm_clk_apq8064 = { 542 .clks = apq8064_clks, 543 .num_clks = ARRAY_SIZE(apq8064_clks), 544 }; 545 546 static const struct of_device_id rpm_clk_match_table[] = { 547 { .compatible = "qcom,rpmcc-msm8660", .data = &rpm_clk_msm8660 }, 548 { .compatible = "qcom,rpmcc-apq8060", .data = &rpm_clk_msm8660 }, 549 { .compatible = "qcom,rpmcc-apq8064", .data = &rpm_clk_apq8064 }, 550 { } 551 }; 552 MODULE_DEVICE_TABLE(of, rpm_clk_match_table); 553 554 static struct clk_hw *qcom_rpm_clk_hw_get(struct of_phandle_args *clkspec, 555 void *data) 556 { 557 struct rpm_cc *rcc = data; 558 unsigned int idx = clkspec->args[0]; 559 560 if (idx >= rcc->num_clks) { 561 pr_err("%s: invalid index %u\n", __func__, idx); 562 return ERR_PTR(-EINVAL); 563 } 564 565 return rcc->clks[idx] ? &rcc->clks[idx]->hw : ERR_PTR(-ENOENT); 566 } 567 568 static int rpm_clk_probe(struct platform_device *pdev) 569 { 570 struct rpm_cc *rcc; 571 int ret; 572 size_t num_clks, i; 573 struct qcom_rpm *rpm; 574 struct clk_rpm **rpm_clks; 575 const struct rpm_clk_desc *desc; 576 577 rpm = dev_get_drvdata(pdev->dev.parent); 578 if (!rpm) { 579 dev_err(&pdev->dev, "Unable to retrieve handle to RPM\n"); 580 return -ENODEV; 581 } 582 583 desc = of_device_get_match_data(&pdev->dev); 584 if (!desc) 585 return -EINVAL; 586 587 rpm_clks = desc->clks; 588 num_clks = desc->num_clks; 589 590 rcc = devm_kzalloc(&pdev->dev, sizeof(*rcc), GFP_KERNEL); 591 if (!rcc) 592 return -ENOMEM; 593 594 rcc->clks = rpm_clks; 595 rcc->num_clks = num_clks; 596 mutex_init(&rcc->xo_lock); 597 598 for (i = 0; i < num_clks; i++) { 599 if (!rpm_clks[i]) 600 continue; 601 602 rpm_clks[i]->rpm = rpm; 603 rpm_clks[i]->rpm_cc = rcc; 604 605 ret = clk_rpm_handoff(rpm_clks[i]); 606 if (ret) 607 goto err; 608 } 609 610 for (i = 0; i < num_clks; i++) { 611 if (!rpm_clks[i]) 612 continue; 613 614 ret = devm_clk_hw_register(&pdev->dev, &rpm_clks[i]->hw); 615 if (ret) 616 goto err; 617 } 618 619 ret = of_clk_add_hw_provider(pdev->dev.of_node, qcom_rpm_clk_hw_get, 620 rcc); 621 if (ret) 622 goto err; 623 624 return 0; 625 err: 626 dev_err(&pdev->dev, "Error registering RPM Clock driver (%d)\n", ret); 627 return ret; 628 } 629 630 static int rpm_clk_remove(struct platform_device *pdev) 631 { 632 of_clk_del_provider(pdev->dev.of_node); 633 return 0; 634 } 635 636 static struct platform_driver rpm_clk_driver = { 637 .driver = { 638 .name = "qcom-clk-rpm", 639 .of_match_table = rpm_clk_match_table, 640 }, 641 .probe = rpm_clk_probe, 642 .remove = rpm_clk_remove, 643 }; 644 645 static int __init rpm_clk_init(void) 646 { 647 return platform_driver_register(&rpm_clk_driver); 648 } 649 core_initcall(rpm_clk_init); 650 651 static void __exit rpm_clk_exit(void) 652 { 653 platform_driver_unregister(&rpm_clk_driver); 654 } 655 module_exit(rpm_clk_exit); 656 657 MODULE_DESCRIPTION("Qualcomm RPM Clock Controller Driver"); 658 MODULE_LICENSE("GPL v2"); 659 MODULE_ALIAS("platform:qcom-clk-rpm"); 660