1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2013, 2018, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/bitops.h> 8 #include <linux/err.h> 9 #include <linux/bug.h> 10 #include <linux/export.h> 11 #include <linux/clk-provider.h> 12 #include <linux/delay.h> 13 #include <linux/regmap.h> 14 #include <linux/math64.h> 15 16 #include <asm/div64.h> 17 18 #include "clk-rcg.h" 19 #include "common.h" 20 21 #define CMD_REG 0x0 22 #define CMD_UPDATE BIT(0) 23 #define CMD_ROOT_EN BIT(1) 24 #define CMD_DIRTY_CFG BIT(4) 25 #define CMD_DIRTY_N BIT(5) 26 #define CMD_DIRTY_M BIT(6) 27 #define CMD_DIRTY_D BIT(7) 28 #define CMD_ROOT_OFF BIT(31) 29 30 #define CFG_REG 0x4 31 #define CFG_SRC_DIV_SHIFT 0 32 #define CFG_SRC_SEL_SHIFT 8 33 #define CFG_SRC_SEL_MASK (0x7 << CFG_SRC_SEL_SHIFT) 34 #define CFG_MODE_SHIFT 12 35 #define CFG_MODE_MASK (0x3 << CFG_MODE_SHIFT) 36 #define CFG_MODE_DUAL_EDGE (0x2 << CFG_MODE_SHIFT) 37 #define CFG_HW_CLK_CTRL_MASK BIT(20) 38 39 #define M_REG 0x8 40 #define N_REG 0xc 41 #define D_REG 0x10 42 43 enum freq_policy { 44 FLOOR, 45 CEIL, 46 }; 47 48 static int clk_rcg2_is_enabled(struct clk_hw *hw) 49 { 50 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 51 u32 cmd; 52 int ret; 53 54 ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd); 55 if (ret) 56 return ret; 57 58 return (cmd & CMD_ROOT_OFF) == 0; 59 } 60 61 static u8 clk_rcg2_get_parent(struct clk_hw *hw) 62 { 63 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 64 int num_parents = clk_hw_get_num_parents(hw); 65 u32 cfg; 66 int i, ret; 67 68 ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg); 69 if (ret) 70 goto err; 71 72 cfg &= CFG_SRC_SEL_MASK; 73 cfg >>= CFG_SRC_SEL_SHIFT; 74 75 for (i = 0; i < num_parents; i++) 76 if (cfg == rcg->parent_map[i].cfg) 77 return i; 78 79 err: 80 pr_debug("%s: Clock %s has invalid parent, using default.\n", 81 __func__, clk_hw_get_name(hw)); 82 return 0; 83 } 84 85 static int update_config(struct clk_rcg2 *rcg) 86 { 87 int count, ret; 88 u32 cmd; 89 struct clk_hw *hw = &rcg->clkr.hw; 90 const char *name = clk_hw_get_name(hw); 91 92 ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, 93 CMD_UPDATE, CMD_UPDATE); 94 if (ret) 95 return ret; 96 97 /* Wait for update to take effect */ 98 for (count = 500; count > 0; count--) { 99 ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd); 100 if (ret) 101 return ret; 102 if (!(cmd & CMD_UPDATE)) 103 return 0; 104 udelay(1); 105 } 106 107 WARN(1, "%s: rcg didn't update its configuration.", name); 108 return 0; 109 } 110 111 static int clk_rcg2_set_parent(struct clk_hw *hw, u8 index) 112 { 113 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 114 int ret; 115 u32 cfg = rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT; 116 117 ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, 118 CFG_SRC_SEL_MASK, cfg); 119 if (ret) 120 return ret; 121 122 return update_config(rcg); 123 } 124 125 /* 126 * Calculate m/n:d rate 127 * 128 * parent_rate m 129 * rate = ----------- x --- 130 * hid_div n 131 */ 132 static unsigned long 133 calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 hid_div) 134 { 135 if (hid_div) { 136 rate *= 2; 137 rate /= hid_div + 1; 138 } 139 140 if (mode) { 141 u64 tmp = rate; 142 tmp *= m; 143 do_div(tmp, n); 144 rate = tmp; 145 } 146 147 return rate; 148 } 149 150 static unsigned long 151 clk_rcg2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 152 { 153 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 154 u32 cfg, hid_div, m = 0, n = 0, mode = 0, mask; 155 156 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg); 157 158 if (rcg->mnd_width) { 159 mask = BIT(rcg->mnd_width) - 1; 160 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + M_REG, &m); 161 m &= mask; 162 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + N_REG, &n); 163 n = ~n; 164 n &= mask; 165 n += m; 166 mode = cfg & CFG_MODE_MASK; 167 mode >>= CFG_MODE_SHIFT; 168 } 169 170 mask = BIT(rcg->hid_width) - 1; 171 hid_div = cfg >> CFG_SRC_DIV_SHIFT; 172 hid_div &= mask; 173 174 return calc_rate(parent_rate, m, n, mode, hid_div); 175 } 176 177 static int _freq_tbl_determine_rate(struct clk_hw *hw, const struct freq_tbl *f, 178 struct clk_rate_request *req, 179 enum freq_policy policy) 180 { 181 unsigned long clk_flags, rate = req->rate; 182 struct clk_hw *p; 183 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 184 int index; 185 186 switch (policy) { 187 case FLOOR: 188 f = qcom_find_freq_floor(f, rate); 189 break; 190 case CEIL: 191 f = qcom_find_freq(f, rate); 192 break; 193 default: 194 return -EINVAL; 195 }; 196 197 if (!f) 198 return -EINVAL; 199 200 index = qcom_find_src_index(hw, rcg->parent_map, f->src); 201 if (index < 0) 202 return index; 203 204 clk_flags = clk_hw_get_flags(hw); 205 p = clk_hw_get_parent_by_index(hw, index); 206 if (clk_flags & CLK_SET_RATE_PARENT) { 207 rate = f->freq; 208 if (f->pre_div) { 209 rate /= 2; 210 rate *= f->pre_div + 1; 211 } 212 213 if (f->n) { 214 u64 tmp = rate; 215 tmp = tmp * f->n; 216 do_div(tmp, f->m); 217 rate = tmp; 218 } 219 } else { 220 rate = clk_hw_get_rate(p); 221 } 222 req->best_parent_hw = p; 223 req->best_parent_rate = rate; 224 req->rate = f->freq; 225 226 return 0; 227 } 228 229 static int clk_rcg2_determine_rate(struct clk_hw *hw, 230 struct clk_rate_request *req) 231 { 232 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 233 234 return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, CEIL); 235 } 236 237 static int clk_rcg2_determine_floor_rate(struct clk_hw *hw, 238 struct clk_rate_request *req) 239 { 240 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 241 242 return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, FLOOR); 243 } 244 245 static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f) 246 { 247 u32 cfg, mask; 248 struct clk_hw *hw = &rcg->clkr.hw; 249 int ret, index = qcom_find_src_index(hw, rcg->parent_map, f->src); 250 251 if (index < 0) 252 return index; 253 254 if (rcg->mnd_width && f->n) { 255 mask = BIT(rcg->mnd_width) - 1; 256 ret = regmap_update_bits(rcg->clkr.regmap, 257 rcg->cmd_rcgr + M_REG, mask, f->m); 258 if (ret) 259 return ret; 260 261 ret = regmap_update_bits(rcg->clkr.regmap, 262 rcg->cmd_rcgr + N_REG, mask, ~(f->n - f->m)); 263 if (ret) 264 return ret; 265 266 ret = regmap_update_bits(rcg->clkr.regmap, 267 rcg->cmd_rcgr + D_REG, mask, ~f->n); 268 if (ret) 269 return ret; 270 } 271 272 mask = BIT(rcg->hid_width) - 1; 273 mask |= CFG_SRC_SEL_MASK | CFG_MODE_MASK | CFG_HW_CLK_CTRL_MASK; 274 cfg = f->pre_div << CFG_SRC_DIV_SHIFT; 275 cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT; 276 if (rcg->mnd_width && f->n && (f->m != f->n)) 277 cfg |= CFG_MODE_DUAL_EDGE; 278 279 return regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, 280 mask, cfg); 281 } 282 283 static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f) 284 { 285 int ret; 286 287 ret = __clk_rcg2_configure(rcg, f); 288 if (ret) 289 return ret; 290 291 return update_config(rcg); 292 } 293 294 static int __clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate, 295 enum freq_policy policy) 296 { 297 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 298 const struct freq_tbl *f; 299 300 switch (policy) { 301 case FLOOR: 302 f = qcom_find_freq_floor(rcg->freq_tbl, rate); 303 break; 304 case CEIL: 305 f = qcom_find_freq(rcg->freq_tbl, rate); 306 break; 307 default: 308 return -EINVAL; 309 }; 310 311 if (!f) 312 return -EINVAL; 313 314 return clk_rcg2_configure(rcg, f); 315 } 316 317 static int clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate, 318 unsigned long parent_rate) 319 { 320 return __clk_rcg2_set_rate(hw, rate, CEIL); 321 } 322 323 static int clk_rcg2_set_floor_rate(struct clk_hw *hw, unsigned long rate, 324 unsigned long parent_rate) 325 { 326 return __clk_rcg2_set_rate(hw, rate, FLOOR); 327 } 328 329 static int clk_rcg2_set_rate_and_parent(struct clk_hw *hw, 330 unsigned long rate, unsigned long parent_rate, u8 index) 331 { 332 return __clk_rcg2_set_rate(hw, rate, CEIL); 333 } 334 335 static int clk_rcg2_set_floor_rate_and_parent(struct clk_hw *hw, 336 unsigned long rate, unsigned long parent_rate, u8 index) 337 { 338 return __clk_rcg2_set_rate(hw, rate, FLOOR); 339 } 340 341 const struct clk_ops clk_rcg2_ops = { 342 .is_enabled = clk_rcg2_is_enabled, 343 .get_parent = clk_rcg2_get_parent, 344 .set_parent = clk_rcg2_set_parent, 345 .recalc_rate = clk_rcg2_recalc_rate, 346 .determine_rate = clk_rcg2_determine_rate, 347 .set_rate = clk_rcg2_set_rate, 348 .set_rate_and_parent = clk_rcg2_set_rate_and_parent, 349 }; 350 EXPORT_SYMBOL_GPL(clk_rcg2_ops); 351 352 const struct clk_ops clk_rcg2_floor_ops = { 353 .is_enabled = clk_rcg2_is_enabled, 354 .get_parent = clk_rcg2_get_parent, 355 .set_parent = clk_rcg2_set_parent, 356 .recalc_rate = clk_rcg2_recalc_rate, 357 .determine_rate = clk_rcg2_determine_floor_rate, 358 .set_rate = clk_rcg2_set_floor_rate, 359 .set_rate_and_parent = clk_rcg2_set_floor_rate_and_parent, 360 }; 361 EXPORT_SYMBOL_GPL(clk_rcg2_floor_ops); 362 363 struct frac_entry { 364 int num; 365 int den; 366 }; 367 368 static const struct frac_entry frac_table_675m[] = { /* link rate of 270M */ 369 { 52, 295 }, /* 119 M */ 370 { 11, 57 }, /* 130.25 M */ 371 { 63, 307 }, /* 138.50 M */ 372 { 11, 50 }, /* 148.50 M */ 373 { 47, 206 }, /* 154 M */ 374 { 31, 100 }, /* 205.25 M */ 375 { 107, 269 }, /* 268.50 M */ 376 { }, 377 }; 378 379 static struct frac_entry frac_table_810m[] = { /* Link rate of 162M */ 380 { 31, 211 }, /* 119 M */ 381 { 32, 199 }, /* 130.25 M */ 382 { 63, 307 }, /* 138.50 M */ 383 { 11, 60 }, /* 148.50 M */ 384 { 50, 263 }, /* 154 M */ 385 { 31, 120 }, /* 205.25 M */ 386 { 119, 359 }, /* 268.50 M */ 387 { }, 388 }; 389 390 static int clk_edp_pixel_set_rate(struct clk_hw *hw, unsigned long rate, 391 unsigned long parent_rate) 392 { 393 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 394 struct freq_tbl f = *rcg->freq_tbl; 395 const struct frac_entry *frac; 396 int delta = 100000; 397 s64 src_rate = parent_rate; 398 s64 request; 399 u32 mask = BIT(rcg->hid_width) - 1; 400 u32 hid_div; 401 402 if (src_rate == 810000000) 403 frac = frac_table_810m; 404 else 405 frac = frac_table_675m; 406 407 for (; frac->num; frac++) { 408 request = rate; 409 request *= frac->den; 410 request = div_s64(request, frac->num); 411 if ((src_rate < (request - delta)) || 412 (src_rate > (request + delta))) 413 continue; 414 415 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, 416 &hid_div); 417 f.pre_div = hid_div; 418 f.pre_div >>= CFG_SRC_DIV_SHIFT; 419 f.pre_div &= mask; 420 f.m = frac->num; 421 f.n = frac->den; 422 423 return clk_rcg2_configure(rcg, &f); 424 } 425 426 return -EINVAL; 427 } 428 429 static int clk_edp_pixel_set_rate_and_parent(struct clk_hw *hw, 430 unsigned long rate, unsigned long parent_rate, u8 index) 431 { 432 /* Parent index is set statically in frequency table */ 433 return clk_edp_pixel_set_rate(hw, rate, parent_rate); 434 } 435 436 static int clk_edp_pixel_determine_rate(struct clk_hw *hw, 437 struct clk_rate_request *req) 438 { 439 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 440 const struct freq_tbl *f = rcg->freq_tbl; 441 const struct frac_entry *frac; 442 int delta = 100000; 443 s64 request; 444 u32 mask = BIT(rcg->hid_width) - 1; 445 u32 hid_div; 446 int index = qcom_find_src_index(hw, rcg->parent_map, f->src); 447 448 /* Force the correct parent */ 449 req->best_parent_hw = clk_hw_get_parent_by_index(hw, index); 450 req->best_parent_rate = clk_hw_get_rate(req->best_parent_hw); 451 452 if (req->best_parent_rate == 810000000) 453 frac = frac_table_810m; 454 else 455 frac = frac_table_675m; 456 457 for (; frac->num; frac++) { 458 request = req->rate; 459 request *= frac->den; 460 request = div_s64(request, frac->num); 461 if ((req->best_parent_rate < (request - delta)) || 462 (req->best_parent_rate > (request + delta))) 463 continue; 464 465 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, 466 &hid_div); 467 hid_div >>= CFG_SRC_DIV_SHIFT; 468 hid_div &= mask; 469 470 req->rate = calc_rate(req->best_parent_rate, 471 frac->num, frac->den, 472 !!frac->den, hid_div); 473 return 0; 474 } 475 476 return -EINVAL; 477 } 478 479 const struct clk_ops clk_edp_pixel_ops = { 480 .is_enabled = clk_rcg2_is_enabled, 481 .get_parent = clk_rcg2_get_parent, 482 .set_parent = clk_rcg2_set_parent, 483 .recalc_rate = clk_rcg2_recalc_rate, 484 .set_rate = clk_edp_pixel_set_rate, 485 .set_rate_and_parent = clk_edp_pixel_set_rate_and_parent, 486 .determine_rate = clk_edp_pixel_determine_rate, 487 }; 488 EXPORT_SYMBOL_GPL(clk_edp_pixel_ops); 489 490 static int clk_byte_determine_rate(struct clk_hw *hw, 491 struct clk_rate_request *req) 492 { 493 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 494 const struct freq_tbl *f = rcg->freq_tbl; 495 int index = qcom_find_src_index(hw, rcg->parent_map, f->src); 496 unsigned long parent_rate, div; 497 u32 mask = BIT(rcg->hid_width) - 1; 498 struct clk_hw *p; 499 500 if (req->rate == 0) 501 return -EINVAL; 502 503 req->best_parent_hw = p = clk_hw_get_parent_by_index(hw, index); 504 req->best_parent_rate = parent_rate = clk_hw_round_rate(p, req->rate); 505 506 div = DIV_ROUND_UP((2 * parent_rate), req->rate) - 1; 507 div = min_t(u32, div, mask); 508 509 req->rate = calc_rate(parent_rate, 0, 0, 0, div); 510 511 return 0; 512 } 513 514 static int clk_byte_set_rate(struct clk_hw *hw, unsigned long rate, 515 unsigned long parent_rate) 516 { 517 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 518 struct freq_tbl f = *rcg->freq_tbl; 519 unsigned long div; 520 u32 mask = BIT(rcg->hid_width) - 1; 521 522 div = DIV_ROUND_UP((2 * parent_rate), rate) - 1; 523 div = min_t(u32, div, mask); 524 525 f.pre_div = div; 526 527 return clk_rcg2_configure(rcg, &f); 528 } 529 530 static int clk_byte_set_rate_and_parent(struct clk_hw *hw, 531 unsigned long rate, unsigned long parent_rate, u8 index) 532 { 533 /* Parent index is set statically in frequency table */ 534 return clk_byte_set_rate(hw, rate, parent_rate); 535 } 536 537 const struct clk_ops clk_byte_ops = { 538 .is_enabled = clk_rcg2_is_enabled, 539 .get_parent = clk_rcg2_get_parent, 540 .set_parent = clk_rcg2_set_parent, 541 .recalc_rate = clk_rcg2_recalc_rate, 542 .set_rate = clk_byte_set_rate, 543 .set_rate_and_parent = clk_byte_set_rate_and_parent, 544 .determine_rate = clk_byte_determine_rate, 545 }; 546 EXPORT_SYMBOL_GPL(clk_byte_ops); 547 548 static int clk_byte2_determine_rate(struct clk_hw *hw, 549 struct clk_rate_request *req) 550 { 551 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 552 unsigned long parent_rate, div; 553 u32 mask = BIT(rcg->hid_width) - 1; 554 struct clk_hw *p; 555 unsigned long rate = req->rate; 556 557 if (rate == 0) 558 return -EINVAL; 559 560 p = req->best_parent_hw; 561 req->best_parent_rate = parent_rate = clk_hw_round_rate(p, rate); 562 563 div = DIV_ROUND_UP((2 * parent_rate), rate) - 1; 564 div = min_t(u32, div, mask); 565 566 req->rate = calc_rate(parent_rate, 0, 0, 0, div); 567 568 return 0; 569 } 570 571 static int clk_byte2_set_rate(struct clk_hw *hw, unsigned long rate, 572 unsigned long parent_rate) 573 { 574 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 575 struct freq_tbl f = { 0 }; 576 unsigned long div; 577 int i, num_parents = clk_hw_get_num_parents(hw); 578 u32 mask = BIT(rcg->hid_width) - 1; 579 u32 cfg; 580 581 div = DIV_ROUND_UP((2 * parent_rate), rate) - 1; 582 div = min_t(u32, div, mask); 583 584 f.pre_div = div; 585 586 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg); 587 cfg &= CFG_SRC_SEL_MASK; 588 cfg >>= CFG_SRC_SEL_SHIFT; 589 590 for (i = 0; i < num_parents; i++) { 591 if (cfg == rcg->parent_map[i].cfg) { 592 f.src = rcg->parent_map[i].src; 593 return clk_rcg2_configure(rcg, &f); 594 } 595 } 596 597 return -EINVAL; 598 } 599 600 static int clk_byte2_set_rate_and_parent(struct clk_hw *hw, 601 unsigned long rate, unsigned long parent_rate, u8 index) 602 { 603 /* Read the hardware to determine parent during set_rate */ 604 return clk_byte2_set_rate(hw, rate, parent_rate); 605 } 606 607 const struct clk_ops clk_byte2_ops = { 608 .is_enabled = clk_rcg2_is_enabled, 609 .get_parent = clk_rcg2_get_parent, 610 .set_parent = clk_rcg2_set_parent, 611 .recalc_rate = clk_rcg2_recalc_rate, 612 .set_rate = clk_byte2_set_rate, 613 .set_rate_and_parent = clk_byte2_set_rate_and_parent, 614 .determine_rate = clk_byte2_determine_rate, 615 }; 616 EXPORT_SYMBOL_GPL(clk_byte2_ops); 617 618 static const struct frac_entry frac_table_pixel[] = { 619 { 3, 8 }, 620 { 2, 9 }, 621 { 4, 9 }, 622 { 1, 1 }, 623 { } 624 }; 625 626 static int clk_pixel_determine_rate(struct clk_hw *hw, 627 struct clk_rate_request *req) 628 { 629 unsigned long request, src_rate; 630 int delta = 100000; 631 const struct frac_entry *frac = frac_table_pixel; 632 633 for (; frac->num; frac++) { 634 request = (req->rate * frac->den) / frac->num; 635 636 src_rate = clk_hw_round_rate(req->best_parent_hw, request); 637 if ((src_rate < (request - delta)) || 638 (src_rate > (request + delta))) 639 continue; 640 641 req->best_parent_rate = src_rate; 642 req->rate = (src_rate * frac->num) / frac->den; 643 return 0; 644 } 645 646 return -EINVAL; 647 } 648 649 static int clk_pixel_set_rate(struct clk_hw *hw, unsigned long rate, 650 unsigned long parent_rate) 651 { 652 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 653 struct freq_tbl f = { 0 }; 654 const struct frac_entry *frac = frac_table_pixel; 655 unsigned long request; 656 int delta = 100000; 657 u32 mask = BIT(rcg->hid_width) - 1; 658 u32 hid_div, cfg; 659 int i, num_parents = clk_hw_get_num_parents(hw); 660 661 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg); 662 cfg &= CFG_SRC_SEL_MASK; 663 cfg >>= CFG_SRC_SEL_SHIFT; 664 665 for (i = 0; i < num_parents; i++) 666 if (cfg == rcg->parent_map[i].cfg) { 667 f.src = rcg->parent_map[i].src; 668 break; 669 } 670 671 for (; frac->num; frac++) { 672 request = (rate * frac->den) / frac->num; 673 674 if ((parent_rate < (request - delta)) || 675 (parent_rate > (request + delta))) 676 continue; 677 678 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, 679 &hid_div); 680 f.pre_div = hid_div; 681 f.pre_div >>= CFG_SRC_DIV_SHIFT; 682 f.pre_div &= mask; 683 f.m = frac->num; 684 f.n = frac->den; 685 686 return clk_rcg2_configure(rcg, &f); 687 } 688 return -EINVAL; 689 } 690 691 static int clk_pixel_set_rate_and_parent(struct clk_hw *hw, unsigned long rate, 692 unsigned long parent_rate, u8 index) 693 { 694 return clk_pixel_set_rate(hw, rate, parent_rate); 695 } 696 697 const struct clk_ops clk_pixel_ops = { 698 .is_enabled = clk_rcg2_is_enabled, 699 .get_parent = clk_rcg2_get_parent, 700 .set_parent = clk_rcg2_set_parent, 701 .recalc_rate = clk_rcg2_recalc_rate, 702 .set_rate = clk_pixel_set_rate, 703 .set_rate_and_parent = clk_pixel_set_rate_and_parent, 704 .determine_rate = clk_pixel_determine_rate, 705 }; 706 EXPORT_SYMBOL_GPL(clk_pixel_ops); 707 708 static int clk_gfx3d_determine_rate(struct clk_hw *hw, 709 struct clk_rate_request *req) 710 { 711 struct clk_rate_request parent_req = { }; 712 struct clk_hw *p2, *p8, *p9, *xo; 713 unsigned long p9_rate; 714 int ret; 715 716 xo = clk_hw_get_parent_by_index(hw, 0); 717 if (req->rate == clk_hw_get_rate(xo)) { 718 req->best_parent_hw = xo; 719 return 0; 720 } 721 722 p9 = clk_hw_get_parent_by_index(hw, 2); 723 p2 = clk_hw_get_parent_by_index(hw, 3); 724 p8 = clk_hw_get_parent_by_index(hw, 4); 725 726 /* PLL9 is a fixed rate PLL */ 727 p9_rate = clk_hw_get_rate(p9); 728 729 parent_req.rate = req->rate = min(req->rate, p9_rate); 730 if (req->rate == p9_rate) { 731 req->rate = req->best_parent_rate = p9_rate; 732 req->best_parent_hw = p9; 733 return 0; 734 } 735 736 if (req->best_parent_hw == p9) { 737 /* Are we going back to a previously used rate? */ 738 if (clk_hw_get_rate(p8) == req->rate) 739 req->best_parent_hw = p8; 740 else 741 req->best_parent_hw = p2; 742 } else if (req->best_parent_hw == p8) { 743 req->best_parent_hw = p2; 744 } else { 745 req->best_parent_hw = p8; 746 } 747 748 ret = __clk_determine_rate(req->best_parent_hw, &parent_req); 749 if (ret) 750 return ret; 751 752 req->rate = req->best_parent_rate = parent_req.rate; 753 754 return 0; 755 } 756 757 static int clk_gfx3d_set_rate_and_parent(struct clk_hw *hw, unsigned long rate, 758 unsigned long parent_rate, u8 index) 759 { 760 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 761 u32 cfg; 762 int ret; 763 764 /* Just mux it, we don't use the division or m/n hardware */ 765 cfg = rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT; 766 ret = regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, cfg); 767 if (ret) 768 return ret; 769 770 return update_config(rcg); 771 } 772 773 static int clk_gfx3d_set_rate(struct clk_hw *hw, unsigned long rate, 774 unsigned long parent_rate) 775 { 776 /* 777 * We should never get here; clk_gfx3d_determine_rate() should always 778 * make us use a different parent than what we're currently using, so 779 * clk_gfx3d_set_rate_and_parent() should always be called. 780 */ 781 return 0; 782 } 783 784 const struct clk_ops clk_gfx3d_ops = { 785 .is_enabled = clk_rcg2_is_enabled, 786 .get_parent = clk_rcg2_get_parent, 787 .set_parent = clk_rcg2_set_parent, 788 .recalc_rate = clk_rcg2_recalc_rate, 789 .set_rate = clk_gfx3d_set_rate, 790 .set_rate_and_parent = clk_gfx3d_set_rate_and_parent, 791 .determine_rate = clk_gfx3d_determine_rate, 792 }; 793 EXPORT_SYMBOL_GPL(clk_gfx3d_ops); 794 795 static int clk_rcg2_set_force_enable(struct clk_hw *hw) 796 { 797 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 798 const char *name = clk_hw_get_name(hw); 799 int ret, count; 800 801 ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, 802 CMD_ROOT_EN, CMD_ROOT_EN); 803 if (ret) 804 return ret; 805 806 /* wait for RCG to turn ON */ 807 for (count = 500; count > 0; count--) { 808 if (clk_rcg2_is_enabled(hw)) 809 return 0; 810 811 udelay(1); 812 } 813 814 pr_err("%s: RCG did not turn on\n", name); 815 return -ETIMEDOUT; 816 } 817 818 static int clk_rcg2_clear_force_enable(struct clk_hw *hw) 819 { 820 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 821 822 return regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, 823 CMD_ROOT_EN, 0); 824 } 825 826 static int 827 clk_rcg2_shared_force_enable_clear(struct clk_hw *hw, const struct freq_tbl *f) 828 { 829 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 830 int ret; 831 832 ret = clk_rcg2_set_force_enable(hw); 833 if (ret) 834 return ret; 835 836 ret = clk_rcg2_configure(rcg, f); 837 if (ret) 838 return ret; 839 840 return clk_rcg2_clear_force_enable(hw); 841 } 842 843 static int clk_rcg2_shared_set_rate(struct clk_hw *hw, unsigned long rate, 844 unsigned long parent_rate) 845 { 846 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 847 const struct freq_tbl *f; 848 849 f = qcom_find_freq(rcg->freq_tbl, rate); 850 if (!f) 851 return -EINVAL; 852 853 /* 854 * In case clock is disabled, update the CFG, M, N and D registers 855 * and don't hit the update bit of CMD register. 856 */ 857 if (!__clk_is_enabled(hw->clk)) 858 return __clk_rcg2_configure(rcg, f); 859 860 return clk_rcg2_shared_force_enable_clear(hw, f); 861 } 862 863 static int clk_rcg2_shared_set_rate_and_parent(struct clk_hw *hw, 864 unsigned long rate, unsigned long parent_rate, u8 index) 865 { 866 return clk_rcg2_shared_set_rate(hw, rate, parent_rate); 867 } 868 869 static int clk_rcg2_shared_enable(struct clk_hw *hw) 870 { 871 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 872 int ret; 873 874 /* 875 * Set the update bit because required configuration has already 876 * been written in clk_rcg2_shared_set_rate() 877 */ 878 ret = clk_rcg2_set_force_enable(hw); 879 if (ret) 880 return ret; 881 882 ret = update_config(rcg); 883 if (ret) 884 return ret; 885 886 return clk_rcg2_clear_force_enable(hw); 887 } 888 889 static void clk_rcg2_shared_disable(struct clk_hw *hw) 890 { 891 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 892 u32 cfg; 893 894 /* 895 * Store current configuration as switching to safe source would clear 896 * the SRC and DIV of CFG register 897 */ 898 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg); 899 900 /* 901 * Park the RCG at a safe configuration - sourced off of safe source. 902 * Force enable and disable the RCG while configuring it to safeguard 903 * against any update signal coming from the downstream clock. 904 * The current parent is still prepared and enabled at this point, and 905 * the safe source is always on while application processor subsystem 906 * is online. Therefore, the RCG can safely switch its parent. 907 */ 908 clk_rcg2_set_force_enable(hw); 909 910 regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, 911 rcg->safe_src_index << CFG_SRC_SEL_SHIFT); 912 913 update_config(rcg); 914 915 clk_rcg2_clear_force_enable(hw); 916 917 /* Write back the stored configuration corresponding to current rate */ 918 regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, cfg); 919 } 920 921 const struct clk_ops clk_rcg2_shared_ops = { 922 .enable = clk_rcg2_shared_enable, 923 .disable = clk_rcg2_shared_disable, 924 .get_parent = clk_rcg2_get_parent, 925 .set_parent = clk_rcg2_set_parent, 926 .recalc_rate = clk_rcg2_recalc_rate, 927 .determine_rate = clk_rcg2_determine_rate, 928 .set_rate = clk_rcg2_shared_set_rate, 929 .set_rate_and_parent = clk_rcg2_shared_set_rate_and_parent, 930 }; 931 EXPORT_SYMBOL_GPL(clk_rcg2_shared_ops); 932