1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2013, 2018, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/bitops.h> 8 #include <linux/err.h> 9 #include <linux/bug.h> 10 #include <linux/export.h> 11 #include <linux/clk-provider.h> 12 #include <linux/delay.h> 13 #include <linux/rational.h> 14 #include <linux/regmap.h> 15 #include <linux/math64.h> 16 #include <linux/slab.h> 17 18 #include <asm/div64.h> 19 20 #include "clk-rcg.h" 21 #include "common.h" 22 23 #define CMD_REG 0x0 24 #define CMD_UPDATE BIT(0) 25 #define CMD_ROOT_EN BIT(1) 26 #define CMD_DIRTY_CFG BIT(4) 27 #define CMD_DIRTY_N BIT(5) 28 #define CMD_DIRTY_M BIT(6) 29 #define CMD_DIRTY_D BIT(7) 30 #define CMD_ROOT_OFF BIT(31) 31 32 #define CFG_REG 0x4 33 #define CFG_SRC_DIV_SHIFT 0 34 #define CFG_SRC_SEL_SHIFT 8 35 #define CFG_SRC_SEL_MASK (0x7 << CFG_SRC_SEL_SHIFT) 36 #define CFG_MODE_SHIFT 12 37 #define CFG_MODE_MASK (0x3 << CFG_MODE_SHIFT) 38 #define CFG_MODE_DUAL_EDGE (0x2 << CFG_MODE_SHIFT) 39 #define CFG_HW_CLK_CTRL_MASK BIT(20) 40 41 #define M_REG 0x8 42 #define N_REG 0xc 43 #define D_REG 0x10 44 45 #define RCG_CFG_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + CFG_REG) 46 #define RCG_M_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + M_REG) 47 #define RCG_N_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + N_REG) 48 #define RCG_D_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + D_REG) 49 50 /* Dynamic Frequency Scaling */ 51 #define MAX_PERF_LEVEL 8 52 #define SE_CMD_DFSR_OFFSET 0x14 53 #define SE_CMD_DFS_EN BIT(0) 54 #define SE_PERF_DFSR(level) (0x1c + 0x4 * (level)) 55 #define SE_PERF_M_DFSR(level) (0x5c + 0x4 * (level)) 56 #define SE_PERF_N_DFSR(level) (0x9c + 0x4 * (level)) 57 58 enum freq_policy { 59 FLOOR, 60 CEIL, 61 }; 62 63 static int clk_rcg2_is_enabled(struct clk_hw *hw) 64 { 65 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 66 u32 cmd; 67 int ret; 68 69 ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd); 70 if (ret) 71 return ret; 72 73 return (cmd & CMD_ROOT_OFF) == 0; 74 } 75 76 static u8 clk_rcg2_get_parent(struct clk_hw *hw) 77 { 78 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 79 int num_parents = clk_hw_get_num_parents(hw); 80 u32 cfg; 81 int i, ret; 82 83 ret = regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg); 84 if (ret) 85 goto err; 86 87 cfg &= CFG_SRC_SEL_MASK; 88 cfg >>= CFG_SRC_SEL_SHIFT; 89 90 for (i = 0; i < num_parents; i++) 91 if (cfg == rcg->parent_map[i].cfg) 92 return i; 93 94 err: 95 pr_debug("%s: Clock %s has invalid parent, using default.\n", 96 __func__, clk_hw_get_name(hw)); 97 return 0; 98 } 99 100 static int update_config(struct clk_rcg2 *rcg) 101 { 102 int count, ret; 103 u32 cmd; 104 struct clk_hw *hw = &rcg->clkr.hw; 105 const char *name = clk_hw_get_name(hw); 106 107 ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, 108 CMD_UPDATE, CMD_UPDATE); 109 if (ret) 110 return ret; 111 112 /* Wait for update to take effect */ 113 for (count = 500; count > 0; count--) { 114 ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd); 115 if (ret) 116 return ret; 117 if (!(cmd & CMD_UPDATE)) 118 return 0; 119 udelay(1); 120 } 121 122 WARN(1, "%s: rcg didn't update its configuration.", name); 123 return -EBUSY; 124 } 125 126 static int clk_rcg2_set_parent(struct clk_hw *hw, u8 index) 127 { 128 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 129 int ret; 130 u32 cfg = rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT; 131 132 ret = regmap_update_bits(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), 133 CFG_SRC_SEL_MASK, cfg); 134 if (ret) 135 return ret; 136 137 return update_config(rcg); 138 } 139 140 /* 141 * Calculate m/n:d rate 142 * 143 * parent_rate m 144 * rate = ----------- x --- 145 * hid_div n 146 */ 147 static unsigned long 148 calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 hid_div) 149 { 150 if (hid_div) { 151 rate *= 2; 152 rate /= hid_div + 1; 153 } 154 155 if (mode) { 156 u64 tmp = rate; 157 tmp *= m; 158 do_div(tmp, n); 159 rate = tmp; 160 } 161 162 return rate; 163 } 164 165 static unsigned long 166 clk_rcg2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 167 { 168 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 169 u32 cfg, hid_div, m = 0, n = 0, mode = 0, mask; 170 171 regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg); 172 173 if (rcg->mnd_width) { 174 mask = BIT(rcg->mnd_width) - 1; 175 regmap_read(rcg->clkr.regmap, RCG_M_OFFSET(rcg), &m); 176 m &= mask; 177 regmap_read(rcg->clkr.regmap, RCG_N_OFFSET(rcg), &n); 178 n = ~n; 179 n &= mask; 180 n += m; 181 mode = cfg & CFG_MODE_MASK; 182 mode >>= CFG_MODE_SHIFT; 183 } 184 185 mask = BIT(rcg->hid_width) - 1; 186 hid_div = cfg >> CFG_SRC_DIV_SHIFT; 187 hid_div &= mask; 188 189 return calc_rate(parent_rate, m, n, mode, hid_div); 190 } 191 192 static int _freq_tbl_determine_rate(struct clk_hw *hw, const struct freq_tbl *f, 193 struct clk_rate_request *req, 194 enum freq_policy policy) 195 { 196 unsigned long clk_flags, rate = req->rate; 197 struct clk_hw *p; 198 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 199 int index; 200 201 switch (policy) { 202 case FLOOR: 203 f = qcom_find_freq_floor(f, rate); 204 break; 205 case CEIL: 206 f = qcom_find_freq(f, rate); 207 break; 208 default: 209 return -EINVAL; 210 } 211 212 if (!f) 213 return -EINVAL; 214 215 index = qcom_find_src_index(hw, rcg->parent_map, f->src); 216 if (index < 0) 217 return index; 218 219 clk_flags = clk_hw_get_flags(hw); 220 p = clk_hw_get_parent_by_index(hw, index); 221 if (!p) 222 return -EINVAL; 223 224 if (clk_flags & CLK_SET_RATE_PARENT) { 225 rate = f->freq; 226 if (f->pre_div) { 227 if (!rate) 228 rate = req->rate; 229 rate /= 2; 230 rate *= f->pre_div + 1; 231 } 232 233 if (f->n) { 234 u64 tmp = rate; 235 tmp = tmp * f->n; 236 do_div(tmp, f->m); 237 rate = tmp; 238 } 239 } else { 240 rate = clk_hw_get_rate(p); 241 } 242 req->best_parent_hw = p; 243 req->best_parent_rate = rate; 244 req->rate = f->freq; 245 246 return 0; 247 } 248 249 static int clk_rcg2_determine_rate(struct clk_hw *hw, 250 struct clk_rate_request *req) 251 { 252 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 253 254 return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, CEIL); 255 } 256 257 static int clk_rcg2_determine_floor_rate(struct clk_hw *hw, 258 struct clk_rate_request *req) 259 { 260 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 261 262 return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, FLOOR); 263 } 264 265 static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f) 266 { 267 u32 cfg, mask; 268 struct clk_hw *hw = &rcg->clkr.hw; 269 int ret, index = qcom_find_src_index(hw, rcg->parent_map, f->src); 270 271 if (index < 0) 272 return index; 273 274 if (rcg->mnd_width && f->n) { 275 mask = BIT(rcg->mnd_width) - 1; 276 ret = regmap_update_bits(rcg->clkr.regmap, 277 RCG_M_OFFSET(rcg), mask, f->m); 278 if (ret) 279 return ret; 280 281 ret = regmap_update_bits(rcg->clkr.regmap, 282 RCG_N_OFFSET(rcg), mask, ~(f->n - f->m)); 283 if (ret) 284 return ret; 285 286 ret = regmap_update_bits(rcg->clkr.regmap, 287 RCG_D_OFFSET(rcg), mask, ~f->n); 288 if (ret) 289 return ret; 290 } 291 292 mask = BIT(rcg->hid_width) - 1; 293 mask |= CFG_SRC_SEL_MASK | CFG_MODE_MASK | CFG_HW_CLK_CTRL_MASK; 294 cfg = f->pre_div << CFG_SRC_DIV_SHIFT; 295 cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT; 296 if (rcg->mnd_width && f->n && (f->m != f->n)) 297 cfg |= CFG_MODE_DUAL_EDGE; 298 return regmap_update_bits(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), 299 mask, cfg); 300 } 301 302 static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f) 303 { 304 int ret; 305 306 ret = __clk_rcg2_configure(rcg, f); 307 if (ret) 308 return ret; 309 310 return update_config(rcg); 311 } 312 313 static int __clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate, 314 enum freq_policy policy) 315 { 316 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 317 const struct freq_tbl *f; 318 319 switch (policy) { 320 case FLOOR: 321 f = qcom_find_freq_floor(rcg->freq_tbl, rate); 322 break; 323 case CEIL: 324 f = qcom_find_freq(rcg->freq_tbl, rate); 325 break; 326 default: 327 return -EINVAL; 328 } 329 330 if (!f) 331 return -EINVAL; 332 333 return clk_rcg2_configure(rcg, f); 334 } 335 336 static int clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate, 337 unsigned long parent_rate) 338 { 339 return __clk_rcg2_set_rate(hw, rate, CEIL); 340 } 341 342 static int clk_rcg2_set_floor_rate(struct clk_hw *hw, unsigned long rate, 343 unsigned long parent_rate) 344 { 345 return __clk_rcg2_set_rate(hw, rate, FLOOR); 346 } 347 348 static int clk_rcg2_set_rate_and_parent(struct clk_hw *hw, 349 unsigned long rate, unsigned long parent_rate, u8 index) 350 { 351 return __clk_rcg2_set_rate(hw, rate, CEIL); 352 } 353 354 static int clk_rcg2_set_floor_rate_and_parent(struct clk_hw *hw, 355 unsigned long rate, unsigned long parent_rate, u8 index) 356 { 357 return __clk_rcg2_set_rate(hw, rate, FLOOR); 358 } 359 360 const struct clk_ops clk_rcg2_ops = { 361 .is_enabled = clk_rcg2_is_enabled, 362 .get_parent = clk_rcg2_get_parent, 363 .set_parent = clk_rcg2_set_parent, 364 .recalc_rate = clk_rcg2_recalc_rate, 365 .determine_rate = clk_rcg2_determine_rate, 366 .set_rate = clk_rcg2_set_rate, 367 .set_rate_and_parent = clk_rcg2_set_rate_and_parent, 368 }; 369 EXPORT_SYMBOL_GPL(clk_rcg2_ops); 370 371 const struct clk_ops clk_rcg2_floor_ops = { 372 .is_enabled = clk_rcg2_is_enabled, 373 .get_parent = clk_rcg2_get_parent, 374 .set_parent = clk_rcg2_set_parent, 375 .recalc_rate = clk_rcg2_recalc_rate, 376 .determine_rate = clk_rcg2_determine_floor_rate, 377 .set_rate = clk_rcg2_set_floor_rate, 378 .set_rate_and_parent = clk_rcg2_set_floor_rate_and_parent, 379 }; 380 EXPORT_SYMBOL_GPL(clk_rcg2_floor_ops); 381 382 struct frac_entry { 383 int num; 384 int den; 385 }; 386 387 static const struct frac_entry frac_table_675m[] = { /* link rate of 270M */ 388 { 52, 295 }, /* 119 M */ 389 { 11, 57 }, /* 130.25 M */ 390 { 63, 307 }, /* 138.50 M */ 391 { 11, 50 }, /* 148.50 M */ 392 { 47, 206 }, /* 154 M */ 393 { 31, 100 }, /* 205.25 M */ 394 { 107, 269 }, /* 268.50 M */ 395 { }, 396 }; 397 398 static struct frac_entry frac_table_810m[] = { /* Link rate of 162M */ 399 { 31, 211 }, /* 119 M */ 400 { 32, 199 }, /* 130.25 M */ 401 { 63, 307 }, /* 138.50 M */ 402 { 11, 60 }, /* 148.50 M */ 403 { 50, 263 }, /* 154 M */ 404 { 31, 120 }, /* 205.25 M */ 405 { 119, 359 }, /* 268.50 M */ 406 { }, 407 }; 408 409 static int clk_edp_pixel_set_rate(struct clk_hw *hw, unsigned long rate, 410 unsigned long parent_rate) 411 { 412 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 413 struct freq_tbl f = *rcg->freq_tbl; 414 const struct frac_entry *frac; 415 int delta = 100000; 416 s64 src_rate = parent_rate; 417 s64 request; 418 u32 mask = BIT(rcg->hid_width) - 1; 419 u32 hid_div; 420 421 if (src_rate == 810000000) 422 frac = frac_table_810m; 423 else 424 frac = frac_table_675m; 425 426 for (; frac->num; frac++) { 427 request = rate; 428 request *= frac->den; 429 request = div_s64(request, frac->num); 430 if ((src_rate < (request - delta)) || 431 (src_rate > (request + delta))) 432 continue; 433 434 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, 435 &hid_div); 436 f.pre_div = hid_div; 437 f.pre_div >>= CFG_SRC_DIV_SHIFT; 438 f.pre_div &= mask; 439 f.m = frac->num; 440 f.n = frac->den; 441 442 return clk_rcg2_configure(rcg, &f); 443 } 444 445 return -EINVAL; 446 } 447 448 static int clk_edp_pixel_set_rate_and_parent(struct clk_hw *hw, 449 unsigned long rate, unsigned long parent_rate, u8 index) 450 { 451 /* Parent index is set statically in frequency table */ 452 return clk_edp_pixel_set_rate(hw, rate, parent_rate); 453 } 454 455 static int clk_edp_pixel_determine_rate(struct clk_hw *hw, 456 struct clk_rate_request *req) 457 { 458 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 459 const struct freq_tbl *f = rcg->freq_tbl; 460 const struct frac_entry *frac; 461 int delta = 100000; 462 s64 request; 463 u32 mask = BIT(rcg->hid_width) - 1; 464 u32 hid_div; 465 int index = qcom_find_src_index(hw, rcg->parent_map, f->src); 466 467 /* Force the correct parent */ 468 req->best_parent_hw = clk_hw_get_parent_by_index(hw, index); 469 req->best_parent_rate = clk_hw_get_rate(req->best_parent_hw); 470 471 if (req->best_parent_rate == 810000000) 472 frac = frac_table_810m; 473 else 474 frac = frac_table_675m; 475 476 for (; frac->num; frac++) { 477 request = req->rate; 478 request *= frac->den; 479 request = div_s64(request, frac->num); 480 if ((req->best_parent_rate < (request - delta)) || 481 (req->best_parent_rate > (request + delta))) 482 continue; 483 484 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, 485 &hid_div); 486 hid_div >>= CFG_SRC_DIV_SHIFT; 487 hid_div &= mask; 488 489 req->rate = calc_rate(req->best_parent_rate, 490 frac->num, frac->den, 491 !!frac->den, hid_div); 492 return 0; 493 } 494 495 return -EINVAL; 496 } 497 498 const struct clk_ops clk_edp_pixel_ops = { 499 .is_enabled = clk_rcg2_is_enabled, 500 .get_parent = clk_rcg2_get_parent, 501 .set_parent = clk_rcg2_set_parent, 502 .recalc_rate = clk_rcg2_recalc_rate, 503 .set_rate = clk_edp_pixel_set_rate, 504 .set_rate_and_parent = clk_edp_pixel_set_rate_and_parent, 505 .determine_rate = clk_edp_pixel_determine_rate, 506 }; 507 EXPORT_SYMBOL_GPL(clk_edp_pixel_ops); 508 509 static int clk_byte_determine_rate(struct clk_hw *hw, 510 struct clk_rate_request *req) 511 { 512 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 513 const struct freq_tbl *f = rcg->freq_tbl; 514 int index = qcom_find_src_index(hw, rcg->parent_map, f->src); 515 unsigned long parent_rate, div; 516 u32 mask = BIT(rcg->hid_width) - 1; 517 struct clk_hw *p; 518 519 if (req->rate == 0) 520 return -EINVAL; 521 522 req->best_parent_hw = p = clk_hw_get_parent_by_index(hw, index); 523 req->best_parent_rate = parent_rate = clk_hw_round_rate(p, req->rate); 524 525 div = DIV_ROUND_UP((2 * parent_rate), req->rate) - 1; 526 div = min_t(u32, div, mask); 527 528 req->rate = calc_rate(parent_rate, 0, 0, 0, div); 529 530 return 0; 531 } 532 533 static int clk_byte_set_rate(struct clk_hw *hw, unsigned long rate, 534 unsigned long parent_rate) 535 { 536 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 537 struct freq_tbl f = *rcg->freq_tbl; 538 unsigned long div; 539 u32 mask = BIT(rcg->hid_width) - 1; 540 541 div = DIV_ROUND_UP((2 * parent_rate), rate) - 1; 542 div = min_t(u32, div, mask); 543 544 f.pre_div = div; 545 546 return clk_rcg2_configure(rcg, &f); 547 } 548 549 static int clk_byte_set_rate_and_parent(struct clk_hw *hw, 550 unsigned long rate, unsigned long parent_rate, u8 index) 551 { 552 /* Parent index is set statically in frequency table */ 553 return clk_byte_set_rate(hw, rate, parent_rate); 554 } 555 556 const struct clk_ops clk_byte_ops = { 557 .is_enabled = clk_rcg2_is_enabled, 558 .get_parent = clk_rcg2_get_parent, 559 .set_parent = clk_rcg2_set_parent, 560 .recalc_rate = clk_rcg2_recalc_rate, 561 .set_rate = clk_byte_set_rate, 562 .set_rate_and_parent = clk_byte_set_rate_and_parent, 563 .determine_rate = clk_byte_determine_rate, 564 }; 565 EXPORT_SYMBOL_GPL(clk_byte_ops); 566 567 static int clk_byte2_determine_rate(struct clk_hw *hw, 568 struct clk_rate_request *req) 569 { 570 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 571 unsigned long parent_rate, div; 572 u32 mask = BIT(rcg->hid_width) - 1; 573 struct clk_hw *p; 574 unsigned long rate = req->rate; 575 576 if (rate == 0) 577 return -EINVAL; 578 579 p = req->best_parent_hw; 580 req->best_parent_rate = parent_rate = clk_hw_round_rate(p, rate); 581 582 div = DIV_ROUND_UP((2 * parent_rate), rate) - 1; 583 div = min_t(u32, div, mask); 584 585 req->rate = calc_rate(parent_rate, 0, 0, 0, div); 586 587 return 0; 588 } 589 590 static int clk_byte2_set_rate(struct clk_hw *hw, unsigned long rate, 591 unsigned long parent_rate) 592 { 593 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 594 struct freq_tbl f = { 0 }; 595 unsigned long div; 596 int i, num_parents = clk_hw_get_num_parents(hw); 597 u32 mask = BIT(rcg->hid_width) - 1; 598 u32 cfg; 599 600 div = DIV_ROUND_UP((2 * parent_rate), rate) - 1; 601 div = min_t(u32, div, mask); 602 603 f.pre_div = div; 604 605 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg); 606 cfg &= CFG_SRC_SEL_MASK; 607 cfg >>= CFG_SRC_SEL_SHIFT; 608 609 for (i = 0; i < num_parents; i++) { 610 if (cfg == rcg->parent_map[i].cfg) { 611 f.src = rcg->parent_map[i].src; 612 return clk_rcg2_configure(rcg, &f); 613 } 614 } 615 616 return -EINVAL; 617 } 618 619 static int clk_byte2_set_rate_and_parent(struct clk_hw *hw, 620 unsigned long rate, unsigned long parent_rate, u8 index) 621 { 622 /* Read the hardware to determine parent during set_rate */ 623 return clk_byte2_set_rate(hw, rate, parent_rate); 624 } 625 626 const struct clk_ops clk_byte2_ops = { 627 .is_enabled = clk_rcg2_is_enabled, 628 .get_parent = clk_rcg2_get_parent, 629 .set_parent = clk_rcg2_set_parent, 630 .recalc_rate = clk_rcg2_recalc_rate, 631 .set_rate = clk_byte2_set_rate, 632 .set_rate_and_parent = clk_byte2_set_rate_and_parent, 633 .determine_rate = clk_byte2_determine_rate, 634 }; 635 EXPORT_SYMBOL_GPL(clk_byte2_ops); 636 637 static const struct frac_entry frac_table_pixel[] = { 638 { 3, 8 }, 639 { 2, 9 }, 640 { 4, 9 }, 641 { 1, 1 }, 642 { } 643 }; 644 645 static int clk_pixel_determine_rate(struct clk_hw *hw, 646 struct clk_rate_request *req) 647 { 648 unsigned long request, src_rate; 649 int delta = 100000; 650 const struct frac_entry *frac = frac_table_pixel; 651 652 for (; frac->num; frac++) { 653 request = (req->rate * frac->den) / frac->num; 654 655 src_rate = clk_hw_round_rate(req->best_parent_hw, request); 656 if ((src_rate < (request - delta)) || 657 (src_rate > (request + delta))) 658 continue; 659 660 req->best_parent_rate = src_rate; 661 req->rate = (src_rate * frac->num) / frac->den; 662 return 0; 663 } 664 665 return -EINVAL; 666 } 667 668 static int clk_pixel_set_rate(struct clk_hw *hw, unsigned long rate, 669 unsigned long parent_rate) 670 { 671 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 672 struct freq_tbl f = { 0 }; 673 const struct frac_entry *frac = frac_table_pixel; 674 unsigned long request; 675 int delta = 100000; 676 u32 mask = BIT(rcg->hid_width) - 1; 677 u32 hid_div, cfg; 678 int i, num_parents = clk_hw_get_num_parents(hw); 679 680 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg); 681 cfg &= CFG_SRC_SEL_MASK; 682 cfg >>= CFG_SRC_SEL_SHIFT; 683 684 for (i = 0; i < num_parents; i++) 685 if (cfg == rcg->parent_map[i].cfg) { 686 f.src = rcg->parent_map[i].src; 687 break; 688 } 689 690 for (; frac->num; frac++) { 691 request = (rate * frac->den) / frac->num; 692 693 if ((parent_rate < (request - delta)) || 694 (parent_rate > (request + delta))) 695 continue; 696 697 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, 698 &hid_div); 699 f.pre_div = hid_div; 700 f.pre_div >>= CFG_SRC_DIV_SHIFT; 701 f.pre_div &= mask; 702 f.m = frac->num; 703 f.n = frac->den; 704 705 return clk_rcg2_configure(rcg, &f); 706 } 707 return -EINVAL; 708 } 709 710 static int clk_pixel_set_rate_and_parent(struct clk_hw *hw, unsigned long rate, 711 unsigned long parent_rate, u8 index) 712 { 713 return clk_pixel_set_rate(hw, rate, parent_rate); 714 } 715 716 const struct clk_ops clk_pixel_ops = { 717 .is_enabled = clk_rcg2_is_enabled, 718 .get_parent = clk_rcg2_get_parent, 719 .set_parent = clk_rcg2_set_parent, 720 .recalc_rate = clk_rcg2_recalc_rate, 721 .set_rate = clk_pixel_set_rate, 722 .set_rate_and_parent = clk_pixel_set_rate_and_parent, 723 .determine_rate = clk_pixel_determine_rate, 724 }; 725 EXPORT_SYMBOL_GPL(clk_pixel_ops); 726 727 static int clk_gfx3d_determine_rate(struct clk_hw *hw, 728 struct clk_rate_request *req) 729 { 730 struct clk_rate_request parent_req = { }; 731 struct clk_rcg2_gfx3d *cgfx = to_clk_rcg2_gfx3d(hw); 732 struct clk_hw *xo, *p0, *p1, *p2; 733 unsigned long request, p0_rate; 734 int ret; 735 736 p0 = cgfx->hws[0]; 737 p1 = cgfx->hws[1]; 738 p2 = cgfx->hws[2]; 739 /* 740 * This function does ping-pong the RCG between PLLs: if we don't 741 * have at least one fixed PLL and two variable ones, 742 * then it's not going to work correctly. 743 */ 744 if (WARN_ON(!p0 || !p1 || !p2)) 745 return -EINVAL; 746 747 xo = clk_hw_get_parent_by_index(hw, 0); 748 if (req->rate == clk_hw_get_rate(xo)) { 749 req->best_parent_hw = xo; 750 return 0; 751 } 752 753 request = req->rate; 754 if (cgfx->div > 1) 755 parent_req.rate = request = request * cgfx->div; 756 757 /* This has to be a fixed rate PLL */ 758 p0_rate = clk_hw_get_rate(p0); 759 760 if (request == p0_rate) { 761 req->rate = req->best_parent_rate = p0_rate; 762 req->best_parent_hw = p0; 763 return 0; 764 } 765 766 if (req->best_parent_hw == p0) { 767 /* Are we going back to a previously used rate? */ 768 if (clk_hw_get_rate(p2) == request) 769 req->best_parent_hw = p2; 770 else 771 req->best_parent_hw = p1; 772 } else if (req->best_parent_hw == p2) { 773 req->best_parent_hw = p1; 774 } else { 775 req->best_parent_hw = p2; 776 } 777 778 ret = __clk_determine_rate(req->best_parent_hw, &parent_req); 779 if (ret) 780 return ret; 781 782 req->rate = req->best_parent_rate = parent_req.rate; 783 if (cgfx->div > 1) 784 req->rate /= cgfx->div; 785 786 return 0; 787 } 788 789 static int clk_gfx3d_set_rate_and_parent(struct clk_hw *hw, unsigned long rate, 790 unsigned long parent_rate, u8 index) 791 { 792 struct clk_rcg2_gfx3d *cgfx = to_clk_rcg2_gfx3d(hw); 793 struct clk_rcg2 *rcg = &cgfx->rcg; 794 u32 cfg; 795 int ret; 796 797 cfg = rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT; 798 /* On some targets, the GFX3D RCG may need to divide PLL frequency */ 799 if (cgfx->div > 1) 800 cfg |= ((2 * cgfx->div) - 1) << CFG_SRC_DIV_SHIFT; 801 802 ret = regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, cfg); 803 if (ret) 804 return ret; 805 806 return update_config(rcg); 807 } 808 809 static int clk_gfx3d_set_rate(struct clk_hw *hw, unsigned long rate, 810 unsigned long parent_rate) 811 { 812 /* 813 * We should never get here; clk_gfx3d_determine_rate() should always 814 * make us use a different parent than what we're currently using, so 815 * clk_gfx3d_set_rate_and_parent() should always be called. 816 */ 817 return 0; 818 } 819 820 const struct clk_ops clk_gfx3d_ops = { 821 .is_enabled = clk_rcg2_is_enabled, 822 .get_parent = clk_rcg2_get_parent, 823 .set_parent = clk_rcg2_set_parent, 824 .recalc_rate = clk_rcg2_recalc_rate, 825 .set_rate = clk_gfx3d_set_rate, 826 .set_rate_and_parent = clk_gfx3d_set_rate_and_parent, 827 .determine_rate = clk_gfx3d_determine_rate, 828 }; 829 EXPORT_SYMBOL_GPL(clk_gfx3d_ops); 830 831 static int clk_rcg2_set_force_enable(struct clk_hw *hw) 832 { 833 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 834 const char *name = clk_hw_get_name(hw); 835 int ret, count; 836 837 ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, 838 CMD_ROOT_EN, CMD_ROOT_EN); 839 if (ret) 840 return ret; 841 842 /* wait for RCG to turn ON */ 843 for (count = 500; count > 0; count--) { 844 if (clk_rcg2_is_enabled(hw)) 845 return 0; 846 847 udelay(1); 848 } 849 850 pr_err("%s: RCG did not turn on\n", name); 851 return -ETIMEDOUT; 852 } 853 854 static int clk_rcg2_clear_force_enable(struct clk_hw *hw) 855 { 856 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 857 858 return regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, 859 CMD_ROOT_EN, 0); 860 } 861 862 static int 863 clk_rcg2_shared_force_enable_clear(struct clk_hw *hw, const struct freq_tbl *f) 864 { 865 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 866 int ret; 867 868 ret = clk_rcg2_set_force_enable(hw); 869 if (ret) 870 return ret; 871 872 ret = clk_rcg2_configure(rcg, f); 873 if (ret) 874 return ret; 875 876 return clk_rcg2_clear_force_enable(hw); 877 } 878 879 static int clk_rcg2_shared_set_rate(struct clk_hw *hw, unsigned long rate, 880 unsigned long parent_rate) 881 { 882 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 883 const struct freq_tbl *f; 884 885 f = qcom_find_freq(rcg->freq_tbl, rate); 886 if (!f) 887 return -EINVAL; 888 889 /* 890 * In case clock is disabled, update the CFG, M, N and D registers 891 * and don't hit the update bit of CMD register. 892 */ 893 if (!__clk_is_enabled(hw->clk)) 894 return __clk_rcg2_configure(rcg, f); 895 896 return clk_rcg2_shared_force_enable_clear(hw, f); 897 } 898 899 static int clk_rcg2_shared_set_rate_and_parent(struct clk_hw *hw, 900 unsigned long rate, unsigned long parent_rate, u8 index) 901 { 902 return clk_rcg2_shared_set_rate(hw, rate, parent_rate); 903 } 904 905 static int clk_rcg2_shared_enable(struct clk_hw *hw) 906 { 907 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 908 int ret; 909 910 /* 911 * Set the update bit because required configuration has already 912 * been written in clk_rcg2_shared_set_rate() 913 */ 914 ret = clk_rcg2_set_force_enable(hw); 915 if (ret) 916 return ret; 917 918 ret = update_config(rcg); 919 if (ret) 920 return ret; 921 922 return clk_rcg2_clear_force_enable(hw); 923 } 924 925 static void clk_rcg2_shared_disable(struct clk_hw *hw) 926 { 927 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 928 u32 cfg; 929 930 /* 931 * Store current configuration as switching to safe source would clear 932 * the SRC and DIV of CFG register 933 */ 934 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg); 935 936 /* 937 * Park the RCG at a safe configuration - sourced off of safe source. 938 * Force enable and disable the RCG while configuring it to safeguard 939 * against any update signal coming from the downstream clock. 940 * The current parent is still prepared and enabled at this point, and 941 * the safe source is always on while application processor subsystem 942 * is online. Therefore, the RCG can safely switch its parent. 943 */ 944 clk_rcg2_set_force_enable(hw); 945 946 regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, 947 rcg->safe_src_index << CFG_SRC_SEL_SHIFT); 948 949 update_config(rcg); 950 951 clk_rcg2_clear_force_enable(hw); 952 953 /* Write back the stored configuration corresponding to current rate */ 954 regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, cfg); 955 } 956 957 const struct clk_ops clk_rcg2_shared_ops = { 958 .enable = clk_rcg2_shared_enable, 959 .disable = clk_rcg2_shared_disable, 960 .get_parent = clk_rcg2_get_parent, 961 .set_parent = clk_rcg2_set_parent, 962 .recalc_rate = clk_rcg2_recalc_rate, 963 .determine_rate = clk_rcg2_determine_rate, 964 .set_rate = clk_rcg2_shared_set_rate, 965 .set_rate_and_parent = clk_rcg2_shared_set_rate_and_parent, 966 }; 967 EXPORT_SYMBOL_GPL(clk_rcg2_shared_ops); 968 969 /* Common APIs to be used for DFS based RCGR */ 970 static void clk_rcg2_dfs_populate_freq(struct clk_hw *hw, unsigned int l, 971 struct freq_tbl *f) 972 { 973 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 974 struct clk_hw *p; 975 unsigned long prate = 0; 976 u32 val, mask, cfg, mode, src; 977 int i, num_parents; 978 979 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_DFSR(l), &cfg); 980 981 mask = BIT(rcg->hid_width) - 1; 982 f->pre_div = 1; 983 if (cfg & mask) 984 f->pre_div = cfg & mask; 985 986 src = cfg & CFG_SRC_SEL_MASK; 987 src >>= CFG_SRC_SEL_SHIFT; 988 989 num_parents = clk_hw_get_num_parents(hw); 990 for (i = 0; i < num_parents; i++) { 991 if (src == rcg->parent_map[i].cfg) { 992 f->src = rcg->parent_map[i].src; 993 p = clk_hw_get_parent_by_index(&rcg->clkr.hw, i); 994 prate = clk_hw_get_rate(p); 995 } 996 } 997 998 mode = cfg & CFG_MODE_MASK; 999 mode >>= CFG_MODE_SHIFT; 1000 if (mode) { 1001 mask = BIT(rcg->mnd_width) - 1; 1002 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_M_DFSR(l), 1003 &val); 1004 val &= mask; 1005 f->m = val; 1006 1007 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_N_DFSR(l), 1008 &val); 1009 val = ~val; 1010 val &= mask; 1011 val += f->m; 1012 f->n = val; 1013 } 1014 1015 f->freq = calc_rate(prate, f->m, f->n, mode, f->pre_div); 1016 } 1017 1018 static int clk_rcg2_dfs_populate_freq_table(struct clk_rcg2 *rcg) 1019 { 1020 struct freq_tbl *freq_tbl; 1021 int i; 1022 1023 /* Allocate space for 1 extra since table is NULL terminated */ 1024 freq_tbl = kcalloc(MAX_PERF_LEVEL + 1, sizeof(*freq_tbl), GFP_KERNEL); 1025 if (!freq_tbl) 1026 return -ENOMEM; 1027 rcg->freq_tbl = freq_tbl; 1028 1029 for (i = 0; i < MAX_PERF_LEVEL; i++) 1030 clk_rcg2_dfs_populate_freq(&rcg->clkr.hw, i, freq_tbl + i); 1031 1032 return 0; 1033 } 1034 1035 static int clk_rcg2_dfs_determine_rate(struct clk_hw *hw, 1036 struct clk_rate_request *req) 1037 { 1038 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 1039 int ret; 1040 1041 if (!rcg->freq_tbl) { 1042 ret = clk_rcg2_dfs_populate_freq_table(rcg); 1043 if (ret) { 1044 pr_err("Failed to update DFS tables for %s\n", 1045 clk_hw_get_name(hw)); 1046 return ret; 1047 } 1048 } 1049 1050 return clk_rcg2_determine_rate(hw, req); 1051 } 1052 1053 static unsigned long 1054 clk_rcg2_dfs_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 1055 { 1056 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 1057 u32 level, mask, cfg, m = 0, n = 0, mode, pre_div; 1058 1059 regmap_read(rcg->clkr.regmap, 1060 rcg->cmd_rcgr + SE_CMD_DFSR_OFFSET, &level); 1061 level &= GENMASK(4, 1); 1062 level >>= 1; 1063 1064 if (rcg->freq_tbl) 1065 return rcg->freq_tbl[level].freq; 1066 1067 /* 1068 * Assume that parent_rate is actually the parent because 1069 * we can't do any better at figuring it out when the table 1070 * hasn't been populated yet. We only populate the table 1071 * in determine_rate because we can't guarantee the parents 1072 * will be registered with the framework until then. 1073 */ 1074 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_DFSR(level), 1075 &cfg); 1076 1077 mask = BIT(rcg->hid_width) - 1; 1078 pre_div = 1; 1079 if (cfg & mask) 1080 pre_div = cfg & mask; 1081 1082 mode = cfg & CFG_MODE_MASK; 1083 mode >>= CFG_MODE_SHIFT; 1084 if (mode) { 1085 mask = BIT(rcg->mnd_width) - 1; 1086 regmap_read(rcg->clkr.regmap, 1087 rcg->cmd_rcgr + SE_PERF_M_DFSR(level), &m); 1088 m &= mask; 1089 1090 regmap_read(rcg->clkr.regmap, 1091 rcg->cmd_rcgr + SE_PERF_N_DFSR(level), &n); 1092 n = ~n; 1093 n &= mask; 1094 n += m; 1095 } 1096 1097 return calc_rate(parent_rate, m, n, mode, pre_div); 1098 } 1099 1100 static const struct clk_ops clk_rcg2_dfs_ops = { 1101 .is_enabled = clk_rcg2_is_enabled, 1102 .get_parent = clk_rcg2_get_parent, 1103 .determine_rate = clk_rcg2_dfs_determine_rate, 1104 .recalc_rate = clk_rcg2_dfs_recalc_rate, 1105 }; 1106 1107 static int clk_rcg2_enable_dfs(const struct clk_rcg_dfs_data *data, 1108 struct regmap *regmap) 1109 { 1110 struct clk_rcg2 *rcg = data->rcg; 1111 struct clk_init_data *init = data->init; 1112 u32 val; 1113 int ret; 1114 1115 ret = regmap_read(regmap, rcg->cmd_rcgr + SE_CMD_DFSR_OFFSET, &val); 1116 if (ret) 1117 return -EINVAL; 1118 1119 if (!(val & SE_CMD_DFS_EN)) 1120 return 0; 1121 1122 /* 1123 * Rate changes with consumer writing a register in 1124 * their own I/O region 1125 */ 1126 init->flags |= CLK_GET_RATE_NOCACHE; 1127 init->ops = &clk_rcg2_dfs_ops; 1128 1129 rcg->freq_tbl = NULL; 1130 1131 return 0; 1132 } 1133 1134 int qcom_cc_register_rcg_dfs(struct regmap *regmap, 1135 const struct clk_rcg_dfs_data *rcgs, size_t len) 1136 { 1137 int i, ret; 1138 1139 for (i = 0; i < len; i++) { 1140 ret = clk_rcg2_enable_dfs(&rcgs[i], regmap); 1141 if (ret) 1142 return ret; 1143 } 1144 1145 return 0; 1146 } 1147 EXPORT_SYMBOL_GPL(qcom_cc_register_rcg_dfs); 1148 1149 static int clk_rcg2_dp_set_rate(struct clk_hw *hw, unsigned long rate, 1150 unsigned long parent_rate) 1151 { 1152 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 1153 struct freq_tbl f = { 0 }; 1154 u32 mask = BIT(rcg->hid_width) - 1; 1155 u32 hid_div, cfg; 1156 int i, num_parents = clk_hw_get_num_parents(hw); 1157 unsigned long num, den; 1158 1159 rational_best_approximation(parent_rate, rate, 1160 GENMASK(rcg->mnd_width - 1, 0), 1161 GENMASK(rcg->mnd_width - 1, 0), &den, &num); 1162 1163 if (!num || !den) 1164 return -EINVAL; 1165 1166 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg); 1167 hid_div = cfg; 1168 cfg &= CFG_SRC_SEL_MASK; 1169 cfg >>= CFG_SRC_SEL_SHIFT; 1170 1171 for (i = 0; i < num_parents; i++) { 1172 if (cfg == rcg->parent_map[i].cfg) { 1173 f.src = rcg->parent_map[i].src; 1174 break; 1175 } 1176 } 1177 1178 f.pre_div = hid_div; 1179 f.pre_div >>= CFG_SRC_DIV_SHIFT; 1180 f.pre_div &= mask; 1181 1182 if (num != den) { 1183 f.m = num; 1184 f.n = den; 1185 } else { 1186 f.m = 0; 1187 f.n = 0; 1188 } 1189 1190 return clk_rcg2_configure(rcg, &f); 1191 } 1192 1193 static int clk_rcg2_dp_set_rate_and_parent(struct clk_hw *hw, 1194 unsigned long rate, unsigned long parent_rate, u8 index) 1195 { 1196 return clk_rcg2_dp_set_rate(hw, rate, parent_rate); 1197 } 1198 1199 static int clk_rcg2_dp_determine_rate(struct clk_hw *hw, 1200 struct clk_rate_request *req) 1201 { 1202 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 1203 unsigned long num, den; 1204 u64 tmp; 1205 1206 /* Parent rate is a fixed phy link rate */ 1207 rational_best_approximation(req->best_parent_rate, req->rate, 1208 GENMASK(rcg->mnd_width - 1, 0), 1209 GENMASK(rcg->mnd_width - 1, 0), &den, &num); 1210 1211 if (!num || !den) 1212 return -EINVAL; 1213 1214 tmp = req->best_parent_rate * num; 1215 do_div(tmp, den); 1216 req->rate = tmp; 1217 1218 return 0; 1219 } 1220 1221 const struct clk_ops clk_dp_ops = { 1222 .is_enabled = clk_rcg2_is_enabled, 1223 .get_parent = clk_rcg2_get_parent, 1224 .set_parent = clk_rcg2_set_parent, 1225 .recalc_rate = clk_rcg2_recalc_rate, 1226 .set_rate = clk_rcg2_dp_set_rate, 1227 .set_rate_and_parent = clk_rcg2_dp_set_rate_and_parent, 1228 .determine_rate = clk_rcg2_dp_determine_rate, 1229 }; 1230 EXPORT_SYMBOL_GPL(clk_dp_ops); 1231