1 /* 2 * Copyright (c) 2013, The Linux Foundation. All rights reserved. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #ifndef __QCOM_CLK_RCG_H__ 15 #define __QCOM_CLK_RCG_H__ 16 17 #include <linux/clk-provider.h> 18 #include "clk-regmap.h" 19 20 struct freq_tbl { 21 unsigned long freq; 22 u8 src; 23 u8 pre_div; 24 u16 m; 25 u16 n; 26 }; 27 28 /** 29 * struct mn - M/N:D counter 30 * @mnctr_en_bit: bit to enable mn counter 31 * @mnctr_reset_bit: bit to assert mn counter reset 32 * @mnctr_mode_shift: lowest bit of mn counter mode field 33 * @n_val_shift: lowest bit of n value field 34 * @m_val_shift: lowest bit of m value field 35 * @width: number of bits in m/n/d values 36 * @reset_in_cc: true if the mnctr_reset_bit is in the CC register 37 */ 38 struct mn { 39 u8 mnctr_en_bit; 40 u8 mnctr_reset_bit; 41 u8 mnctr_mode_shift; 42 #define MNCTR_MODE_DUAL 0x2 43 #define MNCTR_MODE_MASK 0x3 44 u8 n_val_shift; 45 u8 m_val_shift; 46 u8 width; 47 bool reset_in_cc; 48 }; 49 50 /** 51 * struct pre_div - pre-divider 52 * @pre_div_shift: lowest bit of pre divider field 53 * @pre_div_width: number of bits in predivider 54 */ 55 struct pre_div { 56 u8 pre_div_shift; 57 u8 pre_div_width; 58 }; 59 60 /** 61 * struct src_sel - source selector 62 * @src_sel_shift: lowest bit of source selection field 63 * @parent_map: map from software's parent index to hardware's src_sel field 64 */ 65 struct src_sel { 66 u8 src_sel_shift; 67 #define SRC_SEL_MASK 0x7 68 const struct parent_map *parent_map; 69 }; 70 71 /** 72 * struct clk_rcg - root clock generator 73 * 74 * @ns_reg: NS register 75 * @md_reg: MD register 76 * @mn: mn counter 77 * @p: pre divider 78 * @s: source selector 79 * @freq_tbl: frequency table 80 * @clkr: regmap clock handle 81 * @lock: register lock 82 * 83 */ 84 struct clk_rcg { 85 u32 ns_reg; 86 u32 md_reg; 87 88 struct mn mn; 89 struct pre_div p; 90 struct src_sel s; 91 92 const struct freq_tbl *freq_tbl; 93 94 struct clk_regmap clkr; 95 }; 96 97 extern const struct clk_ops clk_rcg_ops; 98 extern const struct clk_ops clk_rcg_bypass_ops; 99 extern const struct clk_ops clk_rcg_bypass2_ops; 100 extern const struct clk_ops clk_rcg_pixel_ops; 101 extern const struct clk_ops clk_rcg_esc_ops; 102 extern const struct clk_ops clk_rcg_lcc_ops; 103 104 #define to_clk_rcg(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg, clkr) 105 106 /** 107 * struct clk_dyn_rcg - root clock generator with glitch free mux 108 * 109 * @mux_sel_bit: bit to switch glitch free mux 110 * @ns_reg: NS0 and NS1 register 111 * @md_reg: MD0 and MD1 register 112 * @bank_reg: register to XOR @mux_sel_bit into to switch glitch free mux 113 * @mn: mn counter (banked) 114 * @s: source selector (banked) 115 * @freq_tbl: frequency table 116 * @clkr: regmap clock handle 117 * @lock: register lock 118 * 119 */ 120 struct clk_dyn_rcg { 121 u32 ns_reg[2]; 122 u32 md_reg[2]; 123 u32 bank_reg; 124 125 u8 mux_sel_bit; 126 127 struct mn mn[2]; 128 struct pre_div p[2]; 129 struct src_sel s[2]; 130 131 const struct freq_tbl *freq_tbl; 132 133 struct clk_regmap clkr; 134 }; 135 136 extern const struct clk_ops clk_dyn_rcg_ops; 137 138 #define to_clk_dyn_rcg(_hw) \ 139 container_of(to_clk_regmap(_hw), struct clk_dyn_rcg, clkr) 140 141 /** 142 * struct clk_rcg2 - root clock generator 143 * 144 * @cmd_rcgr: corresponds to *_CMD_RCGR 145 * @mnd_width: number of bits in m/n/d values 146 * @hid_width: number of bits in half integer divider 147 * @parent_map: map from software's parent index to hardware's src_sel field 148 * @freq_tbl: frequency table 149 * @clkr: regmap clock handle 150 * 151 */ 152 struct clk_rcg2 { 153 u32 cmd_rcgr; 154 u8 mnd_width; 155 u8 hid_width; 156 const struct parent_map *parent_map; 157 const struct freq_tbl *freq_tbl; 158 struct clk_regmap clkr; 159 }; 160 161 #define to_clk_rcg2(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg2, clkr) 162 163 extern const struct clk_ops clk_rcg2_ops; 164 extern const struct clk_ops clk_rcg2_floor_ops; 165 extern const struct clk_ops clk_edp_pixel_ops; 166 extern const struct clk_ops clk_byte_ops; 167 extern const struct clk_ops clk_byte2_ops; 168 extern const struct clk_ops clk_pixel_ops; 169 extern const struct clk_ops clk_gfx3d_ops; 170 171 #endif 172