1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2013, 2018, The Linux Foundation. All rights reserved. */ 3 4 #ifndef __QCOM_CLK_RCG_H__ 5 #define __QCOM_CLK_RCG_H__ 6 7 #include <linux/clk-provider.h> 8 #include "clk-regmap.h" 9 10 struct freq_tbl { 11 unsigned long freq; 12 u8 src; 13 u8 pre_div; 14 u16 m; 15 u16 n; 16 }; 17 18 /** 19 * struct mn - M/N:D counter 20 * @mnctr_en_bit: bit to enable mn counter 21 * @mnctr_reset_bit: bit to assert mn counter reset 22 * @mnctr_mode_shift: lowest bit of mn counter mode field 23 * @n_val_shift: lowest bit of n value field 24 * @m_val_shift: lowest bit of m value field 25 * @width: number of bits in m/n/d values 26 * @reset_in_cc: true if the mnctr_reset_bit is in the CC register 27 */ 28 struct mn { 29 u8 mnctr_en_bit; 30 u8 mnctr_reset_bit; 31 u8 mnctr_mode_shift; 32 #define MNCTR_MODE_DUAL 0x2 33 #define MNCTR_MODE_MASK 0x3 34 u8 n_val_shift; 35 u8 m_val_shift; 36 u8 width; 37 bool reset_in_cc; 38 }; 39 40 /** 41 * struct pre_div - pre-divider 42 * @pre_div_shift: lowest bit of pre divider field 43 * @pre_div_width: number of bits in predivider 44 */ 45 struct pre_div { 46 u8 pre_div_shift; 47 u8 pre_div_width; 48 }; 49 50 /** 51 * struct src_sel - source selector 52 * @src_sel_shift: lowest bit of source selection field 53 * @parent_map: map from software's parent index to hardware's src_sel field 54 */ 55 struct src_sel { 56 u8 src_sel_shift; 57 #define SRC_SEL_MASK 0x7 58 const struct parent_map *parent_map; 59 }; 60 61 /** 62 * struct clk_rcg - root clock generator 63 * 64 * @ns_reg: NS register 65 * @md_reg: MD register 66 * @mn: mn counter 67 * @p: pre divider 68 * @s: source selector 69 * @freq_tbl: frequency table 70 * @clkr: regmap clock handle 71 * @lock: register lock 72 * 73 */ 74 struct clk_rcg { 75 u32 ns_reg; 76 u32 md_reg; 77 78 struct mn mn; 79 struct pre_div p; 80 struct src_sel s; 81 82 const struct freq_tbl *freq_tbl; 83 84 struct clk_regmap clkr; 85 }; 86 87 extern const struct clk_ops clk_rcg_ops; 88 extern const struct clk_ops clk_rcg_bypass_ops; 89 extern const struct clk_ops clk_rcg_bypass2_ops; 90 extern const struct clk_ops clk_rcg_pixel_ops; 91 extern const struct clk_ops clk_rcg_esc_ops; 92 extern const struct clk_ops clk_rcg_lcc_ops; 93 94 #define to_clk_rcg(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg, clkr) 95 96 /** 97 * struct clk_dyn_rcg - root clock generator with glitch free mux 98 * 99 * @mux_sel_bit: bit to switch glitch free mux 100 * @ns_reg: NS0 and NS1 register 101 * @md_reg: MD0 and MD1 register 102 * @bank_reg: register to XOR @mux_sel_bit into to switch glitch free mux 103 * @mn: mn counter (banked) 104 * @s: source selector (banked) 105 * @freq_tbl: frequency table 106 * @clkr: regmap clock handle 107 * @lock: register lock 108 * 109 */ 110 struct clk_dyn_rcg { 111 u32 ns_reg[2]; 112 u32 md_reg[2]; 113 u32 bank_reg; 114 115 u8 mux_sel_bit; 116 117 struct mn mn[2]; 118 struct pre_div p[2]; 119 struct src_sel s[2]; 120 121 const struct freq_tbl *freq_tbl; 122 123 struct clk_regmap clkr; 124 }; 125 126 extern const struct clk_ops clk_dyn_rcg_ops; 127 128 #define to_clk_dyn_rcg(_hw) \ 129 container_of(to_clk_regmap(_hw), struct clk_dyn_rcg, clkr) 130 131 /** 132 * struct clk_rcg2 - root clock generator 133 * 134 * @cmd_rcgr: corresponds to *_CMD_RCGR 135 * @mnd_width: number of bits in m/n/d values 136 * @hid_width: number of bits in half integer divider 137 * @safe_src_index: safe src index value 138 * @parent_map: map from software's parent index to hardware's src_sel field 139 * @freq_tbl: frequency table 140 * @clkr: regmap clock handle 141 * 142 */ 143 struct clk_rcg2 { 144 u32 cmd_rcgr; 145 u8 mnd_width; 146 u8 hid_width; 147 u8 safe_src_index; 148 const struct parent_map *parent_map; 149 const struct freq_tbl *freq_tbl; 150 struct clk_regmap clkr; 151 }; 152 153 #define to_clk_rcg2(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg2, clkr) 154 155 extern const struct clk_ops clk_rcg2_ops; 156 extern const struct clk_ops clk_rcg2_floor_ops; 157 extern const struct clk_ops clk_edp_pixel_ops; 158 extern const struct clk_ops clk_byte_ops; 159 extern const struct clk_ops clk_byte2_ops; 160 extern const struct clk_ops clk_pixel_ops; 161 extern const struct clk_ops clk_gfx3d_ops; 162 extern const struct clk_ops clk_rcg2_shared_ops; 163 164 #endif 165