xref: /openbmc/linux/drivers/clk/qcom/clk-pll.c (revision c819e2cf)
1 /*
2  * Copyright (c) 2013, The Linux Foundation. All rights reserved.
3  *
4  * This software is licensed under the terms of the GNU General Public
5  * License version 2, as published by the Free Software Foundation, and
6  * may be copied, distributed, and modified under those terms.
7  *
8  * This program is distributed in the hope that it will be useful,
9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11  * GNU General Public License for more details.
12  */
13 
14 #include <linux/kernel.h>
15 #include <linux/bitops.h>
16 #include <linux/err.h>
17 #include <linux/bug.h>
18 #include <linux/delay.h>
19 #include <linux/export.h>
20 #include <linux/clk-provider.h>
21 #include <linux/regmap.h>
22 
23 #include <asm/div64.h>
24 
25 #include "clk-pll.h"
26 
27 #define PLL_OUTCTRL		BIT(0)
28 #define PLL_BYPASSNL		BIT(1)
29 #define PLL_RESET_N		BIT(2)
30 #define PLL_LOCK_COUNT_SHIFT	8
31 #define PLL_LOCK_COUNT_MASK	0x3f
32 #define PLL_BIAS_COUNT_SHIFT	14
33 #define PLL_BIAS_COUNT_MASK	0x3f
34 #define PLL_VOTE_FSM_ENA	BIT(20)
35 #define PLL_VOTE_FSM_RESET	BIT(21)
36 
37 static int clk_pll_enable(struct clk_hw *hw)
38 {
39 	struct clk_pll *pll = to_clk_pll(hw);
40 	int ret;
41 	u32 mask, val;
42 
43 	mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL;
44 	ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &val);
45 	if (ret)
46 		return ret;
47 
48 	/* Skip if already enabled or in FSM mode */
49 	if ((val & mask) == mask || val & PLL_VOTE_FSM_ENA)
50 		return 0;
51 
52 	/* Disable PLL bypass mode. */
53 	ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL,
54 				 PLL_BYPASSNL);
55 	if (ret)
56 		return ret;
57 
58 	/*
59 	 * H/W requires a 5us delay between disabling the bypass and
60 	 * de-asserting the reset. Delay 10us just to be safe.
61 	 */
62 	udelay(10);
63 
64 	/* De-assert active-low PLL reset. */
65 	ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N,
66 				 PLL_RESET_N);
67 	if (ret)
68 		return ret;
69 
70 	/* Wait until PLL is locked. */
71 	udelay(50);
72 
73 	/* Enable PLL output. */
74 	ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_OUTCTRL,
75 				 PLL_OUTCTRL);
76 	if (ret)
77 		return ret;
78 
79 	return 0;
80 }
81 
82 static void clk_pll_disable(struct clk_hw *hw)
83 {
84 	struct clk_pll *pll = to_clk_pll(hw);
85 	u32 mask;
86 	u32 val;
87 
88 	regmap_read(pll->clkr.regmap, pll->mode_reg, &val);
89 	/* Skip if in FSM mode */
90 	if (val & PLL_VOTE_FSM_ENA)
91 		return;
92 	mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL;
93 	regmap_update_bits(pll->clkr.regmap, pll->mode_reg, mask, 0);
94 }
95 
96 static unsigned long
97 clk_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
98 {
99 	struct clk_pll *pll = to_clk_pll(hw);
100 	u32 l, m, n, config;
101 	unsigned long rate;
102 	u64 tmp;
103 
104 	regmap_read(pll->clkr.regmap, pll->l_reg, &l);
105 	regmap_read(pll->clkr.regmap, pll->m_reg, &m);
106 	regmap_read(pll->clkr.regmap, pll->n_reg, &n);
107 
108 	l &= 0x3ff;
109 	m &= 0x7ffff;
110 	n &= 0x7ffff;
111 
112 	rate = parent_rate * l;
113 	if (n) {
114 		tmp = parent_rate;
115 		tmp *= m;
116 		do_div(tmp, n);
117 		rate += tmp;
118 	}
119 	if (pll->post_div_width) {
120 		regmap_read(pll->clkr.regmap, pll->config_reg, &config);
121 		config >>= pll->post_div_shift;
122 		config &= BIT(pll->post_div_width) - 1;
123 		rate /= config + 1;
124 	}
125 
126 	return rate;
127 }
128 
129 static const
130 struct pll_freq_tbl *find_freq(const struct pll_freq_tbl *f, unsigned long rate)
131 {
132 	if (!f)
133 		return NULL;
134 
135 	for (; f->freq; f++)
136 		if (rate <= f->freq)
137 			return f;
138 
139 	return NULL;
140 }
141 
142 static long
143 clk_pll_determine_rate(struct clk_hw *hw, unsigned long rate,
144 		       unsigned long *p_rate, struct clk_hw **p)
145 {
146 	struct clk_pll *pll = to_clk_pll(hw);
147 	const struct pll_freq_tbl *f;
148 
149 	f = find_freq(pll->freq_tbl, rate);
150 	if (!f)
151 		return clk_pll_recalc_rate(hw, *p_rate);
152 
153 	return f->freq;
154 }
155 
156 static int
157 clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long p_rate)
158 {
159 	struct clk_pll *pll = to_clk_pll(hw);
160 	const struct pll_freq_tbl *f;
161 	bool enabled;
162 	u32 mode;
163 	u32 enable_mask = PLL_OUTCTRL | PLL_BYPASSNL | PLL_RESET_N;
164 
165 	f = find_freq(pll->freq_tbl, rate);
166 	if (!f)
167 		return -EINVAL;
168 
169 	regmap_read(pll->clkr.regmap, pll->mode_reg, &mode);
170 	enabled = (mode & enable_mask) == enable_mask;
171 
172 	if (enabled)
173 		clk_pll_disable(hw);
174 
175 	regmap_update_bits(pll->clkr.regmap, pll->l_reg, 0x3ff, f->l);
176 	regmap_update_bits(pll->clkr.regmap, pll->m_reg, 0x7ffff, f->m);
177 	regmap_update_bits(pll->clkr.regmap, pll->n_reg, 0x7ffff, f->n);
178 	regmap_write(pll->clkr.regmap, pll->config_reg, f->ibits);
179 
180 	if (enabled)
181 		clk_pll_enable(hw);
182 
183 	return 0;
184 }
185 
186 const struct clk_ops clk_pll_ops = {
187 	.enable = clk_pll_enable,
188 	.disable = clk_pll_disable,
189 	.recalc_rate = clk_pll_recalc_rate,
190 	.determine_rate = clk_pll_determine_rate,
191 	.set_rate = clk_pll_set_rate,
192 };
193 EXPORT_SYMBOL_GPL(clk_pll_ops);
194 
195 static int wait_for_pll(struct clk_pll *pll)
196 {
197 	u32 val;
198 	int count;
199 	int ret;
200 	const char *name = __clk_get_name(pll->clkr.hw.clk);
201 
202 	/* Wait for pll to enable. */
203 	for (count = 200; count > 0; count--) {
204 		ret = regmap_read(pll->clkr.regmap, pll->status_reg, &val);
205 		if (ret)
206 			return ret;
207 		if (val & BIT(pll->status_bit))
208 			return 0;
209 		udelay(1);
210 	}
211 
212 	WARN(1, "%s didn't enable after voting for it!\n", name);
213 	return -ETIMEDOUT;
214 }
215 
216 static int clk_pll_vote_enable(struct clk_hw *hw)
217 {
218 	int ret;
219 	struct clk_pll *p = to_clk_pll(__clk_get_hw(__clk_get_parent(hw->clk)));
220 
221 	ret = clk_enable_regmap(hw);
222 	if (ret)
223 		return ret;
224 
225 	return wait_for_pll(p);
226 }
227 
228 const struct clk_ops clk_pll_vote_ops = {
229 	.enable = clk_pll_vote_enable,
230 	.disable = clk_disable_regmap,
231 };
232 EXPORT_SYMBOL_GPL(clk_pll_vote_ops);
233 
234 static void
235 clk_pll_set_fsm_mode(struct clk_pll *pll, struct regmap *regmap, u8 lock_count)
236 {
237 	u32 val;
238 	u32 mask;
239 
240 	/* De-assert reset to FSM */
241 	regmap_update_bits(regmap, pll->mode_reg, PLL_VOTE_FSM_RESET, 0);
242 
243 	/* Program bias count and lock count */
244 	val = 1 << PLL_BIAS_COUNT_SHIFT | lock_count << PLL_LOCK_COUNT_SHIFT;
245 	mask = PLL_BIAS_COUNT_MASK << PLL_BIAS_COUNT_SHIFT;
246 	mask |= PLL_LOCK_COUNT_MASK << PLL_LOCK_COUNT_SHIFT;
247 	regmap_update_bits(regmap, pll->mode_reg, mask, val);
248 
249 	/* Enable PLL FSM voting */
250 	regmap_update_bits(regmap, pll->mode_reg, PLL_VOTE_FSM_ENA,
251 		PLL_VOTE_FSM_ENA);
252 }
253 
254 static void clk_pll_configure(struct clk_pll *pll, struct regmap *regmap,
255 	const struct pll_config *config)
256 {
257 	u32 val;
258 	u32 mask;
259 
260 	regmap_write(regmap, pll->l_reg, config->l);
261 	regmap_write(regmap, pll->m_reg, config->m);
262 	regmap_write(regmap, pll->n_reg, config->n);
263 
264 	val = config->vco_val;
265 	val |= config->pre_div_val;
266 	val |= config->post_div_val;
267 	val |= config->mn_ena_mask;
268 	val |= config->main_output_mask;
269 	val |= config->aux_output_mask;
270 
271 	mask = config->vco_mask;
272 	mask |= config->pre_div_mask;
273 	mask |= config->post_div_mask;
274 	mask |= config->mn_ena_mask;
275 	mask |= config->main_output_mask;
276 	mask |= config->aux_output_mask;
277 
278 	regmap_update_bits(regmap, pll->config_reg, mask, val);
279 }
280 
281 void clk_pll_configure_sr(struct clk_pll *pll, struct regmap *regmap,
282 		const struct pll_config *config, bool fsm_mode)
283 {
284 	clk_pll_configure(pll, regmap, config);
285 	if (fsm_mode)
286 		clk_pll_set_fsm_mode(pll, regmap, 8);
287 }
288 EXPORT_SYMBOL_GPL(clk_pll_configure_sr);
289 
290 void clk_pll_configure_sr_hpm_lp(struct clk_pll *pll, struct regmap *regmap,
291 		const struct pll_config *config, bool fsm_mode)
292 {
293 	clk_pll_configure(pll, regmap, config);
294 	if (fsm_mode)
295 		clk_pll_set_fsm_mode(pll, regmap, 0);
296 }
297 EXPORT_SYMBOL_GPL(clk_pll_configure_sr_hpm_lp);
298