1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4 */ 5 6 /* 7 * Each of the CPU clusters (Power and Perf) on msm8996 are 8 * clocked via 2 PLLs, a primary and alternate. There are also 9 * 2 Mux'es, a primary and secondary all connected together 10 * as shown below 11 * 12 * +-------+ 13 * XO | | 14 * +------------------>0 | 15 * | | 16 * PLL/2 | SMUX +----+ 17 * +------->1 | | 18 * | | | | 19 * | +-------+ | +-------+ 20 * | +---->0 | 21 * | | | 22 * +---------------+ | +----------->1 | CPU clk 23 * |Primary PLL +----+ PLL_EARLY | | +------> 24 * | +------+-----------+ +------>2 PMUX | 25 * +---------------+ | | | | 26 * | +------+ | +-->3 | 27 * +--^+ ACD +-----+ | +-------+ 28 * +---------------+ +------+ | 29 * |Alt PLL | | 30 * | +---------------------------+ 31 * +---------------+ PLL_EARLY 32 * 33 * The primary PLL is what drives the CPU clk, except for times 34 * when we are reprogramming the PLL itself (for rate changes) when 35 * we temporarily switch to an alternate PLL. 36 * 37 * The primary PLL operates on a single VCO range, between 600MHz 38 * and 3GHz. However the CPUs do support OPPs with frequencies 39 * between 300MHz and 600MHz. In order to support running the CPUs 40 * at those frequencies we end up having to lock the PLL at twice 41 * the rate and drive the CPU clk via the PLL/2 output and SMUX. 42 * 43 * So for frequencies above 600MHz we follow the following path 44 * Primary PLL --> PLL_EARLY --> PMUX(1) --> CPU clk 45 * and for frequencies between 300MHz and 600MHz we follow 46 * Primary PLL --> PLL/2 --> SMUX(1) --> PMUX(0) --> CPU clk 47 * 48 * ACD stands for Adaptive Clock Distribution and is used to 49 * detect voltage droops. 50 */ 51 52 #include <linux/clk.h> 53 #include <linux/clk-provider.h> 54 #include <linux/io.h> 55 #include <linux/module.h> 56 #include <linux/platform_device.h> 57 #include <linux/regmap.h> 58 #include <soc/qcom/kryo-l2-accessors.h> 59 60 #include "clk-alpha-pll.h" 61 #include "clk-regmap.h" 62 #include "clk-regmap-mux.h" 63 64 enum _pmux_input { 65 SMUX_INDEX = 0, 66 PLL_INDEX, 67 ACD_INDEX, 68 ALT_INDEX, 69 NUM_OF_PMUX_INPUTS 70 }; 71 72 #define DIV_2_THRESHOLD 600000000 73 #define PWRCL_REG_OFFSET 0x0 74 #define PERFCL_REG_OFFSET 0x80000 75 #define MUX_OFFSET 0x40 76 #define ALT_PLL_OFFSET 0x100 77 #define SSSCTL_OFFSET 0x160 78 79 static const u8 prim_pll_regs[PLL_OFF_MAX_REGS] = { 80 [PLL_OFF_L_VAL] = 0x04, 81 [PLL_OFF_ALPHA_VAL] = 0x08, 82 [PLL_OFF_USER_CTL] = 0x10, 83 [PLL_OFF_CONFIG_CTL] = 0x18, 84 [PLL_OFF_CONFIG_CTL_U] = 0x1c, 85 [PLL_OFF_TEST_CTL] = 0x20, 86 [PLL_OFF_TEST_CTL_U] = 0x24, 87 [PLL_OFF_STATUS] = 0x28, 88 }; 89 90 static const u8 alt_pll_regs[PLL_OFF_MAX_REGS] = { 91 [PLL_OFF_L_VAL] = 0x04, 92 [PLL_OFF_ALPHA_VAL] = 0x08, 93 [PLL_OFF_ALPHA_VAL_U] = 0x0c, 94 [PLL_OFF_USER_CTL] = 0x10, 95 [PLL_OFF_USER_CTL_U] = 0x14, 96 [PLL_OFF_CONFIG_CTL] = 0x18, 97 [PLL_OFF_TEST_CTL] = 0x20, 98 [PLL_OFF_TEST_CTL_U] = 0x24, 99 [PLL_OFF_STATUS] = 0x28, 100 }; 101 102 /* PLLs */ 103 104 static const struct alpha_pll_config hfpll_config = { 105 .l = 60, 106 .config_ctl_val = 0x200d4aa8, 107 .config_ctl_hi_val = 0x006, 108 .pre_div_mask = BIT(12), 109 .post_div_mask = 0x3 << 8, 110 .post_div_val = 0x1 << 8, 111 .main_output_mask = BIT(0), 112 .early_output_mask = BIT(3), 113 }; 114 115 static const struct clk_parent_data pll_parent[] = { 116 { .fw_name = "xo" }, 117 }; 118 119 static struct clk_alpha_pll pwrcl_pll = { 120 .offset = PWRCL_REG_OFFSET, 121 .regs = prim_pll_regs, 122 .flags = SUPPORTS_DYNAMIC_UPDATE | SUPPORTS_FSM_MODE, 123 .clkr.hw.init = &(struct clk_init_data){ 124 .name = "pwrcl_pll", 125 .parent_data = pll_parent, 126 .num_parents = ARRAY_SIZE(pll_parent), 127 .ops = &clk_alpha_pll_huayra_ops, 128 }, 129 }; 130 131 static struct clk_alpha_pll perfcl_pll = { 132 .offset = PERFCL_REG_OFFSET, 133 .regs = prim_pll_regs, 134 .flags = SUPPORTS_DYNAMIC_UPDATE | SUPPORTS_FSM_MODE, 135 .clkr.hw.init = &(struct clk_init_data){ 136 .name = "perfcl_pll", 137 .parent_data = pll_parent, 138 .num_parents = ARRAY_SIZE(pll_parent), 139 .ops = &clk_alpha_pll_huayra_ops, 140 }, 141 }; 142 143 static struct clk_fixed_factor pwrcl_pll_postdiv = { 144 .mult = 1, 145 .div = 2, 146 .hw.init = &(struct clk_init_data){ 147 .name = "pwrcl_pll_postdiv", 148 .parent_data = &(const struct clk_parent_data){ 149 .hw = &pwrcl_pll.clkr.hw 150 }, 151 .num_parents = 1, 152 .ops = &clk_fixed_factor_ops, 153 .flags = CLK_SET_RATE_PARENT, 154 }, 155 }; 156 157 static struct clk_fixed_factor perfcl_pll_postdiv = { 158 .mult = 1, 159 .div = 2, 160 .hw.init = &(struct clk_init_data){ 161 .name = "perfcl_pll_postdiv", 162 .parent_data = &(const struct clk_parent_data){ 163 .hw = &perfcl_pll.clkr.hw 164 }, 165 .num_parents = 1, 166 .ops = &clk_fixed_factor_ops, 167 .flags = CLK_SET_RATE_PARENT, 168 }, 169 }; 170 171 static const struct pll_vco alt_pll_vco_modes[] = { 172 VCO(3, 250000000, 500000000), 173 VCO(2, 500000000, 750000000), 174 VCO(1, 750000000, 1000000000), 175 VCO(0, 1000000000, 2150400000), 176 }; 177 178 static const struct alpha_pll_config altpll_config = { 179 .l = 16, 180 .vco_val = 0x3 << 20, 181 .vco_mask = 0x3 << 20, 182 .config_ctl_val = 0x4001051b, 183 .post_div_mask = 0x3 << 8, 184 .post_div_val = 0x1 << 8, 185 .main_output_mask = BIT(0), 186 .early_output_mask = BIT(3), 187 }; 188 189 static struct clk_alpha_pll pwrcl_alt_pll = { 190 .offset = PWRCL_REG_OFFSET + ALT_PLL_OFFSET, 191 .regs = alt_pll_regs, 192 .vco_table = alt_pll_vco_modes, 193 .num_vco = ARRAY_SIZE(alt_pll_vco_modes), 194 .flags = SUPPORTS_OFFLINE_REQ | SUPPORTS_FSM_MODE, 195 .clkr.hw.init = &(struct clk_init_data) { 196 .name = "pwrcl_alt_pll", 197 .parent_data = pll_parent, 198 .num_parents = ARRAY_SIZE(pll_parent), 199 .ops = &clk_alpha_pll_hwfsm_ops, 200 }, 201 }; 202 203 static struct clk_alpha_pll perfcl_alt_pll = { 204 .offset = PERFCL_REG_OFFSET + ALT_PLL_OFFSET, 205 .regs = alt_pll_regs, 206 .vco_table = alt_pll_vco_modes, 207 .num_vco = ARRAY_SIZE(alt_pll_vco_modes), 208 .flags = SUPPORTS_OFFLINE_REQ | SUPPORTS_FSM_MODE, 209 .clkr.hw.init = &(struct clk_init_data) { 210 .name = "perfcl_alt_pll", 211 .parent_data = pll_parent, 212 .num_parents = ARRAY_SIZE(pll_parent), 213 .ops = &clk_alpha_pll_hwfsm_ops, 214 }, 215 }; 216 217 struct clk_cpu_8996_pmux { 218 u32 reg; 219 u8 shift; 220 u8 width; 221 struct notifier_block nb; 222 struct clk_hw *pll; 223 struct clk_hw *pll_div_2; 224 struct clk_regmap clkr; 225 }; 226 227 static int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event, 228 void *data); 229 230 #define to_clk_cpu_8996_pmux_nb(_nb) \ 231 container_of(_nb, struct clk_cpu_8996_pmux, nb) 232 233 static inline struct clk_cpu_8996_pmux *to_clk_cpu_8996_pmux_hw(struct clk_hw *hw) 234 { 235 return container_of(to_clk_regmap(hw), struct clk_cpu_8996_pmux, clkr); 236 } 237 238 static u8 clk_cpu_8996_pmux_get_parent(struct clk_hw *hw) 239 { 240 struct clk_regmap *clkr = to_clk_regmap(hw); 241 struct clk_cpu_8996_pmux *cpuclk = to_clk_cpu_8996_pmux_hw(hw); 242 u32 mask = GENMASK(cpuclk->width - 1, 0); 243 u32 val; 244 245 regmap_read(clkr->regmap, cpuclk->reg, &val); 246 val >>= cpuclk->shift; 247 248 return val & mask; 249 } 250 251 static int clk_cpu_8996_pmux_set_parent(struct clk_hw *hw, u8 index) 252 { 253 struct clk_regmap *clkr = to_clk_regmap(hw); 254 struct clk_cpu_8996_pmux *cpuclk = to_clk_cpu_8996_pmux_hw(hw); 255 u32 mask = GENMASK(cpuclk->width + cpuclk->shift - 1, cpuclk->shift); 256 u32 val; 257 258 val = index; 259 /* We always want ACD when using the primary PLL */ 260 if (val == PLL_INDEX) 261 val = ACD_INDEX; 262 val <<= cpuclk->shift; 263 264 return regmap_update_bits(clkr->regmap, cpuclk->reg, mask, val); 265 } 266 267 static int clk_cpu_8996_pmux_determine_rate(struct clk_hw *hw, 268 struct clk_rate_request *req) 269 { 270 struct clk_cpu_8996_pmux *cpuclk = to_clk_cpu_8996_pmux_hw(hw); 271 struct clk_hw *parent = cpuclk->pll; 272 273 if (cpuclk->pll_div_2 && req->rate < DIV_2_THRESHOLD) { 274 if (req->rate < (DIV_2_THRESHOLD / 2)) 275 return -EINVAL; 276 277 parent = cpuclk->pll_div_2; 278 } 279 280 req->best_parent_rate = clk_hw_round_rate(parent, req->rate); 281 req->best_parent_hw = parent; 282 283 return 0; 284 } 285 286 static const struct clk_ops clk_cpu_8996_pmux_ops = { 287 .set_parent = clk_cpu_8996_pmux_set_parent, 288 .get_parent = clk_cpu_8996_pmux_get_parent, 289 .determine_rate = clk_cpu_8996_pmux_determine_rate, 290 }; 291 292 static const struct clk_parent_data pwrcl_smux_parents[] = { 293 { .fw_name = "xo" }, 294 { .hw = &pwrcl_pll_postdiv.hw }, 295 }; 296 297 static const struct clk_parent_data perfcl_smux_parents[] = { 298 { .fw_name = "xo" }, 299 { .hw = &perfcl_pll_postdiv.hw }, 300 }; 301 302 static struct clk_regmap_mux pwrcl_smux = { 303 .reg = PWRCL_REG_OFFSET + MUX_OFFSET, 304 .shift = 2, 305 .width = 2, 306 .clkr.hw.init = &(struct clk_init_data) { 307 .name = "pwrcl_smux", 308 .parent_data = pwrcl_smux_parents, 309 .num_parents = ARRAY_SIZE(pwrcl_smux_parents), 310 .ops = &clk_regmap_mux_closest_ops, 311 .flags = CLK_SET_RATE_PARENT, 312 }, 313 }; 314 315 static struct clk_regmap_mux perfcl_smux = { 316 .reg = PERFCL_REG_OFFSET + MUX_OFFSET, 317 .shift = 2, 318 .width = 2, 319 .clkr.hw.init = &(struct clk_init_data) { 320 .name = "perfcl_smux", 321 .parent_data = perfcl_smux_parents, 322 .num_parents = ARRAY_SIZE(perfcl_smux_parents), 323 .ops = &clk_regmap_mux_closest_ops, 324 .flags = CLK_SET_RATE_PARENT, 325 }, 326 }; 327 328 static const struct clk_hw *pwrcl_pmux_parents[] = { 329 [SMUX_INDEX] = &pwrcl_smux.clkr.hw, 330 [PLL_INDEX] = &pwrcl_pll.clkr.hw, 331 [ACD_INDEX] = &pwrcl_pll.clkr.hw, 332 [ALT_INDEX] = &pwrcl_alt_pll.clkr.hw, 333 }; 334 335 static const struct clk_hw *perfcl_pmux_parents[] = { 336 [SMUX_INDEX] = &perfcl_smux.clkr.hw, 337 [PLL_INDEX] = &perfcl_pll.clkr.hw, 338 [ACD_INDEX] = &perfcl_pll.clkr.hw, 339 [ALT_INDEX] = &perfcl_alt_pll.clkr.hw, 340 }; 341 342 static struct clk_cpu_8996_pmux pwrcl_pmux = { 343 .reg = PWRCL_REG_OFFSET + MUX_OFFSET, 344 .shift = 0, 345 .width = 2, 346 .pll = &pwrcl_pll.clkr.hw, 347 .pll_div_2 = &pwrcl_smux.clkr.hw, 348 .nb.notifier_call = cpu_clk_notifier_cb, 349 .clkr.hw.init = &(struct clk_init_data) { 350 .name = "pwrcl_pmux", 351 .parent_hws = pwrcl_pmux_parents, 352 .num_parents = ARRAY_SIZE(pwrcl_pmux_parents), 353 .ops = &clk_cpu_8996_pmux_ops, 354 /* CPU clock is critical and should never be gated */ 355 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 356 }, 357 }; 358 359 static struct clk_cpu_8996_pmux perfcl_pmux = { 360 .reg = PERFCL_REG_OFFSET + MUX_OFFSET, 361 .shift = 0, 362 .width = 2, 363 .pll = &perfcl_pll.clkr.hw, 364 .pll_div_2 = &perfcl_smux.clkr.hw, 365 .nb.notifier_call = cpu_clk_notifier_cb, 366 .clkr.hw.init = &(struct clk_init_data) { 367 .name = "perfcl_pmux", 368 .parent_hws = perfcl_pmux_parents, 369 .num_parents = ARRAY_SIZE(perfcl_pmux_parents), 370 .ops = &clk_cpu_8996_pmux_ops, 371 /* CPU clock is critical and should never be gated */ 372 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 373 }, 374 }; 375 376 static const struct regmap_config cpu_msm8996_regmap_config = { 377 .reg_bits = 32, 378 .reg_stride = 4, 379 .val_bits = 32, 380 .max_register = 0x80210, 381 .fast_io = true, 382 .val_format_endian = REGMAP_ENDIAN_LITTLE, 383 }; 384 385 static struct clk_regmap *cpu_msm8996_clks[] = { 386 &pwrcl_pll.clkr, 387 &perfcl_pll.clkr, 388 &pwrcl_alt_pll.clkr, 389 &perfcl_alt_pll.clkr, 390 &pwrcl_smux.clkr, 391 &perfcl_smux.clkr, 392 &pwrcl_pmux.clkr, 393 &perfcl_pmux.clkr, 394 }; 395 396 static int qcom_cpu_clk_msm8996_register_clks(struct device *dev, 397 struct regmap *regmap) 398 { 399 int i, ret; 400 401 ret = devm_clk_hw_register(dev, &pwrcl_pll_postdiv.hw); 402 if (ret) { 403 dev_err(dev, "Failed to register pwrcl_pll_postdiv: %d", ret); 404 return ret; 405 } 406 407 ret = devm_clk_hw_register(dev, &perfcl_pll_postdiv.hw); 408 if (ret) { 409 dev_err(dev, "Failed to register perfcl_pll_postdiv: %d", ret); 410 return ret; 411 } 412 413 for (i = 0; i < ARRAY_SIZE(cpu_msm8996_clks); i++) { 414 ret = devm_clk_register_regmap(dev, cpu_msm8996_clks[i]); 415 if (ret) 416 return ret; 417 } 418 419 clk_alpha_pll_configure(&pwrcl_pll, regmap, &hfpll_config); 420 clk_alpha_pll_configure(&perfcl_pll, regmap, &hfpll_config); 421 clk_alpha_pll_configure(&pwrcl_alt_pll, regmap, &altpll_config); 422 clk_alpha_pll_configure(&perfcl_alt_pll, regmap, &altpll_config); 423 424 /* Enable alt PLLs */ 425 clk_prepare_enable(pwrcl_alt_pll.clkr.hw.clk); 426 clk_prepare_enable(perfcl_alt_pll.clkr.hw.clk); 427 428 devm_clk_notifier_register(dev, pwrcl_pmux.clkr.hw.clk, &pwrcl_pmux.nb); 429 devm_clk_notifier_register(dev, perfcl_pmux.clkr.hw.clk, &perfcl_pmux.nb); 430 431 return ret; 432 } 433 434 #define CPU_AFINITY_MASK 0xFFF 435 #define PWRCL_CPU_REG_MASK 0x3 436 #define PERFCL_CPU_REG_MASK 0x103 437 438 #define L2ACDCR_REG 0x580ULL 439 #define L2ACDTD_REG 0x581ULL 440 #define L2ACDDVMRC_REG 0x584ULL 441 #define L2ACDSSCR_REG 0x589ULL 442 443 static DEFINE_SPINLOCK(qcom_clk_acd_lock); 444 static void __iomem *base; 445 446 static void qcom_cpu_clk_msm8996_acd_init(void __iomem *base) 447 { 448 u64 hwid; 449 unsigned long flags; 450 451 spin_lock_irqsave(&qcom_clk_acd_lock, flags); 452 453 hwid = read_cpuid_mpidr() & CPU_AFINITY_MASK; 454 455 kryo_l2_set_indirect_reg(L2ACDTD_REG, 0x00006a11); 456 kryo_l2_set_indirect_reg(L2ACDDVMRC_REG, 0x000e0f0f); 457 kryo_l2_set_indirect_reg(L2ACDSSCR_REG, 0x00000601); 458 459 if (PWRCL_CPU_REG_MASK == (hwid | PWRCL_CPU_REG_MASK)) { 460 writel(0xf, base + PWRCL_REG_OFFSET + SSSCTL_OFFSET); 461 kryo_l2_set_indirect_reg(L2ACDCR_REG, 0x002c5ffd); 462 } 463 464 if (PERFCL_CPU_REG_MASK == (hwid | PERFCL_CPU_REG_MASK)) { 465 kryo_l2_set_indirect_reg(L2ACDCR_REG, 0x002c5ffd); 466 writel(0xf, base + PERFCL_REG_OFFSET + SSSCTL_OFFSET); 467 } 468 469 spin_unlock_irqrestore(&qcom_clk_acd_lock, flags); 470 } 471 472 static int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event, 473 void *data) 474 { 475 struct clk_cpu_8996_pmux *cpuclk = to_clk_cpu_8996_pmux_nb(nb); 476 struct clk_notifier_data *cnd = data; 477 int ret; 478 479 switch (event) { 480 case PRE_RATE_CHANGE: 481 ret = clk_cpu_8996_pmux_set_parent(&cpuclk->clkr.hw, ALT_INDEX); 482 qcom_cpu_clk_msm8996_acd_init(base); 483 break; 484 case POST_RATE_CHANGE: 485 if (cnd->new_rate < DIV_2_THRESHOLD) 486 ret = clk_cpu_8996_pmux_set_parent(&cpuclk->clkr.hw, 487 SMUX_INDEX); 488 else 489 ret = clk_cpu_8996_pmux_set_parent(&cpuclk->clkr.hw, 490 ACD_INDEX); 491 break; 492 default: 493 ret = 0; 494 break; 495 } 496 497 return notifier_from_errno(ret); 498 }; 499 500 static int qcom_cpu_clk_msm8996_driver_probe(struct platform_device *pdev) 501 { 502 struct regmap *regmap; 503 struct clk_hw_onecell_data *data; 504 struct device *dev = &pdev->dev; 505 int ret; 506 507 data = devm_kzalloc(dev, struct_size(data, hws, 2), GFP_KERNEL); 508 if (!data) 509 return -ENOMEM; 510 511 base = devm_platform_ioremap_resource(pdev, 0); 512 if (IS_ERR(base)) 513 return PTR_ERR(base); 514 515 regmap = devm_regmap_init_mmio(dev, base, &cpu_msm8996_regmap_config); 516 if (IS_ERR(regmap)) 517 return PTR_ERR(regmap); 518 519 ret = qcom_cpu_clk_msm8996_register_clks(dev, regmap); 520 if (ret) 521 return ret; 522 523 qcom_cpu_clk_msm8996_acd_init(base); 524 525 data->hws[0] = &pwrcl_pmux.clkr.hw; 526 data->hws[1] = &perfcl_pmux.clkr.hw; 527 data->num = 2; 528 529 return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, data); 530 } 531 532 static const struct of_device_id qcom_cpu_clk_msm8996_match_table[] = { 533 { .compatible = "qcom,msm8996-apcc" }, 534 {} 535 }; 536 MODULE_DEVICE_TABLE(of, qcom_cpu_clk_msm8996_match_table); 537 538 static struct platform_driver qcom_cpu_clk_msm8996_driver = { 539 .probe = qcom_cpu_clk_msm8996_driver_probe, 540 .driver = { 541 .name = "qcom-msm8996-apcc", 542 .of_match_table = qcom_cpu_clk_msm8996_match_table, 543 }, 544 }; 545 module_platform_driver(qcom_cpu_clk_msm8996_driver); 546 547 MODULE_DESCRIPTION("QCOM MSM8996 CPU Clock Driver"); 548 MODULE_LICENSE("GPL v2"); 549