103e342dcSLoic Poulain // SPDX-License-Identifier: GPL-2.0 203e342dcSLoic Poulain /* 303e342dcSLoic Poulain * Copyright (c) 2020, The Linux Foundation. All rights reserved. 403e342dcSLoic Poulain */ 503e342dcSLoic Poulain 603e342dcSLoic Poulain /* 703e342dcSLoic Poulain * Each of the CPU clusters (Power and Perf) on msm8996 are 803e342dcSLoic Poulain * clocked via 2 PLLs, a primary and alternate. There are also 903e342dcSLoic Poulain * 2 Mux'es, a primary and secondary all connected together 1003e342dcSLoic Poulain * as shown below 1103e342dcSLoic Poulain * 1203e342dcSLoic Poulain * +-------+ 1303e342dcSLoic Poulain * XO | | 1403e342dcSLoic Poulain * +------------------>0 | 1503e342dcSLoic Poulain * | | 1603e342dcSLoic Poulain * PLL/2 | SMUX +----+ 1703e342dcSLoic Poulain * +------->1 | | 1803e342dcSLoic Poulain * | | | | 1903e342dcSLoic Poulain * | +-------+ | +-------+ 2003e342dcSLoic Poulain * | +---->0 | 2103e342dcSLoic Poulain * | | | 2203e342dcSLoic Poulain * +---------------+ | +----------->1 | CPU clk 2303e342dcSLoic Poulain * |Primary PLL +----+ PLL_EARLY | | +------> 2403e342dcSLoic Poulain * | +------+-----------+ +------>2 PMUX | 2503e342dcSLoic Poulain * +---------------+ | | | | 2603e342dcSLoic Poulain * | +------+ | +-->3 | 2703e342dcSLoic Poulain * +--^+ ACD +-----+ | +-------+ 2803e342dcSLoic Poulain * +---------------+ +------+ | 2903e342dcSLoic Poulain * |Alt PLL | | 3003e342dcSLoic Poulain * | +---------------------------+ 3103e342dcSLoic Poulain * +---------------+ PLL_EARLY 3203e342dcSLoic Poulain * 3303e342dcSLoic Poulain * The primary PLL is what drives the CPU clk, except for times 3403e342dcSLoic Poulain * when we are reprogramming the PLL itself (for rate changes) when 3503e342dcSLoic Poulain * we temporarily switch to an alternate PLL. 3603e342dcSLoic Poulain * 3703e342dcSLoic Poulain * The primary PLL operates on a single VCO range, between 600MHz 3803e342dcSLoic Poulain * and 3GHz. However the CPUs do support OPPs with frequencies 3903e342dcSLoic Poulain * between 300MHz and 600MHz. In order to support running the CPUs 4003e342dcSLoic Poulain * at those frequencies we end up having to lock the PLL at twice 4103e342dcSLoic Poulain * the rate and drive the CPU clk via the PLL/2 output and SMUX. 4203e342dcSLoic Poulain * 4303e342dcSLoic Poulain * So for frequencies above 600MHz we follow the following path 4403e342dcSLoic Poulain * Primary PLL --> PLL_EARLY --> PMUX(1) --> CPU clk 4503e342dcSLoic Poulain * and for frequencies between 300MHz and 600MHz we follow 4603e342dcSLoic Poulain * Primary PLL --> PLL/2 --> SMUX(1) --> PMUX(0) --> CPU clk 4703e342dcSLoic Poulain * 4803e342dcSLoic Poulain * ACD stands for Adaptive Clock Distribution and is used to 4903e342dcSLoic Poulain * detect voltage droops. 5003e342dcSLoic Poulain */ 5103e342dcSLoic Poulain 52*f9ea0f59SDmitry Baryshkov #include <linux/bitfield.h> 5303e342dcSLoic Poulain #include <linux/clk.h> 5403e342dcSLoic Poulain #include <linux/clk-provider.h> 5503e342dcSLoic Poulain #include <linux/io.h> 5603e342dcSLoic Poulain #include <linux/module.h> 5703e342dcSLoic Poulain #include <linux/platform_device.h> 5803e342dcSLoic Poulain #include <linux/regmap.h> 5903e342dcSLoic Poulain #include <soc/qcom/kryo-l2-accessors.h> 6003e342dcSLoic Poulain 6103e342dcSLoic Poulain #include "clk-alpha-pll.h" 6203e342dcSLoic Poulain #include "clk-regmap.h" 639a9f5f9aSYassine Oudjana #include "clk-regmap-mux.h" 6403e342dcSLoic Poulain 6503e342dcSLoic Poulain enum _pmux_input { 661ba0a3bbSYassine Oudjana SMUX_INDEX = 0, 6703e342dcSLoic Poulain PLL_INDEX, 6803e342dcSLoic Poulain ACD_INDEX, 6903e342dcSLoic Poulain ALT_INDEX, 7003e342dcSLoic Poulain NUM_OF_PMUX_INPUTS 7103e342dcSLoic Poulain }; 7203e342dcSLoic Poulain 7303e342dcSLoic Poulain #define DIV_2_THRESHOLD 600000000 7403e342dcSLoic Poulain #define PWRCL_REG_OFFSET 0x0 7503e342dcSLoic Poulain #define PERFCL_REG_OFFSET 0x80000 7603e342dcSLoic Poulain #define MUX_OFFSET 0x40 7703e342dcSLoic Poulain #define ALT_PLL_OFFSET 0x100 7803e342dcSLoic Poulain #define SSSCTL_OFFSET 0x160 7903e342dcSLoic Poulain 80*f9ea0f59SDmitry Baryshkov #define PMUX_MASK 0x3 81*f9ea0f59SDmitry Baryshkov 8203e342dcSLoic Poulain static const u8 prim_pll_regs[PLL_OFF_MAX_REGS] = { 8303e342dcSLoic Poulain [PLL_OFF_L_VAL] = 0x04, 8403e342dcSLoic Poulain [PLL_OFF_ALPHA_VAL] = 0x08, 8503e342dcSLoic Poulain [PLL_OFF_USER_CTL] = 0x10, 8603e342dcSLoic Poulain [PLL_OFF_CONFIG_CTL] = 0x18, 8703e342dcSLoic Poulain [PLL_OFF_CONFIG_CTL_U] = 0x1c, 8803e342dcSLoic Poulain [PLL_OFF_TEST_CTL] = 0x20, 8903e342dcSLoic Poulain [PLL_OFF_TEST_CTL_U] = 0x24, 9003e342dcSLoic Poulain [PLL_OFF_STATUS] = 0x28, 9103e342dcSLoic Poulain }; 9203e342dcSLoic Poulain 9303e342dcSLoic Poulain static const u8 alt_pll_regs[PLL_OFF_MAX_REGS] = { 9403e342dcSLoic Poulain [PLL_OFF_L_VAL] = 0x04, 9503e342dcSLoic Poulain [PLL_OFF_ALPHA_VAL] = 0x08, 9603e342dcSLoic Poulain [PLL_OFF_ALPHA_VAL_U] = 0x0c, 9703e342dcSLoic Poulain [PLL_OFF_USER_CTL] = 0x10, 9803e342dcSLoic Poulain [PLL_OFF_USER_CTL_U] = 0x14, 9903e342dcSLoic Poulain [PLL_OFF_CONFIG_CTL] = 0x18, 10003e342dcSLoic Poulain [PLL_OFF_TEST_CTL] = 0x20, 10103e342dcSLoic Poulain [PLL_OFF_TEST_CTL_U] = 0x24, 10203e342dcSLoic Poulain [PLL_OFF_STATUS] = 0x28, 10303e342dcSLoic Poulain }; 10403e342dcSLoic Poulain 10503e342dcSLoic Poulain /* PLLs */ 10603e342dcSLoic Poulain 10703e342dcSLoic Poulain static const struct alpha_pll_config hfpll_config = { 10803e342dcSLoic Poulain .l = 60, 10903e342dcSLoic Poulain .config_ctl_val = 0x200d4aa8, 11003e342dcSLoic Poulain .config_ctl_hi_val = 0x006, 11103e342dcSLoic Poulain .pre_div_mask = BIT(12), 11203e342dcSLoic Poulain .post_div_mask = 0x3 << 8, 11303e342dcSLoic Poulain .post_div_val = 0x1 << 8, 11403e342dcSLoic Poulain .main_output_mask = BIT(0), 11503e342dcSLoic Poulain .early_output_mask = BIT(3), 11603e342dcSLoic Poulain }; 11703e342dcSLoic Poulain 118da5daae8SYassine Oudjana static const struct clk_parent_data pll_parent[] = { 119da5daae8SYassine Oudjana { .fw_name = "xo" }, 120da5daae8SYassine Oudjana }; 121da5daae8SYassine Oudjana 12203e342dcSLoic Poulain static struct clk_alpha_pll pwrcl_pll = { 12303e342dcSLoic Poulain .offset = PWRCL_REG_OFFSET, 12403e342dcSLoic Poulain .regs = prim_pll_regs, 12503e342dcSLoic Poulain .flags = SUPPORTS_DYNAMIC_UPDATE | SUPPORTS_FSM_MODE, 12603e342dcSLoic Poulain .clkr.hw.init = &(struct clk_init_data){ 12703e342dcSLoic Poulain .name = "pwrcl_pll", 128da5daae8SYassine Oudjana .parent_data = pll_parent, 129da5daae8SYassine Oudjana .num_parents = ARRAY_SIZE(pll_parent), 13003e342dcSLoic Poulain .ops = &clk_alpha_pll_huayra_ops, 13103e342dcSLoic Poulain }, 13203e342dcSLoic Poulain }; 13303e342dcSLoic Poulain 134382139bfSYassine Oudjana static struct clk_alpha_pll perfcl_pll = { 135382139bfSYassine Oudjana .offset = PERFCL_REG_OFFSET, 136382139bfSYassine Oudjana .regs = prim_pll_regs, 137382139bfSYassine Oudjana .flags = SUPPORTS_DYNAMIC_UPDATE | SUPPORTS_FSM_MODE, 138382139bfSYassine Oudjana .clkr.hw.init = &(struct clk_init_data){ 139382139bfSYassine Oudjana .name = "perfcl_pll", 140da5daae8SYassine Oudjana .parent_data = pll_parent, 141da5daae8SYassine Oudjana .num_parents = ARRAY_SIZE(pll_parent), 142382139bfSYassine Oudjana .ops = &clk_alpha_pll_huayra_ops, 143382139bfSYassine Oudjana }, 144382139bfSYassine Oudjana }; 145382139bfSYassine Oudjana 146de37e021SYassine Oudjana static struct clk_fixed_factor pwrcl_pll_postdiv = { 147de37e021SYassine Oudjana .mult = 1, 148de37e021SYassine Oudjana .div = 2, 149de37e021SYassine Oudjana .hw.init = &(struct clk_init_data){ 150de37e021SYassine Oudjana .name = "pwrcl_pll_postdiv", 151de37e021SYassine Oudjana .parent_data = &(const struct clk_parent_data){ 152de37e021SYassine Oudjana .hw = &pwrcl_pll.clkr.hw 153de37e021SYassine Oudjana }, 154de37e021SYassine Oudjana .num_parents = 1, 155de37e021SYassine Oudjana .ops = &clk_fixed_factor_ops, 156de37e021SYassine Oudjana .flags = CLK_SET_RATE_PARENT, 157de37e021SYassine Oudjana }, 158de37e021SYassine Oudjana }; 159de37e021SYassine Oudjana 160de37e021SYassine Oudjana static struct clk_fixed_factor perfcl_pll_postdiv = { 161de37e021SYassine Oudjana .mult = 1, 162de37e021SYassine Oudjana .div = 2, 163de37e021SYassine Oudjana .hw.init = &(struct clk_init_data){ 164de37e021SYassine Oudjana .name = "perfcl_pll_postdiv", 165de37e021SYassine Oudjana .parent_data = &(const struct clk_parent_data){ 166de37e021SYassine Oudjana .hw = &perfcl_pll.clkr.hw 167de37e021SYassine Oudjana }, 168de37e021SYassine Oudjana .num_parents = 1, 169de37e021SYassine Oudjana .ops = &clk_fixed_factor_ops, 170de37e021SYassine Oudjana .flags = CLK_SET_RATE_PARENT, 171de37e021SYassine Oudjana }, 172de37e021SYassine Oudjana }; 173de37e021SYassine Oudjana 174f1e3fcc4SDmitry Baryshkov static struct clk_fixed_factor perfcl_pll_acd = { 175f1e3fcc4SDmitry Baryshkov .mult = 1, 176f1e3fcc4SDmitry Baryshkov .div = 1, 177f1e3fcc4SDmitry Baryshkov .hw.init = &(struct clk_init_data){ 178f1e3fcc4SDmitry Baryshkov .name = "perfcl_pll_acd", 179f1e3fcc4SDmitry Baryshkov .parent_data = &(const struct clk_parent_data){ 180f1e3fcc4SDmitry Baryshkov .hw = &perfcl_pll.clkr.hw 181f1e3fcc4SDmitry Baryshkov }, 182f1e3fcc4SDmitry Baryshkov .num_parents = 1, 183f1e3fcc4SDmitry Baryshkov .ops = &clk_fixed_factor_ops, 184f1e3fcc4SDmitry Baryshkov .flags = CLK_SET_RATE_PARENT, 185f1e3fcc4SDmitry Baryshkov }, 186f1e3fcc4SDmitry Baryshkov }; 187f1e3fcc4SDmitry Baryshkov 188f1e3fcc4SDmitry Baryshkov static struct clk_fixed_factor pwrcl_pll_acd = { 189f1e3fcc4SDmitry Baryshkov .mult = 1, 190f1e3fcc4SDmitry Baryshkov .div = 1, 191f1e3fcc4SDmitry Baryshkov .hw.init = &(struct clk_init_data){ 192f1e3fcc4SDmitry Baryshkov .name = "pwrcl_pll_acd", 193f1e3fcc4SDmitry Baryshkov .parent_data = &(const struct clk_parent_data){ 194f1e3fcc4SDmitry Baryshkov .hw = &pwrcl_pll.clkr.hw 195f1e3fcc4SDmitry Baryshkov }, 196f1e3fcc4SDmitry Baryshkov .num_parents = 1, 197f1e3fcc4SDmitry Baryshkov .ops = &clk_fixed_factor_ops, 198f1e3fcc4SDmitry Baryshkov .flags = CLK_SET_RATE_PARENT, 199f1e3fcc4SDmitry Baryshkov }, 200f1e3fcc4SDmitry Baryshkov }; 201f1e3fcc4SDmitry Baryshkov 20203e342dcSLoic Poulain static const struct pll_vco alt_pll_vco_modes[] = { 20303e342dcSLoic Poulain VCO(3, 250000000, 500000000), 20403e342dcSLoic Poulain VCO(2, 500000000, 750000000), 20503e342dcSLoic Poulain VCO(1, 750000000, 1000000000), 20603e342dcSLoic Poulain VCO(0, 1000000000, 2150400000), 20703e342dcSLoic Poulain }; 20803e342dcSLoic Poulain 20903e342dcSLoic Poulain static const struct alpha_pll_config altpll_config = { 21003e342dcSLoic Poulain .l = 16, 21103e342dcSLoic Poulain .vco_val = 0x3 << 20, 21203e342dcSLoic Poulain .vco_mask = 0x3 << 20, 21303e342dcSLoic Poulain .config_ctl_val = 0x4001051b, 21403e342dcSLoic Poulain .post_div_mask = 0x3 << 8, 21503e342dcSLoic Poulain .post_div_val = 0x1 << 8, 21603e342dcSLoic Poulain .main_output_mask = BIT(0), 21703e342dcSLoic Poulain .early_output_mask = BIT(3), 21803e342dcSLoic Poulain }; 21903e342dcSLoic Poulain 22003e342dcSLoic Poulain static struct clk_alpha_pll pwrcl_alt_pll = { 22103e342dcSLoic Poulain .offset = PWRCL_REG_OFFSET + ALT_PLL_OFFSET, 22203e342dcSLoic Poulain .regs = alt_pll_regs, 22303e342dcSLoic Poulain .vco_table = alt_pll_vco_modes, 22403e342dcSLoic Poulain .num_vco = ARRAY_SIZE(alt_pll_vco_modes), 22503e342dcSLoic Poulain .flags = SUPPORTS_OFFLINE_REQ | SUPPORTS_FSM_MODE, 22603e342dcSLoic Poulain .clkr.hw.init = &(struct clk_init_data) { 22703e342dcSLoic Poulain .name = "pwrcl_alt_pll", 228da5daae8SYassine Oudjana .parent_data = pll_parent, 229da5daae8SYassine Oudjana .num_parents = ARRAY_SIZE(pll_parent), 23003e342dcSLoic Poulain .ops = &clk_alpha_pll_hwfsm_ops, 23103e342dcSLoic Poulain }, 23203e342dcSLoic Poulain }; 23303e342dcSLoic Poulain 234382139bfSYassine Oudjana static struct clk_alpha_pll perfcl_alt_pll = { 235382139bfSYassine Oudjana .offset = PERFCL_REG_OFFSET + ALT_PLL_OFFSET, 236382139bfSYassine Oudjana .regs = alt_pll_regs, 237382139bfSYassine Oudjana .vco_table = alt_pll_vco_modes, 238382139bfSYassine Oudjana .num_vco = ARRAY_SIZE(alt_pll_vco_modes), 239382139bfSYassine Oudjana .flags = SUPPORTS_OFFLINE_REQ | SUPPORTS_FSM_MODE, 240382139bfSYassine Oudjana .clkr.hw.init = &(struct clk_init_data) { 241382139bfSYassine Oudjana .name = "perfcl_alt_pll", 242da5daae8SYassine Oudjana .parent_data = pll_parent, 243da5daae8SYassine Oudjana .num_parents = ARRAY_SIZE(pll_parent), 244382139bfSYassine Oudjana .ops = &clk_alpha_pll_hwfsm_ops, 245382139bfSYassine Oudjana }, 246382139bfSYassine Oudjana }; 247382139bfSYassine Oudjana 2489a9f5f9aSYassine Oudjana struct clk_cpu_8996_pmux { 24903e342dcSLoic Poulain u32 reg; 25003e342dcSLoic Poulain struct notifier_block nb; 25103e342dcSLoic Poulain struct clk_regmap clkr; 25203e342dcSLoic Poulain }; 25303e342dcSLoic Poulain 25403e342dcSLoic Poulain static int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event, 25503e342dcSLoic Poulain void *data); 25603e342dcSLoic Poulain 2579a9f5f9aSYassine Oudjana #define to_clk_cpu_8996_pmux_nb(_nb) \ 2589a9f5f9aSYassine Oudjana container_of(_nb, struct clk_cpu_8996_pmux, nb) 25903e342dcSLoic Poulain 2609a9f5f9aSYassine Oudjana static inline struct clk_cpu_8996_pmux *to_clk_cpu_8996_pmux_hw(struct clk_hw *hw) 26103e342dcSLoic Poulain { 2629a9f5f9aSYassine Oudjana return container_of(to_clk_regmap(hw), struct clk_cpu_8996_pmux, clkr); 26303e342dcSLoic Poulain } 26403e342dcSLoic Poulain 2659a9f5f9aSYassine Oudjana static u8 clk_cpu_8996_pmux_get_parent(struct clk_hw *hw) 26603e342dcSLoic Poulain { 26703e342dcSLoic Poulain struct clk_regmap *clkr = to_clk_regmap(hw); 2689a9f5f9aSYassine Oudjana struct clk_cpu_8996_pmux *cpuclk = to_clk_cpu_8996_pmux_hw(hw); 26903e342dcSLoic Poulain u32 val; 27003e342dcSLoic Poulain 27103e342dcSLoic Poulain regmap_read(clkr->regmap, cpuclk->reg, &val); 27203e342dcSLoic Poulain 273*f9ea0f59SDmitry Baryshkov return FIELD_GET(PMUX_MASK, val); 27403e342dcSLoic Poulain } 27503e342dcSLoic Poulain 2769a9f5f9aSYassine Oudjana static int clk_cpu_8996_pmux_set_parent(struct clk_hw *hw, u8 index) 27703e342dcSLoic Poulain { 27803e342dcSLoic Poulain struct clk_regmap *clkr = to_clk_regmap(hw); 2799a9f5f9aSYassine Oudjana struct clk_cpu_8996_pmux *cpuclk = to_clk_cpu_8996_pmux_hw(hw); 28003e342dcSLoic Poulain u32 val; 28103e342dcSLoic Poulain 282*f9ea0f59SDmitry Baryshkov val = FIELD_PREP(PMUX_MASK, index); 28303e342dcSLoic Poulain 284*f9ea0f59SDmitry Baryshkov return regmap_update_bits(clkr->regmap, cpuclk->reg, PMUX_MASK, val); 28503e342dcSLoic Poulain } 28603e342dcSLoic Poulain 2879a9f5f9aSYassine Oudjana static int clk_cpu_8996_pmux_determine_rate(struct clk_hw *hw, 28803e342dcSLoic Poulain struct clk_rate_request *req) 28903e342dcSLoic Poulain { 290f387d1c4SDmitry Baryshkov struct clk_hw *parent; 29103e342dcSLoic Poulain 29203e342dcSLoic Poulain if (req->rate < (DIV_2_THRESHOLD / 2)) 29303e342dcSLoic Poulain return -EINVAL; 29403e342dcSLoic Poulain 295f387d1c4SDmitry Baryshkov if (req->rate < DIV_2_THRESHOLD) 296f387d1c4SDmitry Baryshkov parent = clk_hw_get_parent_by_index(hw, SMUX_INDEX); 297f387d1c4SDmitry Baryshkov else 298f387d1c4SDmitry Baryshkov parent = clk_hw_get_parent_by_index(hw, ACD_INDEX); 299f387d1c4SDmitry Baryshkov if (!parent) 300f387d1c4SDmitry Baryshkov return -EINVAL; 30103e342dcSLoic Poulain 30203e342dcSLoic Poulain req->best_parent_rate = clk_hw_round_rate(parent, req->rate); 30303e342dcSLoic Poulain req->best_parent_hw = parent; 30403e342dcSLoic Poulain 30503e342dcSLoic Poulain return 0; 30603e342dcSLoic Poulain } 30703e342dcSLoic Poulain 3089a9f5f9aSYassine Oudjana static const struct clk_ops clk_cpu_8996_pmux_ops = { 3099a9f5f9aSYassine Oudjana .set_parent = clk_cpu_8996_pmux_set_parent, 3109a9f5f9aSYassine Oudjana .get_parent = clk_cpu_8996_pmux_get_parent, 3119a9f5f9aSYassine Oudjana .determine_rate = clk_cpu_8996_pmux_determine_rate, 31203e342dcSLoic Poulain }; 31303e342dcSLoic Poulain 314da5daae8SYassine Oudjana static const struct clk_parent_data pwrcl_smux_parents[] = { 315da5daae8SYassine Oudjana { .fw_name = "xo" }, 316da5daae8SYassine Oudjana { .hw = &pwrcl_pll_postdiv.hw }, 317da5daae8SYassine Oudjana }; 318da5daae8SYassine Oudjana 319da5daae8SYassine Oudjana static const struct clk_parent_data perfcl_smux_parents[] = { 320da5daae8SYassine Oudjana { .fw_name = "xo" }, 321da5daae8SYassine Oudjana { .hw = &perfcl_pll_postdiv.hw }, 322da5daae8SYassine Oudjana }; 323da5daae8SYassine Oudjana 3249a9f5f9aSYassine Oudjana static struct clk_regmap_mux pwrcl_smux = { 32503e342dcSLoic Poulain .reg = PWRCL_REG_OFFSET + MUX_OFFSET, 32603e342dcSLoic Poulain .shift = 2, 32703e342dcSLoic Poulain .width = 2, 32803e342dcSLoic Poulain .clkr.hw.init = &(struct clk_init_data) { 32903e342dcSLoic Poulain .name = "pwrcl_smux", 330da5daae8SYassine Oudjana .parent_data = pwrcl_smux_parents, 331da5daae8SYassine Oudjana .num_parents = ARRAY_SIZE(pwrcl_smux_parents), 3329a9f5f9aSYassine Oudjana .ops = &clk_regmap_mux_closest_ops, 33303e342dcSLoic Poulain .flags = CLK_SET_RATE_PARENT, 33403e342dcSLoic Poulain }, 33503e342dcSLoic Poulain }; 33603e342dcSLoic Poulain 3379a9f5f9aSYassine Oudjana static struct clk_regmap_mux perfcl_smux = { 33803e342dcSLoic Poulain .reg = PERFCL_REG_OFFSET + MUX_OFFSET, 33903e342dcSLoic Poulain .shift = 2, 34003e342dcSLoic Poulain .width = 2, 34103e342dcSLoic Poulain .clkr.hw.init = &(struct clk_init_data) { 34203e342dcSLoic Poulain .name = "perfcl_smux", 343da5daae8SYassine Oudjana .parent_data = perfcl_smux_parents, 344da5daae8SYassine Oudjana .num_parents = ARRAY_SIZE(perfcl_smux_parents), 3459a9f5f9aSYassine Oudjana .ops = &clk_regmap_mux_closest_ops, 34603e342dcSLoic Poulain .flags = CLK_SET_RATE_PARENT, 34703e342dcSLoic Poulain }, 34803e342dcSLoic Poulain }; 34903e342dcSLoic Poulain 350da5daae8SYassine Oudjana static const struct clk_hw *pwrcl_pmux_parents[] = { 351da5daae8SYassine Oudjana [SMUX_INDEX] = &pwrcl_smux.clkr.hw, 352da5daae8SYassine Oudjana [PLL_INDEX] = &pwrcl_pll.clkr.hw, 353f1e3fcc4SDmitry Baryshkov [ACD_INDEX] = &pwrcl_pll_acd.hw, 354da5daae8SYassine Oudjana [ALT_INDEX] = &pwrcl_alt_pll.clkr.hw, 355da5daae8SYassine Oudjana }; 356da5daae8SYassine Oudjana 357da5daae8SYassine Oudjana static const struct clk_hw *perfcl_pmux_parents[] = { 358da5daae8SYassine Oudjana [SMUX_INDEX] = &perfcl_smux.clkr.hw, 359da5daae8SYassine Oudjana [PLL_INDEX] = &perfcl_pll.clkr.hw, 360f1e3fcc4SDmitry Baryshkov [ACD_INDEX] = &perfcl_pll_acd.hw, 361da5daae8SYassine Oudjana [ALT_INDEX] = &perfcl_alt_pll.clkr.hw, 362da5daae8SYassine Oudjana }; 363da5daae8SYassine Oudjana 3649a9f5f9aSYassine Oudjana static struct clk_cpu_8996_pmux pwrcl_pmux = { 36503e342dcSLoic Poulain .reg = PWRCL_REG_OFFSET + MUX_OFFSET, 36603e342dcSLoic Poulain .nb.notifier_call = cpu_clk_notifier_cb, 36703e342dcSLoic Poulain .clkr.hw.init = &(struct clk_init_data) { 36803e342dcSLoic Poulain .name = "pwrcl_pmux", 369da5daae8SYassine Oudjana .parent_hws = pwrcl_pmux_parents, 370da5daae8SYassine Oudjana .num_parents = ARRAY_SIZE(pwrcl_pmux_parents), 3719a9f5f9aSYassine Oudjana .ops = &clk_cpu_8996_pmux_ops, 37203e342dcSLoic Poulain /* CPU clock is critical and should never be gated */ 37303e342dcSLoic Poulain .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 37403e342dcSLoic Poulain }, 37503e342dcSLoic Poulain }; 37603e342dcSLoic Poulain 3779a9f5f9aSYassine Oudjana static struct clk_cpu_8996_pmux perfcl_pmux = { 37803e342dcSLoic Poulain .reg = PERFCL_REG_OFFSET + MUX_OFFSET, 37903e342dcSLoic Poulain .nb.notifier_call = cpu_clk_notifier_cb, 38003e342dcSLoic Poulain .clkr.hw.init = &(struct clk_init_data) { 38103e342dcSLoic Poulain .name = "perfcl_pmux", 382da5daae8SYassine Oudjana .parent_hws = perfcl_pmux_parents, 383da5daae8SYassine Oudjana .num_parents = ARRAY_SIZE(perfcl_pmux_parents), 3849a9f5f9aSYassine Oudjana .ops = &clk_cpu_8996_pmux_ops, 38503e342dcSLoic Poulain /* CPU clock is critical and should never be gated */ 38603e342dcSLoic Poulain .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 38703e342dcSLoic Poulain }, 38803e342dcSLoic Poulain }; 38903e342dcSLoic Poulain 39003e342dcSLoic Poulain static const struct regmap_config cpu_msm8996_regmap_config = { 39103e342dcSLoic Poulain .reg_bits = 32, 39203e342dcSLoic Poulain .reg_stride = 4, 39303e342dcSLoic Poulain .val_bits = 32, 39403e342dcSLoic Poulain .max_register = 0x80210, 39503e342dcSLoic Poulain .fast_io = true, 39603e342dcSLoic Poulain .val_format_endian = REGMAP_ENDIAN_LITTLE, 39703e342dcSLoic Poulain }; 39803e342dcSLoic Poulain 399f1e3fcc4SDmitry Baryshkov static struct clk_hw *cpu_msm8996_hw_clks[] = { 400f1e3fcc4SDmitry Baryshkov &pwrcl_pll_postdiv.hw, 401f1e3fcc4SDmitry Baryshkov &perfcl_pll_postdiv.hw, 402f1e3fcc4SDmitry Baryshkov &pwrcl_pll_acd.hw, 403f1e3fcc4SDmitry Baryshkov &perfcl_pll_acd.hw, 404f1e3fcc4SDmitry Baryshkov }; 405f1e3fcc4SDmitry Baryshkov 4068607fa16SWei Yongjun static struct clk_regmap *cpu_msm8996_clks[] = { 40703e342dcSLoic Poulain &pwrcl_pll.clkr, 408382139bfSYassine Oudjana &perfcl_pll.clkr, 40903e342dcSLoic Poulain &pwrcl_alt_pll.clkr, 410382139bfSYassine Oudjana &perfcl_alt_pll.clkr, 41103e342dcSLoic Poulain &pwrcl_smux.clkr, 412382139bfSYassine Oudjana &perfcl_smux.clkr, 41303e342dcSLoic Poulain &pwrcl_pmux.clkr, 414382139bfSYassine Oudjana &perfcl_pmux.clkr, 41503e342dcSLoic Poulain }; 41603e342dcSLoic Poulain 41703e342dcSLoic Poulain static int qcom_cpu_clk_msm8996_register_clks(struct device *dev, 41803e342dcSLoic Poulain struct regmap *regmap) 41903e342dcSLoic Poulain { 42003e342dcSLoic Poulain int i, ret; 42103e342dcSLoic Poulain 422f1e3fcc4SDmitry Baryshkov for (i = 0; i < ARRAY_SIZE(cpu_msm8996_hw_clks); i++) { 423f1e3fcc4SDmitry Baryshkov ret = devm_clk_hw_register(dev, cpu_msm8996_hw_clks[i]); 424f1e3fcc4SDmitry Baryshkov if (ret) 425de37e021SYassine Oudjana return ret; 42603e342dcSLoic Poulain } 42703e342dcSLoic Poulain 42803e342dcSLoic Poulain for (i = 0; i < ARRAY_SIZE(cpu_msm8996_clks); i++) { 42903e342dcSLoic Poulain ret = devm_clk_register_regmap(dev, cpu_msm8996_clks[i]); 430de37e021SYassine Oudjana if (ret) 43103e342dcSLoic Poulain return ret; 43203e342dcSLoic Poulain } 43303e342dcSLoic Poulain 43403e342dcSLoic Poulain clk_alpha_pll_configure(&pwrcl_pll, regmap, &hfpll_config); 435382139bfSYassine Oudjana clk_alpha_pll_configure(&perfcl_pll, regmap, &hfpll_config); 43603e342dcSLoic Poulain clk_alpha_pll_configure(&pwrcl_alt_pll, regmap, &altpll_config); 437382139bfSYassine Oudjana clk_alpha_pll_configure(&perfcl_alt_pll, regmap, &altpll_config); 43803e342dcSLoic Poulain 43903e342dcSLoic Poulain /* Enable alt PLLs */ 44003e342dcSLoic Poulain clk_prepare_enable(pwrcl_alt_pll.clkr.hw.clk); 44103e342dcSLoic Poulain clk_prepare_enable(perfcl_alt_pll.clkr.hw.clk); 44203e342dcSLoic Poulain 443a808c784SDmitry Baryshkov devm_clk_notifier_register(dev, pwrcl_pmux.clkr.hw.clk, &pwrcl_pmux.nb); 444a808c784SDmitry Baryshkov devm_clk_notifier_register(dev, perfcl_pmux.clkr.hw.clk, &perfcl_pmux.nb); 44503e342dcSLoic Poulain 44603e342dcSLoic Poulain return ret; 44703e342dcSLoic Poulain } 44803e342dcSLoic Poulain 44903e342dcSLoic Poulain #define CPU_AFINITY_MASK 0xFFF 45003e342dcSLoic Poulain #define PWRCL_CPU_REG_MASK 0x3 45103e342dcSLoic Poulain #define PERFCL_CPU_REG_MASK 0x103 45203e342dcSLoic Poulain 45303e342dcSLoic Poulain #define L2ACDCR_REG 0x580ULL 45403e342dcSLoic Poulain #define L2ACDTD_REG 0x581ULL 45503e342dcSLoic Poulain #define L2ACDDVMRC_REG 0x584ULL 45603e342dcSLoic Poulain #define L2ACDSSCR_REG 0x589ULL 45703e342dcSLoic Poulain 45803e342dcSLoic Poulain static DEFINE_SPINLOCK(qcom_clk_acd_lock); 45903e342dcSLoic Poulain static void __iomem *base; 46003e342dcSLoic Poulain 46103e342dcSLoic Poulain static void qcom_cpu_clk_msm8996_acd_init(void __iomem *base) 46203e342dcSLoic Poulain { 46303e342dcSLoic Poulain u64 hwid; 46403e342dcSLoic Poulain unsigned long flags; 46503e342dcSLoic Poulain 46603e342dcSLoic Poulain spin_lock_irqsave(&qcom_clk_acd_lock, flags); 46703e342dcSLoic Poulain 46803e342dcSLoic Poulain hwid = read_cpuid_mpidr() & CPU_AFINITY_MASK; 46903e342dcSLoic Poulain 47003e342dcSLoic Poulain kryo_l2_set_indirect_reg(L2ACDTD_REG, 0x00006a11); 47103e342dcSLoic Poulain kryo_l2_set_indirect_reg(L2ACDDVMRC_REG, 0x000e0f0f); 47203e342dcSLoic Poulain kryo_l2_set_indirect_reg(L2ACDSSCR_REG, 0x00000601); 47303e342dcSLoic Poulain 47403e342dcSLoic Poulain if (PWRCL_CPU_REG_MASK == (hwid | PWRCL_CPU_REG_MASK)) { 47503e342dcSLoic Poulain writel(0xf, base + PWRCL_REG_OFFSET + SSSCTL_OFFSET); 47603e342dcSLoic Poulain kryo_l2_set_indirect_reg(L2ACDCR_REG, 0x002c5ffd); 47703e342dcSLoic Poulain } 47803e342dcSLoic Poulain 47903e342dcSLoic Poulain if (PERFCL_CPU_REG_MASK == (hwid | PERFCL_CPU_REG_MASK)) { 48003e342dcSLoic Poulain kryo_l2_set_indirect_reg(L2ACDCR_REG, 0x002c5ffd); 48103e342dcSLoic Poulain writel(0xf, base + PERFCL_REG_OFFSET + SSSCTL_OFFSET); 48203e342dcSLoic Poulain } 48303e342dcSLoic Poulain 48403e342dcSLoic Poulain spin_unlock_irqrestore(&qcom_clk_acd_lock, flags); 48503e342dcSLoic Poulain } 48603e342dcSLoic Poulain 48703e342dcSLoic Poulain static int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event, 48803e342dcSLoic Poulain void *data) 48903e342dcSLoic Poulain { 4909a9f5f9aSYassine Oudjana struct clk_cpu_8996_pmux *cpuclk = to_clk_cpu_8996_pmux_nb(nb); 49103e342dcSLoic Poulain struct clk_notifier_data *cnd = data; 49203e342dcSLoic Poulain int ret; 49303e342dcSLoic Poulain 49403e342dcSLoic Poulain switch (event) { 49503e342dcSLoic Poulain case PRE_RATE_CHANGE: 4969a9f5f9aSYassine Oudjana ret = clk_cpu_8996_pmux_set_parent(&cpuclk->clkr.hw, ALT_INDEX); 49703e342dcSLoic Poulain qcom_cpu_clk_msm8996_acd_init(base); 49803e342dcSLoic Poulain break; 49903e342dcSLoic Poulain case POST_RATE_CHANGE: 50003e342dcSLoic Poulain if (cnd->new_rate < DIV_2_THRESHOLD) 5019a9f5f9aSYassine Oudjana ret = clk_cpu_8996_pmux_set_parent(&cpuclk->clkr.hw, 5021ba0a3bbSYassine Oudjana SMUX_INDEX); 50303e342dcSLoic Poulain else 5049a9f5f9aSYassine Oudjana ret = clk_cpu_8996_pmux_set_parent(&cpuclk->clkr.hw, 50503e342dcSLoic Poulain ACD_INDEX); 50603e342dcSLoic Poulain break; 50703e342dcSLoic Poulain default: 50803e342dcSLoic Poulain ret = 0; 50903e342dcSLoic Poulain break; 51003e342dcSLoic Poulain } 51103e342dcSLoic Poulain 51203e342dcSLoic Poulain return notifier_from_errno(ret); 51303e342dcSLoic Poulain }; 51403e342dcSLoic Poulain 51503e342dcSLoic Poulain static int qcom_cpu_clk_msm8996_driver_probe(struct platform_device *pdev) 51603e342dcSLoic Poulain { 51703e342dcSLoic Poulain struct regmap *regmap; 51803e342dcSLoic Poulain struct clk_hw_onecell_data *data; 51903e342dcSLoic Poulain struct device *dev = &pdev->dev; 52003e342dcSLoic Poulain int ret; 52103e342dcSLoic Poulain 52203e342dcSLoic Poulain data = devm_kzalloc(dev, struct_size(data, hws, 2), GFP_KERNEL); 52303e342dcSLoic Poulain if (!data) 52403e342dcSLoic Poulain return -ENOMEM; 52503e342dcSLoic Poulain 52603e342dcSLoic Poulain base = devm_platform_ioremap_resource(pdev, 0); 52703e342dcSLoic Poulain if (IS_ERR(base)) 52803e342dcSLoic Poulain return PTR_ERR(base); 52903e342dcSLoic Poulain 53003e342dcSLoic Poulain regmap = devm_regmap_init_mmio(dev, base, &cpu_msm8996_regmap_config); 53103e342dcSLoic Poulain if (IS_ERR(regmap)) 53203e342dcSLoic Poulain return PTR_ERR(regmap); 53303e342dcSLoic Poulain 53403e342dcSLoic Poulain ret = qcom_cpu_clk_msm8996_register_clks(dev, regmap); 53503e342dcSLoic Poulain if (ret) 53603e342dcSLoic Poulain return ret; 53703e342dcSLoic Poulain 53803e342dcSLoic Poulain qcom_cpu_clk_msm8996_acd_init(base); 53903e342dcSLoic Poulain 54003e342dcSLoic Poulain data->hws[0] = &pwrcl_pmux.clkr.hw; 54103e342dcSLoic Poulain data->hws[1] = &perfcl_pmux.clkr.hw; 54203e342dcSLoic Poulain data->num = 2; 54303e342dcSLoic Poulain 54403e342dcSLoic Poulain return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, data); 54503e342dcSLoic Poulain } 54603e342dcSLoic Poulain 54703e342dcSLoic Poulain static const struct of_device_id qcom_cpu_clk_msm8996_match_table[] = { 54803e342dcSLoic Poulain { .compatible = "qcom,msm8996-apcc" }, 54903e342dcSLoic Poulain {} 55003e342dcSLoic Poulain }; 55103e342dcSLoic Poulain MODULE_DEVICE_TABLE(of, qcom_cpu_clk_msm8996_match_table); 55203e342dcSLoic Poulain 55303e342dcSLoic Poulain static struct platform_driver qcom_cpu_clk_msm8996_driver = { 55403e342dcSLoic Poulain .probe = qcom_cpu_clk_msm8996_driver_probe, 55503e342dcSLoic Poulain .driver = { 55603e342dcSLoic Poulain .name = "qcom-msm8996-apcc", 55703e342dcSLoic Poulain .of_match_table = qcom_cpu_clk_msm8996_match_table, 55803e342dcSLoic Poulain }, 55903e342dcSLoic Poulain }; 56003e342dcSLoic Poulain module_platform_driver(qcom_cpu_clk_msm8996_driver); 56103e342dcSLoic Poulain 56203e342dcSLoic Poulain MODULE_DESCRIPTION("QCOM MSM8996 CPU Clock Driver"); 56303e342dcSLoic Poulain MODULE_LICENSE("GPL v2"); 564