1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved. */ 3 4 #ifndef __QCOM_CLK_ALPHA_PLL_H__ 5 #define __QCOM_CLK_ALPHA_PLL_H__ 6 7 #include <linux/clk-provider.h> 8 #include "clk-regmap.h" 9 10 /* Alpha PLL types */ 11 enum { 12 CLK_ALPHA_PLL_TYPE_DEFAULT, 13 CLK_ALPHA_PLL_TYPE_HUAYRA, 14 CLK_ALPHA_PLL_TYPE_BRAMMO, 15 CLK_ALPHA_PLL_TYPE_FABIA, 16 CLK_ALPHA_PLL_TYPE_TRION, 17 CLK_ALPHA_PLL_TYPE_LUCID = CLK_ALPHA_PLL_TYPE_TRION, 18 CLK_ALPHA_PLL_TYPE_AGERA, 19 CLK_ALPHA_PLL_TYPE_ZONDA, 20 CLK_ALPHA_PLL_TYPE_MAX, 21 }; 22 23 enum { 24 PLL_OFF_L_VAL, 25 PLL_OFF_CAL_L_VAL, 26 PLL_OFF_ALPHA_VAL, 27 PLL_OFF_ALPHA_VAL_U, 28 PLL_OFF_USER_CTL, 29 PLL_OFF_USER_CTL_U, 30 PLL_OFF_USER_CTL_U1, 31 PLL_OFF_CONFIG_CTL, 32 PLL_OFF_CONFIG_CTL_U, 33 PLL_OFF_CONFIG_CTL_U1, 34 PLL_OFF_TEST_CTL, 35 PLL_OFF_TEST_CTL_U, 36 PLL_OFF_TEST_CTL_U1, 37 PLL_OFF_STATUS, 38 PLL_OFF_OPMODE, 39 PLL_OFF_FRAC, 40 PLL_OFF_CAL_VAL, 41 PLL_OFF_MAX_REGS 42 }; 43 44 extern const u8 clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_MAX][PLL_OFF_MAX_REGS]; 45 46 struct pll_vco { 47 unsigned long min_freq; 48 unsigned long max_freq; 49 u32 val; 50 }; 51 52 #define VCO(a, b, c) { \ 53 .val = a,\ 54 .min_freq = b,\ 55 .max_freq = c,\ 56 } 57 58 /** 59 * struct clk_alpha_pll - phase locked loop (PLL) 60 * @offset: base address of registers 61 * @vco_table: array of VCO settings 62 * @regs: alpha pll register map (see @clk_alpha_pll_regs) 63 * @clkr: regmap clock handle 64 */ 65 struct clk_alpha_pll { 66 u32 offset; 67 const u8 *regs; 68 69 const struct pll_vco *vco_table; 70 size_t num_vco; 71 #define SUPPORTS_OFFLINE_REQ BIT(0) 72 #define SUPPORTS_FSM_MODE BIT(2) 73 #define SUPPORTS_DYNAMIC_UPDATE BIT(3) 74 u8 flags; 75 76 struct clk_regmap clkr; 77 }; 78 79 /** 80 * struct clk_alpha_pll_postdiv - phase locked loop (PLL) post-divider 81 * @offset: base address of registers 82 * @regs: alpha pll register map (see @clk_alpha_pll_regs) 83 * @width: width of post-divider 84 * @post_div_shift: shift to differentiate between odd & even post-divider 85 * @post_div_table: table with PLL odd and even post-divider settings 86 * @num_post_div: Number of PLL post-divider settings 87 * 88 * @clkr: regmap clock handle 89 */ 90 struct clk_alpha_pll_postdiv { 91 u32 offset; 92 u8 width; 93 const u8 *regs; 94 95 struct clk_regmap clkr; 96 int post_div_shift; 97 const struct clk_div_table *post_div_table; 98 size_t num_post_div; 99 }; 100 101 struct alpha_pll_config { 102 u32 l; 103 u32 alpha; 104 u32 alpha_hi; 105 u32 config_ctl_val; 106 u32 config_ctl_hi_val; 107 u32 config_ctl_hi1_val; 108 u32 user_ctl_val; 109 u32 user_ctl_hi_val; 110 u32 user_ctl_hi1_val; 111 u32 test_ctl_val; 112 u32 test_ctl_hi_val; 113 u32 test_ctl_hi1_val; 114 u32 main_output_mask; 115 u32 aux_output_mask; 116 u32 aux2_output_mask; 117 u32 early_output_mask; 118 u32 alpha_en_mask; 119 u32 alpha_mode_mask; 120 u32 pre_div_val; 121 u32 pre_div_mask; 122 u32 post_div_val; 123 u32 post_div_mask; 124 u32 vco_val; 125 u32 vco_mask; 126 }; 127 128 extern const struct clk_ops clk_alpha_pll_ops; 129 extern const struct clk_ops clk_alpha_pll_fixed_ops; 130 extern const struct clk_ops clk_alpha_pll_hwfsm_ops; 131 extern const struct clk_ops clk_alpha_pll_postdiv_ops; 132 extern const struct clk_ops clk_alpha_pll_huayra_ops; 133 extern const struct clk_ops clk_alpha_pll_postdiv_ro_ops; 134 135 extern const struct clk_ops clk_alpha_pll_fabia_ops; 136 extern const struct clk_ops clk_alpha_pll_fixed_fabia_ops; 137 extern const struct clk_ops clk_alpha_pll_postdiv_fabia_ops; 138 139 extern const struct clk_ops clk_alpha_pll_trion_ops; 140 extern const struct clk_ops clk_alpha_pll_fixed_trion_ops; 141 extern const struct clk_ops clk_alpha_pll_postdiv_trion_ops; 142 143 extern const struct clk_ops clk_alpha_pll_lucid_ops; 144 #define clk_alpha_pll_fixed_lucid_ops clk_alpha_pll_fixed_trion_ops 145 extern const struct clk_ops clk_alpha_pll_postdiv_lucid_ops; 146 extern const struct clk_ops clk_alpha_pll_agera_ops; 147 148 extern const struct clk_ops clk_alpha_pll_lucid_5lpe_ops; 149 extern const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops; 150 extern const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops; 151 152 extern const struct clk_ops clk_alpha_pll_zonda_ops; 153 #define clk_alpha_pll_postdiv_zonda_ops clk_alpha_pll_postdiv_fabia_ops 154 155 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 156 const struct alpha_pll_config *config); 157 void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 158 const struct alpha_pll_config *config); 159 void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 160 const struct alpha_pll_config *config); 161 void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 162 const struct alpha_pll_config *config); 163 #define clk_lucid_pll_configure(pll, regmap, config) \ 164 clk_trion_pll_configure(pll, regmap, config) 165 166 void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 167 const struct alpha_pll_config *config); 168 169 170 #endif 171