1 /* 2 * Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #ifndef __QCOM_CLK_ALPHA_PLL_H__ 15 #define __QCOM_CLK_ALPHA_PLL_H__ 16 17 #include <linux/clk-provider.h> 18 #include "clk-regmap.h" 19 20 /* Alpha PLL types */ 21 enum { 22 CLK_ALPHA_PLL_TYPE_DEFAULT, 23 CLK_ALPHA_PLL_TYPE_HUAYRA, 24 CLK_ALPHA_PLL_TYPE_BRAMMO, 25 CLK_ALPHA_PLL_TYPE_FABIA, 26 CLK_ALPHA_PLL_TYPE_MAX, 27 }; 28 29 enum { 30 PLL_OFF_L_VAL, 31 PLL_OFF_ALPHA_VAL, 32 PLL_OFF_ALPHA_VAL_U, 33 PLL_OFF_USER_CTL, 34 PLL_OFF_USER_CTL_U, 35 PLL_OFF_CONFIG_CTL, 36 PLL_OFF_CONFIG_CTL_U, 37 PLL_OFF_TEST_CTL, 38 PLL_OFF_TEST_CTL_U, 39 PLL_OFF_STATUS, 40 PLL_OFF_OPMODE, 41 PLL_OFF_FRAC, 42 PLL_OFF_MAX_REGS 43 }; 44 45 extern const u8 clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_MAX][PLL_OFF_MAX_REGS]; 46 47 struct pll_vco { 48 unsigned long min_freq; 49 unsigned long max_freq; 50 u32 val; 51 }; 52 53 /** 54 * struct clk_alpha_pll - phase locked loop (PLL) 55 * @offset: base address of registers 56 * @vco_table: array of VCO settings 57 * @regs: alpha pll register map (see @clk_alpha_pll_regs) 58 * @clkr: regmap clock handle 59 */ 60 struct clk_alpha_pll { 61 u32 offset; 62 const u8 *regs; 63 64 const struct pll_vco *vco_table; 65 size_t num_vco; 66 #define SUPPORTS_OFFLINE_REQ BIT(0) 67 #define SUPPORTS_FSM_MODE BIT(2) 68 #define SUPPORTS_DYNAMIC_UPDATE BIT(3) 69 u8 flags; 70 71 struct clk_regmap clkr; 72 }; 73 74 /** 75 * struct clk_alpha_pll_postdiv - phase locked loop (PLL) post-divider 76 * @offset: base address of registers 77 * @regs: alpha pll register map (see @clk_alpha_pll_regs) 78 * @width: width of post-divider 79 * @post_div_shift: shift to differentiate between odd & even post-divider 80 * @post_div_table: table with PLL odd and even post-divider settings 81 * @num_post_div: Number of PLL post-divider settings 82 * 83 * @clkr: regmap clock handle 84 */ 85 struct clk_alpha_pll_postdiv { 86 u32 offset; 87 u8 width; 88 const u8 *regs; 89 90 struct clk_regmap clkr; 91 int post_div_shift; 92 const struct clk_div_table *post_div_table; 93 size_t num_post_div; 94 }; 95 96 struct alpha_pll_config { 97 u32 l; 98 u32 alpha; 99 u32 alpha_hi; 100 u32 config_ctl_val; 101 u32 config_ctl_hi_val; 102 u32 main_output_mask; 103 u32 aux_output_mask; 104 u32 aux2_output_mask; 105 u32 early_output_mask; 106 u32 alpha_en_mask; 107 u32 alpha_mode_mask; 108 u32 pre_div_val; 109 u32 pre_div_mask; 110 u32 post_div_val; 111 u32 post_div_mask; 112 u32 vco_val; 113 u32 vco_mask; 114 }; 115 116 extern const struct clk_ops clk_alpha_pll_ops; 117 extern const struct clk_ops clk_alpha_pll_hwfsm_ops; 118 extern const struct clk_ops clk_alpha_pll_postdiv_ops; 119 extern const struct clk_ops clk_alpha_pll_huayra_ops; 120 extern const struct clk_ops clk_alpha_pll_postdiv_ro_ops; 121 122 extern const struct clk_ops clk_alpha_pll_fabia_ops; 123 extern const struct clk_ops clk_alpha_pll_fixed_fabia_ops; 124 extern const struct clk_ops clk_alpha_pll_postdiv_fabia_ops; 125 126 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 127 const struct alpha_pll_config *config); 128 void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 129 const struct alpha_pll_config *config); 130 131 #endif 132