1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved. */ 3 4 #ifndef __QCOM_CLK_ALPHA_PLL_H__ 5 #define __QCOM_CLK_ALPHA_PLL_H__ 6 7 #include <linux/clk-provider.h> 8 #include "clk-regmap.h" 9 10 /* Alpha PLL types */ 11 enum { 12 CLK_ALPHA_PLL_TYPE_DEFAULT, 13 CLK_ALPHA_PLL_TYPE_HUAYRA, 14 CLK_ALPHA_PLL_TYPE_BRAMMO, 15 CLK_ALPHA_PLL_TYPE_FABIA, 16 CLK_ALPHA_PLL_TYPE_MAX, 17 }; 18 19 enum { 20 PLL_OFF_L_VAL, 21 PLL_OFF_ALPHA_VAL, 22 PLL_OFF_ALPHA_VAL_U, 23 PLL_OFF_USER_CTL, 24 PLL_OFF_USER_CTL_U, 25 PLL_OFF_CONFIG_CTL, 26 PLL_OFF_CONFIG_CTL_U, 27 PLL_OFF_TEST_CTL, 28 PLL_OFF_TEST_CTL_U, 29 PLL_OFF_STATUS, 30 PLL_OFF_OPMODE, 31 PLL_OFF_FRAC, 32 PLL_OFF_MAX_REGS 33 }; 34 35 extern const u8 clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_MAX][PLL_OFF_MAX_REGS]; 36 37 struct pll_vco { 38 unsigned long min_freq; 39 unsigned long max_freq; 40 u32 val; 41 }; 42 43 /** 44 * struct clk_alpha_pll - phase locked loop (PLL) 45 * @offset: base address of registers 46 * @vco_table: array of VCO settings 47 * @regs: alpha pll register map (see @clk_alpha_pll_regs) 48 * @clkr: regmap clock handle 49 */ 50 struct clk_alpha_pll { 51 u32 offset; 52 const u8 *regs; 53 54 const struct pll_vco *vco_table; 55 size_t num_vco; 56 #define SUPPORTS_OFFLINE_REQ BIT(0) 57 #define SUPPORTS_FSM_MODE BIT(2) 58 #define SUPPORTS_DYNAMIC_UPDATE BIT(3) 59 u8 flags; 60 61 struct clk_regmap clkr; 62 }; 63 64 /** 65 * struct clk_alpha_pll_postdiv - phase locked loop (PLL) post-divider 66 * @offset: base address of registers 67 * @regs: alpha pll register map (see @clk_alpha_pll_regs) 68 * @width: width of post-divider 69 * @post_div_shift: shift to differentiate between odd & even post-divider 70 * @post_div_table: table with PLL odd and even post-divider settings 71 * @num_post_div: Number of PLL post-divider settings 72 * 73 * @clkr: regmap clock handle 74 */ 75 struct clk_alpha_pll_postdiv { 76 u32 offset; 77 u8 width; 78 const u8 *regs; 79 80 struct clk_regmap clkr; 81 int post_div_shift; 82 const struct clk_div_table *post_div_table; 83 size_t num_post_div; 84 }; 85 86 struct alpha_pll_config { 87 u32 l; 88 u32 alpha; 89 u32 alpha_hi; 90 u32 config_ctl_val; 91 u32 config_ctl_hi_val; 92 u32 main_output_mask; 93 u32 aux_output_mask; 94 u32 aux2_output_mask; 95 u32 early_output_mask; 96 u32 alpha_en_mask; 97 u32 alpha_mode_mask; 98 u32 pre_div_val; 99 u32 pre_div_mask; 100 u32 post_div_val; 101 u32 post_div_mask; 102 u32 vco_val; 103 u32 vco_mask; 104 }; 105 106 extern const struct clk_ops clk_alpha_pll_ops; 107 extern const struct clk_ops clk_alpha_pll_hwfsm_ops; 108 extern const struct clk_ops clk_alpha_pll_postdiv_ops; 109 extern const struct clk_ops clk_alpha_pll_huayra_ops; 110 extern const struct clk_ops clk_alpha_pll_postdiv_ro_ops; 111 112 extern const struct clk_ops clk_alpha_pll_fabia_ops; 113 extern const struct clk_ops clk_alpha_pll_fixed_fabia_ops; 114 extern const struct clk_ops clk_alpha_pll_postdiv_fabia_ops; 115 116 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 117 const struct alpha_pll_config *config); 118 void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 119 const struct alpha_pll_config *config); 120 121 #endif 122