1 /* 2 * Copyright (c) 2015, The Linux Foundation. All rights reserved. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #ifndef __QCOM_CLK_ALPHA_PLL_H__ 15 #define __QCOM_CLK_ALPHA_PLL_H__ 16 17 #include <linux/clk-provider.h> 18 #include "clk-regmap.h" 19 20 /* Alpha PLL types */ 21 enum { 22 CLK_ALPHA_PLL_TYPE_DEFAULT, 23 CLK_ALPHA_PLL_TYPE_MAX, 24 }; 25 26 enum { 27 PLL_OFF_L_VAL, 28 PLL_OFF_ALPHA_VAL, 29 PLL_OFF_ALPHA_VAL_U, 30 PLL_OFF_USER_CTL, 31 PLL_OFF_USER_CTL_U, 32 PLL_OFF_CONFIG_CTL, 33 PLL_OFF_CONFIG_CTL_U, 34 PLL_OFF_TEST_CTL, 35 PLL_OFF_TEST_CTL_U, 36 PLL_OFF_STATUS, 37 PLL_OFF_MAX_REGS 38 }; 39 40 extern const u8 clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_MAX][PLL_OFF_MAX_REGS]; 41 42 struct pll_vco { 43 unsigned long min_freq; 44 unsigned long max_freq; 45 u32 val; 46 }; 47 48 /** 49 * struct clk_alpha_pll - phase locked loop (PLL) 50 * @offset: base address of registers 51 * @vco_table: array of VCO settings 52 * @regs: alpha pll register map (see @clk_alpha_pll_regs) 53 * @clkr: regmap clock handle 54 */ 55 struct clk_alpha_pll { 56 u32 offset; 57 const u8 *regs; 58 59 const struct pll_vco *vco_table; 60 size_t num_vco; 61 #define SUPPORTS_OFFLINE_REQ BIT(0) 62 #define SUPPORTS_16BIT_ALPHA BIT(1) 63 #define SUPPORTS_FSM_MODE BIT(2) 64 u8 flags; 65 66 struct clk_regmap clkr; 67 }; 68 69 /** 70 * struct clk_alpha_pll_postdiv - phase locked loop (PLL) post-divider 71 * @offset: base address of registers 72 * @regs: alpha pll register map (see @clk_alpha_pll_regs) 73 * @width: width of post-divider 74 * @clkr: regmap clock handle 75 */ 76 struct clk_alpha_pll_postdiv { 77 u32 offset; 78 u8 width; 79 const u8 *regs; 80 81 struct clk_regmap clkr; 82 }; 83 84 struct alpha_pll_config { 85 u32 l; 86 u32 alpha; 87 u32 config_ctl_val; 88 u32 config_ctl_hi_val; 89 u32 main_output_mask; 90 u32 aux_output_mask; 91 u32 aux2_output_mask; 92 u32 early_output_mask; 93 u32 pre_div_val; 94 u32 pre_div_mask; 95 u32 post_div_val; 96 u32 post_div_mask; 97 u32 vco_val; 98 u32 vco_mask; 99 }; 100 101 extern const struct clk_ops clk_alpha_pll_ops; 102 extern const struct clk_ops clk_alpha_pll_hwfsm_ops; 103 extern const struct clk_ops clk_alpha_pll_postdiv_ops; 104 105 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 106 const struct alpha_pll_config *config); 107 108 #endif 109