1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #include <linux/kernel.h> 8 #include <linux/export.h> 9 #include <linux/clk-provider.h> 10 #include <linux/regmap.h> 11 #include <linux/delay.h> 12 13 #include "clk-alpha-pll.h" 14 #include "common.h" 15 16 #define PLL_MODE(p) ((p)->offset + 0x0) 17 # define PLL_OUTCTRL BIT(0) 18 # define PLL_BYPASSNL BIT(1) 19 # define PLL_RESET_N BIT(2) 20 # define PLL_OFFLINE_REQ BIT(7) 21 # define PLL_LOCK_COUNT_SHIFT 8 22 # define PLL_LOCK_COUNT_MASK 0x3f 23 # define PLL_BIAS_COUNT_SHIFT 14 24 # define PLL_BIAS_COUNT_MASK 0x3f 25 # define PLL_VOTE_FSM_ENA BIT(20) 26 # define PLL_FSM_ENA BIT(20) 27 # define PLL_VOTE_FSM_RESET BIT(21) 28 # define PLL_UPDATE BIT(22) 29 # define PLL_UPDATE_BYPASS BIT(23) 30 # define PLL_FSM_LEGACY_MODE BIT(24) 31 # define PLL_OFFLINE_ACK BIT(28) 32 # define ALPHA_PLL_ACK_LATCH BIT(29) 33 # define PLL_ACTIVE_FLAG BIT(30) 34 # define PLL_LOCK_DET BIT(31) 35 36 #define PLL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_L_VAL]) 37 #define PLL_CAL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_CAL_L_VAL]) 38 #define PLL_ALPHA_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL]) 39 #define PLL_ALPHA_VAL_U(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL_U]) 40 41 #define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL]) 42 # define PLL_POST_DIV_SHIFT 8 43 # define PLL_POST_DIV_MASK(p) GENMASK((p)->width, 0) 44 # define PLL_ALPHA_EN BIT(24) 45 # define PLL_ALPHA_MODE BIT(25) 46 # define PLL_VCO_SHIFT 20 47 # define PLL_VCO_MASK 0x3 48 49 #define PLL_USER_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U]) 50 #define PLL_USER_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U1]) 51 52 #define PLL_CONFIG_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL]) 53 #define PLL_CONFIG_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U]) 54 #define PLL_CONFIG_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U1]) 55 #define PLL_TEST_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL]) 56 #define PLL_TEST_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U]) 57 #define PLL_TEST_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U1]) 58 #define PLL_STATUS(p) ((p)->offset + (p)->regs[PLL_OFF_STATUS]) 59 #define PLL_OPMODE(p) ((p)->offset + (p)->regs[PLL_OFF_OPMODE]) 60 #define PLL_FRAC(p) ((p)->offset + (p)->regs[PLL_OFF_FRAC]) 61 62 const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { 63 [CLK_ALPHA_PLL_TYPE_DEFAULT] = { 64 [PLL_OFF_L_VAL] = 0x04, 65 [PLL_OFF_ALPHA_VAL] = 0x08, 66 [PLL_OFF_ALPHA_VAL_U] = 0x0c, 67 [PLL_OFF_USER_CTL] = 0x10, 68 [PLL_OFF_USER_CTL_U] = 0x14, 69 [PLL_OFF_CONFIG_CTL] = 0x18, 70 [PLL_OFF_TEST_CTL] = 0x1c, 71 [PLL_OFF_TEST_CTL_U] = 0x20, 72 [PLL_OFF_STATUS] = 0x24, 73 }, 74 [CLK_ALPHA_PLL_TYPE_HUAYRA] = { 75 [PLL_OFF_L_VAL] = 0x04, 76 [PLL_OFF_ALPHA_VAL] = 0x08, 77 [PLL_OFF_USER_CTL] = 0x10, 78 [PLL_OFF_CONFIG_CTL] = 0x14, 79 [PLL_OFF_CONFIG_CTL_U] = 0x18, 80 [PLL_OFF_TEST_CTL] = 0x1c, 81 [PLL_OFF_TEST_CTL_U] = 0x20, 82 [PLL_OFF_STATUS] = 0x24, 83 }, 84 [CLK_ALPHA_PLL_TYPE_BRAMMO] = { 85 [PLL_OFF_L_VAL] = 0x04, 86 [PLL_OFF_ALPHA_VAL] = 0x08, 87 [PLL_OFF_ALPHA_VAL_U] = 0x0c, 88 [PLL_OFF_USER_CTL] = 0x10, 89 [PLL_OFF_CONFIG_CTL] = 0x18, 90 [PLL_OFF_TEST_CTL] = 0x1c, 91 [PLL_OFF_STATUS] = 0x24, 92 }, 93 [CLK_ALPHA_PLL_TYPE_FABIA] = { 94 [PLL_OFF_L_VAL] = 0x04, 95 [PLL_OFF_USER_CTL] = 0x0c, 96 [PLL_OFF_USER_CTL_U] = 0x10, 97 [PLL_OFF_CONFIG_CTL] = 0x14, 98 [PLL_OFF_CONFIG_CTL_U] = 0x18, 99 [PLL_OFF_TEST_CTL] = 0x1c, 100 [PLL_OFF_TEST_CTL_U] = 0x20, 101 [PLL_OFF_STATUS] = 0x24, 102 [PLL_OFF_OPMODE] = 0x2c, 103 [PLL_OFF_FRAC] = 0x38, 104 }, 105 [CLK_ALPHA_PLL_TYPE_TRION] = { 106 [PLL_OFF_L_VAL] = 0x04, 107 [PLL_OFF_CAL_L_VAL] = 0x08, 108 [PLL_OFF_USER_CTL] = 0x0c, 109 [PLL_OFF_USER_CTL_U] = 0x10, 110 [PLL_OFF_USER_CTL_U1] = 0x14, 111 [PLL_OFF_CONFIG_CTL] = 0x18, 112 [PLL_OFF_CONFIG_CTL_U] = 0x1c, 113 [PLL_OFF_CONFIG_CTL_U1] = 0x20, 114 [PLL_OFF_TEST_CTL] = 0x24, 115 [PLL_OFF_TEST_CTL_U] = 0x28, 116 [PLL_OFF_TEST_CTL_U1] = 0x2c, 117 [PLL_OFF_STATUS] = 0x30, 118 [PLL_OFF_OPMODE] = 0x38, 119 [PLL_OFF_ALPHA_VAL] = 0x40, 120 }, 121 [CLK_ALPHA_PLL_TYPE_AGERA] = { 122 [PLL_OFF_L_VAL] = 0x04, 123 [PLL_OFF_ALPHA_VAL] = 0x08, 124 [PLL_OFF_USER_CTL] = 0x0c, 125 [PLL_OFF_CONFIG_CTL] = 0x10, 126 [PLL_OFF_CONFIG_CTL_U] = 0x14, 127 [PLL_OFF_TEST_CTL] = 0x18, 128 [PLL_OFF_TEST_CTL_U] = 0x1c, 129 [PLL_OFF_STATUS] = 0x2c, 130 }, 131 [CLK_ALPHA_PLL_TYPE_ZONDA] = { 132 [PLL_OFF_L_VAL] = 0x04, 133 [PLL_OFF_ALPHA_VAL] = 0x08, 134 [PLL_OFF_USER_CTL] = 0x0c, 135 [PLL_OFF_CONFIG_CTL] = 0x10, 136 [PLL_OFF_CONFIG_CTL_U] = 0x14, 137 [PLL_OFF_CONFIG_CTL_U1] = 0x18, 138 [PLL_OFF_TEST_CTL] = 0x1c, 139 [PLL_OFF_TEST_CTL_U] = 0x20, 140 [PLL_OFF_TEST_CTL_U1] = 0x24, 141 [PLL_OFF_OPMODE] = 0x28, 142 [PLL_OFF_STATUS] = 0x38, 143 }, 144 [CLK_ALPHA_PLL_TYPE_LUCID_EVO] = { 145 [PLL_OFF_OPMODE] = 0x04, 146 [PLL_OFF_STATUS] = 0x0c, 147 [PLL_OFF_L_VAL] = 0x10, 148 [PLL_OFF_ALPHA_VAL] = 0x14, 149 [PLL_OFF_USER_CTL] = 0x18, 150 [PLL_OFF_USER_CTL_U] = 0x1c, 151 [PLL_OFF_CONFIG_CTL] = 0x20, 152 [PLL_OFF_CONFIG_CTL_U] = 0x24, 153 [PLL_OFF_CONFIG_CTL_U1] = 0x28, 154 [PLL_OFF_TEST_CTL] = 0x2c, 155 [PLL_OFF_TEST_CTL_U] = 0x30, 156 [PLL_OFF_TEST_CTL_U1] = 0x34, 157 }, 158 [CLK_ALPHA_PLL_TYPE_LUCID_OLE] = { 159 [PLL_OFF_OPMODE] = 0x04, 160 [PLL_OFF_STATE] = 0x08, 161 [PLL_OFF_STATUS] = 0x0c, 162 [PLL_OFF_L_VAL] = 0x10, 163 [PLL_OFF_ALPHA_VAL] = 0x14, 164 [PLL_OFF_USER_CTL] = 0x18, 165 [PLL_OFF_USER_CTL_U] = 0x1c, 166 [PLL_OFF_CONFIG_CTL] = 0x20, 167 [PLL_OFF_CONFIG_CTL_U] = 0x24, 168 [PLL_OFF_CONFIG_CTL_U1] = 0x28, 169 [PLL_OFF_TEST_CTL] = 0x2c, 170 [PLL_OFF_TEST_CTL_U] = 0x30, 171 [PLL_OFF_TEST_CTL_U1] = 0x34, 172 [PLL_OFF_TEST_CTL_U2] = 0x38, 173 }, 174 [CLK_ALPHA_PLL_TYPE_RIVIAN_EVO] = { 175 [PLL_OFF_OPMODE] = 0x04, 176 [PLL_OFF_STATUS] = 0x0c, 177 [PLL_OFF_L_VAL] = 0x10, 178 [PLL_OFF_USER_CTL] = 0x14, 179 [PLL_OFF_USER_CTL_U] = 0x18, 180 [PLL_OFF_CONFIG_CTL] = 0x1c, 181 [PLL_OFF_CONFIG_CTL_U] = 0x20, 182 [PLL_OFF_CONFIG_CTL_U1] = 0x24, 183 [PLL_OFF_TEST_CTL] = 0x28, 184 [PLL_OFF_TEST_CTL_U] = 0x2c, 185 }, 186 [CLK_ALPHA_PLL_TYPE_DEFAULT_EVO] = { 187 [PLL_OFF_L_VAL] = 0x04, 188 [PLL_OFF_ALPHA_VAL] = 0x08, 189 [PLL_OFF_ALPHA_VAL_U] = 0x0c, 190 [PLL_OFF_TEST_CTL] = 0x10, 191 [PLL_OFF_TEST_CTL_U] = 0x14, 192 [PLL_OFF_USER_CTL] = 0x18, 193 [PLL_OFF_USER_CTL_U] = 0x1c, 194 [PLL_OFF_CONFIG_CTL] = 0x20, 195 [PLL_OFF_STATUS] = 0x24, 196 }, 197 [CLK_ALPHA_PLL_TYPE_BRAMMO_EVO] = { 198 [PLL_OFF_L_VAL] = 0x04, 199 [PLL_OFF_ALPHA_VAL] = 0x08, 200 [PLL_OFF_ALPHA_VAL_U] = 0x0c, 201 [PLL_OFF_TEST_CTL] = 0x10, 202 [PLL_OFF_TEST_CTL_U] = 0x14, 203 [PLL_OFF_USER_CTL] = 0x18, 204 [PLL_OFF_CONFIG_CTL] = 0x1C, 205 [PLL_OFF_STATUS] = 0x20, 206 }, 207 }; 208 EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); 209 210 /* 211 * Even though 40 bits are present, use only 32 for ease of calculation. 212 */ 213 #define ALPHA_REG_BITWIDTH 40 214 #define ALPHA_REG_16BIT_WIDTH 16 215 #define ALPHA_BITWIDTH 32U 216 #define ALPHA_SHIFT(w) min(w, ALPHA_BITWIDTH) 217 218 #define PLL_HUAYRA_M_WIDTH 8 219 #define PLL_HUAYRA_M_SHIFT 8 220 #define PLL_HUAYRA_M_MASK 0xff 221 #define PLL_HUAYRA_N_SHIFT 0 222 #define PLL_HUAYRA_N_MASK 0xff 223 #define PLL_HUAYRA_ALPHA_WIDTH 16 224 225 #define PLL_STANDBY 0x0 226 #define PLL_RUN 0x1 227 #define PLL_OUT_MASK 0x7 228 #define PLL_RATE_MARGIN 500 229 230 /* TRION PLL specific settings and offsets */ 231 #define TRION_PLL_CAL_VAL 0x44 232 #define TRION_PCAL_DONE BIT(26) 233 234 /* LUCID PLL specific settings and offsets */ 235 #define LUCID_PCAL_DONE BIT(27) 236 237 /* LUCID 5LPE PLL specific settings and offsets */ 238 #define LUCID_5LPE_PCAL_DONE BIT(11) 239 #define LUCID_5LPE_ALPHA_PLL_ACK_LATCH BIT(13) 240 #define LUCID_5LPE_PLL_LATCH_INPUT BIT(14) 241 #define LUCID_5LPE_ENABLE_VOTE_RUN BIT(21) 242 243 /* LUCID EVO PLL specific settings and offsets */ 244 #define LUCID_EVO_PCAL_NOT_DONE BIT(8) 245 #define LUCID_EVO_ENABLE_VOTE_RUN BIT(25) 246 #define LUCID_EVO_PLL_L_VAL_MASK GENMASK(15, 0) 247 #define LUCID_EVO_PLL_CAL_L_VAL_SHIFT 16 248 249 /* ZONDA PLL specific */ 250 #define ZONDA_PLL_OUT_MASK 0xf 251 #define ZONDA_STAY_IN_CFA BIT(16) 252 #define ZONDA_PLL_FREQ_LOCK_DET BIT(29) 253 254 #define pll_alpha_width(p) \ 255 ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \ 256 ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH) 257 258 #define pll_has_64bit_config(p) ((PLL_CONFIG_CTL_U(p) - PLL_CONFIG_CTL(p)) == 4) 259 260 #define to_clk_alpha_pll(_hw) container_of(to_clk_regmap(_hw), \ 261 struct clk_alpha_pll, clkr) 262 263 #define to_clk_alpha_pll_postdiv(_hw) container_of(to_clk_regmap(_hw), \ 264 struct clk_alpha_pll_postdiv, clkr) 265 266 static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse, 267 const char *action) 268 { 269 u32 val; 270 int count; 271 int ret; 272 const char *name = clk_hw_get_name(&pll->clkr.hw); 273 274 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 275 if (ret) 276 return ret; 277 278 for (count = 200; count > 0; count--) { 279 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 280 if (ret) 281 return ret; 282 if (inverse && !(val & mask)) 283 return 0; 284 else if ((val & mask) == mask) 285 return 0; 286 287 udelay(1); 288 } 289 290 WARN(1, "%s failed to %s!\n", name, action); 291 return -ETIMEDOUT; 292 } 293 294 #define wait_for_pll_enable_active(pll) \ 295 wait_for_pll(pll, PLL_ACTIVE_FLAG, 0, "enable") 296 297 #define wait_for_pll_enable_lock(pll) \ 298 wait_for_pll(pll, PLL_LOCK_DET, 0, "enable") 299 300 #define wait_for_zonda_pll_freq_lock(pll) \ 301 wait_for_pll(pll, ZONDA_PLL_FREQ_LOCK_DET, 0, "freq enable") 302 303 #define wait_for_pll_disable(pll) \ 304 wait_for_pll(pll, PLL_ACTIVE_FLAG, 1, "disable") 305 306 #define wait_for_pll_offline(pll) \ 307 wait_for_pll(pll, PLL_OFFLINE_ACK, 0, "offline") 308 309 #define wait_for_pll_update(pll) \ 310 wait_for_pll(pll, PLL_UPDATE, 1, "update") 311 312 #define wait_for_pll_update_ack_set(pll) \ 313 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 0, "update_ack_set") 314 315 #define wait_for_pll_update_ack_clear(pll) \ 316 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 1, "update_ack_clear") 317 318 static void clk_alpha_pll_write_config(struct regmap *regmap, unsigned int reg, 319 unsigned int val) 320 { 321 if (val) 322 regmap_write(regmap, reg, val); 323 } 324 325 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 326 const struct alpha_pll_config *config) 327 { 328 u32 val, mask; 329 330 regmap_write(regmap, PLL_L_VAL(pll), config->l); 331 regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha); 332 regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 333 334 if (pll_has_64bit_config(pll)) 335 regmap_write(regmap, PLL_CONFIG_CTL_U(pll), 336 config->config_ctl_hi_val); 337 338 if (pll_alpha_width(pll) > 32) 339 regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi); 340 341 val = config->main_output_mask; 342 val |= config->aux_output_mask; 343 val |= config->aux2_output_mask; 344 val |= config->early_output_mask; 345 val |= config->pre_div_val; 346 val |= config->post_div_val; 347 val |= config->vco_val; 348 val |= config->alpha_en_mask; 349 val |= config->alpha_mode_mask; 350 351 mask = config->main_output_mask; 352 mask |= config->aux_output_mask; 353 mask |= config->aux2_output_mask; 354 mask |= config->early_output_mask; 355 mask |= config->pre_div_mask; 356 mask |= config->post_div_mask; 357 mask |= config->vco_mask; 358 359 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); 360 361 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), 362 config->test_ctl_val); 363 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), 364 config->test_ctl_hi_val); 365 366 if (pll->flags & SUPPORTS_FSM_MODE) 367 qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0); 368 } 369 EXPORT_SYMBOL_GPL(clk_alpha_pll_configure); 370 371 static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw) 372 { 373 int ret; 374 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 375 u32 val; 376 377 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 378 if (ret) 379 return ret; 380 381 val |= PLL_FSM_ENA; 382 383 if (pll->flags & SUPPORTS_OFFLINE_REQ) 384 val &= ~PLL_OFFLINE_REQ; 385 386 ret = regmap_write(pll->clkr.regmap, PLL_MODE(pll), val); 387 if (ret) 388 return ret; 389 390 /* Make sure enable request goes through before waiting for update */ 391 mb(); 392 393 return wait_for_pll_enable_active(pll); 394 } 395 396 static void clk_alpha_pll_hwfsm_disable(struct clk_hw *hw) 397 { 398 int ret; 399 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 400 u32 val; 401 402 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 403 if (ret) 404 return; 405 406 if (pll->flags & SUPPORTS_OFFLINE_REQ) { 407 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 408 PLL_OFFLINE_REQ, PLL_OFFLINE_REQ); 409 if (ret) 410 return; 411 412 ret = wait_for_pll_offline(pll); 413 if (ret) 414 return; 415 } 416 417 /* Disable hwfsm */ 418 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 419 PLL_FSM_ENA, 0); 420 if (ret) 421 return; 422 423 wait_for_pll_disable(pll); 424 } 425 426 static int pll_is_enabled(struct clk_hw *hw, u32 mask) 427 { 428 int ret; 429 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 430 u32 val; 431 432 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 433 if (ret) 434 return ret; 435 436 return !!(val & mask); 437 } 438 439 static int clk_alpha_pll_hwfsm_is_enabled(struct clk_hw *hw) 440 { 441 return pll_is_enabled(hw, PLL_ACTIVE_FLAG); 442 } 443 444 static int clk_alpha_pll_is_enabled(struct clk_hw *hw) 445 { 446 return pll_is_enabled(hw, PLL_LOCK_DET); 447 } 448 449 static int clk_alpha_pll_enable(struct clk_hw *hw) 450 { 451 int ret; 452 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 453 u32 val, mask; 454 455 mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL; 456 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 457 if (ret) 458 return ret; 459 460 /* If in FSM mode, just vote for it */ 461 if (val & PLL_VOTE_FSM_ENA) { 462 ret = clk_enable_regmap(hw); 463 if (ret) 464 return ret; 465 return wait_for_pll_enable_active(pll); 466 } 467 468 /* Skip if already enabled */ 469 if ((val & mask) == mask) 470 return 0; 471 472 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 473 PLL_BYPASSNL, PLL_BYPASSNL); 474 if (ret) 475 return ret; 476 477 /* 478 * H/W requires a 5us delay between disabling the bypass and 479 * de-asserting the reset. 480 */ 481 mb(); 482 udelay(5); 483 484 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 485 PLL_RESET_N, PLL_RESET_N); 486 if (ret) 487 return ret; 488 489 ret = wait_for_pll_enable_lock(pll); 490 if (ret) 491 return ret; 492 493 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 494 PLL_OUTCTRL, PLL_OUTCTRL); 495 496 /* Ensure that the write above goes through before returning. */ 497 mb(); 498 return ret; 499 } 500 501 static void clk_alpha_pll_disable(struct clk_hw *hw) 502 { 503 int ret; 504 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 505 u32 val, mask; 506 507 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 508 if (ret) 509 return; 510 511 /* If in FSM mode, just unvote it */ 512 if (val & PLL_VOTE_FSM_ENA) { 513 clk_disable_regmap(hw); 514 return; 515 } 516 517 mask = PLL_OUTCTRL; 518 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0); 519 520 /* Delay of 2 output clock ticks required until output is disabled */ 521 mb(); 522 udelay(1); 523 524 mask = PLL_RESET_N | PLL_BYPASSNL; 525 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0); 526 } 527 528 static unsigned long 529 alpha_pll_calc_rate(u64 prate, u32 l, u32 a, u32 alpha_width) 530 { 531 return (prate * l) + ((prate * a) >> ALPHA_SHIFT(alpha_width)); 532 } 533 534 static unsigned long 535 alpha_pll_round_rate(unsigned long rate, unsigned long prate, u32 *l, u64 *a, 536 u32 alpha_width) 537 { 538 u64 remainder; 539 u64 quotient; 540 541 quotient = rate; 542 remainder = do_div(quotient, prate); 543 *l = quotient; 544 545 if (!remainder) { 546 *a = 0; 547 return rate; 548 } 549 550 /* Upper ALPHA_BITWIDTH bits of Alpha */ 551 quotient = remainder << ALPHA_SHIFT(alpha_width); 552 553 remainder = do_div(quotient, prate); 554 555 if (remainder) 556 quotient++; 557 558 *a = quotient; 559 return alpha_pll_calc_rate(prate, *l, *a, alpha_width); 560 } 561 562 static const struct pll_vco * 563 alpha_pll_find_vco(const struct clk_alpha_pll *pll, unsigned long rate) 564 { 565 const struct pll_vco *v = pll->vco_table; 566 const struct pll_vco *end = v + pll->num_vco; 567 568 for (; v < end; v++) 569 if (rate >= v->min_freq && rate <= v->max_freq) 570 return v; 571 572 return NULL; 573 } 574 575 static unsigned long 576 clk_alpha_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 577 { 578 u32 l, low, high, ctl; 579 u64 a = 0, prate = parent_rate; 580 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 581 u32 alpha_width = pll_alpha_width(pll); 582 583 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); 584 585 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); 586 if (ctl & PLL_ALPHA_EN) { 587 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &low); 588 if (alpha_width > 32) { 589 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), 590 &high); 591 a = (u64)high << 32 | low; 592 } else { 593 a = low & GENMASK(alpha_width - 1, 0); 594 } 595 596 if (alpha_width > ALPHA_BITWIDTH) 597 a >>= alpha_width - ALPHA_BITWIDTH; 598 } 599 600 return alpha_pll_calc_rate(prate, l, a, alpha_width); 601 } 602 603 604 static int __clk_alpha_pll_update_latch(struct clk_alpha_pll *pll) 605 { 606 int ret; 607 u32 mode; 608 609 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &mode); 610 611 /* Latch the input to the PLL */ 612 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 613 PLL_UPDATE); 614 615 /* Wait for 2 reference cycle before checking ACK bit */ 616 udelay(1); 617 618 /* 619 * PLL will latch the new L, Alpha and freq control word. 620 * PLL will respond by raising PLL_ACK_LATCH output when new programming 621 * has been latched in and PLL is being updated. When 622 * UPDATE_LOGIC_BYPASS bit is not set, PLL_UPDATE will be cleared 623 * automatically by hardware when PLL_ACK_LATCH is asserted by PLL. 624 */ 625 if (mode & PLL_UPDATE_BYPASS) { 626 ret = wait_for_pll_update_ack_set(pll); 627 if (ret) 628 return ret; 629 630 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 0); 631 } else { 632 ret = wait_for_pll_update(pll); 633 if (ret) 634 return ret; 635 } 636 637 ret = wait_for_pll_update_ack_clear(pll); 638 if (ret) 639 return ret; 640 641 /* Wait for PLL output to stabilize */ 642 udelay(10); 643 644 return 0; 645 } 646 647 static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll, 648 int (*is_enabled)(struct clk_hw *)) 649 { 650 if (!is_enabled(&pll->clkr.hw) || 651 !(pll->flags & SUPPORTS_DYNAMIC_UPDATE)) 652 return 0; 653 654 return __clk_alpha_pll_update_latch(pll); 655 } 656 657 static int __clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate, 658 unsigned long prate, 659 int (*is_enabled)(struct clk_hw *)) 660 { 661 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 662 const struct pll_vco *vco; 663 u32 l, alpha_width = pll_alpha_width(pll); 664 u64 a; 665 666 rate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 667 vco = alpha_pll_find_vco(pll, rate); 668 if (pll->vco_table && !vco) { 669 pr_err("%s: alpha pll not in a valid vco range\n", 670 clk_hw_get_name(hw)); 671 return -EINVAL; 672 } 673 674 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 675 676 if (alpha_width > ALPHA_BITWIDTH) 677 a <<= alpha_width - ALPHA_BITWIDTH; 678 679 if (alpha_width > 32) 680 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), a >> 32); 681 682 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 683 684 if (vco) { 685 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 686 PLL_VCO_MASK << PLL_VCO_SHIFT, 687 vco->val << PLL_VCO_SHIFT); 688 } 689 690 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 691 PLL_ALPHA_EN, PLL_ALPHA_EN); 692 693 return clk_alpha_pll_update_latch(pll, is_enabled); 694 } 695 696 static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate, 697 unsigned long prate) 698 { 699 return __clk_alpha_pll_set_rate(hw, rate, prate, 700 clk_alpha_pll_is_enabled); 701 } 702 703 static int clk_alpha_pll_hwfsm_set_rate(struct clk_hw *hw, unsigned long rate, 704 unsigned long prate) 705 { 706 return __clk_alpha_pll_set_rate(hw, rate, prate, 707 clk_alpha_pll_hwfsm_is_enabled); 708 } 709 710 static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate, 711 unsigned long *prate) 712 { 713 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 714 u32 l, alpha_width = pll_alpha_width(pll); 715 u64 a; 716 unsigned long min_freq, max_freq; 717 718 rate = alpha_pll_round_rate(rate, *prate, &l, &a, alpha_width); 719 if (!pll->vco_table || alpha_pll_find_vco(pll, rate)) 720 return rate; 721 722 min_freq = pll->vco_table[0].min_freq; 723 max_freq = pll->vco_table[pll->num_vco - 1].max_freq; 724 725 return clamp(rate, min_freq, max_freq); 726 } 727 728 static unsigned long 729 alpha_huayra_pll_calc_rate(u64 prate, u32 l, u32 a) 730 { 731 /* 732 * a contains 16 bit alpha_val in two’s complement number in the range 733 * of [-0.5, 0.5). 734 */ 735 if (a >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1)) 736 l -= 1; 737 738 return (prate * l) + (prate * a >> PLL_HUAYRA_ALPHA_WIDTH); 739 } 740 741 static unsigned long 742 alpha_huayra_pll_round_rate(unsigned long rate, unsigned long prate, 743 u32 *l, u32 *a) 744 { 745 u64 remainder; 746 u64 quotient; 747 748 quotient = rate; 749 remainder = do_div(quotient, prate); 750 *l = quotient; 751 752 if (!remainder) { 753 *a = 0; 754 return rate; 755 } 756 757 quotient = remainder << PLL_HUAYRA_ALPHA_WIDTH; 758 remainder = do_div(quotient, prate); 759 760 if (remainder) 761 quotient++; 762 763 /* 764 * alpha_val should be in two’s complement number in the range 765 * of [-0.5, 0.5) so if quotient >= 0.5 then increment the l value 766 * since alpha value will be subtracted in this case. 767 */ 768 if (quotient >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1)) 769 *l += 1; 770 771 *a = quotient; 772 return alpha_huayra_pll_calc_rate(prate, *l, *a); 773 } 774 775 static unsigned long 776 alpha_pll_huayra_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 777 { 778 u64 rate = parent_rate, tmp; 779 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 780 u32 l, alpha = 0, ctl, alpha_m, alpha_n; 781 782 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); 783 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); 784 785 if (ctl & PLL_ALPHA_EN) { 786 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &alpha); 787 /* 788 * Depending upon alpha_mode, it can be treated as M/N value or 789 * as a two’s complement number. When alpha_mode=1, 790 * pll_alpha_val<15:8>=M and pll_apla_val<7:0>=N 791 * 792 * Fout=FIN*(L+(M/N)) 793 * 794 * M is a signed number (-128 to 127) and N is unsigned 795 * (0 to 255). M/N has to be within +/-0.5. 796 * 797 * When alpha_mode=0, it is a two’s complement number in the 798 * range [-0.5, 0.5). 799 * 800 * Fout=FIN*(L+(alpha_val)/2^16) 801 * 802 * where alpha_val is two’s complement number. 803 */ 804 if (!(ctl & PLL_ALPHA_MODE)) 805 return alpha_huayra_pll_calc_rate(rate, l, alpha); 806 807 alpha_m = alpha >> PLL_HUAYRA_M_SHIFT & PLL_HUAYRA_M_MASK; 808 alpha_n = alpha >> PLL_HUAYRA_N_SHIFT & PLL_HUAYRA_N_MASK; 809 810 rate *= l; 811 tmp = parent_rate; 812 if (alpha_m >= BIT(PLL_HUAYRA_M_WIDTH - 1)) { 813 alpha_m = BIT(PLL_HUAYRA_M_WIDTH) - alpha_m; 814 tmp *= alpha_m; 815 do_div(tmp, alpha_n); 816 rate -= tmp; 817 } else { 818 tmp *= alpha_m; 819 do_div(tmp, alpha_n); 820 rate += tmp; 821 } 822 823 return rate; 824 } 825 826 return alpha_huayra_pll_calc_rate(rate, l, alpha); 827 } 828 829 static int alpha_pll_huayra_set_rate(struct clk_hw *hw, unsigned long rate, 830 unsigned long prate) 831 { 832 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 833 u32 l, a, ctl, cur_alpha = 0; 834 835 rate = alpha_huayra_pll_round_rate(rate, prate, &l, &a); 836 837 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); 838 839 if (ctl & PLL_ALPHA_EN) 840 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &cur_alpha); 841 842 /* 843 * Huayra PLL supports PLL dynamic programming. User can change L_VAL, 844 * without having to go through the power on sequence. 845 */ 846 if (clk_alpha_pll_is_enabled(hw)) { 847 if (cur_alpha != a) { 848 pr_err("%s: clock needs to be gated\n", 849 clk_hw_get_name(hw)); 850 return -EBUSY; 851 } 852 853 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 854 /* Ensure that the write above goes to detect L val change. */ 855 mb(); 856 return wait_for_pll_enable_lock(pll); 857 } 858 859 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 860 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 861 862 if (a == 0) 863 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 864 PLL_ALPHA_EN, 0x0); 865 else 866 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 867 PLL_ALPHA_EN | PLL_ALPHA_MODE, PLL_ALPHA_EN); 868 869 return 0; 870 } 871 872 static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long rate, 873 unsigned long *prate) 874 { 875 u32 l, a; 876 877 return alpha_huayra_pll_round_rate(rate, *prate, &l, &a); 878 } 879 880 static int trion_pll_is_enabled(struct clk_alpha_pll *pll, 881 struct regmap *regmap) 882 { 883 u32 mode_val, opmode_val; 884 int ret; 885 886 ret = regmap_read(regmap, PLL_MODE(pll), &mode_val); 887 ret |= regmap_read(regmap, PLL_OPMODE(pll), &opmode_val); 888 if (ret) 889 return 0; 890 891 return ((opmode_val & PLL_RUN) && (mode_val & PLL_OUTCTRL)); 892 } 893 894 static int clk_trion_pll_is_enabled(struct clk_hw *hw) 895 { 896 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 897 898 return trion_pll_is_enabled(pll, pll->clkr.regmap); 899 } 900 901 static int clk_trion_pll_enable(struct clk_hw *hw) 902 { 903 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 904 struct regmap *regmap = pll->clkr.regmap; 905 u32 val; 906 int ret; 907 908 ret = regmap_read(regmap, PLL_MODE(pll), &val); 909 if (ret) 910 return ret; 911 912 /* If in FSM mode, just vote for it */ 913 if (val & PLL_VOTE_FSM_ENA) { 914 ret = clk_enable_regmap(hw); 915 if (ret) 916 return ret; 917 return wait_for_pll_enable_active(pll); 918 } 919 920 /* Set operation mode to RUN */ 921 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); 922 923 ret = wait_for_pll_enable_lock(pll); 924 if (ret) 925 return ret; 926 927 /* Enable the PLL outputs */ 928 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), 929 PLL_OUT_MASK, PLL_OUT_MASK); 930 if (ret) 931 return ret; 932 933 /* Enable the global PLL outputs */ 934 return regmap_update_bits(regmap, PLL_MODE(pll), 935 PLL_OUTCTRL, PLL_OUTCTRL); 936 } 937 938 static void clk_trion_pll_disable(struct clk_hw *hw) 939 { 940 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 941 struct regmap *regmap = pll->clkr.regmap; 942 u32 val; 943 int ret; 944 945 ret = regmap_read(regmap, PLL_MODE(pll), &val); 946 if (ret) 947 return; 948 949 /* If in FSM mode, just unvote it */ 950 if (val & PLL_VOTE_FSM_ENA) { 951 clk_disable_regmap(hw); 952 return; 953 } 954 955 /* Disable the global PLL output */ 956 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 957 if (ret) 958 return; 959 960 /* Disable the PLL outputs */ 961 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), 962 PLL_OUT_MASK, 0); 963 if (ret) 964 return; 965 966 /* Place the PLL mode in STANDBY */ 967 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 968 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 969 } 970 971 static unsigned long 972 clk_trion_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 973 { 974 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 975 u32 l, frac, alpha_width = pll_alpha_width(pll); 976 977 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); 978 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac); 979 980 return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width); 981 } 982 983 const struct clk_ops clk_alpha_pll_fixed_ops = { 984 .enable = clk_alpha_pll_enable, 985 .disable = clk_alpha_pll_disable, 986 .is_enabled = clk_alpha_pll_is_enabled, 987 .recalc_rate = clk_alpha_pll_recalc_rate, 988 }; 989 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_ops); 990 991 const struct clk_ops clk_alpha_pll_ops = { 992 .enable = clk_alpha_pll_enable, 993 .disable = clk_alpha_pll_disable, 994 .is_enabled = clk_alpha_pll_is_enabled, 995 .recalc_rate = clk_alpha_pll_recalc_rate, 996 .round_rate = clk_alpha_pll_round_rate, 997 .set_rate = clk_alpha_pll_set_rate, 998 }; 999 EXPORT_SYMBOL_GPL(clk_alpha_pll_ops); 1000 1001 const struct clk_ops clk_alpha_pll_huayra_ops = { 1002 .enable = clk_alpha_pll_enable, 1003 .disable = clk_alpha_pll_disable, 1004 .is_enabled = clk_alpha_pll_is_enabled, 1005 .recalc_rate = alpha_pll_huayra_recalc_rate, 1006 .round_rate = alpha_pll_huayra_round_rate, 1007 .set_rate = alpha_pll_huayra_set_rate, 1008 }; 1009 EXPORT_SYMBOL_GPL(clk_alpha_pll_huayra_ops); 1010 1011 const struct clk_ops clk_alpha_pll_hwfsm_ops = { 1012 .enable = clk_alpha_pll_hwfsm_enable, 1013 .disable = clk_alpha_pll_hwfsm_disable, 1014 .is_enabled = clk_alpha_pll_hwfsm_is_enabled, 1015 .recalc_rate = clk_alpha_pll_recalc_rate, 1016 .round_rate = clk_alpha_pll_round_rate, 1017 .set_rate = clk_alpha_pll_hwfsm_set_rate, 1018 }; 1019 EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops); 1020 1021 const struct clk_ops clk_alpha_pll_fixed_trion_ops = { 1022 .enable = clk_trion_pll_enable, 1023 .disable = clk_trion_pll_disable, 1024 .is_enabled = clk_trion_pll_is_enabled, 1025 .recalc_rate = clk_trion_pll_recalc_rate, 1026 .round_rate = clk_alpha_pll_round_rate, 1027 }; 1028 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_trion_ops); 1029 1030 static unsigned long 1031 clk_alpha_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 1032 { 1033 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1034 u32 ctl; 1035 1036 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); 1037 1038 ctl >>= PLL_POST_DIV_SHIFT; 1039 ctl &= PLL_POST_DIV_MASK(pll); 1040 1041 return parent_rate >> fls(ctl); 1042 } 1043 1044 static const struct clk_div_table clk_alpha_div_table[] = { 1045 { 0x0, 1 }, 1046 { 0x1, 2 }, 1047 { 0x3, 4 }, 1048 { 0x7, 8 }, 1049 { 0xf, 16 }, 1050 { } 1051 }; 1052 1053 static const struct clk_div_table clk_alpha_2bit_div_table[] = { 1054 { 0x0, 1 }, 1055 { 0x1, 2 }, 1056 { 0x3, 4 }, 1057 { } 1058 }; 1059 1060 static long 1061 clk_alpha_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate, 1062 unsigned long *prate) 1063 { 1064 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1065 const struct clk_div_table *table; 1066 1067 if (pll->width == 2) 1068 table = clk_alpha_2bit_div_table; 1069 else 1070 table = clk_alpha_div_table; 1071 1072 return divider_round_rate(hw, rate, prate, table, 1073 pll->width, CLK_DIVIDER_POWER_OF_TWO); 1074 } 1075 1076 static long 1077 clk_alpha_pll_postdiv_round_ro_rate(struct clk_hw *hw, unsigned long rate, 1078 unsigned long *prate) 1079 { 1080 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1081 u32 ctl, div; 1082 1083 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); 1084 1085 ctl >>= PLL_POST_DIV_SHIFT; 1086 ctl &= BIT(pll->width) - 1; 1087 div = 1 << fls(ctl); 1088 1089 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) 1090 *prate = clk_hw_round_rate(clk_hw_get_parent(hw), div * rate); 1091 1092 return DIV_ROUND_UP_ULL((u64)*prate, div); 1093 } 1094 1095 static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 1096 unsigned long parent_rate) 1097 { 1098 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1099 int div; 1100 1101 /* 16 -> 0xf, 8 -> 0x7, 4 -> 0x3, 2 -> 0x1, 1 -> 0x0 */ 1102 div = DIV_ROUND_UP_ULL(parent_rate, rate) - 1; 1103 1104 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 1105 PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT, 1106 div << PLL_POST_DIV_SHIFT); 1107 } 1108 1109 const struct clk_ops clk_alpha_pll_postdiv_ops = { 1110 .recalc_rate = clk_alpha_pll_postdiv_recalc_rate, 1111 .round_rate = clk_alpha_pll_postdiv_round_rate, 1112 .set_rate = clk_alpha_pll_postdiv_set_rate, 1113 }; 1114 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ops); 1115 1116 const struct clk_ops clk_alpha_pll_postdiv_ro_ops = { 1117 .round_rate = clk_alpha_pll_postdiv_round_ro_rate, 1118 .recalc_rate = clk_alpha_pll_postdiv_recalc_rate, 1119 }; 1120 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ro_ops); 1121 1122 void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 1123 const struct alpha_pll_config *config) 1124 { 1125 u32 val, mask; 1126 1127 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 1128 clk_alpha_pll_write_config(regmap, PLL_FRAC(pll), config->alpha); 1129 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), 1130 config->config_ctl_val); 1131 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), 1132 config->config_ctl_hi_val); 1133 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), 1134 config->user_ctl_val); 1135 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), 1136 config->user_ctl_hi_val); 1137 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), 1138 config->test_ctl_val); 1139 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), 1140 config->test_ctl_hi_val); 1141 1142 if (config->post_div_mask) { 1143 mask = config->post_div_mask; 1144 val = config->post_div_val; 1145 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); 1146 } 1147 1148 if (pll->flags & SUPPORTS_FSM_LEGACY_MODE) 1149 regmap_update_bits(regmap, PLL_MODE(pll), PLL_FSM_LEGACY_MODE, 1150 PLL_FSM_LEGACY_MODE); 1151 1152 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS, 1153 PLL_UPDATE_BYPASS); 1154 1155 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 1156 } 1157 EXPORT_SYMBOL_GPL(clk_fabia_pll_configure); 1158 1159 static int alpha_pll_fabia_enable(struct clk_hw *hw) 1160 { 1161 int ret; 1162 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1163 u32 val, opmode_val; 1164 struct regmap *regmap = pll->clkr.regmap; 1165 1166 ret = regmap_read(regmap, PLL_MODE(pll), &val); 1167 if (ret) 1168 return ret; 1169 1170 /* If in FSM mode, just vote for it */ 1171 if (val & PLL_VOTE_FSM_ENA) { 1172 ret = clk_enable_regmap(hw); 1173 if (ret) 1174 return ret; 1175 return wait_for_pll_enable_active(pll); 1176 } 1177 1178 ret = regmap_read(regmap, PLL_OPMODE(pll), &opmode_val); 1179 if (ret) 1180 return ret; 1181 1182 /* Skip If PLL is already running */ 1183 if ((opmode_val & PLL_RUN) && (val & PLL_OUTCTRL)) 1184 return 0; 1185 1186 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1187 if (ret) 1188 return ret; 1189 1190 ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 1191 if (ret) 1192 return ret; 1193 1194 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, 1195 PLL_RESET_N); 1196 if (ret) 1197 return ret; 1198 1199 ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); 1200 if (ret) 1201 return ret; 1202 1203 ret = wait_for_pll_enable_lock(pll); 1204 if (ret) 1205 return ret; 1206 1207 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), 1208 PLL_OUT_MASK, PLL_OUT_MASK); 1209 if (ret) 1210 return ret; 1211 1212 return regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 1213 PLL_OUTCTRL); 1214 } 1215 1216 static void alpha_pll_fabia_disable(struct clk_hw *hw) 1217 { 1218 int ret; 1219 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1220 u32 val; 1221 struct regmap *regmap = pll->clkr.regmap; 1222 1223 ret = regmap_read(regmap, PLL_MODE(pll), &val); 1224 if (ret) 1225 return; 1226 1227 /* If in FSM mode, just unvote it */ 1228 if (val & PLL_FSM_ENA) { 1229 clk_disable_regmap(hw); 1230 return; 1231 } 1232 1233 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1234 if (ret) 1235 return; 1236 1237 /* Disable main outputs */ 1238 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); 1239 if (ret) 1240 return; 1241 1242 /* Place the PLL in STANDBY */ 1243 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 1244 } 1245 1246 static unsigned long alpha_pll_fabia_recalc_rate(struct clk_hw *hw, 1247 unsigned long parent_rate) 1248 { 1249 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1250 u32 l, frac, alpha_width = pll_alpha_width(pll); 1251 1252 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); 1253 regmap_read(pll->clkr.regmap, PLL_FRAC(pll), &frac); 1254 1255 return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width); 1256 } 1257 1258 /* 1259 * Due to limited number of bits for fractional rate programming, the 1260 * rounded up rate could be marginally higher than the requested rate. 1261 */ 1262 static int alpha_pll_check_rate_margin(struct clk_hw *hw, 1263 unsigned long rrate, unsigned long rate) 1264 { 1265 unsigned long rate_margin = rate + PLL_RATE_MARGIN; 1266 1267 if (rrate > rate_margin || rrate < rate) { 1268 pr_err("%s: Rounded rate %lu not within range [%lu, %lu)\n", 1269 clk_hw_get_name(hw), rrate, rate, rate_margin); 1270 return -EINVAL; 1271 } 1272 1273 return 0; 1274 } 1275 1276 static int alpha_pll_fabia_set_rate(struct clk_hw *hw, unsigned long rate, 1277 unsigned long prate) 1278 { 1279 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1280 u32 l, alpha_width = pll_alpha_width(pll); 1281 unsigned long rrate; 1282 int ret; 1283 u64 a; 1284 1285 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 1286 1287 ret = alpha_pll_check_rate_margin(hw, rrate, rate); 1288 if (ret < 0) 1289 return ret; 1290 1291 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 1292 regmap_write(pll->clkr.regmap, PLL_FRAC(pll), a); 1293 1294 return __clk_alpha_pll_update_latch(pll); 1295 } 1296 1297 static int alpha_pll_fabia_prepare(struct clk_hw *hw) 1298 { 1299 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1300 const struct pll_vco *vco; 1301 struct clk_hw *parent_hw; 1302 unsigned long cal_freq, rrate; 1303 u32 cal_l, val, alpha_width = pll_alpha_width(pll); 1304 const char *name = clk_hw_get_name(hw); 1305 u64 a; 1306 int ret; 1307 1308 /* Check if calibration needs to be done i.e. PLL is in reset */ 1309 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 1310 if (ret) 1311 return ret; 1312 1313 /* Return early if calibration is not needed. */ 1314 if (val & PLL_RESET_N) 1315 return 0; 1316 1317 vco = alpha_pll_find_vco(pll, clk_hw_get_rate(hw)); 1318 if (!vco) { 1319 pr_err("%s: alpha pll not in a valid vco range\n", name); 1320 return -EINVAL; 1321 } 1322 1323 cal_freq = DIV_ROUND_CLOSEST((pll->vco_table[0].min_freq + 1324 pll->vco_table[0].max_freq) * 54, 100); 1325 1326 parent_hw = clk_hw_get_parent(hw); 1327 if (!parent_hw) 1328 return -EINVAL; 1329 1330 rrate = alpha_pll_round_rate(cal_freq, clk_hw_get_rate(parent_hw), 1331 &cal_l, &a, alpha_width); 1332 1333 ret = alpha_pll_check_rate_margin(hw, rrate, cal_freq); 1334 if (ret < 0) 1335 return ret; 1336 1337 /* Setup PLL for calibration frequency */ 1338 regmap_write(pll->clkr.regmap, PLL_CAL_L_VAL(pll), cal_l); 1339 1340 /* Bringup the PLL at calibration frequency */ 1341 ret = clk_alpha_pll_enable(hw); 1342 if (ret) { 1343 pr_err("%s: alpha pll calibration failed\n", name); 1344 return ret; 1345 } 1346 1347 clk_alpha_pll_disable(hw); 1348 1349 return 0; 1350 } 1351 1352 const struct clk_ops clk_alpha_pll_fabia_ops = { 1353 .prepare = alpha_pll_fabia_prepare, 1354 .enable = alpha_pll_fabia_enable, 1355 .disable = alpha_pll_fabia_disable, 1356 .is_enabled = clk_alpha_pll_is_enabled, 1357 .set_rate = alpha_pll_fabia_set_rate, 1358 .recalc_rate = alpha_pll_fabia_recalc_rate, 1359 .round_rate = clk_alpha_pll_round_rate, 1360 }; 1361 EXPORT_SYMBOL_GPL(clk_alpha_pll_fabia_ops); 1362 1363 const struct clk_ops clk_alpha_pll_fixed_fabia_ops = { 1364 .enable = alpha_pll_fabia_enable, 1365 .disable = alpha_pll_fabia_disable, 1366 .is_enabled = clk_alpha_pll_is_enabled, 1367 .recalc_rate = alpha_pll_fabia_recalc_rate, 1368 .round_rate = clk_alpha_pll_round_rate, 1369 }; 1370 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_fabia_ops); 1371 1372 static unsigned long clk_alpha_pll_postdiv_fabia_recalc_rate(struct clk_hw *hw, 1373 unsigned long parent_rate) 1374 { 1375 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1376 u32 i, div = 1, val; 1377 int ret; 1378 1379 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); 1380 if (ret) 1381 return ret; 1382 1383 val >>= pll->post_div_shift; 1384 val &= BIT(pll->width) - 1; 1385 1386 for (i = 0; i < pll->num_post_div; i++) { 1387 if (pll->post_div_table[i].val == val) { 1388 div = pll->post_div_table[i].div; 1389 break; 1390 } 1391 } 1392 1393 return (parent_rate / div); 1394 } 1395 1396 static unsigned long 1397 clk_trion_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 1398 { 1399 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1400 struct regmap *regmap = pll->clkr.regmap; 1401 u32 i, div = 1, val; 1402 1403 regmap_read(regmap, PLL_USER_CTL(pll), &val); 1404 1405 val >>= pll->post_div_shift; 1406 val &= PLL_POST_DIV_MASK(pll); 1407 1408 for (i = 0; i < pll->num_post_div; i++) { 1409 if (pll->post_div_table[i].val == val) { 1410 div = pll->post_div_table[i].div; 1411 break; 1412 } 1413 } 1414 1415 return (parent_rate / div); 1416 } 1417 1418 static long 1419 clk_trion_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate, 1420 unsigned long *prate) 1421 { 1422 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1423 1424 return divider_round_rate(hw, rate, prate, pll->post_div_table, 1425 pll->width, CLK_DIVIDER_ROUND_CLOSEST); 1426 }; 1427 1428 static int 1429 clk_trion_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 1430 unsigned long parent_rate) 1431 { 1432 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1433 struct regmap *regmap = pll->clkr.regmap; 1434 int i, val = 0, div; 1435 1436 div = DIV_ROUND_UP_ULL(parent_rate, rate); 1437 for (i = 0; i < pll->num_post_div; i++) { 1438 if (pll->post_div_table[i].div == div) { 1439 val = pll->post_div_table[i].val; 1440 break; 1441 } 1442 } 1443 1444 return regmap_update_bits(regmap, PLL_USER_CTL(pll), 1445 PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT, 1446 val << PLL_POST_DIV_SHIFT); 1447 } 1448 1449 const struct clk_ops clk_alpha_pll_postdiv_trion_ops = { 1450 .recalc_rate = clk_trion_pll_postdiv_recalc_rate, 1451 .round_rate = clk_trion_pll_postdiv_round_rate, 1452 .set_rate = clk_trion_pll_postdiv_set_rate, 1453 }; 1454 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_trion_ops); 1455 1456 static long clk_alpha_pll_postdiv_fabia_round_rate(struct clk_hw *hw, 1457 unsigned long rate, unsigned long *prate) 1458 { 1459 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1460 1461 return divider_round_rate(hw, rate, prate, pll->post_div_table, 1462 pll->width, CLK_DIVIDER_ROUND_CLOSEST); 1463 } 1464 1465 static int clk_alpha_pll_postdiv_fabia_set_rate(struct clk_hw *hw, 1466 unsigned long rate, unsigned long parent_rate) 1467 { 1468 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1469 int i, val = 0, div, ret; 1470 1471 /* 1472 * If the PLL is in FSM mode, then treat set_rate callback as a 1473 * no-operation. 1474 */ 1475 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 1476 if (ret) 1477 return ret; 1478 1479 if (val & PLL_VOTE_FSM_ENA) 1480 return 0; 1481 1482 div = DIV_ROUND_UP_ULL(parent_rate, rate); 1483 for (i = 0; i < pll->num_post_div; i++) { 1484 if (pll->post_div_table[i].div == div) { 1485 val = pll->post_div_table[i].val; 1486 break; 1487 } 1488 } 1489 1490 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 1491 (BIT(pll->width) - 1) << pll->post_div_shift, 1492 val << pll->post_div_shift); 1493 } 1494 1495 const struct clk_ops clk_alpha_pll_postdiv_fabia_ops = { 1496 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate, 1497 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate, 1498 .set_rate = clk_alpha_pll_postdiv_fabia_set_rate, 1499 }; 1500 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_fabia_ops); 1501 1502 /** 1503 * clk_trion_pll_configure - configure the trion pll 1504 * 1505 * @pll: clk alpha pll 1506 * @regmap: register map 1507 * @config: configuration to apply for pll 1508 */ 1509 void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 1510 const struct alpha_pll_config *config) 1511 { 1512 /* 1513 * If the bootloader left the PLL enabled it's likely that there are 1514 * RCGs that will lock up if we disable the PLL below. 1515 */ 1516 if (trion_pll_is_enabled(pll, regmap)) { 1517 pr_debug("Trion PLL is already enabled, skipping configuration\n"); 1518 return; 1519 } 1520 1521 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 1522 regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL); 1523 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 1524 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), 1525 config->config_ctl_val); 1526 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), 1527 config->config_ctl_hi_val); 1528 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), 1529 config->config_ctl_hi1_val); 1530 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), 1531 config->user_ctl_val); 1532 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), 1533 config->user_ctl_hi_val); 1534 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), 1535 config->user_ctl_hi1_val); 1536 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), 1537 config->test_ctl_val); 1538 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), 1539 config->test_ctl_hi_val); 1540 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), 1541 config->test_ctl_hi1_val); 1542 1543 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS, 1544 PLL_UPDATE_BYPASS); 1545 1546 /* Disable PLL output */ 1547 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1548 1549 /* Set operation mode to OFF */ 1550 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 1551 1552 /* Place the PLL in STANDBY mode */ 1553 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 1554 } 1555 EXPORT_SYMBOL_GPL(clk_trion_pll_configure); 1556 1557 /* 1558 * The TRION PLL requires a power-on self-calibration which happens when the 1559 * PLL comes out of reset. Calibrate in case it is not completed. 1560 */ 1561 static int __alpha_pll_trion_prepare(struct clk_hw *hw, u32 pcal_done) 1562 { 1563 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1564 u32 val; 1565 int ret; 1566 1567 /* Return early if calibration is not needed. */ 1568 regmap_read(pll->clkr.regmap, PLL_STATUS(pll), &val); 1569 if (val & pcal_done) 1570 return 0; 1571 1572 /* On/off to calibrate */ 1573 ret = clk_trion_pll_enable(hw); 1574 if (!ret) 1575 clk_trion_pll_disable(hw); 1576 1577 return ret; 1578 } 1579 1580 static int alpha_pll_trion_prepare(struct clk_hw *hw) 1581 { 1582 return __alpha_pll_trion_prepare(hw, TRION_PCAL_DONE); 1583 } 1584 1585 static int alpha_pll_lucid_prepare(struct clk_hw *hw) 1586 { 1587 return __alpha_pll_trion_prepare(hw, LUCID_PCAL_DONE); 1588 } 1589 1590 static int __alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate, 1591 unsigned long prate, u32 latch_bit, u32 latch_ack) 1592 { 1593 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1594 unsigned long rrate; 1595 u32 val, l, alpha_width = pll_alpha_width(pll); 1596 u64 a; 1597 int ret; 1598 1599 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 1600 1601 ret = alpha_pll_check_rate_margin(hw, rrate, rate); 1602 if (ret < 0) 1603 return ret; 1604 1605 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 1606 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 1607 1608 /* Latch the PLL input */ 1609 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, latch_bit); 1610 if (ret) 1611 return ret; 1612 1613 /* Wait for 2 reference cycles before checking the ACK bit. */ 1614 udelay(1); 1615 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 1616 if (!(val & latch_ack)) { 1617 pr_err("Lucid PLL latch failed. Output may be unstable!\n"); 1618 return -EINVAL; 1619 } 1620 1621 /* Return the latch input to 0 */ 1622 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, 0); 1623 if (ret) 1624 return ret; 1625 1626 if (clk_hw_is_enabled(hw)) { 1627 ret = wait_for_pll_enable_lock(pll); 1628 if (ret) 1629 return ret; 1630 } 1631 1632 /* Wait for PLL output to stabilize */ 1633 udelay(100); 1634 return 0; 1635 } 1636 1637 static int alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate, 1638 unsigned long prate) 1639 { 1640 return __alpha_pll_trion_set_rate(hw, rate, prate, PLL_UPDATE, ALPHA_PLL_ACK_LATCH); 1641 } 1642 1643 const struct clk_ops clk_alpha_pll_trion_ops = { 1644 .prepare = alpha_pll_trion_prepare, 1645 .enable = clk_trion_pll_enable, 1646 .disable = clk_trion_pll_disable, 1647 .is_enabled = clk_trion_pll_is_enabled, 1648 .recalc_rate = clk_trion_pll_recalc_rate, 1649 .round_rate = clk_alpha_pll_round_rate, 1650 .set_rate = alpha_pll_trion_set_rate, 1651 }; 1652 EXPORT_SYMBOL_GPL(clk_alpha_pll_trion_ops); 1653 1654 const struct clk_ops clk_alpha_pll_lucid_ops = { 1655 .prepare = alpha_pll_lucid_prepare, 1656 .enable = clk_trion_pll_enable, 1657 .disable = clk_trion_pll_disable, 1658 .is_enabled = clk_trion_pll_is_enabled, 1659 .recalc_rate = clk_trion_pll_recalc_rate, 1660 .round_rate = clk_alpha_pll_round_rate, 1661 .set_rate = alpha_pll_trion_set_rate, 1662 }; 1663 EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_ops); 1664 1665 const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = { 1666 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate, 1667 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate, 1668 .set_rate = clk_alpha_pll_postdiv_fabia_set_rate, 1669 }; 1670 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_ops); 1671 1672 void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 1673 const struct alpha_pll_config *config) 1674 { 1675 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 1676 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 1677 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), 1678 config->user_ctl_val); 1679 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), 1680 config->config_ctl_val); 1681 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), 1682 config->config_ctl_hi_val); 1683 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), 1684 config->test_ctl_val); 1685 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), 1686 config->test_ctl_hi_val); 1687 } 1688 EXPORT_SYMBOL_GPL(clk_agera_pll_configure); 1689 1690 static int clk_alpha_pll_agera_set_rate(struct clk_hw *hw, unsigned long rate, 1691 unsigned long prate) 1692 { 1693 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1694 u32 l, alpha_width = pll_alpha_width(pll); 1695 int ret; 1696 unsigned long rrate; 1697 u64 a; 1698 1699 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 1700 ret = alpha_pll_check_rate_margin(hw, rrate, rate); 1701 if (ret < 0) 1702 return ret; 1703 1704 /* change L_VAL without having to go through the power on sequence */ 1705 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 1706 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 1707 1708 if (clk_hw_is_enabled(hw)) 1709 return wait_for_pll_enable_lock(pll); 1710 1711 return 0; 1712 } 1713 1714 const struct clk_ops clk_alpha_pll_agera_ops = { 1715 .enable = clk_alpha_pll_enable, 1716 .disable = clk_alpha_pll_disable, 1717 .is_enabled = clk_alpha_pll_is_enabled, 1718 .recalc_rate = alpha_pll_fabia_recalc_rate, 1719 .round_rate = clk_alpha_pll_round_rate, 1720 .set_rate = clk_alpha_pll_agera_set_rate, 1721 }; 1722 EXPORT_SYMBOL_GPL(clk_alpha_pll_agera_ops); 1723 1724 static int alpha_pll_lucid_5lpe_enable(struct clk_hw *hw) 1725 { 1726 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1727 u32 val; 1728 int ret; 1729 1730 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); 1731 if (ret) 1732 return ret; 1733 1734 /* If in FSM mode, just vote for it */ 1735 if (val & LUCID_5LPE_ENABLE_VOTE_RUN) { 1736 ret = clk_enable_regmap(hw); 1737 if (ret) 1738 return ret; 1739 return wait_for_pll_enable_lock(pll); 1740 } 1741 1742 /* Check if PLL is already enabled, return if enabled */ 1743 ret = trion_pll_is_enabled(pll, pll->clkr.regmap); 1744 if (ret < 0) 1745 return ret; 1746 1747 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 1748 if (ret) 1749 return ret; 1750 1751 regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_RUN); 1752 1753 ret = wait_for_pll_enable_lock(pll); 1754 if (ret) 1755 return ret; 1756 1757 /* Enable the PLL outputs */ 1758 ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK); 1759 if (ret) 1760 return ret; 1761 1762 /* Enable the global PLL outputs */ 1763 return regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); 1764 } 1765 1766 static void alpha_pll_lucid_5lpe_disable(struct clk_hw *hw) 1767 { 1768 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1769 u32 val; 1770 int ret; 1771 1772 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); 1773 if (ret) 1774 return; 1775 1776 /* If in FSM mode, just unvote it */ 1777 if (val & LUCID_5LPE_ENABLE_VOTE_RUN) { 1778 clk_disable_regmap(hw); 1779 return; 1780 } 1781 1782 /* Disable the global PLL output */ 1783 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1784 if (ret) 1785 return; 1786 1787 /* Disable the PLL outputs */ 1788 ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); 1789 if (ret) 1790 return; 1791 1792 /* Place the PLL mode in STANDBY */ 1793 regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_STANDBY); 1794 } 1795 1796 /* 1797 * The Lucid 5LPE PLL requires a power-on self-calibration which happens 1798 * when the PLL comes out of reset. Calibrate in case it is not completed. 1799 */ 1800 static int alpha_pll_lucid_5lpe_prepare(struct clk_hw *hw) 1801 { 1802 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1803 struct clk_hw *p; 1804 u32 val = 0; 1805 int ret; 1806 1807 /* Return early if calibration is not needed. */ 1808 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 1809 if (val & LUCID_5LPE_PCAL_DONE) 1810 return 0; 1811 1812 p = clk_hw_get_parent(hw); 1813 if (!p) 1814 return -EINVAL; 1815 1816 ret = alpha_pll_lucid_5lpe_enable(hw); 1817 if (ret) 1818 return ret; 1819 1820 alpha_pll_lucid_5lpe_disable(hw); 1821 1822 return 0; 1823 } 1824 1825 static int alpha_pll_lucid_5lpe_set_rate(struct clk_hw *hw, unsigned long rate, 1826 unsigned long prate) 1827 { 1828 return __alpha_pll_trion_set_rate(hw, rate, prate, 1829 LUCID_5LPE_PLL_LATCH_INPUT, 1830 LUCID_5LPE_ALPHA_PLL_ACK_LATCH); 1831 } 1832 1833 static int __clk_lucid_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 1834 unsigned long parent_rate, 1835 unsigned long enable_vote_run) 1836 { 1837 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1838 struct regmap *regmap = pll->clkr.regmap; 1839 int i, val, div, ret; 1840 u32 mask; 1841 1842 /* 1843 * If the PLL is in FSM mode, then treat set_rate callback as a 1844 * no-operation. 1845 */ 1846 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); 1847 if (ret) 1848 return ret; 1849 1850 if (val & enable_vote_run) 1851 return 0; 1852 1853 if (!pll->post_div_table) { 1854 pr_err("Missing the post_div_table for the %s PLL\n", 1855 clk_hw_get_name(&pll->clkr.hw)); 1856 return -EINVAL; 1857 } 1858 1859 div = DIV_ROUND_UP_ULL((u64)parent_rate, rate); 1860 for (i = 0; i < pll->num_post_div; i++) { 1861 if (pll->post_div_table[i].div == div) { 1862 val = pll->post_div_table[i].val; 1863 break; 1864 } 1865 } 1866 1867 mask = GENMASK(pll->width + pll->post_div_shift - 1, pll->post_div_shift); 1868 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 1869 mask, val << pll->post_div_shift); 1870 } 1871 1872 static int clk_lucid_5lpe_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 1873 unsigned long parent_rate) 1874 { 1875 return __clk_lucid_pll_postdiv_set_rate(hw, rate, parent_rate, LUCID_5LPE_ENABLE_VOTE_RUN); 1876 } 1877 1878 const struct clk_ops clk_alpha_pll_lucid_5lpe_ops = { 1879 .prepare = alpha_pll_lucid_5lpe_prepare, 1880 .enable = alpha_pll_lucid_5lpe_enable, 1881 .disable = alpha_pll_lucid_5lpe_disable, 1882 .is_enabled = clk_trion_pll_is_enabled, 1883 .recalc_rate = clk_trion_pll_recalc_rate, 1884 .round_rate = clk_alpha_pll_round_rate, 1885 .set_rate = alpha_pll_lucid_5lpe_set_rate, 1886 }; 1887 EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_5lpe_ops); 1888 1889 const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops = { 1890 .enable = alpha_pll_lucid_5lpe_enable, 1891 .disable = alpha_pll_lucid_5lpe_disable, 1892 .is_enabled = clk_trion_pll_is_enabled, 1893 .recalc_rate = clk_trion_pll_recalc_rate, 1894 .round_rate = clk_alpha_pll_round_rate, 1895 }; 1896 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_5lpe_ops); 1897 1898 const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops = { 1899 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate, 1900 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate, 1901 .set_rate = clk_lucid_5lpe_pll_postdiv_set_rate, 1902 }; 1903 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_5lpe_ops); 1904 1905 void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 1906 const struct alpha_pll_config *config) 1907 { 1908 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 1909 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 1910 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 1911 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); 1912 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); 1913 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); 1914 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); 1915 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), config->user_ctl_hi1_val); 1916 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 1917 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 1918 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); 1919 1920 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, 0); 1921 1922 /* Disable PLL output */ 1923 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1924 1925 /* Set operation mode to OFF */ 1926 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 1927 1928 /* Place the PLL in STANDBY mode */ 1929 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 1930 } 1931 EXPORT_SYMBOL_GPL(clk_zonda_pll_configure); 1932 1933 static int clk_zonda_pll_enable(struct clk_hw *hw) 1934 { 1935 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1936 struct regmap *regmap = pll->clkr.regmap; 1937 u32 val; 1938 int ret; 1939 1940 regmap_read(regmap, PLL_MODE(pll), &val); 1941 1942 /* If in FSM mode, just vote for it */ 1943 if (val & PLL_VOTE_FSM_ENA) { 1944 ret = clk_enable_regmap(hw); 1945 if (ret) 1946 return ret; 1947 return wait_for_pll_enable_active(pll); 1948 } 1949 1950 /* Get the PLL out of bypass mode */ 1951 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL); 1952 1953 /* 1954 * H/W requires a 1us delay between disabling the bypass and 1955 * de-asserting the reset. 1956 */ 1957 udelay(1); 1958 1959 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 1960 1961 /* Set operation mode to RUN */ 1962 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); 1963 1964 regmap_read(regmap, PLL_TEST_CTL(pll), &val); 1965 1966 /* If cfa mode then poll for freq lock */ 1967 if (val & ZONDA_STAY_IN_CFA) 1968 ret = wait_for_zonda_pll_freq_lock(pll); 1969 else 1970 ret = wait_for_pll_enable_lock(pll); 1971 if (ret) 1972 return ret; 1973 1974 /* Enable the PLL outputs */ 1975 regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, ZONDA_PLL_OUT_MASK); 1976 1977 /* Enable the global PLL outputs */ 1978 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); 1979 1980 return 0; 1981 } 1982 1983 static void clk_zonda_pll_disable(struct clk_hw *hw) 1984 { 1985 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1986 struct regmap *regmap = pll->clkr.regmap; 1987 u32 val; 1988 1989 regmap_read(regmap, PLL_MODE(pll), &val); 1990 1991 /* If in FSM mode, just unvote it */ 1992 if (val & PLL_VOTE_FSM_ENA) { 1993 clk_disable_regmap(hw); 1994 return; 1995 } 1996 1997 /* Disable the global PLL output */ 1998 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1999 2000 /* Disable the PLL outputs */ 2001 regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, 0); 2002 2003 /* Put the PLL in bypass and reset */ 2004 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N | PLL_BYPASSNL, 0); 2005 2006 /* Place the PLL mode in OFF state */ 2007 regmap_write(regmap, PLL_OPMODE(pll), 0x0); 2008 } 2009 2010 static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate, 2011 unsigned long prate) 2012 { 2013 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2014 unsigned long rrate; 2015 u32 test_ctl_val; 2016 u32 l, alpha_width = pll_alpha_width(pll); 2017 u64 a; 2018 int ret; 2019 2020 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 2021 2022 ret = alpha_pll_check_rate_margin(hw, rrate, rate); 2023 if (ret < 0) 2024 return ret; 2025 2026 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 2027 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 2028 2029 /* Wait before polling for the frequency latch */ 2030 udelay(5); 2031 2032 /* Read stay in cfa mode */ 2033 regmap_read(pll->clkr.regmap, PLL_TEST_CTL(pll), &test_ctl_val); 2034 2035 /* If cfa mode then poll for freq lock */ 2036 if (test_ctl_val & ZONDA_STAY_IN_CFA) 2037 ret = wait_for_zonda_pll_freq_lock(pll); 2038 else 2039 ret = wait_for_pll_enable_lock(pll); 2040 if (ret) 2041 return ret; 2042 2043 /* Wait for PLL output to stabilize */ 2044 udelay(100); 2045 return 0; 2046 } 2047 2048 const struct clk_ops clk_alpha_pll_zonda_ops = { 2049 .enable = clk_zonda_pll_enable, 2050 .disable = clk_zonda_pll_disable, 2051 .is_enabled = clk_trion_pll_is_enabled, 2052 .recalc_rate = clk_trion_pll_recalc_rate, 2053 .round_rate = clk_alpha_pll_round_rate, 2054 .set_rate = clk_zonda_pll_set_rate, 2055 }; 2056 EXPORT_SYMBOL_GPL(clk_alpha_pll_zonda_ops); 2057 2058 void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 2059 const struct alpha_pll_config *config) 2060 { 2061 u32 lval = config->l; 2062 2063 lval |= TRION_PLL_CAL_VAL << LUCID_EVO_PLL_CAL_L_VAL_SHIFT; 2064 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval); 2065 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 2066 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 2067 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); 2068 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); 2069 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); 2070 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); 2071 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 2072 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 2073 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); 2074 2075 /* Disable PLL output */ 2076 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 2077 2078 /* Set operation mode to STANDBY and de-assert the reset */ 2079 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 2080 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 2081 } 2082 EXPORT_SYMBOL_GPL(clk_lucid_evo_pll_configure); 2083 2084 static int alpha_pll_lucid_evo_enable(struct clk_hw *hw) 2085 { 2086 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2087 struct regmap *regmap = pll->clkr.regmap; 2088 u32 val; 2089 int ret; 2090 2091 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); 2092 if (ret) 2093 return ret; 2094 2095 /* If in FSM mode, just vote for it */ 2096 if (val & LUCID_EVO_ENABLE_VOTE_RUN) { 2097 ret = clk_enable_regmap(hw); 2098 if (ret) 2099 return ret; 2100 return wait_for_pll_enable_lock(pll); 2101 } 2102 2103 /* Check if PLL is already enabled */ 2104 ret = trion_pll_is_enabled(pll, regmap); 2105 if (ret < 0) { 2106 return ret; 2107 } else if (ret) { 2108 pr_warn("%s PLL is already enabled\n", clk_hw_get_name(&pll->clkr.hw)); 2109 return 0; 2110 } 2111 2112 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 2113 if (ret) 2114 return ret; 2115 2116 /* Set operation mode to RUN */ 2117 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); 2118 2119 ret = wait_for_pll_enable_lock(pll); 2120 if (ret) 2121 return ret; 2122 2123 /* Enable the PLL outputs */ 2124 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK); 2125 if (ret) 2126 return ret; 2127 2128 /* Enable the global PLL outputs */ 2129 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); 2130 if (ret) 2131 return ret; 2132 2133 /* Ensure that the write above goes through before returning. */ 2134 mb(); 2135 return ret; 2136 } 2137 2138 static void _alpha_pll_lucid_evo_disable(struct clk_hw *hw, bool reset) 2139 { 2140 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2141 struct regmap *regmap = pll->clkr.regmap; 2142 u32 val; 2143 int ret; 2144 2145 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); 2146 if (ret) 2147 return; 2148 2149 /* If in FSM mode, just unvote it */ 2150 if (val & LUCID_EVO_ENABLE_VOTE_RUN) { 2151 clk_disable_regmap(hw); 2152 return; 2153 } 2154 2155 /* Disable the global PLL output */ 2156 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 2157 if (ret) 2158 return; 2159 2160 /* Disable the PLL outputs */ 2161 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); 2162 if (ret) 2163 return; 2164 2165 /* Place the PLL mode in STANDBY */ 2166 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 2167 2168 if (reset) 2169 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, 0); 2170 } 2171 2172 static int _alpha_pll_lucid_evo_prepare(struct clk_hw *hw, bool reset) 2173 { 2174 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2175 struct clk_hw *p; 2176 u32 val = 0; 2177 int ret; 2178 2179 /* Return early if calibration is not needed. */ 2180 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 2181 if (!(val & LUCID_EVO_PCAL_NOT_DONE)) 2182 return 0; 2183 2184 p = clk_hw_get_parent(hw); 2185 if (!p) 2186 return -EINVAL; 2187 2188 ret = alpha_pll_lucid_evo_enable(hw); 2189 if (ret) 2190 return ret; 2191 2192 _alpha_pll_lucid_evo_disable(hw, reset); 2193 2194 return 0; 2195 } 2196 2197 static void alpha_pll_lucid_evo_disable(struct clk_hw *hw) 2198 { 2199 _alpha_pll_lucid_evo_disable(hw, false); 2200 } 2201 2202 static int alpha_pll_lucid_evo_prepare(struct clk_hw *hw) 2203 { 2204 return _alpha_pll_lucid_evo_prepare(hw, false); 2205 } 2206 2207 static void alpha_pll_reset_lucid_evo_disable(struct clk_hw *hw) 2208 { 2209 _alpha_pll_lucid_evo_disable(hw, true); 2210 } 2211 2212 static int alpha_pll_reset_lucid_evo_prepare(struct clk_hw *hw) 2213 { 2214 return _alpha_pll_lucid_evo_prepare(hw, true); 2215 } 2216 2217 static unsigned long alpha_pll_lucid_evo_recalc_rate(struct clk_hw *hw, 2218 unsigned long parent_rate) 2219 { 2220 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2221 struct regmap *regmap = pll->clkr.regmap; 2222 u32 l, frac; 2223 2224 regmap_read(regmap, PLL_L_VAL(pll), &l); 2225 l &= LUCID_EVO_PLL_L_VAL_MASK; 2226 regmap_read(regmap, PLL_ALPHA_VAL(pll), &frac); 2227 2228 return alpha_pll_calc_rate(parent_rate, l, frac, pll_alpha_width(pll)); 2229 } 2230 2231 static int clk_lucid_evo_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 2232 unsigned long parent_rate) 2233 { 2234 return __clk_lucid_pll_postdiv_set_rate(hw, rate, parent_rate, LUCID_EVO_ENABLE_VOTE_RUN); 2235 } 2236 2237 const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops = { 2238 .enable = alpha_pll_lucid_evo_enable, 2239 .disable = alpha_pll_lucid_evo_disable, 2240 .is_enabled = clk_trion_pll_is_enabled, 2241 .recalc_rate = alpha_pll_lucid_evo_recalc_rate, 2242 .round_rate = clk_alpha_pll_round_rate, 2243 }; 2244 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_evo_ops); 2245 2246 const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops = { 2247 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate, 2248 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate, 2249 .set_rate = clk_lucid_evo_pll_postdiv_set_rate, 2250 }; 2251 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_evo_ops); 2252 2253 const struct clk_ops clk_alpha_pll_lucid_evo_ops = { 2254 .prepare = alpha_pll_lucid_evo_prepare, 2255 .enable = alpha_pll_lucid_evo_enable, 2256 .disable = alpha_pll_lucid_evo_disable, 2257 .is_enabled = clk_trion_pll_is_enabled, 2258 .recalc_rate = alpha_pll_lucid_evo_recalc_rate, 2259 .round_rate = clk_alpha_pll_round_rate, 2260 .set_rate = alpha_pll_lucid_5lpe_set_rate, 2261 }; 2262 EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_evo_ops); 2263 2264 const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops = { 2265 .prepare = alpha_pll_reset_lucid_evo_prepare, 2266 .enable = alpha_pll_lucid_evo_enable, 2267 .disable = alpha_pll_reset_lucid_evo_disable, 2268 .is_enabled = clk_trion_pll_is_enabled, 2269 .recalc_rate = alpha_pll_lucid_evo_recalc_rate, 2270 .round_rate = clk_alpha_pll_round_rate, 2271 .set_rate = alpha_pll_lucid_5lpe_set_rate, 2272 }; 2273 EXPORT_SYMBOL_GPL(clk_alpha_pll_reset_lucid_evo_ops); 2274 2275 void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 2276 const struct alpha_pll_config *config) 2277 { 2278 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 2279 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); 2280 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); 2281 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 2282 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 2283 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 2284 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); 2285 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); 2286 2287 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 2288 2289 regmap_update_bits(regmap, PLL_MODE(pll), 2290 PLL_RESET_N | PLL_BYPASSNL | PLL_OUTCTRL, 2291 PLL_RESET_N | PLL_BYPASSNL); 2292 } 2293 EXPORT_SYMBOL_GPL(clk_rivian_evo_pll_configure); 2294 2295 static unsigned long clk_rivian_evo_pll_recalc_rate(struct clk_hw *hw, 2296 unsigned long parent_rate) 2297 { 2298 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2299 u32 l; 2300 2301 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); 2302 2303 return parent_rate * l; 2304 } 2305 2306 static long clk_rivian_evo_pll_round_rate(struct clk_hw *hw, unsigned long rate, 2307 unsigned long *prate) 2308 { 2309 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2310 unsigned long min_freq, max_freq; 2311 u32 l; 2312 u64 a; 2313 2314 rate = alpha_pll_round_rate(rate, *prate, &l, &a, 0); 2315 if (!pll->vco_table || alpha_pll_find_vco(pll, rate)) 2316 return rate; 2317 2318 min_freq = pll->vco_table[0].min_freq; 2319 max_freq = pll->vco_table[pll->num_vco - 1].max_freq; 2320 2321 return clamp(rate, min_freq, max_freq); 2322 } 2323 2324 const struct clk_ops clk_alpha_pll_rivian_evo_ops = { 2325 .enable = alpha_pll_lucid_5lpe_enable, 2326 .disable = alpha_pll_lucid_5lpe_disable, 2327 .is_enabled = clk_trion_pll_is_enabled, 2328 .recalc_rate = clk_rivian_evo_pll_recalc_rate, 2329 .round_rate = clk_rivian_evo_pll_round_rate, 2330 }; 2331 EXPORT_SYMBOL_GPL(clk_alpha_pll_rivian_evo_ops); 2332