1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/export.h> 8 #include <linux/clk-provider.h> 9 #include <linux/regmap.h> 10 #include <linux/delay.h> 11 12 #include "clk-alpha-pll.h" 13 #include "common.h" 14 15 #define PLL_MODE(p) ((p)->offset + 0x0) 16 # define PLL_OUTCTRL BIT(0) 17 # define PLL_BYPASSNL BIT(1) 18 # define PLL_RESET_N BIT(2) 19 # define PLL_OFFLINE_REQ BIT(7) 20 # define PLL_LOCK_COUNT_SHIFT 8 21 # define PLL_LOCK_COUNT_MASK 0x3f 22 # define PLL_BIAS_COUNT_SHIFT 14 23 # define PLL_BIAS_COUNT_MASK 0x3f 24 # define PLL_VOTE_FSM_ENA BIT(20) 25 # define PLL_FSM_ENA BIT(20) 26 # define PLL_VOTE_FSM_RESET BIT(21) 27 # define PLL_UPDATE BIT(22) 28 # define PLL_UPDATE_BYPASS BIT(23) 29 # define PLL_OFFLINE_ACK BIT(28) 30 # define ALPHA_PLL_ACK_LATCH BIT(29) 31 # define PLL_ACTIVE_FLAG BIT(30) 32 # define PLL_LOCK_DET BIT(31) 33 34 #define PLL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_L_VAL]) 35 #define PLL_CAL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_CAL_L_VAL]) 36 #define PLL_ALPHA_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL]) 37 #define PLL_ALPHA_VAL_U(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL_U]) 38 39 #define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL]) 40 # define PLL_POST_DIV_SHIFT 8 41 # define PLL_POST_DIV_MASK(p) GENMASK((p)->width, 0) 42 # define PLL_ALPHA_EN BIT(24) 43 # define PLL_ALPHA_MODE BIT(25) 44 # define PLL_VCO_SHIFT 20 45 # define PLL_VCO_MASK 0x3 46 47 #define PLL_USER_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U]) 48 #define PLL_USER_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U1]) 49 50 #define PLL_CONFIG_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL]) 51 #define PLL_CONFIG_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U]) 52 #define PLL_CONFIG_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U1]) 53 #define PLL_TEST_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL]) 54 #define PLL_TEST_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U]) 55 #define PLL_TEST_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U1]) 56 #define PLL_STATUS(p) ((p)->offset + (p)->regs[PLL_OFF_STATUS]) 57 #define PLL_OPMODE(p) ((p)->offset + (p)->regs[PLL_OFF_OPMODE]) 58 #define PLL_FRAC(p) ((p)->offset + (p)->regs[PLL_OFF_FRAC]) 59 60 const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { 61 [CLK_ALPHA_PLL_TYPE_DEFAULT] = { 62 [PLL_OFF_L_VAL] = 0x04, 63 [PLL_OFF_ALPHA_VAL] = 0x08, 64 [PLL_OFF_ALPHA_VAL_U] = 0x0c, 65 [PLL_OFF_USER_CTL] = 0x10, 66 [PLL_OFF_USER_CTL_U] = 0x14, 67 [PLL_OFF_CONFIG_CTL] = 0x18, 68 [PLL_OFF_TEST_CTL] = 0x1c, 69 [PLL_OFF_TEST_CTL_U] = 0x20, 70 [PLL_OFF_STATUS] = 0x24, 71 }, 72 [CLK_ALPHA_PLL_TYPE_HUAYRA] = { 73 [PLL_OFF_L_VAL] = 0x04, 74 [PLL_OFF_ALPHA_VAL] = 0x08, 75 [PLL_OFF_USER_CTL] = 0x10, 76 [PLL_OFF_CONFIG_CTL] = 0x14, 77 [PLL_OFF_CONFIG_CTL_U] = 0x18, 78 [PLL_OFF_TEST_CTL] = 0x1c, 79 [PLL_OFF_TEST_CTL_U] = 0x20, 80 [PLL_OFF_STATUS] = 0x24, 81 }, 82 [CLK_ALPHA_PLL_TYPE_BRAMMO] = { 83 [PLL_OFF_L_VAL] = 0x04, 84 [PLL_OFF_ALPHA_VAL] = 0x08, 85 [PLL_OFF_ALPHA_VAL_U] = 0x0c, 86 [PLL_OFF_USER_CTL] = 0x10, 87 [PLL_OFF_CONFIG_CTL] = 0x18, 88 [PLL_OFF_TEST_CTL] = 0x1c, 89 [PLL_OFF_STATUS] = 0x24, 90 }, 91 [CLK_ALPHA_PLL_TYPE_FABIA] = { 92 [PLL_OFF_L_VAL] = 0x04, 93 [PLL_OFF_USER_CTL] = 0x0c, 94 [PLL_OFF_USER_CTL_U] = 0x10, 95 [PLL_OFF_CONFIG_CTL] = 0x14, 96 [PLL_OFF_CONFIG_CTL_U] = 0x18, 97 [PLL_OFF_TEST_CTL] = 0x1c, 98 [PLL_OFF_TEST_CTL_U] = 0x20, 99 [PLL_OFF_STATUS] = 0x24, 100 [PLL_OFF_OPMODE] = 0x2c, 101 [PLL_OFF_FRAC] = 0x38, 102 }, 103 [CLK_ALPHA_PLL_TYPE_TRION] = { 104 [PLL_OFF_L_VAL] = 0x04, 105 [PLL_OFF_CAL_L_VAL] = 0x08, 106 [PLL_OFF_USER_CTL] = 0x0c, 107 [PLL_OFF_USER_CTL_U] = 0x10, 108 [PLL_OFF_USER_CTL_U1] = 0x14, 109 [PLL_OFF_CONFIG_CTL] = 0x18, 110 [PLL_OFF_CONFIG_CTL_U] = 0x1c, 111 [PLL_OFF_CONFIG_CTL_U1] = 0x20, 112 [PLL_OFF_TEST_CTL] = 0x24, 113 [PLL_OFF_TEST_CTL_U] = 0x28, 114 [PLL_OFF_TEST_CTL_U1] = 0x2c, 115 [PLL_OFF_STATUS] = 0x30, 116 [PLL_OFF_OPMODE] = 0x38, 117 [PLL_OFF_ALPHA_VAL] = 0x40, 118 }, 119 [CLK_ALPHA_PLL_TYPE_AGERA] = { 120 [PLL_OFF_L_VAL] = 0x04, 121 [PLL_OFF_ALPHA_VAL] = 0x08, 122 [PLL_OFF_USER_CTL] = 0x0c, 123 [PLL_OFF_CONFIG_CTL] = 0x10, 124 [PLL_OFF_CONFIG_CTL_U] = 0x14, 125 [PLL_OFF_TEST_CTL] = 0x18, 126 [PLL_OFF_TEST_CTL_U] = 0x1c, 127 [PLL_OFF_STATUS] = 0x2c, 128 }, 129 }; 130 EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); 131 132 /* 133 * Even though 40 bits are present, use only 32 for ease of calculation. 134 */ 135 #define ALPHA_REG_BITWIDTH 40 136 #define ALPHA_REG_16BIT_WIDTH 16 137 #define ALPHA_BITWIDTH 32U 138 #define ALPHA_SHIFT(w) min(w, ALPHA_BITWIDTH) 139 140 #define PLL_HUAYRA_M_WIDTH 8 141 #define PLL_HUAYRA_M_SHIFT 8 142 #define PLL_HUAYRA_M_MASK 0xff 143 #define PLL_HUAYRA_N_SHIFT 0 144 #define PLL_HUAYRA_N_MASK 0xff 145 #define PLL_HUAYRA_ALPHA_WIDTH 16 146 147 #define PLL_STANDBY 0x0 148 #define PLL_RUN 0x1 149 #define PLL_OUT_MASK 0x7 150 #define PLL_RATE_MARGIN 500 151 152 /* TRION PLL specific settings and offsets */ 153 #define TRION_PLL_CAL_VAL 0x44 154 #define TRION_PCAL_DONE BIT(26) 155 156 /* LUCID PLL specific settings and offsets */ 157 #define LUCID_PCAL_DONE BIT(27) 158 159 /* LUCID 5LPE PLL specific settings and offsets */ 160 #define LUCID_5LPE_PCAL_DONE BIT(11) 161 #define LUCID_5LPE_ALPHA_PLL_ACK_LATCH BIT(13) 162 #define LUCID_5LPE_PLL_LATCH_INPUT BIT(14) 163 #define LUCID_5LPE_ENABLE_VOTE_RUN BIT(21) 164 165 #define pll_alpha_width(p) \ 166 ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \ 167 ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH) 168 169 #define pll_has_64bit_config(p) ((PLL_CONFIG_CTL_U(p) - PLL_CONFIG_CTL(p)) == 4) 170 171 #define to_clk_alpha_pll(_hw) container_of(to_clk_regmap(_hw), \ 172 struct clk_alpha_pll, clkr) 173 174 #define to_clk_alpha_pll_postdiv(_hw) container_of(to_clk_regmap(_hw), \ 175 struct clk_alpha_pll_postdiv, clkr) 176 177 static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse, 178 const char *action) 179 { 180 u32 val; 181 int count; 182 int ret; 183 const char *name = clk_hw_get_name(&pll->clkr.hw); 184 185 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 186 if (ret) 187 return ret; 188 189 for (count = 100; count > 0; count--) { 190 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 191 if (ret) 192 return ret; 193 if (inverse && !(val & mask)) 194 return 0; 195 else if ((val & mask) == mask) 196 return 0; 197 198 udelay(1); 199 } 200 201 WARN(1, "%s failed to %s!\n", name, action); 202 return -ETIMEDOUT; 203 } 204 205 #define wait_for_pll_enable_active(pll) \ 206 wait_for_pll(pll, PLL_ACTIVE_FLAG, 0, "enable") 207 208 #define wait_for_pll_enable_lock(pll) \ 209 wait_for_pll(pll, PLL_LOCK_DET, 0, "enable") 210 211 #define wait_for_pll_disable(pll) \ 212 wait_for_pll(pll, PLL_ACTIVE_FLAG, 1, "disable") 213 214 #define wait_for_pll_offline(pll) \ 215 wait_for_pll(pll, PLL_OFFLINE_ACK, 0, "offline") 216 217 #define wait_for_pll_update(pll) \ 218 wait_for_pll(pll, PLL_UPDATE, 1, "update") 219 220 #define wait_for_pll_update_ack_set(pll) \ 221 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 0, "update_ack_set") 222 223 #define wait_for_pll_update_ack_clear(pll) \ 224 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 1, "update_ack_clear") 225 226 static void clk_alpha_pll_write_config(struct regmap *regmap, unsigned int reg, 227 unsigned int val) 228 { 229 if (val) 230 regmap_write(regmap, reg, val); 231 } 232 233 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 234 const struct alpha_pll_config *config) 235 { 236 u32 val, mask; 237 238 regmap_write(regmap, PLL_L_VAL(pll), config->l); 239 regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha); 240 regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 241 242 if (pll_has_64bit_config(pll)) 243 regmap_write(regmap, PLL_CONFIG_CTL_U(pll), 244 config->config_ctl_hi_val); 245 246 if (pll_alpha_width(pll) > 32) 247 regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi); 248 249 val = config->main_output_mask; 250 val |= config->aux_output_mask; 251 val |= config->aux2_output_mask; 252 val |= config->early_output_mask; 253 val |= config->pre_div_val; 254 val |= config->post_div_val; 255 val |= config->vco_val; 256 val |= config->alpha_en_mask; 257 val |= config->alpha_mode_mask; 258 259 mask = config->main_output_mask; 260 mask |= config->aux_output_mask; 261 mask |= config->aux2_output_mask; 262 mask |= config->early_output_mask; 263 mask |= config->pre_div_mask; 264 mask |= config->post_div_mask; 265 mask |= config->vco_mask; 266 267 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); 268 269 if (pll->flags & SUPPORTS_FSM_MODE) 270 qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0); 271 } 272 EXPORT_SYMBOL_GPL(clk_alpha_pll_configure); 273 274 static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw) 275 { 276 int ret; 277 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 278 u32 val; 279 280 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 281 if (ret) 282 return ret; 283 284 val |= PLL_FSM_ENA; 285 286 if (pll->flags & SUPPORTS_OFFLINE_REQ) 287 val &= ~PLL_OFFLINE_REQ; 288 289 ret = regmap_write(pll->clkr.regmap, PLL_MODE(pll), val); 290 if (ret) 291 return ret; 292 293 /* Make sure enable request goes through before waiting for update */ 294 mb(); 295 296 return wait_for_pll_enable_active(pll); 297 } 298 299 static void clk_alpha_pll_hwfsm_disable(struct clk_hw *hw) 300 { 301 int ret; 302 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 303 u32 val; 304 305 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 306 if (ret) 307 return; 308 309 if (pll->flags & SUPPORTS_OFFLINE_REQ) { 310 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 311 PLL_OFFLINE_REQ, PLL_OFFLINE_REQ); 312 if (ret) 313 return; 314 315 ret = wait_for_pll_offline(pll); 316 if (ret) 317 return; 318 } 319 320 /* Disable hwfsm */ 321 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 322 PLL_FSM_ENA, 0); 323 if (ret) 324 return; 325 326 wait_for_pll_disable(pll); 327 } 328 329 static int pll_is_enabled(struct clk_hw *hw, u32 mask) 330 { 331 int ret; 332 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 333 u32 val; 334 335 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 336 if (ret) 337 return ret; 338 339 return !!(val & mask); 340 } 341 342 static int clk_alpha_pll_hwfsm_is_enabled(struct clk_hw *hw) 343 { 344 return pll_is_enabled(hw, PLL_ACTIVE_FLAG); 345 } 346 347 static int clk_alpha_pll_is_enabled(struct clk_hw *hw) 348 { 349 return pll_is_enabled(hw, PLL_LOCK_DET); 350 } 351 352 static int clk_alpha_pll_enable(struct clk_hw *hw) 353 { 354 int ret; 355 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 356 u32 val, mask; 357 358 mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL; 359 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 360 if (ret) 361 return ret; 362 363 /* If in FSM mode, just vote for it */ 364 if (val & PLL_VOTE_FSM_ENA) { 365 ret = clk_enable_regmap(hw); 366 if (ret) 367 return ret; 368 return wait_for_pll_enable_active(pll); 369 } 370 371 /* Skip if already enabled */ 372 if ((val & mask) == mask) 373 return 0; 374 375 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 376 PLL_BYPASSNL, PLL_BYPASSNL); 377 if (ret) 378 return ret; 379 380 /* 381 * H/W requires a 5us delay between disabling the bypass and 382 * de-asserting the reset. 383 */ 384 mb(); 385 udelay(5); 386 387 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 388 PLL_RESET_N, PLL_RESET_N); 389 if (ret) 390 return ret; 391 392 ret = wait_for_pll_enable_lock(pll); 393 if (ret) 394 return ret; 395 396 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 397 PLL_OUTCTRL, PLL_OUTCTRL); 398 399 /* Ensure that the write above goes through before returning. */ 400 mb(); 401 return ret; 402 } 403 404 static void clk_alpha_pll_disable(struct clk_hw *hw) 405 { 406 int ret; 407 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 408 u32 val, mask; 409 410 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 411 if (ret) 412 return; 413 414 /* If in FSM mode, just unvote it */ 415 if (val & PLL_VOTE_FSM_ENA) { 416 clk_disable_regmap(hw); 417 return; 418 } 419 420 mask = PLL_OUTCTRL; 421 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0); 422 423 /* Delay of 2 output clock ticks required until output is disabled */ 424 mb(); 425 udelay(1); 426 427 mask = PLL_RESET_N | PLL_BYPASSNL; 428 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0); 429 } 430 431 static unsigned long 432 alpha_pll_calc_rate(u64 prate, u32 l, u32 a, u32 alpha_width) 433 { 434 return (prate * l) + ((prate * a) >> ALPHA_SHIFT(alpha_width)); 435 } 436 437 static unsigned long 438 alpha_pll_round_rate(unsigned long rate, unsigned long prate, u32 *l, u64 *a, 439 u32 alpha_width) 440 { 441 u64 remainder; 442 u64 quotient; 443 444 quotient = rate; 445 remainder = do_div(quotient, prate); 446 *l = quotient; 447 448 if (!remainder) { 449 *a = 0; 450 return rate; 451 } 452 453 /* Upper ALPHA_BITWIDTH bits of Alpha */ 454 quotient = remainder << ALPHA_SHIFT(alpha_width); 455 456 remainder = do_div(quotient, prate); 457 458 if (remainder) 459 quotient++; 460 461 *a = quotient; 462 return alpha_pll_calc_rate(prate, *l, *a, alpha_width); 463 } 464 465 static const struct pll_vco * 466 alpha_pll_find_vco(const struct clk_alpha_pll *pll, unsigned long rate) 467 { 468 const struct pll_vco *v = pll->vco_table; 469 const struct pll_vco *end = v + pll->num_vco; 470 471 for (; v < end; v++) 472 if (rate >= v->min_freq && rate <= v->max_freq) 473 return v; 474 475 return NULL; 476 } 477 478 static unsigned long 479 clk_alpha_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 480 { 481 u32 l, low, high, ctl; 482 u64 a = 0, prate = parent_rate; 483 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 484 u32 alpha_width = pll_alpha_width(pll); 485 486 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); 487 488 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); 489 if (ctl & PLL_ALPHA_EN) { 490 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &low); 491 if (alpha_width > 32) { 492 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), 493 &high); 494 a = (u64)high << 32 | low; 495 } else { 496 a = low & GENMASK(alpha_width - 1, 0); 497 } 498 499 if (alpha_width > ALPHA_BITWIDTH) 500 a >>= alpha_width - ALPHA_BITWIDTH; 501 } 502 503 return alpha_pll_calc_rate(prate, l, a, alpha_width); 504 } 505 506 507 static int __clk_alpha_pll_update_latch(struct clk_alpha_pll *pll) 508 { 509 int ret; 510 u32 mode; 511 512 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &mode); 513 514 /* Latch the input to the PLL */ 515 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 516 PLL_UPDATE); 517 518 /* Wait for 2 reference cycle before checking ACK bit */ 519 udelay(1); 520 521 /* 522 * PLL will latch the new L, Alpha and freq control word. 523 * PLL will respond by raising PLL_ACK_LATCH output when new programming 524 * has been latched in and PLL is being updated. When 525 * UPDATE_LOGIC_BYPASS bit is not set, PLL_UPDATE will be cleared 526 * automatically by hardware when PLL_ACK_LATCH is asserted by PLL. 527 */ 528 if (mode & PLL_UPDATE_BYPASS) { 529 ret = wait_for_pll_update_ack_set(pll); 530 if (ret) 531 return ret; 532 533 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 0); 534 } else { 535 ret = wait_for_pll_update(pll); 536 if (ret) 537 return ret; 538 } 539 540 ret = wait_for_pll_update_ack_clear(pll); 541 if (ret) 542 return ret; 543 544 /* Wait for PLL output to stabilize */ 545 udelay(10); 546 547 return 0; 548 } 549 550 static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll, 551 int (*is_enabled)(struct clk_hw *)) 552 { 553 if (!is_enabled(&pll->clkr.hw) || 554 !(pll->flags & SUPPORTS_DYNAMIC_UPDATE)) 555 return 0; 556 557 return __clk_alpha_pll_update_latch(pll); 558 } 559 560 static int __clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate, 561 unsigned long prate, 562 int (*is_enabled)(struct clk_hw *)) 563 { 564 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 565 const struct pll_vco *vco; 566 u32 l, alpha_width = pll_alpha_width(pll); 567 u64 a; 568 569 rate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 570 vco = alpha_pll_find_vco(pll, rate); 571 if (pll->vco_table && !vco) { 572 pr_err("%s: alpha pll not in a valid vco range\n", 573 clk_hw_get_name(hw)); 574 return -EINVAL; 575 } 576 577 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 578 579 if (alpha_width > ALPHA_BITWIDTH) 580 a <<= alpha_width - ALPHA_BITWIDTH; 581 582 if (alpha_width > 32) 583 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), a >> 32); 584 585 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 586 587 if (vco) { 588 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 589 PLL_VCO_MASK << PLL_VCO_SHIFT, 590 vco->val << PLL_VCO_SHIFT); 591 } 592 593 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 594 PLL_ALPHA_EN, PLL_ALPHA_EN); 595 596 return clk_alpha_pll_update_latch(pll, is_enabled); 597 } 598 599 static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate, 600 unsigned long prate) 601 { 602 return __clk_alpha_pll_set_rate(hw, rate, prate, 603 clk_alpha_pll_is_enabled); 604 } 605 606 static int clk_alpha_pll_hwfsm_set_rate(struct clk_hw *hw, unsigned long rate, 607 unsigned long prate) 608 { 609 return __clk_alpha_pll_set_rate(hw, rate, prate, 610 clk_alpha_pll_hwfsm_is_enabled); 611 } 612 613 static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate, 614 unsigned long *prate) 615 { 616 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 617 u32 l, alpha_width = pll_alpha_width(pll); 618 u64 a; 619 unsigned long min_freq, max_freq; 620 621 rate = alpha_pll_round_rate(rate, *prate, &l, &a, alpha_width); 622 if (!pll->vco_table || alpha_pll_find_vco(pll, rate)) 623 return rate; 624 625 min_freq = pll->vco_table[0].min_freq; 626 max_freq = pll->vco_table[pll->num_vco - 1].max_freq; 627 628 return clamp(rate, min_freq, max_freq); 629 } 630 631 static unsigned long 632 alpha_huayra_pll_calc_rate(u64 prate, u32 l, u32 a) 633 { 634 /* 635 * a contains 16 bit alpha_val in two’s complement number in the range 636 * of [-0.5, 0.5). 637 */ 638 if (a >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1)) 639 l -= 1; 640 641 return (prate * l) + (prate * a >> PLL_HUAYRA_ALPHA_WIDTH); 642 } 643 644 static unsigned long 645 alpha_huayra_pll_round_rate(unsigned long rate, unsigned long prate, 646 u32 *l, u32 *a) 647 { 648 u64 remainder; 649 u64 quotient; 650 651 quotient = rate; 652 remainder = do_div(quotient, prate); 653 *l = quotient; 654 655 if (!remainder) { 656 *a = 0; 657 return rate; 658 } 659 660 quotient = remainder << PLL_HUAYRA_ALPHA_WIDTH; 661 remainder = do_div(quotient, prate); 662 663 if (remainder) 664 quotient++; 665 666 /* 667 * alpha_val should be in two’s complement number in the range 668 * of [-0.5, 0.5) so if quotient >= 0.5 then increment the l value 669 * since alpha value will be subtracted in this case. 670 */ 671 if (quotient >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1)) 672 *l += 1; 673 674 *a = quotient; 675 return alpha_huayra_pll_calc_rate(prate, *l, *a); 676 } 677 678 static unsigned long 679 alpha_pll_huayra_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 680 { 681 u64 rate = parent_rate, tmp; 682 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 683 u32 l, alpha = 0, ctl, alpha_m, alpha_n; 684 685 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); 686 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); 687 688 if (ctl & PLL_ALPHA_EN) { 689 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &alpha); 690 /* 691 * Depending upon alpha_mode, it can be treated as M/N value or 692 * as a two’s complement number. When alpha_mode=1, 693 * pll_alpha_val<15:8>=M and pll_apla_val<7:0>=N 694 * 695 * Fout=FIN*(L+(M/N)) 696 * 697 * M is a signed number (-128 to 127) and N is unsigned 698 * (0 to 255). M/N has to be within +/-0.5. 699 * 700 * When alpha_mode=0, it is a two’s complement number in the 701 * range [-0.5, 0.5). 702 * 703 * Fout=FIN*(L+(alpha_val)/2^16) 704 * 705 * where alpha_val is two’s complement number. 706 */ 707 if (!(ctl & PLL_ALPHA_MODE)) 708 return alpha_huayra_pll_calc_rate(rate, l, alpha); 709 710 alpha_m = alpha >> PLL_HUAYRA_M_SHIFT & PLL_HUAYRA_M_MASK; 711 alpha_n = alpha >> PLL_HUAYRA_N_SHIFT & PLL_HUAYRA_N_MASK; 712 713 rate *= l; 714 tmp = parent_rate; 715 if (alpha_m >= BIT(PLL_HUAYRA_M_WIDTH - 1)) { 716 alpha_m = BIT(PLL_HUAYRA_M_WIDTH) - alpha_m; 717 tmp *= alpha_m; 718 do_div(tmp, alpha_n); 719 rate -= tmp; 720 } else { 721 tmp *= alpha_m; 722 do_div(tmp, alpha_n); 723 rate += tmp; 724 } 725 726 return rate; 727 } 728 729 return alpha_huayra_pll_calc_rate(rate, l, alpha); 730 } 731 732 static int alpha_pll_huayra_set_rate(struct clk_hw *hw, unsigned long rate, 733 unsigned long prate) 734 { 735 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 736 u32 l, a, ctl, cur_alpha = 0; 737 738 rate = alpha_huayra_pll_round_rate(rate, prate, &l, &a); 739 740 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); 741 742 if (ctl & PLL_ALPHA_EN) 743 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &cur_alpha); 744 745 /* 746 * Huayra PLL supports PLL dynamic programming. User can change L_VAL, 747 * without having to go through the power on sequence. 748 */ 749 if (clk_alpha_pll_is_enabled(hw)) { 750 if (cur_alpha != a) { 751 pr_err("%s: clock needs to be gated\n", 752 clk_hw_get_name(hw)); 753 return -EBUSY; 754 } 755 756 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 757 /* Ensure that the write above goes to detect L val change. */ 758 mb(); 759 return wait_for_pll_enable_lock(pll); 760 } 761 762 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 763 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 764 765 if (a == 0) 766 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 767 PLL_ALPHA_EN, 0x0); 768 else 769 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 770 PLL_ALPHA_EN | PLL_ALPHA_MODE, PLL_ALPHA_EN); 771 772 return 0; 773 } 774 775 static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long rate, 776 unsigned long *prate) 777 { 778 u32 l, a; 779 780 return alpha_huayra_pll_round_rate(rate, *prate, &l, &a); 781 } 782 783 static int trion_pll_is_enabled(struct clk_alpha_pll *pll, 784 struct regmap *regmap) 785 { 786 u32 mode_val, opmode_val; 787 int ret; 788 789 ret = regmap_read(regmap, PLL_MODE(pll), &mode_val); 790 ret |= regmap_read(regmap, PLL_OPMODE(pll), &opmode_val); 791 if (ret) 792 return 0; 793 794 return ((opmode_val & PLL_RUN) && (mode_val & PLL_OUTCTRL)); 795 } 796 797 static int clk_trion_pll_is_enabled(struct clk_hw *hw) 798 { 799 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 800 801 return trion_pll_is_enabled(pll, pll->clkr.regmap); 802 } 803 804 static int clk_trion_pll_enable(struct clk_hw *hw) 805 { 806 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 807 struct regmap *regmap = pll->clkr.regmap; 808 u32 val; 809 int ret; 810 811 ret = regmap_read(regmap, PLL_MODE(pll), &val); 812 if (ret) 813 return ret; 814 815 /* If in FSM mode, just vote for it */ 816 if (val & PLL_VOTE_FSM_ENA) { 817 ret = clk_enable_regmap(hw); 818 if (ret) 819 return ret; 820 return wait_for_pll_enable_active(pll); 821 } 822 823 /* Set operation mode to RUN */ 824 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); 825 826 ret = wait_for_pll_enable_lock(pll); 827 if (ret) 828 return ret; 829 830 /* Enable the PLL outputs */ 831 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), 832 PLL_OUT_MASK, PLL_OUT_MASK); 833 if (ret) 834 return ret; 835 836 /* Enable the global PLL outputs */ 837 return regmap_update_bits(regmap, PLL_MODE(pll), 838 PLL_OUTCTRL, PLL_OUTCTRL); 839 } 840 841 static void clk_trion_pll_disable(struct clk_hw *hw) 842 { 843 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 844 struct regmap *regmap = pll->clkr.regmap; 845 u32 val; 846 int ret; 847 848 ret = regmap_read(regmap, PLL_MODE(pll), &val); 849 if (ret) 850 return; 851 852 /* If in FSM mode, just unvote it */ 853 if (val & PLL_VOTE_FSM_ENA) { 854 clk_disable_regmap(hw); 855 return; 856 } 857 858 /* Disable the global PLL output */ 859 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 860 if (ret) 861 return; 862 863 /* Disable the PLL outputs */ 864 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), 865 PLL_OUT_MASK, 0); 866 if (ret) 867 return; 868 869 /* Place the PLL mode in STANDBY */ 870 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 871 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 872 } 873 874 static unsigned long 875 clk_trion_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 876 { 877 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 878 u32 l, frac, alpha_width = pll_alpha_width(pll); 879 880 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); 881 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac); 882 883 return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width); 884 } 885 886 const struct clk_ops clk_alpha_pll_fixed_ops = { 887 .enable = clk_alpha_pll_enable, 888 .disable = clk_alpha_pll_disable, 889 .is_enabled = clk_alpha_pll_is_enabled, 890 .recalc_rate = clk_alpha_pll_recalc_rate, 891 }; 892 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_ops); 893 894 const struct clk_ops clk_alpha_pll_ops = { 895 .enable = clk_alpha_pll_enable, 896 .disable = clk_alpha_pll_disable, 897 .is_enabled = clk_alpha_pll_is_enabled, 898 .recalc_rate = clk_alpha_pll_recalc_rate, 899 .round_rate = clk_alpha_pll_round_rate, 900 .set_rate = clk_alpha_pll_set_rate, 901 }; 902 EXPORT_SYMBOL_GPL(clk_alpha_pll_ops); 903 904 const struct clk_ops clk_alpha_pll_huayra_ops = { 905 .enable = clk_alpha_pll_enable, 906 .disable = clk_alpha_pll_disable, 907 .is_enabled = clk_alpha_pll_is_enabled, 908 .recalc_rate = alpha_pll_huayra_recalc_rate, 909 .round_rate = alpha_pll_huayra_round_rate, 910 .set_rate = alpha_pll_huayra_set_rate, 911 }; 912 EXPORT_SYMBOL_GPL(clk_alpha_pll_huayra_ops); 913 914 const struct clk_ops clk_alpha_pll_hwfsm_ops = { 915 .enable = clk_alpha_pll_hwfsm_enable, 916 .disable = clk_alpha_pll_hwfsm_disable, 917 .is_enabled = clk_alpha_pll_hwfsm_is_enabled, 918 .recalc_rate = clk_alpha_pll_recalc_rate, 919 .round_rate = clk_alpha_pll_round_rate, 920 .set_rate = clk_alpha_pll_hwfsm_set_rate, 921 }; 922 EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops); 923 924 const struct clk_ops clk_alpha_pll_fixed_trion_ops = { 925 .enable = clk_trion_pll_enable, 926 .disable = clk_trion_pll_disable, 927 .is_enabled = clk_trion_pll_is_enabled, 928 .recalc_rate = clk_trion_pll_recalc_rate, 929 .round_rate = clk_alpha_pll_round_rate, 930 }; 931 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_trion_ops); 932 933 static unsigned long 934 clk_alpha_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 935 { 936 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 937 u32 ctl; 938 939 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); 940 941 ctl >>= PLL_POST_DIV_SHIFT; 942 ctl &= PLL_POST_DIV_MASK(pll); 943 944 return parent_rate >> fls(ctl); 945 } 946 947 static const struct clk_div_table clk_alpha_div_table[] = { 948 { 0x0, 1 }, 949 { 0x1, 2 }, 950 { 0x3, 4 }, 951 { 0x7, 8 }, 952 { 0xf, 16 }, 953 { } 954 }; 955 956 static const struct clk_div_table clk_alpha_2bit_div_table[] = { 957 { 0x0, 1 }, 958 { 0x1, 2 }, 959 { 0x3, 4 }, 960 { } 961 }; 962 963 static long 964 clk_alpha_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate, 965 unsigned long *prate) 966 { 967 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 968 const struct clk_div_table *table; 969 970 if (pll->width == 2) 971 table = clk_alpha_2bit_div_table; 972 else 973 table = clk_alpha_div_table; 974 975 return divider_round_rate(hw, rate, prate, table, 976 pll->width, CLK_DIVIDER_POWER_OF_TWO); 977 } 978 979 static long 980 clk_alpha_pll_postdiv_round_ro_rate(struct clk_hw *hw, unsigned long rate, 981 unsigned long *prate) 982 { 983 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 984 u32 ctl, div; 985 986 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); 987 988 ctl >>= PLL_POST_DIV_SHIFT; 989 ctl &= BIT(pll->width) - 1; 990 div = 1 << fls(ctl); 991 992 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) 993 *prate = clk_hw_round_rate(clk_hw_get_parent(hw), div * rate); 994 995 return DIV_ROUND_UP_ULL((u64)*prate, div); 996 } 997 998 static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 999 unsigned long parent_rate) 1000 { 1001 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1002 int div; 1003 1004 /* 16 -> 0xf, 8 -> 0x7, 4 -> 0x3, 2 -> 0x1, 1 -> 0x0 */ 1005 div = DIV_ROUND_UP_ULL(parent_rate, rate) - 1; 1006 1007 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 1008 PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT, 1009 div << PLL_POST_DIV_SHIFT); 1010 } 1011 1012 const struct clk_ops clk_alpha_pll_postdiv_ops = { 1013 .recalc_rate = clk_alpha_pll_postdiv_recalc_rate, 1014 .round_rate = clk_alpha_pll_postdiv_round_rate, 1015 .set_rate = clk_alpha_pll_postdiv_set_rate, 1016 }; 1017 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ops); 1018 1019 const struct clk_ops clk_alpha_pll_postdiv_ro_ops = { 1020 .round_rate = clk_alpha_pll_postdiv_round_ro_rate, 1021 .recalc_rate = clk_alpha_pll_postdiv_recalc_rate, 1022 }; 1023 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ro_ops); 1024 1025 void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 1026 const struct alpha_pll_config *config) 1027 { 1028 u32 val, mask; 1029 1030 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 1031 clk_alpha_pll_write_config(regmap, PLL_FRAC(pll), config->alpha); 1032 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), 1033 config->config_ctl_val); 1034 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), 1035 config->config_ctl_hi_val); 1036 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), 1037 config->user_ctl_val); 1038 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), 1039 config->user_ctl_hi_val); 1040 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), 1041 config->test_ctl_val); 1042 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), 1043 config->test_ctl_hi_val); 1044 1045 if (config->post_div_mask) { 1046 mask = config->post_div_mask; 1047 val = config->post_div_val; 1048 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); 1049 } 1050 1051 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS, 1052 PLL_UPDATE_BYPASS); 1053 1054 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 1055 } 1056 EXPORT_SYMBOL_GPL(clk_fabia_pll_configure); 1057 1058 static int alpha_pll_fabia_enable(struct clk_hw *hw) 1059 { 1060 int ret; 1061 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1062 u32 val, opmode_val; 1063 struct regmap *regmap = pll->clkr.regmap; 1064 1065 ret = regmap_read(regmap, PLL_MODE(pll), &val); 1066 if (ret) 1067 return ret; 1068 1069 /* If in FSM mode, just vote for it */ 1070 if (val & PLL_VOTE_FSM_ENA) { 1071 ret = clk_enable_regmap(hw); 1072 if (ret) 1073 return ret; 1074 return wait_for_pll_enable_active(pll); 1075 } 1076 1077 ret = regmap_read(regmap, PLL_OPMODE(pll), &opmode_val); 1078 if (ret) 1079 return ret; 1080 1081 /* Skip If PLL is already running */ 1082 if ((opmode_val & PLL_RUN) && (val & PLL_OUTCTRL)) 1083 return 0; 1084 1085 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1086 if (ret) 1087 return ret; 1088 1089 ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 1090 if (ret) 1091 return ret; 1092 1093 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, 1094 PLL_RESET_N); 1095 if (ret) 1096 return ret; 1097 1098 ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); 1099 if (ret) 1100 return ret; 1101 1102 ret = wait_for_pll_enable_lock(pll); 1103 if (ret) 1104 return ret; 1105 1106 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), 1107 PLL_OUT_MASK, PLL_OUT_MASK); 1108 if (ret) 1109 return ret; 1110 1111 return regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 1112 PLL_OUTCTRL); 1113 } 1114 1115 static void alpha_pll_fabia_disable(struct clk_hw *hw) 1116 { 1117 int ret; 1118 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1119 u32 val; 1120 struct regmap *regmap = pll->clkr.regmap; 1121 1122 ret = regmap_read(regmap, PLL_MODE(pll), &val); 1123 if (ret) 1124 return; 1125 1126 /* If in FSM mode, just unvote it */ 1127 if (val & PLL_FSM_ENA) { 1128 clk_disable_regmap(hw); 1129 return; 1130 } 1131 1132 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1133 if (ret) 1134 return; 1135 1136 /* Disable main outputs */ 1137 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); 1138 if (ret) 1139 return; 1140 1141 /* Place the PLL in STANDBY */ 1142 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 1143 } 1144 1145 static unsigned long alpha_pll_fabia_recalc_rate(struct clk_hw *hw, 1146 unsigned long parent_rate) 1147 { 1148 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1149 u32 l, frac, alpha_width = pll_alpha_width(pll); 1150 1151 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); 1152 regmap_read(pll->clkr.regmap, PLL_FRAC(pll), &frac); 1153 1154 return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width); 1155 } 1156 1157 /* 1158 * Due to limited number of bits for fractional rate programming, the 1159 * rounded up rate could be marginally higher than the requested rate. 1160 */ 1161 static int alpha_pll_check_rate_margin(struct clk_hw *hw, 1162 unsigned long rrate, unsigned long rate) 1163 { 1164 unsigned long rate_margin = rate + PLL_RATE_MARGIN; 1165 1166 if (rrate > rate_margin || rrate < rate) { 1167 pr_err("%s: Rounded rate %lu not within range [%lu, %lu)\n", 1168 clk_hw_get_name(hw), rrate, rate, rate_margin); 1169 return -EINVAL; 1170 } 1171 1172 return 0; 1173 } 1174 1175 static int alpha_pll_fabia_set_rate(struct clk_hw *hw, unsigned long rate, 1176 unsigned long prate) 1177 { 1178 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1179 u32 l, alpha_width = pll_alpha_width(pll); 1180 unsigned long rrate; 1181 int ret; 1182 u64 a; 1183 1184 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 1185 1186 ret = alpha_pll_check_rate_margin(hw, rrate, rate); 1187 if (ret < 0) 1188 return ret; 1189 1190 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 1191 regmap_write(pll->clkr.regmap, PLL_FRAC(pll), a); 1192 1193 return __clk_alpha_pll_update_latch(pll); 1194 } 1195 1196 static int alpha_pll_fabia_prepare(struct clk_hw *hw) 1197 { 1198 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1199 const struct pll_vco *vco; 1200 struct clk_hw *parent_hw; 1201 unsigned long cal_freq, rrate; 1202 u32 cal_l, val, alpha_width = pll_alpha_width(pll); 1203 const char *name = clk_hw_get_name(hw); 1204 u64 a; 1205 int ret; 1206 1207 /* Check if calibration needs to be done i.e. PLL is in reset */ 1208 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 1209 if (ret) 1210 return ret; 1211 1212 /* Return early if calibration is not needed. */ 1213 if (val & PLL_RESET_N) 1214 return 0; 1215 1216 vco = alpha_pll_find_vco(pll, clk_hw_get_rate(hw)); 1217 if (!vco) { 1218 pr_err("%s: alpha pll not in a valid vco range\n", name); 1219 return -EINVAL; 1220 } 1221 1222 cal_freq = DIV_ROUND_CLOSEST((pll->vco_table[0].min_freq + 1223 pll->vco_table[0].max_freq) * 54, 100); 1224 1225 parent_hw = clk_hw_get_parent(hw); 1226 if (!parent_hw) 1227 return -EINVAL; 1228 1229 rrate = alpha_pll_round_rate(cal_freq, clk_hw_get_rate(parent_hw), 1230 &cal_l, &a, alpha_width); 1231 1232 ret = alpha_pll_check_rate_margin(hw, rrate, cal_freq); 1233 if (ret < 0) 1234 return ret; 1235 1236 /* Setup PLL for calibration frequency */ 1237 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), cal_l); 1238 1239 /* Bringup the PLL at calibration frequency */ 1240 ret = clk_alpha_pll_enable(hw); 1241 if (ret) { 1242 pr_err("%s: alpha pll calibration failed\n", name); 1243 return ret; 1244 } 1245 1246 clk_alpha_pll_disable(hw); 1247 1248 return 0; 1249 } 1250 1251 const struct clk_ops clk_alpha_pll_fabia_ops = { 1252 .prepare = alpha_pll_fabia_prepare, 1253 .enable = alpha_pll_fabia_enable, 1254 .disable = alpha_pll_fabia_disable, 1255 .is_enabled = clk_alpha_pll_is_enabled, 1256 .set_rate = alpha_pll_fabia_set_rate, 1257 .recalc_rate = alpha_pll_fabia_recalc_rate, 1258 .round_rate = clk_alpha_pll_round_rate, 1259 }; 1260 EXPORT_SYMBOL_GPL(clk_alpha_pll_fabia_ops); 1261 1262 const struct clk_ops clk_alpha_pll_fixed_fabia_ops = { 1263 .enable = alpha_pll_fabia_enable, 1264 .disable = alpha_pll_fabia_disable, 1265 .is_enabled = clk_alpha_pll_is_enabled, 1266 .recalc_rate = alpha_pll_fabia_recalc_rate, 1267 .round_rate = clk_alpha_pll_round_rate, 1268 }; 1269 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_fabia_ops); 1270 1271 static unsigned long clk_alpha_pll_postdiv_fabia_recalc_rate(struct clk_hw *hw, 1272 unsigned long parent_rate) 1273 { 1274 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1275 u32 i, div = 1, val; 1276 int ret; 1277 1278 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); 1279 if (ret) 1280 return ret; 1281 1282 val >>= pll->post_div_shift; 1283 val &= BIT(pll->width) - 1; 1284 1285 for (i = 0; i < pll->num_post_div; i++) { 1286 if (pll->post_div_table[i].val == val) { 1287 div = pll->post_div_table[i].div; 1288 break; 1289 } 1290 } 1291 1292 return (parent_rate / div); 1293 } 1294 1295 static unsigned long 1296 clk_trion_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 1297 { 1298 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1299 struct regmap *regmap = pll->clkr.regmap; 1300 u32 i, div = 1, val; 1301 1302 regmap_read(regmap, PLL_USER_CTL(pll), &val); 1303 1304 val >>= pll->post_div_shift; 1305 val &= PLL_POST_DIV_MASK(pll); 1306 1307 for (i = 0; i < pll->num_post_div; i++) { 1308 if (pll->post_div_table[i].val == val) { 1309 div = pll->post_div_table[i].div; 1310 break; 1311 } 1312 } 1313 1314 return (parent_rate / div); 1315 } 1316 1317 static long 1318 clk_trion_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate, 1319 unsigned long *prate) 1320 { 1321 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1322 1323 return divider_round_rate(hw, rate, prate, pll->post_div_table, 1324 pll->width, CLK_DIVIDER_ROUND_CLOSEST); 1325 }; 1326 1327 static int 1328 clk_trion_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 1329 unsigned long parent_rate) 1330 { 1331 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1332 struct regmap *regmap = pll->clkr.regmap; 1333 int i, val = 0, div; 1334 1335 div = DIV_ROUND_UP_ULL(parent_rate, rate); 1336 for (i = 0; i < pll->num_post_div; i++) { 1337 if (pll->post_div_table[i].div == div) { 1338 val = pll->post_div_table[i].val; 1339 break; 1340 } 1341 } 1342 1343 return regmap_update_bits(regmap, PLL_USER_CTL(pll), 1344 PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT, 1345 val << PLL_POST_DIV_SHIFT); 1346 } 1347 1348 const struct clk_ops clk_alpha_pll_postdiv_trion_ops = { 1349 .recalc_rate = clk_trion_pll_postdiv_recalc_rate, 1350 .round_rate = clk_trion_pll_postdiv_round_rate, 1351 .set_rate = clk_trion_pll_postdiv_set_rate, 1352 }; 1353 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_trion_ops); 1354 1355 static long clk_alpha_pll_postdiv_fabia_round_rate(struct clk_hw *hw, 1356 unsigned long rate, unsigned long *prate) 1357 { 1358 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1359 1360 return divider_round_rate(hw, rate, prate, pll->post_div_table, 1361 pll->width, CLK_DIVIDER_ROUND_CLOSEST); 1362 } 1363 1364 static int clk_alpha_pll_postdiv_fabia_set_rate(struct clk_hw *hw, 1365 unsigned long rate, unsigned long parent_rate) 1366 { 1367 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1368 int i, val = 0, div, ret; 1369 1370 /* 1371 * If the PLL is in FSM mode, then treat set_rate callback as a 1372 * no-operation. 1373 */ 1374 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 1375 if (ret) 1376 return ret; 1377 1378 if (val & PLL_VOTE_FSM_ENA) 1379 return 0; 1380 1381 div = DIV_ROUND_UP_ULL(parent_rate, rate); 1382 for (i = 0; i < pll->num_post_div; i++) { 1383 if (pll->post_div_table[i].div == div) { 1384 val = pll->post_div_table[i].val; 1385 break; 1386 } 1387 } 1388 1389 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 1390 (BIT(pll->width) - 1) << pll->post_div_shift, 1391 val << pll->post_div_shift); 1392 } 1393 1394 const struct clk_ops clk_alpha_pll_postdiv_fabia_ops = { 1395 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate, 1396 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate, 1397 .set_rate = clk_alpha_pll_postdiv_fabia_set_rate, 1398 }; 1399 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_fabia_ops); 1400 1401 /** 1402 * clk_lucid_pll_configure - configure the lucid pll 1403 * 1404 * @pll: clk alpha pll 1405 * @regmap: register map 1406 * @config: configuration to apply for pll 1407 */ 1408 void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 1409 const struct alpha_pll_config *config) 1410 { 1411 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 1412 regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL); 1413 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 1414 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), 1415 config->config_ctl_val); 1416 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), 1417 config->config_ctl_hi_val); 1418 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), 1419 config->config_ctl_hi1_val); 1420 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), 1421 config->user_ctl_val); 1422 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), 1423 config->user_ctl_hi_val); 1424 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), 1425 config->user_ctl_hi1_val); 1426 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), 1427 config->test_ctl_val); 1428 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), 1429 config->test_ctl_hi_val); 1430 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), 1431 config->test_ctl_hi1_val); 1432 1433 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS, 1434 PLL_UPDATE_BYPASS); 1435 1436 /* Disable PLL output */ 1437 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1438 1439 /* Set operation mode to OFF */ 1440 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 1441 1442 /* Place the PLL in STANDBY mode */ 1443 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 1444 } 1445 EXPORT_SYMBOL_GPL(clk_trion_pll_configure); 1446 1447 /* 1448 * The TRION PLL requires a power-on self-calibration which happens when the 1449 * PLL comes out of reset. Calibrate in case it is not completed. 1450 */ 1451 static int __alpha_pll_trion_prepare(struct clk_hw *hw, u32 pcal_done) 1452 { 1453 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1454 u32 val; 1455 int ret; 1456 1457 /* Return early if calibration is not needed. */ 1458 regmap_read(pll->clkr.regmap, PLL_STATUS(pll), &val); 1459 if (val & pcal_done) 1460 return 0; 1461 1462 /* On/off to calibrate */ 1463 ret = clk_trion_pll_enable(hw); 1464 if (!ret) 1465 clk_trion_pll_disable(hw); 1466 1467 return ret; 1468 } 1469 1470 static int alpha_pll_trion_prepare(struct clk_hw *hw) 1471 { 1472 return __alpha_pll_trion_prepare(hw, TRION_PCAL_DONE); 1473 } 1474 1475 static int alpha_pll_lucid_prepare(struct clk_hw *hw) 1476 { 1477 return __alpha_pll_trion_prepare(hw, LUCID_PCAL_DONE); 1478 } 1479 1480 static int __alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate, 1481 unsigned long prate, u32 latch_bit, u32 latch_ack) 1482 { 1483 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1484 unsigned long rrate; 1485 u32 val, l, alpha_width = pll_alpha_width(pll); 1486 u64 a; 1487 int ret; 1488 1489 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 1490 1491 ret = alpha_pll_check_rate_margin(hw, rrate, rate); 1492 if (ret < 0) 1493 return ret; 1494 1495 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 1496 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 1497 1498 /* Latch the PLL input */ 1499 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, latch_bit); 1500 if (ret) 1501 return ret; 1502 1503 /* Wait for 2 reference cycles before checking the ACK bit. */ 1504 udelay(1); 1505 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 1506 if (!(val & latch_ack)) { 1507 pr_err("Lucid PLL latch failed. Output may be unstable!\n"); 1508 return -EINVAL; 1509 } 1510 1511 /* Return the latch input to 0 */ 1512 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, 0); 1513 if (ret) 1514 return ret; 1515 1516 if (clk_hw_is_enabled(hw)) { 1517 ret = wait_for_pll_enable_lock(pll); 1518 if (ret) 1519 return ret; 1520 } 1521 1522 /* Wait for PLL output to stabilize */ 1523 udelay(100); 1524 return 0; 1525 } 1526 1527 static int alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate, 1528 unsigned long prate) 1529 { 1530 return __alpha_pll_trion_set_rate(hw, rate, prate, PLL_UPDATE, ALPHA_PLL_ACK_LATCH); 1531 } 1532 1533 const struct clk_ops clk_alpha_pll_trion_ops = { 1534 .prepare = alpha_pll_trion_prepare, 1535 .enable = clk_trion_pll_enable, 1536 .disable = clk_trion_pll_disable, 1537 .is_enabled = clk_trion_pll_is_enabled, 1538 .recalc_rate = clk_trion_pll_recalc_rate, 1539 .round_rate = clk_alpha_pll_round_rate, 1540 .set_rate = alpha_pll_trion_set_rate, 1541 }; 1542 EXPORT_SYMBOL_GPL(clk_alpha_pll_trion_ops); 1543 1544 const struct clk_ops clk_alpha_pll_lucid_ops = { 1545 .prepare = alpha_pll_lucid_prepare, 1546 .enable = clk_trion_pll_enable, 1547 .disable = clk_trion_pll_disable, 1548 .is_enabled = clk_trion_pll_is_enabled, 1549 .recalc_rate = clk_trion_pll_recalc_rate, 1550 .round_rate = clk_alpha_pll_round_rate, 1551 .set_rate = alpha_pll_trion_set_rate, 1552 }; 1553 EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_ops); 1554 1555 const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = { 1556 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate, 1557 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate, 1558 .set_rate = clk_alpha_pll_postdiv_fabia_set_rate, 1559 }; 1560 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_ops); 1561 1562 void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 1563 const struct alpha_pll_config *config) 1564 { 1565 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 1566 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 1567 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), 1568 config->user_ctl_val); 1569 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), 1570 config->config_ctl_val); 1571 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), 1572 config->config_ctl_hi_val); 1573 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), 1574 config->test_ctl_val); 1575 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), 1576 config->test_ctl_hi_val); 1577 } 1578 EXPORT_SYMBOL_GPL(clk_agera_pll_configure); 1579 1580 static int clk_alpha_pll_agera_set_rate(struct clk_hw *hw, unsigned long rate, 1581 unsigned long prate) 1582 { 1583 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1584 u32 l, alpha_width = pll_alpha_width(pll); 1585 int ret; 1586 unsigned long rrate; 1587 u64 a; 1588 1589 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 1590 ret = alpha_pll_check_rate_margin(hw, rrate, rate); 1591 if (ret < 0) 1592 return ret; 1593 1594 /* change L_VAL without having to go through the power on sequence */ 1595 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 1596 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 1597 1598 if (clk_hw_is_enabled(hw)) 1599 return wait_for_pll_enable_lock(pll); 1600 1601 return 0; 1602 } 1603 1604 const struct clk_ops clk_alpha_pll_agera_ops = { 1605 .enable = clk_alpha_pll_enable, 1606 .disable = clk_alpha_pll_disable, 1607 .is_enabled = clk_alpha_pll_is_enabled, 1608 .recalc_rate = alpha_pll_fabia_recalc_rate, 1609 .round_rate = clk_alpha_pll_round_rate, 1610 .set_rate = clk_alpha_pll_agera_set_rate, 1611 }; 1612 EXPORT_SYMBOL_GPL(clk_alpha_pll_agera_ops); 1613 1614 static int alpha_pll_lucid_5lpe_enable(struct clk_hw *hw) 1615 { 1616 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1617 u32 val; 1618 int ret; 1619 1620 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); 1621 if (ret) 1622 return ret; 1623 1624 /* If in FSM mode, just vote for it */ 1625 if (val & LUCID_5LPE_ENABLE_VOTE_RUN) { 1626 ret = clk_enable_regmap(hw); 1627 if (ret) 1628 return ret; 1629 return wait_for_pll_enable_lock(pll); 1630 } 1631 1632 /* Check if PLL is already enabled, return if enabled */ 1633 ret = trion_pll_is_enabled(pll, pll->clkr.regmap); 1634 if (ret < 0) 1635 return ret; 1636 1637 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 1638 if (ret) 1639 return ret; 1640 1641 regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_RUN); 1642 1643 ret = wait_for_pll_enable_lock(pll); 1644 if (ret) 1645 return ret; 1646 1647 /* Enable the PLL outputs */ 1648 ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK); 1649 if (ret) 1650 return ret; 1651 1652 /* Enable the global PLL outputs */ 1653 return regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); 1654 } 1655 1656 static void alpha_pll_lucid_5lpe_disable(struct clk_hw *hw) 1657 { 1658 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1659 u32 val; 1660 int ret; 1661 1662 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); 1663 if (ret) 1664 return; 1665 1666 /* If in FSM mode, just unvote it */ 1667 if (val & LUCID_5LPE_ENABLE_VOTE_RUN) { 1668 clk_disable_regmap(hw); 1669 return; 1670 } 1671 1672 /* Disable the global PLL output */ 1673 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1674 if (ret) 1675 return; 1676 1677 /* Disable the PLL outputs */ 1678 ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); 1679 if (ret) 1680 return; 1681 1682 /* Place the PLL mode in STANDBY */ 1683 regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_STANDBY); 1684 } 1685 1686 /* 1687 * The Lucid 5LPE PLL requires a power-on self-calibration which happens 1688 * when the PLL comes out of reset. Calibrate in case it is not completed. 1689 */ 1690 static int alpha_pll_lucid_5lpe_prepare(struct clk_hw *hw) 1691 { 1692 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1693 struct clk_hw *p; 1694 u32 val = 0; 1695 int ret; 1696 1697 /* Return early if calibration is not needed. */ 1698 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 1699 if (val & LUCID_5LPE_PCAL_DONE) 1700 return 0; 1701 1702 p = clk_hw_get_parent(hw); 1703 if (!p) 1704 return -EINVAL; 1705 1706 ret = alpha_pll_lucid_5lpe_enable(hw); 1707 if (ret) 1708 return ret; 1709 1710 alpha_pll_lucid_5lpe_disable(hw); 1711 1712 return 0; 1713 } 1714 1715 static int alpha_pll_lucid_5lpe_set_rate(struct clk_hw *hw, unsigned long rate, 1716 unsigned long prate) 1717 { 1718 return __alpha_pll_trion_set_rate(hw, rate, prate, 1719 LUCID_5LPE_PLL_LATCH_INPUT, 1720 LUCID_5LPE_ALPHA_PLL_ACK_LATCH); 1721 } 1722 1723 static int clk_lucid_5lpe_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 1724 unsigned long parent_rate) 1725 { 1726 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1727 int i, val = 0, div, ret; 1728 u32 mask; 1729 1730 /* 1731 * If the PLL is in FSM mode, then treat set_rate callback as a 1732 * no-operation. 1733 */ 1734 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); 1735 if (ret) 1736 return ret; 1737 1738 if (val & LUCID_5LPE_ENABLE_VOTE_RUN) 1739 return 0; 1740 1741 div = DIV_ROUND_UP_ULL((u64)parent_rate, rate); 1742 for (i = 0; i < pll->num_post_div; i++) { 1743 if (pll->post_div_table[i].div == div) { 1744 val = pll->post_div_table[i].val; 1745 break; 1746 } 1747 } 1748 1749 mask = GENMASK(pll->width + pll->post_div_shift - 1, pll->post_div_shift); 1750 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 1751 mask, val << pll->post_div_shift); 1752 } 1753 1754 const struct clk_ops clk_alpha_pll_lucid_5lpe_ops = { 1755 .prepare = alpha_pll_lucid_5lpe_prepare, 1756 .enable = alpha_pll_lucid_5lpe_enable, 1757 .disable = alpha_pll_lucid_5lpe_disable, 1758 .is_enabled = clk_trion_pll_is_enabled, 1759 .recalc_rate = clk_trion_pll_recalc_rate, 1760 .round_rate = clk_alpha_pll_round_rate, 1761 .set_rate = alpha_pll_lucid_5lpe_set_rate, 1762 }; 1763 EXPORT_SYMBOL(clk_alpha_pll_lucid_5lpe_ops); 1764 1765 const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops = { 1766 .enable = alpha_pll_lucid_5lpe_enable, 1767 .disable = alpha_pll_lucid_5lpe_disable, 1768 .is_enabled = clk_trion_pll_is_enabled, 1769 .recalc_rate = clk_trion_pll_recalc_rate, 1770 .round_rate = clk_alpha_pll_round_rate, 1771 }; 1772 EXPORT_SYMBOL(clk_alpha_pll_fixed_lucid_5lpe_ops); 1773 1774 const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops = { 1775 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate, 1776 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate, 1777 .set_rate = clk_lucid_5lpe_pll_postdiv_set_rate, 1778 }; 1779 EXPORT_SYMBOL(clk_alpha_pll_postdiv_lucid_5lpe_ops); 1780