1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #include <linux/kernel.h> 8 #include <linux/export.h> 9 #include <linux/clk-provider.h> 10 #include <linux/regmap.h> 11 #include <linux/delay.h> 12 13 #include "clk-alpha-pll.h" 14 #include "common.h" 15 16 #define PLL_MODE(p) ((p)->offset + 0x0) 17 # define PLL_OUTCTRL BIT(0) 18 # define PLL_BYPASSNL BIT(1) 19 # define PLL_RESET_N BIT(2) 20 # define PLL_OFFLINE_REQ BIT(7) 21 # define PLL_LOCK_COUNT_SHIFT 8 22 # define PLL_LOCK_COUNT_MASK 0x3f 23 # define PLL_BIAS_COUNT_SHIFT 14 24 # define PLL_BIAS_COUNT_MASK 0x3f 25 # define PLL_VOTE_FSM_ENA BIT(20) 26 # define PLL_FSM_ENA BIT(20) 27 # define PLL_VOTE_FSM_RESET BIT(21) 28 # define PLL_UPDATE BIT(22) 29 # define PLL_UPDATE_BYPASS BIT(23) 30 # define PLL_OFFLINE_ACK BIT(28) 31 # define ALPHA_PLL_ACK_LATCH BIT(29) 32 # define PLL_ACTIVE_FLAG BIT(30) 33 # define PLL_LOCK_DET BIT(31) 34 35 #define PLL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_L_VAL]) 36 #define PLL_CAL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_CAL_L_VAL]) 37 #define PLL_ALPHA_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL]) 38 #define PLL_ALPHA_VAL_U(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL_U]) 39 40 #define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL]) 41 # define PLL_POST_DIV_SHIFT 8 42 # define PLL_POST_DIV_MASK(p) GENMASK((p)->width, 0) 43 # define PLL_ALPHA_EN BIT(24) 44 # define PLL_ALPHA_MODE BIT(25) 45 # define PLL_VCO_SHIFT 20 46 # define PLL_VCO_MASK 0x3 47 48 #define PLL_USER_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U]) 49 #define PLL_USER_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U1]) 50 51 #define PLL_CONFIG_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL]) 52 #define PLL_CONFIG_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U]) 53 #define PLL_CONFIG_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U1]) 54 #define PLL_TEST_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL]) 55 #define PLL_TEST_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U]) 56 #define PLL_TEST_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U1]) 57 #define PLL_STATUS(p) ((p)->offset + (p)->regs[PLL_OFF_STATUS]) 58 #define PLL_OPMODE(p) ((p)->offset + (p)->regs[PLL_OFF_OPMODE]) 59 #define PLL_FRAC(p) ((p)->offset + (p)->regs[PLL_OFF_FRAC]) 60 61 const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { 62 [CLK_ALPHA_PLL_TYPE_DEFAULT] = { 63 [PLL_OFF_L_VAL] = 0x04, 64 [PLL_OFF_ALPHA_VAL] = 0x08, 65 [PLL_OFF_ALPHA_VAL_U] = 0x0c, 66 [PLL_OFF_USER_CTL] = 0x10, 67 [PLL_OFF_USER_CTL_U] = 0x14, 68 [PLL_OFF_CONFIG_CTL] = 0x18, 69 [PLL_OFF_TEST_CTL] = 0x1c, 70 [PLL_OFF_TEST_CTL_U] = 0x20, 71 [PLL_OFF_STATUS] = 0x24, 72 }, 73 [CLK_ALPHA_PLL_TYPE_HUAYRA] = { 74 [PLL_OFF_L_VAL] = 0x04, 75 [PLL_OFF_ALPHA_VAL] = 0x08, 76 [PLL_OFF_USER_CTL] = 0x10, 77 [PLL_OFF_CONFIG_CTL] = 0x14, 78 [PLL_OFF_CONFIG_CTL_U] = 0x18, 79 [PLL_OFF_TEST_CTL] = 0x1c, 80 [PLL_OFF_TEST_CTL_U] = 0x20, 81 [PLL_OFF_STATUS] = 0x24, 82 }, 83 [CLK_ALPHA_PLL_TYPE_BRAMMO] = { 84 [PLL_OFF_L_VAL] = 0x04, 85 [PLL_OFF_ALPHA_VAL] = 0x08, 86 [PLL_OFF_ALPHA_VAL_U] = 0x0c, 87 [PLL_OFF_USER_CTL] = 0x10, 88 [PLL_OFF_CONFIG_CTL] = 0x18, 89 [PLL_OFF_TEST_CTL] = 0x1c, 90 [PLL_OFF_STATUS] = 0x24, 91 }, 92 [CLK_ALPHA_PLL_TYPE_FABIA] = { 93 [PLL_OFF_L_VAL] = 0x04, 94 [PLL_OFF_USER_CTL] = 0x0c, 95 [PLL_OFF_USER_CTL_U] = 0x10, 96 [PLL_OFF_CONFIG_CTL] = 0x14, 97 [PLL_OFF_CONFIG_CTL_U] = 0x18, 98 [PLL_OFF_TEST_CTL] = 0x1c, 99 [PLL_OFF_TEST_CTL_U] = 0x20, 100 [PLL_OFF_STATUS] = 0x24, 101 [PLL_OFF_OPMODE] = 0x2c, 102 [PLL_OFF_FRAC] = 0x38, 103 }, 104 [CLK_ALPHA_PLL_TYPE_TRION] = { 105 [PLL_OFF_L_VAL] = 0x04, 106 [PLL_OFF_CAL_L_VAL] = 0x08, 107 [PLL_OFF_USER_CTL] = 0x0c, 108 [PLL_OFF_USER_CTL_U] = 0x10, 109 [PLL_OFF_USER_CTL_U1] = 0x14, 110 [PLL_OFF_CONFIG_CTL] = 0x18, 111 [PLL_OFF_CONFIG_CTL_U] = 0x1c, 112 [PLL_OFF_CONFIG_CTL_U1] = 0x20, 113 [PLL_OFF_TEST_CTL] = 0x24, 114 [PLL_OFF_TEST_CTL_U] = 0x28, 115 [PLL_OFF_TEST_CTL_U1] = 0x2c, 116 [PLL_OFF_STATUS] = 0x30, 117 [PLL_OFF_OPMODE] = 0x38, 118 [PLL_OFF_ALPHA_VAL] = 0x40, 119 }, 120 [CLK_ALPHA_PLL_TYPE_AGERA] = { 121 [PLL_OFF_L_VAL] = 0x04, 122 [PLL_OFF_ALPHA_VAL] = 0x08, 123 [PLL_OFF_USER_CTL] = 0x0c, 124 [PLL_OFF_CONFIG_CTL] = 0x10, 125 [PLL_OFF_CONFIG_CTL_U] = 0x14, 126 [PLL_OFF_TEST_CTL] = 0x18, 127 [PLL_OFF_TEST_CTL_U] = 0x1c, 128 [PLL_OFF_STATUS] = 0x2c, 129 }, 130 [CLK_ALPHA_PLL_TYPE_ZONDA] = { 131 [PLL_OFF_L_VAL] = 0x04, 132 [PLL_OFF_ALPHA_VAL] = 0x08, 133 [PLL_OFF_USER_CTL] = 0x0c, 134 [PLL_OFF_CONFIG_CTL] = 0x10, 135 [PLL_OFF_CONFIG_CTL_U] = 0x14, 136 [PLL_OFF_CONFIG_CTL_U1] = 0x18, 137 [PLL_OFF_TEST_CTL] = 0x1c, 138 [PLL_OFF_TEST_CTL_U] = 0x20, 139 [PLL_OFF_TEST_CTL_U1] = 0x24, 140 [PLL_OFF_OPMODE] = 0x28, 141 [PLL_OFF_STATUS] = 0x38, 142 }, 143 [CLK_ALPHA_PLL_TYPE_LUCID_EVO] = { 144 [PLL_OFF_OPMODE] = 0x04, 145 [PLL_OFF_STATUS] = 0x0c, 146 [PLL_OFF_L_VAL] = 0x10, 147 [PLL_OFF_ALPHA_VAL] = 0x14, 148 [PLL_OFF_USER_CTL] = 0x18, 149 [PLL_OFF_USER_CTL_U] = 0x1c, 150 [PLL_OFF_CONFIG_CTL] = 0x20, 151 [PLL_OFF_CONFIG_CTL_U] = 0x24, 152 [PLL_OFF_CONFIG_CTL_U1] = 0x28, 153 [PLL_OFF_TEST_CTL] = 0x2c, 154 [PLL_OFF_TEST_CTL_U] = 0x30, 155 [PLL_OFF_TEST_CTL_U1] = 0x34, 156 }, 157 [CLK_ALPHA_PLL_TYPE_RIVIAN_EVO] = { 158 [PLL_OFF_OPMODE] = 0x04, 159 [PLL_OFF_STATUS] = 0x0c, 160 [PLL_OFF_L_VAL] = 0x10, 161 [PLL_OFF_USER_CTL] = 0x14, 162 [PLL_OFF_USER_CTL_U] = 0x18, 163 [PLL_OFF_CONFIG_CTL] = 0x1c, 164 [PLL_OFF_CONFIG_CTL_U] = 0x20, 165 [PLL_OFF_CONFIG_CTL_U1] = 0x24, 166 [PLL_OFF_TEST_CTL] = 0x28, 167 [PLL_OFF_TEST_CTL_U] = 0x2c, 168 }, 169 }; 170 EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); 171 172 /* 173 * Even though 40 bits are present, use only 32 for ease of calculation. 174 */ 175 #define ALPHA_REG_BITWIDTH 40 176 #define ALPHA_REG_16BIT_WIDTH 16 177 #define ALPHA_BITWIDTH 32U 178 #define ALPHA_SHIFT(w) min(w, ALPHA_BITWIDTH) 179 180 #define PLL_HUAYRA_M_WIDTH 8 181 #define PLL_HUAYRA_M_SHIFT 8 182 #define PLL_HUAYRA_M_MASK 0xff 183 #define PLL_HUAYRA_N_SHIFT 0 184 #define PLL_HUAYRA_N_MASK 0xff 185 #define PLL_HUAYRA_ALPHA_WIDTH 16 186 187 #define PLL_STANDBY 0x0 188 #define PLL_RUN 0x1 189 #define PLL_OUT_MASK 0x7 190 #define PLL_RATE_MARGIN 500 191 192 /* TRION PLL specific settings and offsets */ 193 #define TRION_PLL_CAL_VAL 0x44 194 #define TRION_PCAL_DONE BIT(26) 195 196 /* LUCID PLL specific settings and offsets */ 197 #define LUCID_PCAL_DONE BIT(27) 198 199 /* LUCID 5LPE PLL specific settings and offsets */ 200 #define LUCID_5LPE_PCAL_DONE BIT(11) 201 #define LUCID_5LPE_ALPHA_PLL_ACK_LATCH BIT(13) 202 #define LUCID_5LPE_PLL_LATCH_INPUT BIT(14) 203 #define LUCID_5LPE_ENABLE_VOTE_RUN BIT(21) 204 205 /* LUCID EVO PLL specific settings and offsets */ 206 #define LUCID_EVO_PCAL_NOT_DONE BIT(8) 207 #define LUCID_EVO_ENABLE_VOTE_RUN BIT(25) 208 #define LUCID_EVO_PLL_L_VAL_MASK GENMASK(15, 0) 209 #define LUCID_EVO_PLL_CAL_L_VAL_SHIFT 16 210 211 /* ZONDA PLL specific */ 212 #define ZONDA_PLL_OUT_MASK 0xf 213 #define ZONDA_STAY_IN_CFA BIT(16) 214 #define ZONDA_PLL_FREQ_LOCK_DET BIT(29) 215 216 #define pll_alpha_width(p) \ 217 ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \ 218 ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH) 219 220 #define pll_has_64bit_config(p) ((PLL_CONFIG_CTL_U(p) - PLL_CONFIG_CTL(p)) == 4) 221 222 #define to_clk_alpha_pll(_hw) container_of(to_clk_regmap(_hw), \ 223 struct clk_alpha_pll, clkr) 224 225 #define to_clk_alpha_pll_postdiv(_hw) container_of(to_clk_regmap(_hw), \ 226 struct clk_alpha_pll_postdiv, clkr) 227 228 static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse, 229 const char *action) 230 { 231 u32 val; 232 int count; 233 int ret; 234 const char *name = clk_hw_get_name(&pll->clkr.hw); 235 236 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 237 if (ret) 238 return ret; 239 240 for (count = 200; count > 0; count--) { 241 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 242 if (ret) 243 return ret; 244 if (inverse && !(val & mask)) 245 return 0; 246 else if ((val & mask) == mask) 247 return 0; 248 249 udelay(1); 250 } 251 252 WARN(1, "%s failed to %s!\n", name, action); 253 return -ETIMEDOUT; 254 } 255 256 #define wait_for_pll_enable_active(pll) \ 257 wait_for_pll(pll, PLL_ACTIVE_FLAG, 0, "enable") 258 259 #define wait_for_pll_enable_lock(pll) \ 260 wait_for_pll(pll, PLL_LOCK_DET, 0, "enable") 261 262 #define wait_for_zonda_pll_freq_lock(pll) \ 263 wait_for_pll(pll, ZONDA_PLL_FREQ_LOCK_DET, 0, "freq enable") 264 265 #define wait_for_pll_disable(pll) \ 266 wait_for_pll(pll, PLL_ACTIVE_FLAG, 1, "disable") 267 268 #define wait_for_pll_offline(pll) \ 269 wait_for_pll(pll, PLL_OFFLINE_ACK, 0, "offline") 270 271 #define wait_for_pll_update(pll) \ 272 wait_for_pll(pll, PLL_UPDATE, 1, "update") 273 274 #define wait_for_pll_update_ack_set(pll) \ 275 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 0, "update_ack_set") 276 277 #define wait_for_pll_update_ack_clear(pll) \ 278 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 1, "update_ack_clear") 279 280 static void clk_alpha_pll_write_config(struct regmap *regmap, unsigned int reg, 281 unsigned int val) 282 { 283 if (val) 284 regmap_write(regmap, reg, val); 285 } 286 287 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 288 const struct alpha_pll_config *config) 289 { 290 u32 val, mask; 291 292 regmap_write(regmap, PLL_L_VAL(pll), config->l); 293 regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha); 294 regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 295 296 if (pll_has_64bit_config(pll)) 297 regmap_write(regmap, PLL_CONFIG_CTL_U(pll), 298 config->config_ctl_hi_val); 299 300 if (pll_alpha_width(pll) > 32) 301 regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi); 302 303 val = config->main_output_mask; 304 val |= config->aux_output_mask; 305 val |= config->aux2_output_mask; 306 val |= config->early_output_mask; 307 val |= config->pre_div_val; 308 val |= config->post_div_val; 309 val |= config->vco_val; 310 val |= config->alpha_en_mask; 311 val |= config->alpha_mode_mask; 312 313 mask = config->main_output_mask; 314 mask |= config->aux_output_mask; 315 mask |= config->aux2_output_mask; 316 mask |= config->early_output_mask; 317 mask |= config->pre_div_mask; 318 mask |= config->post_div_mask; 319 mask |= config->vco_mask; 320 321 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); 322 323 if (pll->flags & SUPPORTS_FSM_MODE) 324 qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0); 325 } 326 EXPORT_SYMBOL_GPL(clk_alpha_pll_configure); 327 328 static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw) 329 { 330 int ret; 331 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 332 u32 val; 333 334 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 335 if (ret) 336 return ret; 337 338 val |= PLL_FSM_ENA; 339 340 if (pll->flags & SUPPORTS_OFFLINE_REQ) 341 val &= ~PLL_OFFLINE_REQ; 342 343 ret = regmap_write(pll->clkr.regmap, PLL_MODE(pll), val); 344 if (ret) 345 return ret; 346 347 /* Make sure enable request goes through before waiting for update */ 348 mb(); 349 350 return wait_for_pll_enable_active(pll); 351 } 352 353 static void clk_alpha_pll_hwfsm_disable(struct clk_hw *hw) 354 { 355 int ret; 356 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 357 u32 val; 358 359 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 360 if (ret) 361 return; 362 363 if (pll->flags & SUPPORTS_OFFLINE_REQ) { 364 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 365 PLL_OFFLINE_REQ, PLL_OFFLINE_REQ); 366 if (ret) 367 return; 368 369 ret = wait_for_pll_offline(pll); 370 if (ret) 371 return; 372 } 373 374 /* Disable hwfsm */ 375 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 376 PLL_FSM_ENA, 0); 377 if (ret) 378 return; 379 380 wait_for_pll_disable(pll); 381 } 382 383 static int pll_is_enabled(struct clk_hw *hw, u32 mask) 384 { 385 int ret; 386 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 387 u32 val; 388 389 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 390 if (ret) 391 return ret; 392 393 return !!(val & mask); 394 } 395 396 static int clk_alpha_pll_hwfsm_is_enabled(struct clk_hw *hw) 397 { 398 return pll_is_enabled(hw, PLL_ACTIVE_FLAG); 399 } 400 401 static int clk_alpha_pll_is_enabled(struct clk_hw *hw) 402 { 403 return pll_is_enabled(hw, PLL_LOCK_DET); 404 } 405 406 static int clk_alpha_pll_enable(struct clk_hw *hw) 407 { 408 int ret; 409 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 410 u32 val, mask; 411 412 mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL; 413 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 414 if (ret) 415 return ret; 416 417 /* If in FSM mode, just vote for it */ 418 if (val & PLL_VOTE_FSM_ENA) { 419 ret = clk_enable_regmap(hw); 420 if (ret) 421 return ret; 422 return wait_for_pll_enable_active(pll); 423 } 424 425 /* Skip if already enabled */ 426 if ((val & mask) == mask) 427 return 0; 428 429 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 430 PLL_BYPASSNL, PLL_BYPASSNL); 431 if (ret) 432 return ret; 433 434 /* 435 * H/W requires a 5us delay between disabling the bypass and 436 * de-asserting the reset. 437 */ 438 mb(); 439 udelay(5); 440 441 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 442 PLL_RESET_N, PLL_RESET_N); 443 if (ret) 444 return ret; 445 446 ret = wait_for_pll_enable_lock(pll); 447 if (ret) 448 return ret; 449 450 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 451 PLL_OUTCTRL, PLL_OUTCTRL); 452 453 /* Ensure that the write above goes through before returning. */ 454 mb(); 455 return ret; 456 } 457 458 static void clk_alpha_pll_disable(struct clk_hw *hw) 459 { 460 int ret; 461 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 462 u32 val, mask; 463 464 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 465 if (ret) 466 return; 467 468 /* If in FSM mode, just unvote it */ 469 if (val & PLL_VOTE_FSM_ENA) { 470 clk_disable_regmap(hw); 471 return; 472 } 473 474 mask = PLL_OUTCTRL; 475 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0); 476 477 /* Delay of 2 output clock ticks required until output is disabled */ 478 mb(); 479 udelay(1); 480 481 mask = PLL_RESET_N | PLL_BYPASSNL; 482 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0); 483 } 484 485 static unsigned long 486 alpha_pll_calc_rate(u64 prate, u32 l, u32 a, u32 alpha_width) 487 { 488 return (prate * l) + ((prate * a) >> ALPHA_SHIFT(alpha_width)); 489 } 490 491 static unsigned long 492 alpha_pll_round_rate(unsigned long rate, unsigned long prate, u32 *l, u64 *a, 493 u32 alpha_width) 494 { 495 u64 remainder; 496 u64 quotient; 497 498 quotient = rate; 499 remainder = do_div(quotient, prate); 500 *l = quotient; 501 502 if (!remainder) { 503 *a = 0; 504 return rate; 505 } 506 507 /* Upper ALPHA_BITWIDTH bits of Alpha */ 508 quotient = remainder << ALPHA_SHIFT(alpha_width); 509 510 remainder = do_div(quotient, prate); 511 512 if (remainder) 513 quotient++; 514 515 *a = quotient; 516 return alpha_pll_calc_rate(prate, *l, *a, alpha_width); 517 } 518 519 static const struct pll_vco * 520 alpha_pll_find_vco(const struct clk_alpha_pll *pll, unsigned long rate) 521 { 522 const struct pll_vco *v = pll->vco_table; 523 const struct pll_vco *end = v + pll->num_vco; 524 525 for (; v < end; v++) 526 if (rate >= v->min_freq && rate <= v->max_freq) 527 return v; 528 529 return NULL; 530 } 531 532 static unsigned long 533 clk_alpha_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 534 { 535 u32 l, low, high, ctl; 536 u64 a = 0, prate = parent_rate; 537 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 538 u32 alpha_width = pll_alpha_width(pll); 539 540 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); 541 542 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); 543 if (ctl & PLL_ALPHA_EN) { 544 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &low); 545 if (alpha_width > 32) { 546 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), 547 &high); 548 a = (u64)high << 32 | low; 549 } else { 550 a = low & GENMASK(alpha_width - 1, 0); 551 } 552 553 if (alpha_width > ALPHA_BITWIDTH) 554 a >>= alpha_width - ALPHA_BITWIDTH; 555 } 556 557 return alpha_pll_calc_rate(prate, l, a, alpha_width); 558 } 559 560 561 static int __clk_alpha_pll_update_latch(struct clk_alpha_pll *pll) 562 { 563 int ret; 564 u32 mode; 565 566 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &mode); 567 568 /* Latch the input to the PLL */ 569 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 570 PLL_UPDATE); 571 572 /* Wait for 2 reference cycle before checking ACK bit */ 573 udelay(1); 574 575 /* 576 * PLL will latch the new L, Alpha and freq control word. 577 * PLL will respond by raising PLL_ACK_LATCH output when new programming 578 * has been latched in and PLL is being updated. When 579 * UPDATE_LOGIC_BYPASS bit is not set, PLL_UPDATE will be cleared 580 * automatically by hardware when PLL_ACK_LATCH is asserted by PLL. 581 */ 582 if (mode & PLL_UPDATE_BYPASS) { 583 ret = wait_for_pll_update_ack_set(pll); 584 if (ret) 585 return ret; 586 587 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 0); 588 } else { 589 ret = wait_for_pll_update(pll); 590 if (ret) 591 return ret; 592 } 593 594 ret = wait_for_pll_update_ack_clear(pll); 595 if (ret) 596 return ret; 597 598 /* Wait for PLL output to stabilize */ 599 udelay(10); 600 601 return 0; 602 } 603 604 static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll, 605 int (*is_enabled)(struct clk_hw *)) 606 { 607 if (!is_enabled(&pll->clkr.hw) || 608 !(pll->flags & SUPPORTS_DYNAMIC_UPDATE)) 609 return 0; 610 611 return __clk_alpha_pll_update_latch(pll); 612 } 613 614 static int __clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate, 615 unsigned long prate, 616 int (*is_enabled)(struct clk_hw *)) 617 { 618 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 619 const struct pll_vco *vco; 620 u32 l, alpha_width = pll_alpha_width(pll); 621 u64 a; 622 623 rate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 624 vco = alpha_pll_find_vco(pll, rate); 625 if (pll->vco_table && !vco) { 626 pr_err("%s: alpha pll not in a valid vco range\n", 627 clk_hw_get_name(hw)); 628 return -EINVAL; 629 } 630 631 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 632 633 if (alpha_width > ALPHA_BITWIDTH) 634 a <<= alpha_width - ALPHA_BITWIDTH; 635 636 if (alpha_width > 32) 637 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), a >> 32); 638 639 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 640 641 if (vco) { 642 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 643 PLL_VCO_MASK << PLL_VCO_SHIFT, 644 vco->val << PLL_VCO_SHIFT); 645 } 646 647 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 648 PLL_ALPHA_EN, PLL_ALPHA_EN); 649 650 return clk_alpha_pll_update_latch(pll, is_enabled); 651 } 652 653 static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate, 654 unsigned long prate) 655 { 656 return __clk_alpha_pll_set_rate(hw, rate, prate, 657 clk_alpha_pll_is_enabled); 658 } 659 660 static int clk_alpha_pll_hwfsm_set_rate(struct clk_hw *hw, unsigned long rate, 661 unsigned long prate) 662 { 663 return __clk_alpha_pll_set_rate(hw, rate, prate, 664 clk_alpha_pll_hwfsm_is_enabled); 665 } 666 667 static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate, 668 unsigned long *prate) 669 { 670 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 671 u32 l, alpha_width = pll_alpha_width(pll); 672 u64 a; 673 unsigned long min_freq, max_freq; 674 675 rate = alpha_pll_round_rate(rate, *prate, &l, &a, alpha_width); 676 if (!pll->vco_table || alpha_pll_find_vco(pll, rate)) 677 return rate; 678 679 min_freq = pll->vco_table[0].min_freq; 680 max_freq = pll->vco_table[pll->num_vco - 1].max_freq; 681 682 return clamp(rate, min_freq, max_freq); 683 } 684 685 static unsigned long 686 alpha_huayra_pll_calc_rate(u64 prate, u32 l, u32 a) 687 { 688 /* 689 * a contains 16 bit alpha_val in two’s complement number in the range 690 * of [-0.5, 0.5). 691 */ 692 if (a >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1)) 693 l -= 1; 694 695 return (prate * l) + (prate * a >> PLL_HUAYRA_ALPHA_WIDTH); 696 } 697 698 static unsigned long 699 alpha_huayra_pll_round_rate(unsigned long rate, unsigned long prate, 700 u32 *l, u32 *a) 701 { 702 u64 remainder; 703 u64 quotient; 704 705 quotient = rate; 706 remainder = do_div(quotient, prate); 707 *l = quotient; 708 709 if (!remainder) { 710 *a = 0; 711 return rate; 712 } 713 714 quotient = remainder << PLL_HUAYRA_ALPHA_WIDTH; 715 remainder = do_div(quotient, prate); 716 717 if (remainder) 718 quotient++; 719 720 /* 721 * alpha_val should be in two’s complement number in the range 722 * of [-0.5, 0.5) so if quotient >= 0.5 then increment the l value 723 * since alpha value will be subtracted in this case. 724 */ 725 if (quotient >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1)) 726 *l += 1; 727 728 *a = quotient; 729 return alpha_huayra_pll_calc_rate(prate, *l, *a); 730 } 731 732 static unsigned long 733 alpha_pll_huayra_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 734 { 735 u64 rate = parent_rate, tmp; 736 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 737 u32 l, alpha = 0, ctl, alpha_m, alpha_n; 738 739 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); 740 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); 741 742 if (ctl & PLL_ALPHA_EN) { 743 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &alpha); 744 /* 745 * Depending upon alpha_mode, it can be treated as M/N value or 746 * as a two’s complement number. When alpha_mode=1, 747 * pll_alpha_val<15:8>=M and pll_apla_val<7:0>=N 748 * 749 * Fout=FIN*(L+(M/N)) 750 * 751 * M is a signed number (-128 to 127) and N is unsigned 752 * (0 to 255). M/N has to be within +/-0.5. 753 * 754 * When alpha_mode=0, it is a two’s complement number in the 755 * range [-0.5, 0.5). 756 * 757 * Fout=FIN*(L+(alpha_val)/2^16) 758 * 759 * where alpha_val is two’s complement number. 760 */ 761 if (!(ctl & PLL_ALPHA_MODE)) 762 return alpha_huayra_pll_calc_rate(rate, l, alpha); 763 764 alpha_m = alpha >> PLL_HUAYRA_M_SHIFT & PLL_HUAYRA_M_MASK; 765 alpha_n = alpha >> PLL_HUAYRA_N_SHIFT & PLL_HUAYRA_N_MASK; 766 767 rate *= l; 768 tmp = parent_rate; 769 if (alpha_m >= BIT(PLL_HUAYRA_M_WIDTH - 1)) { 770 alpha_m = BIT(PLL_HUAYRA_M_WIDTH) - alpha_m; 771 tmp *= alpha_m; 772 do_div(tmp, alpha_n); 773 rate -= tmp; 774 } else { 775 tmp *= alpha_m; 776 do_div(tmp, alpha_n); 777 rate += tmp; 778 } 779 780 return rate; 781 } 782 783 return alpha_huayra_pll_calc_rate(rate, l, alpha); 784 } 785 786 static int alpha_pll_huayra_set_rate(struct clk_hw *hw, unsigned long rate, 787 unsigned long prate) 788 { 789 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 790 u32 l, a, ctl, cur_alpha = 0; 791 792 rate = alpha_huayra_pll_round_rate(rate, prate, &l, &a); 793 794 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); 795 796 if (ctl & PLL_ALPHA_EN) 797 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &cur_alpha); 798 799 /* 800 * Huayra PLL supports PLL dynamic programming. User can change L_VAL, 801 * without having to go through the power on sequence. 802 */ 803 if (clk_alpha_pll_is_enabled(hw)) { 804 if (cur_alpha != a) { 805 pr_err("%s: clock needs to be gated\n", 806 clk_hw_get_name(hw)); 807 return -EBUSY; 808 } 809 810 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 811 /* Ensure that the write above goes to detect L val change. */ 812 mb(); 813 return wait_for_pll_enable_lock(pll); 814 } 815 816 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 817 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 818 819 if (a == 0) 820 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 821 PLL_ALPHA_EN, 0x0); 822 else 823 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 824 PLL_ALPHA_EN | PLL_ALPHA_MODE, PLL_ALPHA_EN); 825 826 return 0; 827 } 828 829 static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long rate, 830 unsigned long *prate) 831 { 832 u32 l, a; 833 834 return alpha_huayra_pll_round_rate(rate, *prate, &l, &a); 835 } 836 837 static int trion_pll_is_enabled(struct clk_alpha_pll *pll, 838 struct regmap *regmap) 839 { 840 u32 mode_val, opmode_val; 841 int ret; 842 843 ret = regmap_read(regmap, PLL_MODE(pll), &mode_val); 844 ret |= regmap_read(regmap, PLL_OPMODE(pll), &opmode_val); 845 if (ret) 846 return 0; 847 848 return ((opmode_val & PLL_RUN) && (mode_val & PLL_OUTCTRL)); 849 } 850 851 static int clk_trion_pll_is_enabled(struct clk_hw *hw) 852 { 853 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 854 855 return trion_pll_is_enabled(pll, pll->clkr.regmap); 856 } 857 858 static int clk_trion_pll_enable(struct clk_hw *hw) 859 { 860 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 861 struct regmap *regmap = pll->clkr.regmap; 862 u32 val; 863 int ret; 864 865 ret = regmap_read(regmap, PLL_MODE(pll), &val); 866 if (ret) 867 return ret; 868 869 /* If in FSM mode, just vote for it */ 870 if (val & PLL_VOTE_FSM_ENA) { 871 ret = clk_enable_regmap(hw); 872 if (ret) 873 return ret; 874 return wait_for_pll_enable_active(pll); 875 } 876 877 /* Set operation mode to RUN */ 878 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); 879 880 ret = wait_for_pll_enable_lock(pll); 881 if (ret) 882 return ret; 883 884 /* Enable the PLL outputs */ 885 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), 886 PLL_OUT_MASK, PLL_OUT_MASK); 887 if (ret) 888 return ret; 889 890 /* Enable the global PLL outputs */ 891 return regmap_update_bits(regmap, PLL_MODE(pll), 892 PLL_OUTCTRL, PLL_OUTCTRL); 893 } 894 895 static void clk_trion_pll_disable(struct clk_hw *hw) 896 { 897 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 898 struct regmap *regmap = pll->clkr.regmap; 899 u32 val; 900 int ret; 901 902 ret = regmap_read(regmap, PLL_MODE(pll), &val); 903 if (ret) 904 return; 905 906 /* If in FSM mode, just unvote it */ 907 if (val & PLL_VOTE_FSM_ENA) { 908 clk_disable_regmap(hw); 909 return; 910 } 911 912 /* Disable the global PLL output */ 913 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 914 if (ret) 915 return; 916 917 /* Disable the PLL outputs */ 918 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), 919 PLL_OUT_MASK, 0); 920 if (ret) 921 return; 922 923 /* Place the PLL mode in STANDBY */ 924 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 925 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 926 } 927 928 static unsigned long 929 clk_trion_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 930 { 931 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 932 u32 l, frac, alpha_width = pll_alpha_width(pll); 933 934 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); 935 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac); 936 937 return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width); 938 } 939 940 const struct clk_ops clk_alpha_pll_fixed_ops = { 941 .enable = clk_alpha_pll_enable, 942 .disable = clk_alpha_pll_disable, 943 .is_enabled = clk_alpha_pll_is_enabled, 944 .recalc_rate = clk_alpha_pll_recalc_rate, 945 }; 946 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_ops); 947 948 const struct clk_ops clk_alpha_pll_ops = { 949 .enable = clk_alpha_pll_enable, 950 .disable = clk_alpha_pll_disable, 951 .is_enabled = clk_alpha_pll_is_enabled, 952 .recalc_rate = clk_alpha_pll_recalc_rate, 953 .round_rate = clk_alpha_pll_round_rate, 954 .set_rate = clk_alpha_pll_set_rate, 955 }; 956 EXPORT_SYMBOL_GPL(clk_alpha_pll_ops); 957 958 const struct clk_ops clk_alpha_pll_huayra_ops = { 959 .enable = clk_alpha_pll_enable, 960 .disable = clk_alpha_pll_disable, 961 .is_enabled = clk_alpha_pll_is_enabled, 962 .recalc_rate = alpha_pll_huayra_recalc_rate, 963 .round_rate = alpha_pll_huayra_round_rate, 964 .set_rate = alpha_pll_huayra_set_rate, 965 }; 966 EXPORT_SYMBOL_GPL(clk_alpha_pll_huayra_ops); 967 968 const struct clk_ops clk_alpha_pll_hwfsm_ops = { 969 .enable = clk_alpha_pll_hwfsm_enable, 970 .disable = clk_alpha_pll_hwfsm_disable, 971 .is_enabled = clk_alpha_pll_hwfsm_is_enabled, 972 .recalc_rate = clk_alpha_pll_recalc_rate, 973 .round_rate = clk_alpha_pll_round_rate, 974 .set_rate = clk_alpha_pll_hwfsm_set_rate, 975 }; 976 EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops); 977 978 const struct clk_ops clk_alpha_pll_fixed_trion_ops = { 979 .enable = clk_trion_pll_enable, 980 .disable = clk_trion_pll_disable, 981 .is_enabled = clk_trion_pll_is_enabled, 982 .recalc_rate = clk_trion_pll_recalc_rate, 983 .round_rate = clk_alpha_pll_round_rate, 984 }; 985 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_trion_ops); 986 987 static unsigned long 988 clk_alpha_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 989 { 990 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 991 u32 ctl; 992 993 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); 994 995 ctl >>= PLL_POST_DIV_SHIFT; 996 ctl &= PLL_POST_DIV_MASK(pll); 997 998 return parent_rate >> fls(ctl); 999 } 1000 1001 static const struct clk_div_table clk_alpha_div_table[] = { 1002 { 0x0, 1 }, 1003 { 0x1, 2 }, 1004 { 0x3, 4 }, 1005 { 0x7, 8 }, 1006 { 0xf, 16 }, 1007 { } 1008 }; 1009 1010 static const struct clk_div_table clk_alpha_2bit_div_table[] = { 1011 { 0x0, 1 }, 1012 { 0x1, 2 }, 1013 { 0x3, 4 }, 1014 { } 1015 }; 1016 1017 static long 1018 clk_alpha_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate, 1019 unsigned long *prate) 1020 { 1021 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1022 const struct clk_div_table *table; 1023 1024 if (pll->width == 2) 1025 table = clk_alpha_2bit_div_table; 1026 else 1027 table = clk_alpha_div_table; 1028 1029 return divider_round_rate(hw, rate, prate, table, 1030 pll->width, CLK_DIVIDER_POWER_OF_TWO); 1031 } 1032 1033 static long 1034 clk_alpha_pll_postdiv_round_ro_rate(struct clk_hw *hw, unsigned long rate, 1035 unsigned long *prate) 1036 { 1037 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1038 u32 ctl, div; 1039 1040 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); 1041 1042 ctl >>= PLL_POST_DIV_SHIFT; 1043 ctl &= BIT(pll->width) - 1; 1044 div = 1 << fls(ctl); 1045 1046 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) 1047 *prate = clk_hw_round_rate(clk_hw_get_parent(hw), div * rate); 1048 1049 return DIV_ROUND_UP_ULL((u64)*prate, div); 1050 } 1051 1052 static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 1053 unsigned long parent_rate) 1054 { 1055 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1056 int div; 1057 1058 /* 16 -> 0xf, 8 -> 0x7, 4 -> 0x3, 2 -> 0x1, 1 -> 0x0 */ 1059 div = DIV_ROUND_UP_ULL(parent_rate, rate) - 1; 1060 1061 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 1062 PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT, 1063 div << PLL_POST_DIV_SHIFT); 1064 } 1065 1066 const struct clk_ops clk_alpha_pll_postdiv_ops = { 1067 .recalc_rate = clk_alpha_pll_postdiv_recalc_rate, 1068 .round_rate = clk_alpha_pll_postdiv_round_rate, 1069 .set_rate = clk_alpha_pll_postdiv_set_rate, 1070 }; 1071 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ops); 1072 1073 const struct clk_ops clk_alpha_pll_postdiv_ro_ops = { 1074 .round_rate = clk_alpha_pll_postdiv_round_ro_rate, 1075 .recalc_rate = clk_alpha_pll_postdiv_recalc_rate, 1076 }; 1077 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ro_ops); 1078 1079 void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 1080 const struct alpha_pll_config *config) 1081 { 1082 u32 val, mask; 1083 1084 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 1085 clk_alpha_pll_write_config(regmap, PLL_FRAC(pll), config->alpha); 1086 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), 1087 config->config_ctl_val); 1088 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), 1089 config->config_ctl_hi_val); 1090 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), 1091 config->user_ctl_val); 1092 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), 1093 config->user_ctl_hi_val); 1094 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), 1095 config->test_ctl_val); 1096 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), 1097 config->test_ctl_hi_val); 1098 1099 if (config->post_div_mask) { 1100 mask = config->post_div_mask; 1101 val = config->post_div_val; 1102 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); 1103 } 1104 1105 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS, 1106 PLL_UPDATE_BYPASS); 1107 1108 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 1109 } 1110 EXPORT_SYMBOL_GPL(clk_fabia_pll_configure); 1111 1112 static int alpha_pll_fabia_enable(struct clk_hw *hw) 1113 { 1114 int ret; 1115 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1116 u32 val, opmode_val; 1117 struct regmap *regmap = pll->clkr.regmap; 1118 1119 ret = regmap_read(regmap, PLL_MODE(pll), &val); 1120 if (ret) 1121 return ret; 1122 1123 /* If in FSM mode, just vote for it */ 1124 if (val & PLL_VOTE_FSM_ENA) { 1125 ret = clk_enable_regmap(hw); 1126 if (ret) 1127 return ret; 1128 return wait_for_pll_enable_active(pll); 1129 } 1130 1131 ret = regmap_read(regmap, PLL_OPMODE(pll), &opmode_val); 1132 if (ret) 1133 return ret; 1134 1135 /* Skip If PLL is already running */ 1136 if ((opmode_val & PLL_RUN) && (val & PLL_OUTCTRL)) 1137 return 0; 1138 1139 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1140 if (ret) 1141 return ret; 1142 1143 ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 1144 if (ret) 1145 return ret; 1146 1147 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, 1148 PLL_RESET_N); 1149 if (ret) 1150 return ret; 1151 1152 ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); 1153 if (ret) 1154 return ret; 1155 1156 ret = wait_for_pll_enable_lock(pll); 1157 if (ret) 1158 return ret; 1159 1160 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), 1161 PLL_OUT_MASK, PLL_OUT_MASK); 1162 if (ret) 1163 return ret; 1164 1165 return regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 1166 PLL_OUTCTRL); 1167 } 1168 1169 static void alpha_pll_fabia_disable(struct clk_hw *hw) 1170 { 1171 int ret; 1172 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1173 u32 val; 1174 struct regmap *regmap = pll->clkr.regmap; 1175 1176 ret = regmap_read(regmap, PLL_MODE(pll), &val); 1177 if (ret) 1178 return; 1179 1180 /* If in FSM mode, just unvote it */ 1181 if (val & PLL_FSM_ENA) { 1182 clk_disable_regmap(hw); 1183 return; 1184 } 1185 1186 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1187 if (ret) 1188 return; 1189 1190 /* Disable main outputs */ 1191 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); 1192 if (ret) 1193 return; 1194 1195 /* Place the PLL in STANDBY */ 1196 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 1197 } 1198 1199 static unsigned long alpha_pll_fabia_recalc_rate(struct clk_hw *hw, 1200 unsigned long parent_rate) 1201 { 1202 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1203 u32 l, frac, alpha_width = pll_alpha_width(pll); 1204 1205 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); 1206 regmap_read(pll->clkr.regmap, PLL_FRAC(pll), &frac); 1207 1208 return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width); 1209 } 1210 1211 /* 1212 * Due to limited number of bits for fractional rate programming, the 1213 * rounded up rate could be marginally higher than the requested rate. 1214 */ 1215 static int alpha_pll_check_rate_margin(struct clk_hw *hw, 1216 unsigned long rrate, unsigned long rate) 1217 { 1218 unsigned long rate_margin = rate + PLL_RATE_MARGIN; 1219 1220 if (rrate > rate_margin || rrate < rate) { 1221 pr_err("%s: Rounded rate %lu not within range [%lu, %lu)\n", 1222 clk_hw_get_name(hw), rrate, rate, rate_margin); 1223 return -EINVAL; 1224 } 1225 1226 return 0; 1227 } 1228 1229 static int alpha_pll_fabia_set_rate(struct clk_hw *hw, unsigned long rate, 1230 unsigned long prate) 1231 { 1232 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1233 u32 l, alpha_width = pll_alpha_width(pll); 1234 unsigned long rrate; 1235 int ret; 1236 u64 a; 1237 1238 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 1239 1240 ret = alpha_pll_check_rate_margin(hw, rrate, rate); 1241 if (ret < 0) 1242 return ret; 1243 1244 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 1245 regmap_write(pll->clkr.regmap, PLL_FRAC(pll), a); 1246 1247 return __clk_alpha_pll_update_latch(pll); 1248 } 1249 1250 static int alpha_pll_fabia_prepare(struct clk_hw *hw) 1251 { 1252 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1253 const struct pll_vco *vco; 1254 struct clk_hw *parent_hw; 1255 unsigned long cal_freq, rrate; 1256 u32 cal_l, val, alpha_width = pll_alpha_width(pll); 1257 const char *name = clk_hw_get_name(hw); 1258 u64 a; 1259 int ret; 1260 1261 /* Check if calibration needs to be done i.e. PLL is in reset */ 1262 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 1263 if (ret) 1264 return ret; 1265 1266 /* Return early if calibration is not needed. */ 1267 if (val & PLL_RESET_N) 1268 return 0; 1269 1270 vco = alpha_pll_find_vco(pll, clk_hw_get_rate(hw)); 1271 if (!vco) { 1272 pr_err("%s: alpha pll not in a valid vco range\n", name); 1273 return -EINVAL; 1274 } 1275 1276 cal_freq = DIV_ROUND_CLOSEST((pll->vco_table[0].min_freq + 1277 pll->vco_table[0].max_freq) * 54, 100); 1278 1279 parent_hw = clk_hw_get_parent(hw); 1280 if (!parent_hw) 1281 return -EINVAL; 1282 1283 rrate = alpha_pll_round_rate(cal_freq, clk_hw_get_rate(parent_hw), 1284 &cal_l, &a, alpha_width); 1285 1286 ret = alpha_pll_check_rate_margin(hw, rrate, cal_freq); 1287 if (ret < 0) 1288 return ret; 1289 1290 /* Setup PLL for calibration frequency */ 1291 regmap_write(pll->clkr.regmap, PLL_CAL_L_VAL(pll), cal_l); 1292 1293 /* Bringup the PLL at calibration frequency */ 1294 ret = clk_alpha_pll_enable(hw); 1295 if (ret) { 1296 pr_err("%s: alpha pll calibration failed\n", name); 1297 return ret; 1298 } 1299 1300 clk_alpha_pll_disable(hw); 1301 1302 return 0; 1303 } 1304 1305 const struct clk_ops clk_alpha_pll_fabia_ops = { 1306 .prepare = alpha_pll_fabia_prepare, 1307 .enable = alpha_pll_fabia_enable, 1308 .disable = alpha_pll_fabia_disable, 1309 .is_enabled = clk_alpha_pll_is_enabled, 1310 .set_rate = alpha_pll_fabia_set_rate, 1311 .recalc_rate = alpha_pll_fabia_recalc_rate, 1312 .round_rate = clk_alpha_pll_round_rate, 1313 }; 1314 EXPORT_SYMBOL_GPL(clk_alpha_pll_fabia_ops); 1315 1316 const struct clk_ops clk_alpha_pll_fixed_fabia_ops = { 1317 .enable = alpha_pll_fabia_enable, 1318 .disable = alpha_pll_fabia_disable, 1319 .is_enabled = clk_alpha_pll_is_enabled, 1320 .recalc_rate = alpha_pll_fabia_recalc_rate, 1321 .round_rate = clk_alpha_pll_round_rate, 1322 }; 1323 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_fabia_ops); 1324 1325 static unsigned long clk_alpha_pll_postdiv_fabia_recalc_rate(struct clk_hw *hw, 1326 unsigned long parent_rate) 1327 { 1328 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1329 u32 i, div = 1, val; 1330 int ret; 1331 1332 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); 1333 if (ret) 1334 return ret; 1335 1336 val >>= pll->post_div_shift; 1337 val &= BIT(pll->width) - 1; 1338 1339 for (i = 0; i < pll->num_post_div; i++) { 1340 if (pll->post_div_table[i].val == val) { 1341 div = pll->post_div_table[i].div; 1342 break; 1343 } 1344 } 1345 1346 return (parent_rate / div); 1347 } 1348 1349 static unsigned long 1350 clk_trion_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 1351 { 1352 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1353 struct regmap *regmap = pll->clkr.regmap; 1354 u32 i, div = 1, val; 1355 1356 regmap_read(regmap, PLL_USER_CTL(pll), &val); 1357 1358 val >>= pll->post_div_shift; 1359 val &= PLL_POST_DIV_MASK(pll); 1360 1361 for (i = 0; i < pll->num_post_div; i++) { 1362 if (pll->post_div_table[i].val == val) { 1363 div = pll->post_div_table[i].div; 1364 break; 1365 } 1366 } 1367 1368 return (parent_rate / div); 1369 } 1370 1371 static long 1372 clk_trion_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate, 1373 unsigned long *prate) 1374 { 1375 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1376 1377 return divider_round_rate(hw, rate, prate, pll->post_div_table, 1378 pll->width, CLK_DIVIDER_ROUND_CLOSEST); 1379 }; 1380 1381 static int 1382 clk_trion_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 1383 unsigned long parent_rate) 1384 { 1385 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1386 struct regmap *regmap = pll->clkr.regmap; 1387 int i, val = 0, div; 1388 1389 div = DIV_ROUND_UP_ULL(parent_rate, rate); 1390 for (i = 0; i < pll->num_post_div; i++) { 1391 if (pll->post_div_table[i].div == div) { 1392 val = pll->post_div_table[i].val; 1393 break; 1394 } 1395 } 1396 1397 return regmap_update_bits(regmap, PLL_USER_CTL(pll), 1398 PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT, 1399 val << PLL_POST_DIV_SHIFT); 1400 } 1401 1402 const struct clk_ops clk_alpha_pll_postdiv_trion_ops = { 1403 .recalc_rate = clk_trion_pll_postdiv_recalc_rate, 1404 .round_rate = clk_trion_pll_postdiv_round_rate, 1405 .set_rate = clk_trion_pll_postdiv_set_rate, 1406 }; 1407 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_trion_ops); 1408 1409 static long clk_alpha_pll_postdiv_fabia_round_rate(struct clk_hw *hw, 1410 unsigned long rate, unsigned long *prate) 1411 { 1412 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1413 1414 return divider_round_rate(hw, rate, prate, pll->post_div_table, 1415 pll->width, CLK_DIVIDER_ROUND_CLOSEST); 1416 } 1417 1418 static int clk_alpha_pll_postdiv_fabia_set_rate(struct clk_hw *hw, 1419 unsigned long rate, unsigned long parent_rate) 1420 { 1421 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1422 int i, val = 0, div, ret; 1423 1424 /* 1425 * If the PLL is in FSM mode, then treat set_rate callback as a 1426 * no-operation. 1427 */ 1428 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 1429 if (ret) 1430 return ret; 1431 1432 if (val & PLL_VOTE_FSM_ENA) 1433 return 0; 1434 1435 div = DIV_ROUND_UP_ULL(parent_rate, rate); 1436 for (i = 0; i < pll->num_post_div; i++) { 1437 if (pll->post_div_table[i].div == div) { 1438 val = pll->post_div_table[i].val; 1439 break; 1440 } 1441 } 1442 1443 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 1444 (BIT(pll->width) - 1) << pll->post_div_shift, 1445 val << pll->post_div_shift); 1446 } 1447 1448 const struct clk_ops clk_alpha_pll_postdiv_fabia_ops = { 1449 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate, 1450 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate, 1451 .set_rate = clk_alpha_pll_postdiv_fabia_set_rate, 1452 }; 1453 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_fabia_ops); 1454 1455 /** 1456 * clk_trion_pll_configure - configure the trion pll 1457 * 1458 * @pll: clk alpha pll 1459 * @regmap: register map 1460 * @config: configuration to apply for pll 1461 */ 1462 void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 1463 const struct alpha_pll_config *config) 1464 { 1465 /* 1466 * If the bootloader left the PLL enabled it's likely that there are 1467 * RCGs that will lock up if we disable the PLL below. 1468 */ 1469 if (trion_pll_is_enabled(pll, regmap)) { 1470 pr_debug("Trion PLL is already enabled, skipping configuration\n"); 1471 return; 1472 } 1473 1474 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 1475 regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL); 1476 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 1477 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), 1478 config->config_ctl_val); 1479 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), 1480 config->config_ctl_hi_val); 1481 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), 1482 config->config_ctl_hi1_val); 1483 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), 1484 config->user_ctl_val); 1485 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), 1486 config->user_ctl_hi_val); 1487 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), 1488 config->user_ctl_hi1_val); 1489 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), 1490 config->test_ctl_val); 1491 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), 1492 config->test_ctl_hi_val); 1493 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), 1494 config->test_ctl_hi1_val); 1495 1496 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS, 1497 PLL_UPDATE_BYPASS); 1498 1499 /* Disable PLL output */ 1500 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1501 1502 /* Set operation mode to OFF */ 1503 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 1504 1505 /* Place the PLL in STANDBY mode */ 1506 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 1507 } 1508 EXPORT_SYMBOL_GPL(clk_trion_pll_configure); 1509 1510 /* 1511 * The TRION PLL requires a power-on self-calibration which happens when the 1512 * PLL comes out of reset. Calibrate in case it is not completed. 1513 */ 1514 static int __alpha_pll_trion_prepare(struct clk_hw *hw, u32 pcal_done) 1515 { 1516 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1517 u32 val; 1518 int ret; 1519 1520 /* Return early if calibration is not needed. */ 1521 regmap_read(pll->clkr.regmap, PLL_STATUS(pll), &val); 1522 if (val & pcal_done) 1523 return 0; 1524 1525 /* On/off to calibrate */ 1526 ret = clk_trion_pll_enable(hw); 1527 if (!ret) 1528 clk_trion_pll_disable(hw); 1529 1530 return ret; 1531 } 1532 1533 static int alpha_pll_trion_prepare(struct clk_hw *hw) 1534 { 1535 return __alpha_pll_trion_prepare(hw, TRION_PCAL_DONE); 1536 } 1537 1538 static int alpha_pll_lucid_prepare(struct clk_hw *hw) 1539 { 1540 return __alpha_pll_trion_prepare(hw, LUCID_PCAL_DONE); 1541 } 1542 1543 static int __alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate, 1544 unsigned long prate, u32 latch_bit, u32 latch_ack) 1545 { 1546 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1547 unsigned long rrate; 1548 u32 val, l, alpha_width = pll_alpha_width(pll); 1549 u64 a; 1550 int ret; 1551 1552 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 1553 1554 ret = alpha_pll_check_rate_margin(hw, rrate, rate); 1555 if (ret < 0) 1556 return ret; 1557 1558 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 1559 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 1560 1561 /* Latch the PLL input */ 1562 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, latch_bit); 1563 if (ret) 1564 return ret; 1565 1566 /* Wait for 2 reference cycles before checking the ACK bit. */ 1567 udelay(1); 1568 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 1569 if (!(val & latch_ack)) { 1570 pr_err("Lucid PLL latch failed. Output may be unstable!\n"); 1571 return -EINVAL; 1572 } 1573 1574 /* Return the latch input to 0 */ 1575 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, 0); 1576 if (ret) 1577 return ret; 1578 1579 if (clk_hw_is_enabled(hw)) { 1580 ret = wait_for_pll_enable_lock(pll); 1581 if (ret) 1582 return ret; 1583 } 1584 1585 /* Wait for PLL output to stabilize */ 1586 udelay(100); 1587 return 0; 1588 } 1589 1590 static int alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate, 1591 unsigned long prate) 1592 { 1593 return __alpha_pll_trion_set_rate(hw, rate, prate, PLL_UPDATE, ALPHA_PLL_ACK_LATCH); 1594 } 1595 1596 const struct clk_ops clk_alpha_pll_trion_ops = { 1597 .prepare = alpha_pll_trion_prepare, 1598 .enable = clk_trion_pll_enable, 1599 .disable = clk_trion_pll_disable, 1600 .is_enabled = clk_trion_pll_is_enabled, 1601 .recalc_rate = clk_trion_pll_recalc_rate, 1602 .round_rate = clk_alpha_pll_round_rate, 1603 .set_rate = alpha_pll_trion_set_rate, 1604 }; 1605 EXPORT_SYMBOL_GPL(clk_alpha_pll_trion_ops); 1606 1607 const struct clk_ops clk_alpha_pll_lucid_ops = { 1608 .prepare = alpha_pll_lucid_prepare, 1609 .enable = clk_trion_pll_enable, 1610 .disable = clk_trion_pll_disable, 1611 .is_enabled = clk_trion_pll_is_enabled, 1612 .recalc_rate = clk_trion_pll_recalc_rate, 1613 .round_rate = clk_alpha_pll_round_rate, 1614 .set_rate = alpha_pll_trion_set_rate, 1615 }; 1616 EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_ops); 1617 1618 const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = { 1619 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate, 1620 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate, 1621 .set_rate = clk_alpha_pll_postdiv_fabia_set_rate, 1622 }; 1623 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_ops); 1624 1625 void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 1626 const struct alpha_pll_config *config) 1627 { 1628 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 1629 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 1630 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), 1631 config->user_ctl_val); 1632 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), 1633 config->config_ctl_val); 1634 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), 1635 config->config_ctl_hi_val); 1636 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), 1637 config->test_ctl_val); 1638 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), 1639 config->test_ctl_hi_val); 1640 } 1641 EXPORT_SYMBOL_GPL(clk_agera_pll_configure); 1642 1643 static int clk_alpha_pll_agera_set_rate(struct clk_hw *hw, unsigned long rate, 1644 unsigned long prate) 1645 { 1646 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1647 u32 l, alpha_width = pll_alpha_width(pll); 1648 int ret; 1649 unsigned long rrate; 1650 u64 a; 1651 1652 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 1653 ret = alpha_pll_check_rate_margin(hw, rrate, rate); 1654 if (ret < 0) 1655 return ret; 1656 1657 /* change L_VAL without having to go through the power on sequence */ 1658 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 1659 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 1660 1661 if (clk_hw_is_enabled(hw)) 1662 return wait_for_pll_enable_lock(pll); 1663 1664 return 0; 1665 } 1666 1667 const struct clk_ops clk_alpha_pll_agera_ops = { 1668 .enable = clk_alpha_pll_enable, 1669 .disable = clk_alpha_pll_disable, 1670 .is_enabled = clk_alpha_pll_is_enabled, 1671 .recalc_rate = alpha_pll_fabia_recalc_rate, 1672 .round_rate = clk_alpha_pll_round_rate, 1673 .set_rate = clk_alpha_pll_agera_set_rate, 1674 }; 1675 EXPORT_SYMBOL_GPL(clk_alpha_pll_agera_ops); 1676 1677 static int alpha_pll_lucid_5lpe_enable(struct clk_hw *hw) 1678 { 1679 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1680 u32 val; 1681 int ret; 1682 1683 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); 1684 if (ret) 1685 return ret; 1686 1687 /* If in FSM mode, just vote for it */ 1688 if (val & LUCID_5LPE_ENABLE_VOTE_RUN) { 1689 ret = clk_enable_regmap(hw); 1690 if (ret) 1691 return ret; 1692 return wait_for_pll_enable_lock(pll); 1693 } 1694 1695 /* Check if PLL is already enabled, return if enabled */ 1696 ret = trion_pll_is_enabled(pll, pll->clkr.regmap); 1697 if (ret < 0) 1698 return ret; 1699 1700 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 1701 if (ret) 1702 return ret; 1703 1704 regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_RUN); 1705 1706 ret = wait_for_pll_enable_lock(pll); 1707 if (ret) 1708 return ret; 1709 1710 /* Enable the PLL outputs */ 1711 ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK); 1712 if (ret) 1713 return ret; 1714 1715 /* Enable the global PLL outputs */ 1716 return regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); 1717 } 1718 1719 static void alpha_pll_lucid_5lpe_disable(struct clk_hw *hw) 1720 { 1721 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1722 u32 val; 1723 int ret; 1724 1725 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); 1726 if (ret) 1727 return; 1728 1729 /* If in FSM mode, just unvote it */ 1730 if (val & LUCID_5LPE_ENABLE_VOTE_RUN) { 1731 clk_disable_regmap(hw); 1732 return; 1733 } 1734 1735 /* Disable the global PLL output */ 1736 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1737 if (ret) 1738 return; 1739 1740 /* Disable the PLL outputs */ 1741 ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); 1742 if (ret) 1743 return; 1744 1745 /* Place the PLL mode in STANDBY */ 1746 regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_STANDBY); 1747 } 1748 1749 /* 1750 * The Lucid 5LPE PLL requires a power-on self-calibration which happens 1751 * when the PLL comes out of reset. Calibrate in case it is not completed. 1752 */ 1753 static int alpha_pll_lucid_5lpe_prepare(struct clk_hw *hw) 1754 { 1755 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1756 struct clk_hw *p; 1757 u32 val = 0; 1758 int ret; 1759 1760 /* Return early if calibration is not needed. */ 1761 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 1762 if (val & LUCID_5LPE_PCAL_DONE) 1763 return 0; 1764 1765 p = clk_hw_get_parent(hw); 1766 if (!p) 1767 return -EINVAL; 1768 1769 ret = alpha_pll_lucid_5lpe_enable(hw); 1770 if (ret) 1771 return ret; 1772 1773 alpha_pll_lucid_5lpe_disable(hw); 1774 1775 return 0; 1776 } 1777 1778 static int alpha_pll_lucid_5lpe_set_rate(struct clk_hw *hw, unsigned long rate, 1779 unsigned long prate) 1780 { 1781 return __alpha_pll_trion_set_rate(hw, rate, prate, 1782 LUCID_5LPE_PLL_LATCH_INPUT, 1783 LUCID_5LPE_ALPHA_PLL_ACK_LATCH); 1784 } 1785 1786 static int __clk_lucid_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 1787 unsigned long parent_rate, 1788 unsigned long enable_vote_run) 1789 { 1790 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1791 struct regmap *regmap = pll->clkr.regmap; 1792 int i, val, div, ret; 1793 u32 mask; 1794 1795 /* 1796 * If the PLL is in FSM mode, then treat set_rate callback as a 1797 * no-operation. 1798 */ 1799 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); 1800 if (ret) 1801 return ret; 1802 1803 if (val & enable_vote_run) 1804 return 0; 1805 1806 if (!pll->post_div_table) { 1807 pr_err("Missing the post_div_table for the %s PLL\n", 1808 clk_hw_get_name(&pll->clkr.hw)); 1809 return -EINVAL; 1810 } 1811 1812 div = DIV_ROUND_UP_ULL((u64)parent_rate, rate); 1813 for (i = 0; i < pll->num_post_div; i++) { 1814 if (pll->post_div_table[i].div == div) { 1815 val = pll->post_div_table[i].val; 1816 break; 1817 } 1818 } 1819 1820 mask = GENMASK(pll->width + pll->post_div_shift - 1, pll->post_div_shift); 1821 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 1822 mask, val << pll->post_div_shift); 1823 } 1824 1825 static int clk_lucid_5lpe_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 1826 unsigned long parent_rate) 1827 { 1828 return __clk_lucid_pll_postdiv_set_rate(hw, rate, parent_rate, LUCID_5LPE_ENABLE_VOTE_RUN); 1829 } 1830 1831 const struct clk_ops clk_alpha_pll_lucid_5lpe_ops = { 1832 .prepare = alpha_pll_lucid_5lpe_prepare, 1833 .enable = alpha_pll_lucid_5lpe_enable, 1834 .disable = alpha_pll_lucid_5lpe_disable, 1835 .is_enabled = clk_trion_pll_is_enabled, 1836 .recalc_rate = clk_trion_pll_recalc_rate, 1837 .round_rate = clk_alpha_pll_round_rate, 1838 .set_rate = alpha_pll_lucid_5lpe_set_rate, 1839 }; 1840 EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_5lpe_ops); 1841 1842 const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops = { 1843 .enable = alpha_pll_lucid_5lpe_enable, 1844 .disable = alpha_pll_lucid_5lpe_disable, 1845 .is_enabled = clk_trion_pll_is_enabled, 1846 .recalc_rate = clk_trion_pll_recalc_rate, 1847 .round_rate = clk_alpha_pll_round_rate, 1848 }; 1849 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_5lpe_ops); 1850 1851 const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops = { 1852 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate, 1853 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate, 1854 .set_rate = clk_lucid_5lpe_pll_postdiv_set_rate, 1855 }; 1856 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_5lpe_ops); 1857 1858 void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 1859 const struct alpha_pll_config *config) 1860 { 1861 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 1862 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 1863 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 1864 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); 1865 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); 1866 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); 1867 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); 1868 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), config->user_ctl_hi1_val); 1869 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 1870 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 1871 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); 1872 1873 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, 0); 1874 1875 /* Disable PLL output */ 1876 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1877 1878 /* Set operation mode to OFF */ 1879 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 1880 1881 /* Place the PLL in STANDBY mode */ 1882 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 1883 } 1884 EXPORT_SYMBOL_GPL(clk_zonda_pll_configure); 1885 1886 static int clk_zonda_pll_enable(struct clk_hw *hw) 1887 { 1888 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1889 struct regmap *regmap = pll->clkr.regmap; 1890 u32 val; 1891 int ret; 1892 1893 regmap_read(regmap, PLL_MODE(pll), &val); 1894 1895 /* If in FSM mode, just vote for it */ 1896 if (val & PLL_VOTE_FSM_ENA) { 1897 ret = clk_enable_regmap(hw); 1898 if (ret) 1899 return ret; 1900 return wait_for_pll_enable_active(pll); 1901 } 1902 1903 /* Get the PLL out of bypass mode */ 1904 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL); 1905 1906 /* 1907 * H/W requires a 1us delay between disabling the bypass and 1908 * de-asserting the reset. 1909 */ 1910 udelay(1); 1911 1912 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 1913 1914 /* Set operation mode to RUN */ 1915 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); 1916 1917 regmap_read(regmap, PLL_TEST_CTL(pll), &val); 1918 1919 /* If cfa mode then poll for freq lock */ 1920 if (val & ZONDA_STAY_IN_CFA) 1921 ret = wait_for_zonda_pll_freq_lock(pll); 1922 else 1923 ret = wait_for_pll_enable_lock(pll); 1924 if (ret) 1925 return ret; 1926 1927 /* Enable the PLL outputs */ 1928 regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, ZONDA_PLL_OUT_MASK); 1929 1930 /* Enable the global PLL outputs */ 1931 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); 1932 1933 return 0; 1934 } 1935 1936 static void clk_zonda_pll_disable(struct clk_hw *hw) 1937 { 1938 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1939 struct regmap *regmap = pll->clkr.regmap; 1940 u32 val; 1941 1942 regmap_read(regmap, PLL_MODE(pll), &val); 1943 1944 /* If in FSM mode, just unvote it */ 1945 if (val & PLL_VOTE_FSM_ENA) { 1946 clk_disable_regmap(hw); 1947 return; 1948 } 1949 1950 /* Disable the global PLL output */ 1951 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1952 1953 /* Disable the PLL outputs */ 1954 regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, 0); 1955 1956 /* Put the PLL in bypass and reset */ 1957 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N | PLL_BYPASSNL, 0); 1958 1959 /* Place the PLL mode in OFF state */ 1960 regmap_write(regmap, PLL_OPMODE(pll), 0x0); 1961 } 1962 1963 static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate, 1964 unsigned long prate) 1965 { 1966 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1967 unsigned long rrate; 1968 u32 test_ctl_val; 1969 u32 l, alpha_width = pll_alpha_width(pll); 1970 u64 a; 1971 int ret; 1972 1973 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 1974 1975 ret = alpha_pll_check_rate_margin(hw, rrate, rate); 1976 if (ret < 0) 1977 return ret; 1978 1979 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 1980 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 1981 1982 /* Wait before polling for the frequency latch */ 1983 udelay(5); 1984 1985 /* Read stay in cfa mode */ 1986 regmap_read(pll->clkr.regmap, PLL_TEST_CTL(pll), &test_ctl_val); 1987 1988 /* If cfa mode then poll for freq lock */ 1989 if (test_ctl_val & ZONDA_STAY_IN_CFA) 1990 ret = wait_for_zonda_pll_freq_lock(pll); 1991 else 1992 ret = wait_for_pll_enable_lock(pll); 1993 if (ret) 1994 return ret; 1995 1996 /* Wait for PLL output to stabilize */ 1997 udelay(100); 1998 return 0; 1999 } 2000 2001 const struct clk_ops clk_alpha_pll_zonda_ops = { 2002 .enable = clk_zonda_pll_enable, 2003 .disable = clk_zonda_pll_disable, 2004 .is_enabled = clk_trion_pll_is_enabled, 2005 .recalc_rate = clk_trion_pll_recalc_rate, 2006 .round_rate = clk_alpha_pll_round_rate, 2007 .set_rate = clk_zonda_pll_set_rate, 2008 }; 2009 EXPORT_SYMBOL_GPL(clk_alpha_pll_zonda_ops); 2010 2011 void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 2012 const struct alpha_pll_config *config) 2013 { 2014 u32 lval = config->l; 2015 2016 lval |= TRION_PLL_CAL_VAL << LUCID_EVO_PLL_CAL_L_VAL_SHIFT; 2017 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval); 2018 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 2019 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 2020 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); 2021 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); 2022 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); 2023 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); 2024 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 2025 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 2026 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); 2027 2028 /* Disable PLL output */ 2029 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 2030 2031 /* Set operation mode to STANDBY and de-assert the reset */ 2032 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 2033 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 2034 } 2035 EXPORT_SYMBOL_GPL(clk_lucid_evo_pll_configure); 2036 2037 static int alpha_pll_lucid_evo_enable(struct clk_hw *hw) 2038 { 2039 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2040 struct regmap *regmap = pll->clkr.regmap; 2041 u32 val; 2042 int ret; 2043 2044 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); 2045 if (ret) 2046 return ret; 2047 2048 /* If in FSM mode, just vote for it */ 2049 if (val & LUCID_EVO_ENABLE_VOTE_RUN) { 2050 ret = clk_enable_regmap(hw); 2051 if (ret) 2052 return ret; 2053 return wait_for_pll_enable_lock(pll); 2054 } 2055 2056 /* Check if PLL is already enabled */ 2057 ret = trion_pll_is_enabled(pll, regmap); 2058 if (ret < 0) { 2059 return ret; 2060 } else if (ret) { 2061 pr_warn("%s PLL is already enabled\n", clk_hw_get_name(&pll->clkr.hw)); 2062 return 0; 2063 } 2064 2065 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 2066 if (ret) 2067 return ret; 2068 2069 /* Set operation mode to RUN */ 2070 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); 2071 2072 ret = wait_for_pll_enable_lock(pll); 2073 if (ret) 2074 return ret; 2075 2076 /* Enable the PLL outputs */ 2077 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK); 2078 if (ret) 2079 return ret; 2080 2081 /* Enable the global PLL outputs */ 2082 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); 2083 if (ret) 2084 return ret; 2085 2086 /* Ensure that the write above goes through before returning. */ 2087 mb(); 2088 return ret; 2089 } 2090 2091 static void alpha_pll_lucid_evo_disable(struct clk_hw *hw) 2092 { 2093 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2094 struct regmap *regmap = pll->clkr.regmap; 2095 u32 val; 2096 int ret; 2097 2098 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); 2099 if (ret) 2100 return; 2101 2102 /* If in FSM mode, just unvote it */ 2103 if (val & LUCID_EVO_ENABLE_VOTE_RUN) { 2104 clk_disable_regmap(hw); 2105 return; 2106 } 2107 2108 /* Disable the global PLL output */ 2109 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 2110 if (ret) 2111 return; 2112 2113 /* Disable the PLL outputs */ 2114 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); 2115 if (ret) 2116 return; 2117 2118 /* Place the PLL mode in STANDBY */ 2119 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 2120 } 2121 2122 static int alpha_pll_lucid_evo_prepare(struct clk_hw *hw) 2123 { 2124 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2125 struct clk_hw *p; 2126 u32 val = 0; 2127 int ret; 2128 2129 /* Return early if calibration is not needed. */ 2130 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 2131 if (!(val & LUCID_EVO_PCAL_NOT_DONE)) 2132 return 0; 2133 2134 p = clk_hw_get_parent(hw); 2135 if (!p) 2136 return -EINVAL; 2137 2138 ret = alpha_pll_lucid_evo_enable(hw); 2139 if (ret) 2140 return ret; 2141 2142 alpha_pll_lucid_evo_disable(hw); 2143 2144 return 0; 2145 } 2146 2147 static unsigned long alpha_pll_lucid_evo_recalc_rate(struct clk_hw *hw, 2148 unsigned long parent_rate) 2149 { 2150 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2151 struct regmap *regmap = pll->clkr.regmap; 2152 u32 l, frac; 2153 2154 regmap_read(regmap, PLL_L_VAL(pll), &l); 2155 l &= LUCID_EVO_PLL_L_VAL_MASK; 2156 regmap_read(regmap, PLL_ALPHA_VAL(pll), &frac); 2157 2158 return alpha_pll_calc_rate(parent_rate, l, frac, pll_alpha_width(pll)); 2159 } 2160 2161 static int clk_lucid_evo_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 2162 unsigned long parent_rate) 2163 { 2164 return __clk_lucid_pll_postdiv_set_rate(hw, rate, parent_rate, LUCID_EVO_ENABLE_VOTE_RUN); 2165 } 2166 2167 const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops = { 2168 .enable = alpha_pll_lucid_evo_enable, 2169 .disable = alpha_pll_lucid_evo_disable, 2170 .is_enabled = clk_trion_pll_is_enabled, 2171 .recalc_rate = alpha_pll_lucid_evo_recalc_rate, 2172 .round_rate = clk_alpha_pll_round_rate, 2173 }; 2174 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_evo_ops); 2175 2176 const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops = { 2177 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate, 2178 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate, 2179 .set_rate = clk_lucid_evo_pll_postdiv_set_rate, 2180 }; 2181 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_evo_ops); 2182 2183 const struct clk_ops clk_alpha_pll_lucid_evo_ops = { 2184 .prepare = alpha_pll_lucid_evo_prepare, 2185 .enable = alpha_pll_lucid_evo_enable, 2186 .disable = alpha_pll_lucid_evo_disable, 2187 .is_enabled = clk_trion_pll_is_enabled, 2188 .recalc_rate = alpha_pll_lucid_evo_recalc_rate, 2189 .round_rate = clk_alpha_pll_round_rate, 2190 .set_rate = alpha_pll_lucid_5lpe_set_rate, 2191 }; 2192 EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_evo_ops); 2193 2194 void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 2195 const struct alpha_pll_config *config) 2196 { 2197 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 2198 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); 2199 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); 2200 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 2201 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 2202 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 2203 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); 2204 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); 2205 2206 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 2207 2208 regmap_update_bits(regmap, PLL_MODE(pll), 2209 PLL_RESET_N | PLL_BYPASSNL | PLL_OUTCTRL, 2210 PLL_RESET_N | PLL_BYPASSNL); 2211 } 2212 EXPORT_SYMBOL_GPL(clk_rivian_evo_pll_configure); 2213 2214 static unsigned long clk_rivian_evo_pll_recalc_rate(struct clk_hw *hw, 2215 unsigned long parent_rate) 2216 { 2217 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2218 u32 l; 2219 2220 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); 2221 2222 return parent_rate * l; 2223 } 2224 2225 static long clk_rivian_evo_pll_round_rate(struct clk_hw *hw, unsigned long rate, 2226 unsigned long *prate) 2227 { 2228 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2229 unsigned long min_freq, max_freq; 2230 u32 l; 2231 u64 a; 2232 2233 rate = alpha_pll_round_rate(rate, *prate, &l, &a, 0); 2234 if (!pll->vco_table || alpha_pll_find_vco(pll, rate)) 2235 return rate; 2236 2237 min_freq = pll->vco_table[0].min_freq; 2238 max_freq = pll->vco_table[pll->num_vco - 1].max_freq; 2239 2240 return clamp(rate, min_freq, max_freq); 2241 } 2242 2243 const struct clk_ops clk_alpha_pll_rivian_evo_ops = { 2244 .enable = alpha_pll_lucid_5lpe_enable, 2245 .disable = alpha_pll_lucid_5lpe_disable, 2246 .is_enabled = clk_trion_pll_is_enabled, 2247 .recalc_rate = clk_rivian_evo_pll_recalc_rate, 2248 .round_rate = clk_rivian_evo_pll_round_rate, 2249 }; 2250 EXPORT_SYMBOL_GPL(clk_alpha_pll_rivian_evo_ops); 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