1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021, 2023, Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #include <linux/kernel.h> 8 #include <linux/export.h> 9 #include <linux/clk-provider.h> 10 #include <linux/regmap.h> 11 #include <linux/delay.h> 12 13 #include "clk-alpha-pll.h" 14 #include "common.h" 15 16 #define PLL_MODE(p) ((p)->offset + 0x0) 17 # define PLL_OUTCTRL BIT(0) 18 # define PLL_BYPASSNL BIT(1) 19 # define PLL_RESET_N BIT(2) 20 # define PLL_OFFLINE_REQ BIT(7) 21 # define PLL_LOCK_COUNT_SHIFT 8 22 # define PLL_LOCK_COUNT_MASK 0x3f 23 # define PLL_BIAS_COUNT_SHIFT 14 24 # define PLL_BIAS_COUNT_MASK 0x3f 25 # define PLL_VOTE_FSM_ENA BIT(20) 26 # define PLL_FSM_ENA BIT(20) 27 # define PLL_VOTE_FSM_RESET BIT(21) 28 # define PLL_UPDATE BIT(22) 29 # define PLL_UPDATE_BYPASS BIT(23) 30 # define PLL_FSM_LEGACY_MODE BIT(24) 31 # define PLL_OFFLINE_ACK BIT(28) 32 # define ALPHA_PLL_ACK_LATCH BIT(29) 33 # define PLL_ACTIVE_FLAG BIT(30) 34 # define PLL_LOCK_DET BIT(31) 35 36 #define PLL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_L_VAL]) 37 #define PLL_CAL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_CAL_L_VAL]) 38 #define PLL_ALPHA_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL]) 39 #define PLL_ALPHA_VAL_U(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL_U]) 40 41 #define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL]) 42 # define PLL_POST_DIV_SHIFT 8 43 # define PLL_POST_DIV_MASK(p) GENMASK((p)->width, 0) 44 # define PLL_ALPHA_EN BIT(24) 45 # define PLL_ALPHA_MODE BIT(25) 46 # define PLL_VCO_SHIFT 20 47 # define PLL_VCO_MASK 0x3 48 49 #define PLL_USER_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U]) 50 #define PLL_USER_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U1]) 51 52 #define PLL_CONFIG_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL]) 53 #define PLL_CONFIG_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U]) 54 #define PLL_CONFIG_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U1]) 55 #define PLL_TEST_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL]) 56 #define PLL_TEST_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U]) 57 #define PLL_TEST_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U1]) 58 #define PLL_TEST_CTL_U2(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U2]) 59 #define PLL_STATUS(p) ((p)->offset + (p)->regs[PLL_OFF_STATUS]) 60 #define PLL_OPMODE(p) ((p)->offset + (p)->regs[PLL_OFF_OPMODE]) 61 #define PLL_FRAC(p) ((p)->offset + (p)->regs[PLL_OFF_FRAC]) 62 63 const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { 64 [CLK_ALPHA_PLL_TYPE_DEFAULT] = { 65 [PLL_OFF_L_VAL] = 0x04, 66 [PLL_OFF_ALPHA_VAL] = 0x08, 67 [PLL_OFF_ALPHA_VAL_U] = 0x0c, 68 [PLL_OFF_USER_CTL] = 0x10, 69 [PLL_OFF_USER_CTL_U] = 0x14, 70 [PLL_OFF_CONFIG_CTL] = 0x18, 71 [PLL_OFF_TEST_CTL] = 0x1c, 72 [PLL_OFF_TEST_CTL_U] = 0x20, 73 [PLL_OFF_STATUS] = 0x24, 74 }, 75 [CLK_ALPHA_PLL_TYPE_HUAYRA] = { 76 [PLL_OFF_L_VAL] = 0x04, 77 [PLL_OFF_ALPHA_VAL] = 0x08, 78 [PLL_OFF_USER_CTL] = 0x10, 79 [PLL_OFF_CONFIG_CTL] = 0x14, 80 [PLL_OFF_CONFIG_CTL_U] = 0x18, 81 [PLL_OFF_TEST_CTL] = 0x1c, 82 [PLL_OFF_TEST_CTL_U] = 0x20, 83 [PLL_OFF_STATUS] = 0x24, 84 }, 85 [CLK_ALPHA_PLL_TYPE_BRAMMO] = { 86 [PLL_OFF_L_VAL] = 0x04, 87 [PLL_OFF_ALPHA_VAL] = 0x08, 88 [PLL_OFF_ALPHA_VAL_U] = 0x0c, 89 [PLL_OFF_USER_CTL] = 0x10, 90 [PLL_OFF_CONFIG_CTL] = 0x18, 91 [PLL_OFF_TEST_CTL] = 0x1c, 92 [PLL_OFF_STATUS] = 0x24, 93 }, 94 [CLK_ALPHA_PLL_TYPE_FABIA] = { 95 [PLL_OFF_L_VAL] = 0x04, 96 [PLL_OFF_USER_CTL] = 0x0c, 97 [PLL_OFF_USER_CTL_U] = 0x10, 98 [PLL_OFF_CONFIG_CTL] = 0x14, 99 [PLL_OFF_CONFIG_CTL_U] = 0x18, 100 [PLL_OFF_TEST_CTL] = 0x1c, 101 [PLL_OFF_TEST_CTL_U] = 0x20, 102 [PLL_OFF_STATUS] = 0x24, 103 [PLL_OFF_OPMODE] = 0x2c, 104 [PLL_OFF_FRAC] = 0x38, 105 }, 106 [CLK_ALPHA_PLL_TYPE_TRION] = { 107 [PLL_OFF_L_VAL] = 0x04, 108 [PLL_OFF_CAL_L_VAL] = 0x08, 109 [PLL_OFF_USER_CTL] = 0x0c, 110 [PLL_OFF_USER_CTL_U] = 0x10, 111 [PLL_OFF_USER_CTL_U1] = 0x14, 112 [PLL_OFF_CONFIG_CTL] = 0x18, 113 [PLL_OFF_CONFIG_CTL_U] = 0x1c, 114 [PLL_OFF_CONFIG_CTL_U1] = 0x20, 115 [PLL_OFF_TEST_CTL] = 0x24, 116 [PLL_OFF_TEST_CTL_U] = 0x28, 117 [PLL_OFF_TEST_CTL_U1] = 0x2c, 118 [PLL_OFF_STATUS] = 0x30, 119 [PLL_OFF_OPMODE] = 0x38, 120 [PLL_OFF_ALPHA_VAL] = 0x40, 121 }, 122 [CLK_ALPHA_PLL_TYPE_AGERA] = { 123 [PLL_OFF_L_VAL] = 0x04, 124 [PLL_OFF_ALPHA_VAL] = 0x08, 125 [PLL_OFF_USER_CTL] = 0x0c, 126 [PLL_OFF_CONFIG_CTL] = 0x10, 127 [PLL_OFF_CONFIG_CTL_U] = 0x14, 128 [PLL_OFF_TEST_CTL] = 0x18, 129 [PLL_OFF_TEST_CTL_U] = 0x1c, 130 [PLL_OFF_STATUS] = 0x2c, 131 }, 132 [CLK_ALPHA_PLL_TYPE_ZONDA] = { 133 [PLL_OFF_L_VAL] = 0x04, 134 [PLL_OFF_ALPHA_VAL] = 0x08, 135 [PLL_OFF_USER_CTL] = 0x0c, 136 [PLL_OFF_CONFIG_CTL] = 0x10, 137 [PLL_OFF_CONFIG_CTL_U] = 0x14, 138 [PLL_OFF_CONFIG_CTL_U1] = 0x18, 139 [PLL_OFF_TEST_CTL] = 0x1c, 140 [PLL_OFF_TEST_CTL_U] = 0x20, 141 [PLL_OFF_TEST_CTL_U1] = 0x24, 142 [PLL_OFF_OPMODE] = 0x28, 143 [PLL_OFF_STATUS] = 0x38, 144 }, 145 [CLK_ALPHA_PLL_TYPE_LUCID_EVO] = { 146 [PLL_OFF_OPMODE] = 0x04, 147 [PLL_OFF_STATUS] = 0x0c, 148 [PLL_OFF_L_VAL] = 0x10, 149 [PLL_OFF_ALPHA_VAL] = 0x14, 150 [PLL_OFF_USER_CTL] = 0x18, 151 [PLL_OFF_USER_CTL_U] = 0x1c, 152 [PLL_OFF_CONFIG_CTL] = 0x20, 153 [PLL_OFF_CONFIG_CTL_U] = 0x24, 154 [PLL_OFF_CONFIG_CTL_U1] = 0x28, 155 [PLL_OFF_TEST_CTL] = 0x2c, 156 [PLL_OFF_TEST_CTL_U] = 0x30, 157 [PLL_OFF_TEST_CTL_U1] = 0x34, 158 }, 159 [CLK_ALPHA_PLL_TYPE_LUCID_OLE] = { 160 [PLL_OFF_OPMODE] = 0x04, 161 [PLL_OFF_STATE] = 0x08, 162 [PLL_OFF_STATUS] = 0x0c, 163 [PLL_OFF_L_VAL] = 0x10, 164 [PLL_OFF_ALPHA_VAL] = 0x14, 165 [PLL_OFF_USER_CTL] = 0x18, 166 [PLL_OFF_USER_CTL_U] = 0x1c, 167 [PLL_OFF_CONFIG_CTL] = 0x20, 168 [PLL_OFF_CONFIG_CTL_U] = 0x24, 169 [PLL_OFF_CONFIG_CTL_U1] = 0x28, 170 [PLL_OFF_TEST_CTL] = 0x2c, 171 [PLL_OFF_TEST_CTL_U] = 0x30, 172 [PLL_OFF_TEST_CTL_U1] = 0x34, 173 [PLL_OFF_TEST_CTL_U2] = 0x38, 174 }, 175 [CLK_ALPHA_PLL_TYPE_RIVIAN_EVO] = { 176 [PLL_OFF_OPMODE] = 0x04, 177 [PLL_OFF_STATUS] = 0x0c, 178 [PLL_OFF_L_VAL] = 0x10, 179 [PLL_OFF_USER_CTL] = 0x14, 180 [PLL_OFF_USER_CTL_U] = 0x18, 181 [PLL_OFF_CONFIG_CTL] = 0x1c, 182 [PLL_OFF_CONFIG_CTL_U] = 0x20, 183 [PLL_OFF_CONFIG_CTL_U1] = 0x24, 184 [PLL_OFF_TEST_CTL] = 0x28, 185 [PLL_OFF_TEST_CTL_U] = 0x2c, 186 }, 187 [CLK_ALPHA_PLL_TYPE_DEFAULT_EVO] = { 188 [PLL_OFF_L_VAL] = 0x04, 189 [PLL_OFF_ALPHA_VAL] = 0x08, 190 [PLL_OFF_ALPHA_VAL_U] = 0x0c, 191 [PLL_OFF_TEST_CTL] = 0x10, 192 [PLL_OFF_TEST_CTL_U] = 0x14, 193 [PLL_OFF_USER_CTL] = 0x18, 194 [PLL_OFF_USER_CTL_U] = 0x1c, 195 [PLL_OFF_CONFIG_CTL] = 0x20, 196 [PLL_OFF_STATUS] = 0x24, 197 }, 198 [CLK_ALPHA_PLL_TYPE_BRAMMO_EVO] = { 199 [PLL_OFF_L_VAL] = 0x04, 200 [PLL_OFF_ALPHA_VAL] = 0x08, 201 [PLL_OFF_ALPHA_VAL_U] = 0x0c, 202 [PLL_OFF_TEST_CTL] = 0x10, 203 [PLL_OFF_TEST_CTL_U] = 0x14, 204 [PLL_OFF_USER_CTL] = 0x18, 205 [PLL_OFF_CONFIG_CTL] = 0x1C, 206 [PLL_OFF_STATUS] = 0x20, 207 }, 208 [CLK_ALPHA_PLL_TYPE_STROMER] = { 209 [PLL_OFF_L_VAL] = 0x08, 210 [PLL_OFF_ALPHA_VAL] = 0x10, 211 [PLL_OFF_ALPHA_VAL_U] = 0x14, 212 [PLL_OFF_USER_CTL] = 0x18, 213 [PLL_OFF_USER_CTL_U] = 0x1c, 214 [PLL_OFF_CONFIG_CTL] = 0x20, 215 [PLL_OFF_TEST_CTL] = 0x30, 216 [PLL_OFF_TEST_CTL_U] = 0x34, 217 [PLL_OFF_STATUS] = 0x28, 218 }, 219 [CLK_ALPHA_PLL_TYPE_STROMER_PLUS] = { 220 [PLL_OFF_L_VAL] = 0x04, 221 [PLL_OFF_USER_CTL] = 0x08, 222 [PLL_OFF_USER_CTL_U] = 0x0c, 223 [PLL_OFF_CONFIG_CTL] = 0x10, 224 [PLL_OFF_TEST_CTL] = 0x14, 225 [PLL_OFF_TEST_CTL_U] = 0x18, 226 [PLL_OFF_STATUS] = 0x1c, 227 [PLL_OFF_ALPHA_VAL] = 0x24, 228 [PLL_OFF_ALPHA_VAL_U] = 0x28, 229 }, 230 }; 231 EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); 232 233 /* 234 * Even though 40 bits are present, use only 32 for ease of calculation. 235 */ 236 #define ALPHA_REG_BITWIDTH 40 237 #define ALPHA_REG_16BIT_WIDTH 16 238 #define ALPHA_BITWIDTH 32U 239 #define ALPHA_SHIFT(w) min(w, ALPHA_BITWIDTH) 240 241 #define ALPHA_PLL_STATUS_REG_SHIFT 8 242 243 #define PLL_HUAYRA_M_WIDTH 8 244 #define PLL_HUAYRA_M_SHIFT 8 245 #define PLL_HUAYRA_M_MASK 0xff 246 #define PLL_HUAYRA_N_SHIFT 0 247 #define PLL_HUAYRA_N_MASK 0xff 248 #define PLL_HUAYRA_ALPHA_WIDTH 16 249 250 #define PLL_STANDBY 0x0 251 #define PLL_RUN 0x1 252 #define PLL_OUT_MASK 0x7 253 #define PLL_RATE_MARGIN 500 254 255 /* TRION PLL specific settings and offsets */ 256 #define TRION_PLL_CAL_VAL 0x44 257 #define TRION_PCAL_DONE BIT(26) 258 259 /* LUCID PLL specific settings and offsets */ 260 #define LUCID_PCAL_DONE BIT(27) 261 262 /* LUCID 5LPE PLL specific settings and offsets */ 263 #define LUCID_5LPE_PCAL_DONE BIT(11) 264 #define LUCID_5LPE_ALPHA_PLL_ACK_LATCH BIT(13) 265 #define LUCID_5LPE_PLL_LATCH_INPUT BIT(14) 266 #define LUCID_5LPE_ENABLE_VOTE_RUN BIT(21) 267 268 /* LUCID EVO PLL specific settings and offsets */ 269 #define LUCID_EVO_PCAL_NOT_DONE BIT(8) 270 #define LUCID_EVO_ENABLE_VOTE_RUN BIT(25) 271 #define LUCID_EVO_PLL_L_VAL_MASK GENMASK(15, 0) 272 #define LUCID_EVO_PLL_CAL_L_VAL_SHIFT 16 273 274 /* ZONDA PLL specific */ 275 #define ZONDA_PLL_OUT_MASK 0xf 276 #define ZONDA_STAY_IN_CFA BIT(16) 277 #define ZONDA_PLL_FREQ_LOCK_DET BIT(29) 278 279 #define pll_alpha_width(p) \ 280 ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \ 281 ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH) 282 283 #define pll_has_64bit_config(p) ((PLL_CONFIG_CTL_U(p) - PLL_CONFIG_CTL(p)) == 4) 284 285 #define to_clk_alpha_pll(_hw) container_of(to_clk_regmap(_hw), \ 286 struct clk_alpha_pll, clkr) 287 288 #define to_clk_alpha_pll_postdiv(_hw) container_of(to_clk_regmap(_hw), \ 289 struct clk_alpha_pll_postdiv, clkr) 290 291 static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse, 292 const char *action) 293 { 294 u32 val; 295 int count; 296 int ret; 297 const char *name = clk_hw_get_name(&pll->clkr.hw); 298 299 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 300 if (ret) 301 return ret; 302 303 for (count = 200; count > 0; count--) { 304 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 305 if (ret) 306 return ret; 307 if (inverse && !(val & mask)) 308 return 0; 309 else if ((val & mask) == mask) 310 return 0; 311 312 udelay(1); 313 } 314 315 WARN(1, "%s failed to %s!\n", name, action); 316 return -ETIMEDOUT; 317 } 318 319 #define wait_for_pll_enable_active(pll) \ 320 wait_for_pll(pll, PLL_ACTIVE_FLAG, 0, "enable") 321 322 #define wait_for_pll_enable_lock(pll) \ 323 wait_for_pll(pll, PLL_LOCK_DET, 0, "enable") 324 325 #define wait_for_zonda_pll_freq_lock(pll) \ 326 wait_for_pll(pll, ZONDA_PLL_FREQ_LOCK_DET, 0, "freq enable") 327 328 #define wait_for_pll_disable(pll) \ 329 wait_for_pll(pll, PLL_ACTIVE_FLAG, 1, "disable") 330 331 #define wait_for_pll_offline(pll) \ 332 wait_for_pll(pll, PLL_OFFLINE_ACK, 0, "offline") 333 334 #define wait_for_pll_update(pll) \ 335 wait_for_pll(pll, PLL_UPDATE, 1, "update") 336 337 #define wait_for_pll_update_ack_set(pll) \ 338 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 0, "update_ack_set") 339 340 #define wait_for_pll_update_ack_clear(pll) \ 341 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 1, "update_ack_clear") 342 343 static void clk_alpha_pll_write_config(struct regmap *regmap, unsigned int reg, 344 unsigned int val) 345 { 346 if (val) 347 regmap_write(regmap, reg, val); 348 } 349 350 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 351 const struct alpha_pll_config *config) 352 { 353 u32 val, mask; 354 355 regmap_write(regmap, PLL_L_VAL(pll), config->l); 356 regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha); 357 regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 358 359 if (pll_has_64bit_config(pll)) 360 regmap_write(regmap, PLL_CONFIG_CTL_U(pll), 361 config->config_ctl_hi_val); 362 363 if (pll_alpha_width(pll) > 32) 364 regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi); 365 366 val = config->main_output_mask; 367 val |= config->aux_output_mask; 368 val |= config->aux2_output_mask; 369 val |= config->early_output_mask; 370 val |= config->pre_div_val; 371 val |= config->post_div_val; 372 val |= config->vco_val; 373 val |= config->alpha_en_mask; 374 val |= config->alpha_mode_mask; 375 376 mask = config->main_output_mask; 377 mask |= config->aux_output_mask; 378 mask |= config->aux2_output_mask; 379 mask |= config->early_output_mask; 380 mask |= config->pre_div_mask; 381 mask |= config->post_div_mask; 382 mask |= config->vco_mask; 383 384 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); 385 386 if (config->test_ctl_mask) 387 regmap_update_bits(regmap, PLL_TEST_CTL(pll), 388 config->test_ctl_mask, 389 config->test_ctl_val); 390 else 391 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), 392 config->test_ctl_val); 393 394 if (config->test_ctl_hi_mask) 395 regmap_update_bits(regmap, PLL_TEST_CTL_U(pll), 396 config->test_ctl_hi_mask, 397 config->test_ctl_hi_val); 398 else 399 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), 400 config->test_ctl_hi_val); 401 402 if (pll->flags & SUPPORTS_FSM_MODE) 403 qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0); 404 } 405 EXPORT_SYMBOL_GPL(clk_alpha_pll_configure); 406 407 static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw) 408 { 409 int ret; 410 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 411 u32 val; 412 413 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 414 if (ret) 415 return ret; 416 417 val |= PLL_FSM_ENA; 418 419 if (pll->flags & SUPPORTS_OFFLINE_REQ) 420 val &= ~PLL_OFFLINE_REQ; 421 422 ret = regmap_write(pll->clkr.regmap, PLL_MODE(pll), val); 423 if (ret) 424 return ret; 425 426 /* Make sure enable request goes through before waiting for update */ 427 mb(); 428 429 return wait_for_pll_enable_active(pll); 430 } 431 432 static void clk_alpha_pll_hwfsm_disable(struct clk_hw *hw) 433 { 434 int ret; 435 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 436 u32 val; 437 438 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 439 if (ret) 440 return; 441 442 if (pll->flags & SUPPORTS_OFFLINE_REQ) { 443 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 444 PLL_OFFLINE_REQ, PLL_OFFLINE_REQ); 445 if (ret) 446 return; 447 448 ret = wait_for_pll_offline(pll); 449 if (ret) 450 return; 451 } 452 453 /* Disable hwfsm */ 454 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 455 PLL_FSM_ENA, 0); 456 if (ret) 457 return; 458 459 wait_for_pll_disable(pll); 460 } 461 462 static int pll_is_enabled(struct clk_hw *hw, u32 mask) 463 { 464 int ret; 465 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 466 u32 val; 467 468 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 469 if (ret) 470 return ret; 471 472 return !!(val & mask); 473 } 474 475 static int clk_alpha_pll_hwfsm_is_enabled(struct clk_hw *hw) 476 { 477 return pll_is_enabled(hw, PLL_ACTIVE_FLAG); 478 } 479 480 static int clk_alpha_pll_is_enabled(struct clk_hw *hw) 481 { 482 return pll_is_enabled(hw, PLL_LOCK_DET); 483 } 484 485 static int clk_alpha_pll_enable(struct clk_hw *hw) 486 { 487 int ret; 488 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 489 u32 val, mask; 490 491 mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL; 492 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 493 if (ret) 494 return ret; 495 496 /* If in FSM mode, just vote for it */ 497 if (val & PLL_VOTE_FSM_ENA) { 498 ret = clk_enable_regmap(hw); 499 if (ret) 500 return ret; 501 return wait_for_pll_enable_active(pll); 502 } 503 504 /* Skip if already enabled */ 505 if ((val & mask) == mask) 506 return 0; 507 508 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 509 PLL_BYPASSNL, PLL_BYPASSNL); 510 if (ret) 511 return ret; 512 513 /* 514 * H/W requires a 5us delay between disabling the bypass and 515 * de-asserting the reset. 516 */ 517 mb(); 518 udelay(5); 519 520 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 521 PLL_RESET_N, PLL_RESET_N); 522 if (ret) 523 return ret; 524 525 ret = wait_for_pll_enable_lock(pll); 526 if (ret) 527 return ret; 528 529 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 530 PLL_OUTCTRL, PLL_OUTCTRL); 531 532 /* Ensure that the write above goes through before returning. */ 533 mb(); 534 return ret; 535 } 536 537 static void clk_alpha_pll_disable(struct clk_hw *hw) 538 { 539 int ret; 540 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 541 u32 val, mask; 542 543 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 544 if (ret) 545 return; 546 547 /* If in FSM mode, just unvote it */ 548 if (val & PLL_VOTE_FSM_ENA) { 549 clk_disable_regmap(hw); 550 return; 551 } 552 553 mask = PLL_OUTCTRL; 554 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0); 555 556 /* Delay of 2 output clock ticks required until output is disabled */ 557 mb(); 558 udelay(1); 559 560 mask = PLL_RESET_N | PLL_BYPASSNL; 561 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0); 562 } 563 564 static unsigned long 565 alpha_pll_calc_rate(u64 prate, u32 l, u32 a, u32 alpha_width) 566 { 567 return (prate * l) + ((prate * a) >> ALPHA_SHIFT(alpha_width)); 568 } 569 570 static unsigned long 571 alpha_pll_round_rate(unsigned long rate, unsigned long prate, u32 *l, u64 *a, 572 u32 alpha_width) 573 { 574 u64 remainder; 575 u64 quotient; 576 577 quotient = rate; 578 remainder = do_div(quotient, prate); 579 *l = quotient; 580 581 if (!remainder) { 582 *a = 0; 583 return rate; 584 } 585 586 /* Upper ALPHA_BITWIDTH bits of Alpha */ 587 quotient = remainder << ALPHA_SHIFT(alpha_width); 588 589 remainder = do_div(quotient, prate); 590 591 if (remainder) 592 quotient++; 593 594 *a = quotient; 595 return alpha_pll_calc_rate(prate, *l, *a, alpha_width); 596 } 597 598 static const struct pll_vco * 599 alpha_pll_find_vco(const struct clk_alpha_pll *pll, unsigned long rate) 600 { 601 const struct pll_vco *v = pll->vco_table; 602 const struct pll_vco *end = v + pll->num_vco; 603 604 for (; v < end; v++) 605 if (rate >= v->min_freq && rate <= v->max_freq) 606 return v; 607 608 return NULL; 609 } 610 611 static unsigned long 612 clk_alpha_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 613 { 614 u32 l, low, high, ctl; 615 u64 a = 0, prate = parent_rate; 616 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 617 u32 alpha_width = pll_alpha_width(pll); 618 619 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); 620 621 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); 622 if (ctl & PLL_ALPHA_EN) { 623 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &low); 624 if (alpha_width > 32) { 625 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), 626 &high); 627 a = (u64)high << 32 | low; 628 } else { 629 a = low & GENMASK(alpha_width - 1, 0); 630 } 631 632 if (alpha_width > ALPHA_BITWIDTH) 633 a >>= alpha_width - ALPHA_BITWIDTH; 634 } 635 636 return alpha_pll_calc_rate(prate, l, a, alpha_width); 637 } 638 639 640 static int __clk_alpha_pll_update_latch(struct clk_alpha_pll *pll) 641 { 642 int ret; 643 u32 mode; 644 645 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &mode); 646 647 /* Latch the input to the PLL */ 648 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 649 PLL_UPDATE); 650 651 /* Wait for 2 reference cycle before checking ACK bit */ 652 udelay(1); 653 654 /* 655 * PLL will latch the new L, Alpha and freq control word. 656 * PLL will respond by raising PLL_ACK_LATCH output when new programming 657 * has been latched in and PLL is being updated. When 658 * UPDATE_LOGIC_BYPASS bit is not set, PLL_UPDATE will be cleared 659 * automatically by hardware when PLL_ACK_LATCH is asserted by PLL. 660 */ 661 if (mode & PLL_UPDATE_BYPASS) { 662 ret = wait_for_pll_update_ack_set(pll); 663 if (ret) 664 return ret; 665 666 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 0); 667 } else { 668 ret = wait_for_pll_update(pll); 669 if (ret) 670 return ret; 671 } 672 673 ret = wait_for_pll_update_ack_clear(pll); 674 if (ret) 675 return ret; 676 677 /* Wait for PLL output to stabilize */ 678 udelay(10); 679 680 return 0; 681 } 682 683 static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll, 684 int (*is_enabled)(struct clk_hw *)) 685 { 686 if (!is_enabled(&pll->clkr.hw) || 687 !(pll->flags & SUPPORTS_DYNAMIC_UPDATE)) 688 return 0; 689 690 return __clk_alpha_pll_update_latch(pll); 691 } 692 693 static int __clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate, 694 unsigned long prate, 695 int (*is_enabled)(struct clk_hw *)) 696 { 697 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 698 const struct pll_vco *vco; 699 u32 l, alpha_width = pll_alpha_width(pll); 700 u64 a; 701 702 rate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 703 vco = alpha_pll_find_vco(pll, rate); 704 if (pll->vco_table && !vco) { 705 pr_err("%s: alpha pll not in a valid vco range\n", 706 clk_hw_get_name(hw)); 707 return -EINVAL; 708 } 709 710 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 711 712 if (alpha_width > ALPHA_BITWIDTH) 713 a <<= alpha_width - ALPHA_BITWIDTH; 714 715 if (alpha_width > 32) 716 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), a >> 32); 717 718 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 719 720 if (vco) { 721 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 722 PLL_VCO_MASK << PLL_VCO_SHIFT, 723 vco->val << PLL_VCO_SHIFT); 724 } 725 726 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 727 PLL_ALPHA_EN, PLL_ALPHA_EN); 728 729 return clk_alpha_pll_update_latch(pll, is_enabled); 730 } 731 732 static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate, 733 unsigned long prate) 734 { 735 return __clk_alpha_pll_set_rate(hw, rate, prate, 736 clk_alpha_pll_is_enabled); 737 } 738 739 static int clk_alpha_pll_hwfsm_set_rate(struct clk_hw *hw, unsigned long rate, 740 unsigned long prate) 741 { 742 return __clk_alpha_pll_set_rate(hw, rate, prate, 743 clk_alpha_pll_hwfsm_is_enabled); 744 } 745 746 static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate, 747 unsigned long *prate) 748 { 749 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 750 u32 l, alpha_width = pll_alpha_width(pll); 751 u64 a; 752 unsigned long min_freq, max_freq; 753 754 rate = alpha_pll_round_rate(rate, *prate, &l, &a, alpha_width); 755 if (!pll->vco_table || alpha_pll_find_vco(pll, rate)) 756 return rate; 757 758 min_freq = pll->vco_table[0].min_freq; 759 max_freq = pll->vco_table[pll->num_vco - 1].max_freq; 760 761 return clamp(rate, min_freq, max_freq); 762 } 763 764 static unsigned long 765 alpha_huayra_pll_calc_rate(u64 prate, u32 l, u32 a) 766 { 767 /* 768 * a contains 16 bit alpha_val in two’s complement number in the range 769 * of [-0.5, 0.5). 770 */ 771 if (a >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1)) 772 l -= 1; 773 774 return (prate * l) + (prate * a >> PLL_HUAYRA_ALPHA_WIDTH); 775 } 776 777 static unsigned long 778 alpha_huayra_pll_round_rate(unsigned long rate, unsigned long prate, 779 u32 *l, u32 *a) 780 { 781 u64 remainder; 782 u64 quotient; 783 784 quotient = rate; 785 remainder = do_div(quotient, prate); 786 *l = quotient; 787 788 if (!remainder) { 789 *a = 0; 790 return rate; 791 } 792 793 quotient = remainder << PLL_HUAYRA_ALPHA_WIDTH; 794 remainder = do_div(quotient, prate); 795 796 if (remainder) 797 quotient++; 798 799 /* 800 * alpha_val should be in two’s complement number in the range 801 * of [-0.5, 0.5) so if quotient >= 0.5 then increment the l value 802 * since alpha value will be subtracted in this case. 803 */ 804 if (quotient >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1)) 805 *l += 1; 806 807 *a = quotient; 808 return alpha_huayra_pll_calc_rate(prate, *l, *a); 809 } 810 811 static unsigned long 812 alpha_pll_huayra_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 813 { 814 u64 rate = parent_rate, tmp; 815 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 816 u32 l, alpha = 0, ctl, alpha_m, alpha_n; 817 818 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); 819 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); 820 821 if (ctl & PLL_ALPHA_EN) { 822 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &alpha); 823 /* 824 * Depending upon alpha_mode, it can be treated as M/N value or 825 * as a two’s complement number. When alpha_mode=1, 826 * pll_alpha_val<15:8>=M and pll_apla_val<7:0>=N 827 * 828 * Fout=FIN*(L+(M/N)) 829 * 830 * M is a signed number (-128 to 127) and N is unsigned 831 * (0 to 255). M/N has to be within +/-0.5. 832 * 833 * When alpha_mode=0, it is a two’s complement number in the 834 * range [-0.5, 0.5). 835 * 836 * Fout=FIN*(L+(alpha_val)/2^16) 837 * 838 * where alpha_val is two’s complement number. 839 */ 840 if (!(ctl & PLL_ALPHA_MODE)) 841 return alpha_huayra_pll_calc_rate(rate, l, alpha); 842 843 alpha_m = alpha >> PLL_HUAYRA_M_SHIFT & PLL_HUAYRA_M_MASK; 844 alpha_n = alpha >> PLL_HUAYRA_N_SHIFT & PLL_HUAYRA_N_MASK; 845 846 rate *= l; 847 tmp = parent_rate; 848 if (alpha_m >= BIT(PLL_HUAYRA_M_WIDTH - 1)) { 849 alpha_m = BIT(PLL_HUAYRA_M_WIDTH) - alpha_m; 850 tmp *= alpha_m; 851 do_div(tmp, alpha_n); 852 rate -= tmp; 853 } else { 854 tmp *= alpha_m; 855 do_div(tmp, alpha_n); 856 rate += tmp; 857 } 858 859 return rate; 860 } 861 862 return alpha_huayra_pll_calc_rate(rate, l, alpha); 863 } 864 865 static int alpha_pll_huayra_set_rate(struct clk_hw *hw, unsigned long rate, 866 unsigned long prate) 867 { 868 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 869 u32 l, a, ctl, cur_alpha = 0; 870 871 rate = alpha_huayra_pll_round_rate(rate, prate, &l, &a); 872 873 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); 874 875 if (ctl & PLL_ALPHA_EN) 876 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &cur_alpha); 877 878 /* 879 * Huayra PLL supports PLL dynamic programming. User can change L_VAL, 880 * without having to go through the power on sequence. 881 */ 882 if (clk_alpha_pll_is_enabled(hw)) { 883 if (cur_alpha != a) { 884 pr_err("%s: clock needs to be gated\n", 885 clk_hw_get_name(hw)); 886 return -EBUSY; 887 } 888 889 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 890 /* Ensure that the write above goes to detect L val change. */ 891 mb(); 892 return wait_for_pll_enable_lock(pll); 893 } 894 895 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 896 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 897 898 if (a == 0) 899 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 900 PLL_ALPHA_EN, 0x0); 901 else 902 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 903 PLL_ALPHA_EN | PLL_ALPHA_MODE, PLL_ALPHA_EN); 904 905 return 0; 906 } 907 908 static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long rate, 909 unsigned long *prate) 910 { 911 u32 l, a; 912 913 return alpha_huayra_pll_round_rate(rate, *prate, &l, &a); 914 } 915 916 static int trion_pll_is_enabled(struct clk_alpha_pll *pll, 917 struct regmap *regmap) 918 { 919 u32 mode_val, opmode_val; 920 int ret; 921 922 ret = regmap_read(regmap, PLL_MODE(pll), &mode_val); 923 ret |= regmap_read(regmap, PLL_OPMODE(pll), &opmode_val); 924 if (ret) 925 return 0; 926 927 return ((opmode_val & PLL_RUN) && (mode_val & PLL_OUTCTRL)); 928 } 929 930 static int clk_trion_pll_is_enabled(struct clk_hw *hw) 931 { 932 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 933 934 return trion_pll_is_enabled(pll, pll->clkr.regmap); 935 } 936 937 static int clk_trion_pll_enable(struct clk_hw *hw) 938 { 939 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 940 struct regmap *regmap = pll->clkr.regmap; 941 u32 val; 942 int ret; 943 944 ret = regmap_read(regmap, PLL_MODE(pll), &val); 945 if (ret) 946 return ret; 947 948 /* If in FSM mode, just vote for it */ 949 if (val & PLL_VOTE_FSM_ENA) { 950 ret = clk_enable_regmap(hw); 951 if (ret) 952 return ret; 953 return wait_for_pll_enable_active(pll); 954 } 955 956 /* Set operation mode to RUN */ 957 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); 958 959 ret = wait_for_pll_enable_lock(pll); 960 if (ret) 961 return ret; 962 963 /* Enable the PLL outputs */ 964 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), 965 PLL_OUT_MASK, PLL_OUT_MASK); 966 if (ret) 967 return ret; 968 969 /* Enable the global PLL outputs */ 970 return regmap_update_bits(regmap, PLL_MODE(pll), 971 PLL_OUTCTRL, PLL_OUTCTRL); 972 } 973 974 static void clk_trion_pll_disable(struct clk_hw *hw) 975 { 976 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 977 struct regmap *regmap = pll->clkr.regmap; 978 u32 val; 979 int ret; 980 981 ret = regmap_read(regmap, PLL_MODE(pll), &val); 982 if (ret) 983 return; 984 985 /* If in FSM mode, just unvote it */ 986 if (val & PLL_VOTE_FSM_ENA) { 987 clk_disable_regmap(hw); 988 return; 989 } 990 991 /* Disable the global PLL output */ 992 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 993 if (ret) 994 return; 995 996 /* Disable the PLL outputs */ 997 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), 998 PLL_OUT_MASK, 0); 999 if (ret) 1000 return; 1001 1002 /* Place the PLL mode in STANDBY */ 1003 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 1004 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 1005 } 1006 1007 static unsigned long 1008 clk_trion_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 1009 { 1010 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1011 u32 l, frac, alpha_width = pll_alpha_width(pll); 1012 1013 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); 1014 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac); 1015 1016 return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width); 1017 } 1018 1019 const struct clk_ops clk_alpha_pll_fixed_ops = { 1020 .enable = clk_alpha_pll_enable, 1021 .disable = clk_alpha_pll_disable, 1022 .is_enabled = clk_alpha_pll_is_enabled, 1023 .recalc_rate = clk_alpha_pll_recalc_rate, 1024 }; 1025 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_ops); 1026 1027 const struct clk_ops clk_alpha_pll_ops = { 1028 .enable = clk_alpha_pll_enable, 1029 .disable = clk_alpha_pll_disable, 1030 .is_enabled = clk_alpha_pll_is_enabled, 1031 .recalc_rate = clk_alpha_pll_recalc_rate, 1032 .round_rate = clk_alpha_pll_round_rate, 1033 .set_rate = clk_alpha_pll_set_rate, 1034 }; 1035 EXPORT_SYMBOL_GPL(clk_alpha_pll_ops); 1036 1037 const struct clk_ops clk_alpha_pll_huayra_ops = { 1038 .enable = clk_alpha_pll_enable, 1039 .disable = clk_alpha_pll_disable, 1040 .is_enabled = clk_alpha_pll_is_enabled, 1041 .recalc_rate = alpha_pll_huayra_recalc_rate, 1042 .round_rate = alpha_pll_huayra_round_rate, 1043 .set_rate = alpha_pll_huayra_set_rate, 1044 }; 1045 EXPORT_SYMBOL_GPL(clk_alpha_pll_huayra_ops); 1046 1047 const struct clk_ops clk_alpha_pll_hwfsm_ops = { 1048 .enable = clk_alpha_pll_hwfsm_enable, 1049 .disable = clk_alpha_pll_hwfsm_disable, 1050 .is_enabled = clk_alpha_pll_hwfsm_is_enabled, 1051 .recalc_rate = clk_alpha_pll_recalc_rate, 1052 .round_rate = clk_alpha_pll_round_rate, 1053 .set_rate = clk_alpha_pll_hwfsm_set_rate, 1054 }; 1055 EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops); 1056 1057 const struct clk_ops clk_alpha_pll_fixed_trion_ops = { 1058 .enable = clk_trion_pll_enable, 1059 .disable = clk_trion_pll_disable, 1060 .is_enabled = clk_trion_pll_is_enabled, 1061 .recalc_rate = clk_trion_pll_recalc_rate, 1062 .round_rate = clk_alpha_pll_round_rate, 1063 }; 1064 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_trion_ops); 1065 1066 static unsigned long 1067 clk_alpha_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 1068 { 1069 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1070 u32 ctl; 1071 1072 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); 1073 1074 ctl >>= PLL_POST_DIV_SHIFT; 1075 ctl &= PLL_POST_DIV_MASK(pll); 1076 1077 return parent_rate >> fls(ctl); 1078 } 1079 1080 static const struct clk_div_table clk_alpha_div_table[] = { 1081 { 0x0, 1 }, 1082 { 0x1, 2 }, 1083 { 0x3, 4 }, 1084 { 0x7, 8 }, 1085 { 0xf, 16 }, 1086 { } 1087 }; 1088 1089 static const struct clk_div_table clk_alpha_2bit_div_table[] = { 1090 { 0x0, 1 }, 1091 { 0x1, 2 }, 1092 { 0x3, 4 }, 1093 { } 1094 }; 1095 1096 static long 1097 clk_alpha_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate, 1098 unsigned long *prate) 1099 { 1100 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1101 const struct clk_div_table *table; 1102 1103 if (pll->width == 2) 1104 table = clk_alpha_2bit_div_table; 1105 else 1106 table = clk_alpha_div_table; 1107 1108 return divider_round_rate(hw, rate, prate, table, 1109 pll->width, CLK_DIVIDER_POWER_OF_TWO); 1110 } 1111 1112 static long 1113 clk_alpha_pll_postdiv_round_ro_rate(struct clk_hw *hw, unsigned long rate, 1114 unsigned long *prate) 1115 { 1116 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1117 u32 ctl, div; 1118 1119 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); 1120 1121 ctl >>= PLL_POST_DIV_SHIFT; 1122 ctl &= BIT(pll->width) - 1; 1123 div = 1 << fls(ctl); 1124 1125 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) 1126 *prate = clk_hw_round_rate(clk_hw_get_parent(hw), div * rate); 1127 1128 return DIV_ROUND_UP_ULL((u64)*prate, div); 1129 } 1130 1131 static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 1132 unsigned long parent_rate) 1133 { 1134 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1135 int div; 1136 1137 /* 16 -> 0xf, 8 -> 0x7, 4 -> 0x3, 2 -> 0x1, 1 -> 0x0 */ 1138 div = DIV_ROUND_UP_ULL(parent_rate, rate) - 1; 1139 1140 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 1141 PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT, 1142 div << PLL_POST_DIV_SHIFT); 1143 } 1144 1145 const struct clk_ops clk_alpha_pll_postdiv_ops = { 1146 .recalc_rate = clk_alpha_pll_postdiv_recalc_rate, 1147 .round_rate = clk_alpha_pll_postdiv_round_rate, 1148 .set_rate = clk_alpha_pll_postdiv_set_rate, 1149 }; 1150 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ops); 1151 1152 const struct clk_ops clk_alpha_pll_postdiv_ro_ops = { 1153 .round_rate = clk_alpha_pll_postdiv_round_ro_rate, 1154 .recalc_rate = clk_alpha_pll_postdiv_recalc_rate, 1155 }; 1156 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ro_ops); 1157 1158 void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 1159 const struct alpha_pll_config *config) 1160 { 1161 u32 val, mask; 1162 1163 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 1164 clk_alpha_pll_write_config(regmap, PLL_FRAC(pll), config->alpha); 1165 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), 1166 config->config_ctl_val); 1167 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), 1168 config->config_ctl_hi_val); 1169 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), 1170 config->user_ctl_val); 1171 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), 1172 config->user_ctl_hi_val); 1173 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), 1174 config->test_ctl_val); 1175 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), 1176 config->test_ctl_hi_val); 1177 1178 if (config->post_div_mask) { 1179 mask = config->post_div_mask; 1180 val = config->post_div_val; 1181 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); 1182 } 1183 1184 if (pll->flags & SUPPORTS_FSM_LEGACY_MODE) 1185 regmap_update_bits(regmap, PLL_MODE(pll), PLL_FSM_LEGACY_MODE, 1186 PLL_FSM_LEGACY_MODE); 1187 1188 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS, 1189 PLL_UPDATE_BYPASS); 1190 1191 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 1192 } 1193 EXPORT_SYMBOL_GPL(clk_fabia_pll_configure); 1194 1195 static int alpha_pll_fabia_enable(struct clk_hw *hw) 1196 { 1197 int ret; 1198 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1199 u32 val, opmode_val; 1200 struct regmap *regmap = pll->clkr.regmap; 1201 1202 ret = regmap_read(regmap, PLL_MODE(pll), &val); 1203 if (ret) 1204 return ret; 1205 1206 /* If in FSM mode, just vote for it */ 1207 if (val & PLL_VOTE_FSM_ENA) { 1208 ret = clk_enable_regmap(hw); 1209 if (ret) 1210 return ret; 1211 return wait_for_pll_enable_active(pll); 1212 } 1213 1214 ret = regmap_read(regmap, PLL_OPMODE(pll), &opmode_val); 1215 if (ret) 1216 return ret; 1217 1218 /* Skip If PLL is already running */ 1219 if ((opmode_val & PLL_RUN) && (val & PLL_OUTCTRL)) 1220 return 0; 1221 1222 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1223 if (ret) 1224 return ret; 1225 1226 ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 1227 if (ret) 1228 return ret; 1229 1230 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, 1231 PLL_RESET_N); 1232 if (ret) 1233 return ret; 1234 1235 ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); 1236 if (ret) 1237 return ret; 1238 1239 ret = wait_for_pll_enable_lock(pll); 1240 if (ret) 1241 return ret; 1242 1243 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), 1244 PLL_OUT_MASK, PLL_OUT_MASK); 1245 if (ret) 1246 return ret; 1247 1248 return regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 1249 PLL_OUTCTRL); 1250 } 1251 1252 static void alpha_pll_fabia_disable(struct clk_hw *hw) 1253 { 1254 int ret; 1255 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1256 u32 val; 1257 struct regmap *regmap = pll->clkr.regmap; 1258 1259 ret = regmap_read(regmap, PLL_MODE(pll), &val); 1260 if (ret) 1261 return; 1262 1263 /* If in FSM mode, just unvote it */ 1264 if (val & PLL_FSM_ENA) { 1265 clk_disable_regmap(hw); 1266 return; 1267 } 1268 1269 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1270 if (ret) 1271 return; 1272 1273 /* Disable main outputs */ 1274 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); 1275 if (ret) 1276 return; 1277 1278 /* Place the PLL in STANDBY */ 1279 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 1280 } 1281 1282 static unsigned long alpha_pll_fabia_recalc_rate(struct clk_hw *hw, 1283 unsigned long parent_rate) 1284 { 1285 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1286 u32 l, frac, alpha_width = pll_alpha_width(pll); 1287 1288 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); 1289 regmap_read(pll->clkr.regmap, PLL_FRAC(pll), &frac); 1290 1291 return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width); 1292 } 1293 1294 /* 1295 * Due to limited number of bits for fractional rate programming, the 1296 * rounded up rate could be marginally higher than the requested rate. 1297 */ 1298 static int alpha_pll_check_rate_margin(struct clk_hw *hw, 1299 unsigned long rrate, unsigned long rate) 1300 { 1301 unsigned long rate_margin = rate + PLL_RATE_MARGIN; 1302 1303 if (rrate > rate_margin || rrate < rate) { 1304 pr_err("%s: Rounded rate %lu not within range [%lu, %lu)\n", 1305 clk_hw_get_name(hw), rrate, rate, rate_margin); 1306 return -EINVAL; 1307 } 1308 1309 return 0; 1310 } 1311 1312 static int alpha_pll_fabia_set_rate(struct clk_hw *hw, unsigned long rate, 1313 unsigned long prate) 1314 { 1315 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1316 u32 l, alpha_width = pll_alpha_width(pll); 1317 unsigned long rrate; 1318 int ret; 1319 u64 a; 1320 1321 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 1322 1323 ret = alpha_pll_check_rate_margin(hw, rrate, rate); 1324 if (ret < 0) 1325 return ret; 1326 1327 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 1328 regmap_write(pll->clkr.regmap, PLL_FRAC(pll), a); 1329 1330 return __clk_alpha_pll_update_latch(pll); 1331 } 1332 1333 static int alpha_pll_fabia_prepare(struct clk_hw *hw) 1334 { 1335 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1336 const struct pll_vco *vco; 1337 struct clk_hw *parent_hw; 1338 unsigned long cal_freq, rrate; 1339 u32 cal_l, val, alpha_width = pll_alpha_width(pll); 1340 const char *name = clk_hw_get_name(hw); 1341 u64 a; 1342 int ret; 1343 1344 /* Check if calibration needs to be done i.e. PLL is in reset */ 1345 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 1346 if (ret) 1347 return ret; 1348 1349 /* Return early if calibration is not needed. */ 1350 if (val & PLL_RESET_N) 1351 return 0; 1352 1353 vco = alpha_pll_find_vco(pll, clk_hw_get_rate(hw)); 1354 if (!vco) { 1355 pr_err("%s: alpha pll not in a valid vco range\n", name); 1356 return -EINVAL; 1357 } 1358 1359 cal_freq = DIV_ROUND_CLOSEST((pll->vco_table[0].min_freq + 1360 pll->vco_table[0].max_freq) * 54, 100); 1361 1362 parent_hw = clk_hw_get_parent(hw); 1363 if (!parent_hw) 1364 return -EINVAL; 1365 1366 rrate = alpha_pll_round_rate(cal_freq, clk_hw_get_rate(parent_hw), 1367 &cal_l, &a, alpha_width); 1368 1369 ret = alpha_pll_check_rate_margin(hw, rrate, cal_freq); 1370 if (ret < 0) 1371 return ret; 1372 1373 /* Setup PLL for calibration frequency */ 1374 regmap_write(pll->clkr.regmap, PLL_CAL_L_VAL(pll), cal_l); 1375 1376 /* Bringup the PLL at calibration frequency */ 1377 ret = clk_alpha_pll_enable(hw); 1378 if (ret) { 1379 pr_err("%s: alpha pll calibration failed\n", name); 1380 return ret; 1381 } 1382 1383 clk_alpha_pll_disable(hw); 1384 1385 return 0; 1386 } 1387 1388 const struct clk_ops clk_alpha_pll_fabia_ops = { 1389 .prepare = alpha_pll_fabia_prepare, 1390 .enable = alpha_pll_fabia_enable, 1391 .disable = alpha_pll_fabia_disable, 1392 .is_enabled = clk_alpha_pll_is_enabled, 1393 .set_rate = alpha_pll_fabia_set_rate, 1394 .recalc_rate = alpha_pll_fabia_recalc_rate, 1395 .round_rate = clk_alpha_pll_round_rate, 1396 }; 1397 EXPORT_SYMBOL_GPL(clk_alpha_pll_fabia_ops); 1398 1399 const struct clk_ops clk_alpha_pll_fixed_fabia_ops = { 1400 .enable = alpha_pll_fabia_enable, 1401 .disable = alpha_pll_fabia_disable, 1402 .is_enabled = clk_alpha_pll_is_enabled, 1403 .recalc_rate = alpha_pll_fabia_recalc_rate, 1404 .round_rate = clk_alpha_pll_round_rate, 1405 }; 1406 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_fabia_ops); 1407 1408 static unsigned long clk_alpha_pll_postdiv_fabia_recalc_rate(struct clk_hw *hw, 1409 unsigned long parent_rate) 1410 { 1411 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1412 u32 i, div = 1, val; 1413 int ret; 1414 1415 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); 1416 if (ret) 1417 return ret; 1418 1419 val >>= pll->post_div_shift; 1420 val &= BIT(pll->width) - 1; 1421 1422 for (i = 0; i < pll->num_post_div; i++) { 1423 if (pll->post_div_table[i].val == val) { 1424 div = pll->post_div_table[i].div; 1425 break; 1426 } 1427 } 1428 1429 return (parent_rate / div); 1430 } 1431 1432 static unsigned long 1433 clk_trion_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 1434 { 1435 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1436 struct regmap *regmap = pll->clkr.regmap; 1437 u32 i, div = 1, val; 1438 1439 regmap_read(regmap, PLL_USER_CTL(pll), &val); 1440 1441 val >>= pll->post_div_shift; 1442 val &= PLL_POST_DIV_MASK(pll); 1443 1444 for (i = 0; i < pll->num_post_div; i++) { 1445 if (pll->post_div_table[i].val == val) { 1446 div = pll->post_div_table[i].div; 1447 break; 1448 } 1449 } 1450 1451 return (parent_rate / div); 1452 } 1453 1454 static long 1455 clk_trion_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate, 1456 unsigned long *prate) 1457 { 1458 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1459 1460 return divider_round_rate(hw, rate, prate, pll->post_div_table, 1461 pll->width, CLK_DIVIDER_ROUND_CLOSEST); 1462 }; 1463 1464 static int 1465 clk_trion_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 1466 unsigned long parent_rate) 1467 { 1468 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1469 struct regmap *regmap = pll->clkr.regmap; 1470 int i, val = 0, div; 1471 1472 div = DIV_ROUND_UP_ULL(parent_rate, rate); 1473 for (i = 0; i < pll->num_post_div; i++) { 1474 if (pll->post_div_table[i].div == div) { 1475 val = pll->post_div_table[i].val; 1476 break; 1477 } 1478 } 1479 1480 return regmap_update_bits(regmap, PLL_USER_CTL(pll), 1481 PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT, 1482 val << PLL_POST_DIV_SHIFT); 1483 } 1484 1485 const struct clk_ops clk_alpha_pll_postdiv_trion_ops = { 1486 .recalc_rate = clk_trion_pll_postdiv_recalc_rate, 1487 .round_rate = clk_trion_pll_postdiv_round_rate, 1488 .set_rate = clk_trion_pll_postdiv_set_rate, 1489 }; 1490 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_trion_ops); 1491 1492 static long clk_alpha_pll_postdiv_fabia_round_rate(struct clk_hw *hw, 1493 unsigned long rate, unsigned long *prate) 1494 { 1495 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1496 1497 return divider_round_rate(hw, rate, prate, pll->post_div_table, 1498 pll->width, CLK_DIVIDER_ROUND_CLOSEST); 1499 } 1500 1501 static int clk_alpha_pll_postdiv_fabia_set_rate(struct clk_hw *hw, 1502 unsigned long rate, unsigned long parent_rate) 1503 { 1504 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1505 int i, val = 0, div, ret; 1506 1507 /* 1508 * If the PLL is in FSM mode, then treat set_rate callback as a 1509 * no-operation. 1510 */ 1511 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 1512 if (ret) 1513 return ret; 1514 1515 if (val & PLL_VOTE_FSM_ENA) 1516 return 0; 1517 1518 div = DIV_ROUND_UP_ULL(parent_rate, rate); 1519 for (i = 0; i < pll->num_post_div; i++) { 1520 if (pll->post_div_table[i].div == div) { 1521 val = pll->post_div_table[i].val; 1522 break; 1523 } 1524 } 1525 1526 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 1527 (BIT(pll->width) - 1) << pll->post_div_shift, 1528 val << pll->post_div_shift); 1529 } 1530 1531 const struct clk_ops clk_alpha_pll_postdiv_fabia_ops = { 1532 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate, 1533 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate, 1534 .set_rate = clk_alpha_pll_postdiv_fabia_set_rate, 1535 }; 1536 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_fabia_ops); 1537 1538 /** 1539 * clk_trion_pll_configure - configure the trion pll 1540 * 1541 * @pll: clk alpha pll 1542 * @regmap: register map 1543 * @config: configuration to apply for pll 1544 */ 1545 void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 1546 const struct alpha_pll_config *config) 1547 { 1548 /* 1549 * If the bootloader left the PLL enabled it's likely that there are 1550 * RCGs that will lock up if we disable the PLL below. 1551 */ 1552 if (trion_pll_is_enabled(pll, regmap)) { 1553 pr_debug("Trion PLL is already enabled, skipping configuration\n"); 1554 return; 1555 } 1556 1557 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 1558 regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL); 1559 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 1560 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), 1561 config->config_ctl_val); 1562 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), 1563 config->config_ctl_hi_val); 1564 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), 1565 config->config_ctl_hi1_val); 1566 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), 1567 config->user_ctl_val); 1568 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), 1569 config->user_ctl_hi_val); 1570 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), 1571 config->user_ctl_hi1_val); 1572 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), 1573 config->test_ctl_val); 1574 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), 1575 config->test_ctl_hi_val); 1576 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), 1577 config->test_ctl_hi1_val); 1578 1579 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS, 1580 PLL_UPDATE_BYPASS); 1581 1582 /* Disable PLL output */ 1583 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1584 1585 /* Set operation mode to OFF */ 1586 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 1587 1588 /* Place the PLL in STANDBY mode */ 1589 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 1590 } 1591 EXPORT_SYMBOL_GPL(clk_trion_pll_configure); 1592 1593 /* 1594 * The TRION PLL requires a power-on self-calibration which happens when the 1595 * PLL comes out of reset. Calibrate in case it is not completed. 1596 */ 1597 static int __alpha_pll_trion_prepare(struct clk_hw *hw, u32 pcal_done) 1598 { 1599 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1600 u32 val; 1601 int ret; 1602 1603 /* Return early if calibration is not needed. */ 1604 regmap_read(pll->clkr.regmap, PLL_STATUS(pll), &val); 1605 if (val & pcal_done) 1606 return 0; 1607 1608 /* On/off to calibrate */ 1609 ret = clk_trion_pll_enable(hw); 1610 if (!ret) 1611 clk_trion_pll_disable(hw); 1612 1613 return ret; 1614 } 1615 1616 static int alpha_pll_trion_prepare(struct clk_hw *hw) 1617 { 1618 return __alpha_pll_trion_prepare(hw, TRION_PCAL_DONE); 1619 } 1620 1621 static int alpha_pll_lucid_prepare(struct clk_hw *hw) 1622 { 1623 return __alpha_pll_trion_prepare(hw, LUCID_PCAL_DONE); 1624 } 1625 1626 static int __alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate, 1627 unsigned long prate, u32 latch_bit, u32 latch_ack) 1628 { 1629 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1630 unsigned long rrate; 1631 u32 val, l, alpha_width = pll_alpha_width(pll); 1632 u64 a; 1633 int ret; 1634 1635 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 1636 1637 ret = alpha_pll_check_rate_margin(hw, rrate, rate); 1638 if (ret < 0) 1639 return ret; 1640 1641 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 1642 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 1643 1644 /* Latch the PLL input */ 1645 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, latch_bit); 1646 if (ret) 1647 return ret; 1648 1649 /* Wait for 2 reference cycles before checking the ACK bit. */ 1650 udelay(1); 1651 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 1652 if (!(val & latch_ack)) { 1653 pr_err("Lucid PLL latch failed. Output may be unstable!\n"); 1654 return -EINVAL; 1655 } 1656 1657 /* Return the latch input to 0 */ 1658 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, 0); 1659 if (ret) 1660 return ret; 1661 1662 if (clk_hw_is_enabled(hw)) { 1663 ret = wait_for_pll_enable_lock(pll); 1664 if (ret) 1665 return ret; 1666 } 1667 1668 /* Wait for PLL output to stabilize */ 1669 udelay(100); 1670 return 0; 1671 } 1672 1673 static int alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate, 1674 unsigned long prate) 1675 { 1676 return __alpha_pll_trion_set_rate(hw, rate, prate, PLL_UPDATE, ALPHA_PLL_ACK_LATCH); 1677 } 1678 1679 const struct clk_ops clk_alpha_pll_trion_ops = { 1680 .prepare = alpha_pll_trion_prepare, 1681 .enable = clk_trion_pll_enable, 1682 .disable = clk_trion_pll_disable, 1683 .is_enabled = clk_trion_pll_is_enabled, 1684 .recalc_rate = clk_trion_pll_recalc_rate, 1685 .round_rate = clk_alpha_pll_round_rate, 1686 .set_rate = alpha_pll_trion_set_rate, 1687 }; 1688 EXPORT_SYMBOL_GPL(clk_alpha_pll_trion_ops); 1689 1690 const struct clk_ops clk_alpha_pll_lucid_ops = { 1691 .prepare = alpha_pll_lucid_prepare, 1692 .enable = clk_trion_pll_enable, 1693 .disable = clk_trion_pll_disable, 1694 .is_enabled = clk_trion_pll_is_enabled, 1695 .recalc_rate = clk_trion_pll_recalc_rate, 1696 .round_rate = clk_alpha_pll_round_rate, 1697 .set_rate = alpha_pll_trion_set_rate, 1698 }; 1699 EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_ops); 1700 1701 const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = { 1702 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate, 1703 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate, 1704 .set_rate = clk_alpha_pll_postdiv_fabia_set_rate, 1705 }; 1706 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_ops); 1707 1708 void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 1709 const struct alpha_pll_config *config) 1710 { 1711 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 1712 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 1713 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), 1714 config->user_ctl_val); 1715 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), 1716 config->config_ctl_val); 1717 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), 1718 config->config_ctl_hi_val); 1719 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), 1720 config->test_ctl_val); 1721 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), 1722 config->test_ctl_hi_val); 1723 } 1724 EXPORT_SYMBOL_GPL(clk_agera_pll_configure); 1725 1726 static int clk_alpha_pll_agera_set_rate(struct clk_hw *hw, unsigned long rate, 1727 unsigned long prate) 1728 { 1729 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1730 u32 l, alpha_width = pll_alpha_width(pll); 1731 int ret; 1732 unsigned long rrate; 1733 u64 a; 1734 1735 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 1736 ret = alpha_pll_check_rate_margin(hw, rrate, rate); 1737 if (ret < 0) 1738 return ret; 1739 1740 /* change L_VAL without having to go through the power on sequence */ 1741 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 1742 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 1743 1744 if (clk_hw_is_enabled(hw)) 1745 return wait_for_pll_enable_lock(pll); 1746 1747 return 0; 1748 } 1749 1750 const struct clk_ops clk_alpha_pll_agera_ops = { 1751 .enable = clk_alpha_pll_enable, 1752 .disable = clk_alpha_pll_disable, 1753 .is_enabled = clk_alpha_pll_is_enabled, 1754 .recalc_rate = alpha_pll_fabia_recalc_rate, 1755 .round_rate = clk_alpha_pll_round_rate, 1756 .set_rate = clk_alpha_pll_agera_set_rate, 1757 }; 1758 EXPORT_SYMBOL_GPL(clk_alpha_pll_agera_ops); 1759 1760 static int alpha_pll_lucid_5lpe_enable(struct clk_hw *hw) 1761 { 1762 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1763 u32 val; 1764 int ret; 1765 1766 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); 1767 if (ret) 1768 return ret; 1769 1770 /* If in FSM mode, just vote for it */ 1771 if (val & LUCID_5LPE_ENABLE_VOTE_RUN) { 1772 ret = clk_enable_regmap(hw); 1773 if (ret) 1774 return ret; 1775 return wait_for_pll_enable_lock(pll); 1776 } 1777 1778 /* Check if PLL is already enabled, return if enabled */ 1779 ret = trion_pll_is_enabled(pll, pll->clkr.regmap); 1780 if (ret < 0) 1781 return ret; 1782 1783 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 1784 if (ret) 1785 return ret; 1786 1787 regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_RUN); 1788 1789 ret = wait_for_pll_enable_lock(pll); 1790 if (ret) 1791 return ret; 1792 1793 /* Enable the PLL outputs */ 1794 ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK); 1795 if (ret) 1796 return ret; 1797 1798 /* Enable the global PLL outputs */ 1799 return regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); 1800 } 1801 1802 static void alpha_pll_lucid_5lpe_disable(struct clk_hw *hw) 1803 { 1804 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1805 u32 val; 1806 int ret; 1807 1808 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); 1809 if (ret) 1810 return; 1811 1812 /* If in FSM mode, just unvote it */ 1813 if (val & LUCID_5LPE_ENABLE_VOTE_RUN) { 1814 clk_disable_regmap(hw); 1815 return; 1816 } 1817 1818 /* Disable the global PLL output */ 1819 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1820 if (ret) 1821 return; 1822 1823 /* Disable the PLL outputs */ 1824 ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); 1825 if (ret) 1826 return; 1827 1828 /* Place the PLL mode in STANDBY */ 1829 regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_STANDBY); 1830 } 1831 1832 /* 1833 * The Lucid 5LPE PLL requires a power-on self-calibration which happens 1834 * when the PLL comes out of reset. Calibrate in case it is not completed. 1835 */ 1836 static int alpha_pll_lucid_5lpe_prepare(struct clk_hw *hw) 1837 { 1838 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1839 struct clk_hw *p; 1840 u32 val = 0; 1841 int ret; 1842 1843 /* Return early if calibration is not needed. */ 1844 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 1845 if (val & LUCID_5LPE_PCAL_DONE) 1846 return 0; 1847 1848 p = clk_hw_get_parent(hw); 1849 if (!p) 1850 return -EINVAL; 1851 1852 ret = alpha_pll_lucid_5lpe_enable(hw); 1853 if (ret) 1854 return ret; 1855 1856 alpha_pll_lucid_5lpe_disable(hw); 1857 1858 return 0; 1859 } 1860 1861 static int alpha_pll_lucid_5lpe_set_rate(struct clk_hw *hw, unsigned long rate, 1862 unsigned long prate) 1863 { 1864 return __alpha_pll_trion_set_rate(hw, rate, prate, 1865 LUCID_5LPE_PLL_LATCH_INPUT, 1866 LUCID_5LPE_ALPHA_PLL_ACK_LATCH); 1867 } 1868 1869 static int __clk_lucid_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 1870 unsigned long parent_rate, 1871 unsigned long enable_vote_run) 1872 { 1873 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1874 struct regmap *regmap = pll->clkr.regmap; 1875 int i, val, div, ret; 1876 u32 mask; 1877 1878 /* 1879 * If the PLL is in FSM mode, then treat set_rate callback as a 1880 * no-operation. 1881 */ 1882 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); 1883 if (ret) 1884 return ret; 1885 1886 if (val & enable_vote_run) 1887 return 0; 1888 1889 if (!pll->post_div_table) { 1890 pr_err("Missing the post_div_table for the %s PLL\n", 1891 clk_hw_get_name(&pll->clkr.hw)); 1892 return -EINVAL; 1893 } 1894 1895 div = DIV_ROUND_UP_ULL((u64)parent_rate, rate); 1896 for (i = 0; i < pll->num_post_div; i++) { 1897 if (pll->post_div_table[i].div == div) { 1898 val = pll->post_div_table[i].val; 1899 break; 1900 } 1901 } 1902 1903 mask = GENMASK(pll->width + pll->post_div_shift - 1, pll->post_div_shift); 1904 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 1905 mask, val << pll->post_div_shift); 1906 } 1907 1908 static int clk_lucid_5lpe_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 1909 unsigned long parent_rate) 1910 { 1911 return __clk_lucid_pll_postdiv_set_rate(hw, rate, parent_rate, LUCID_5LPE_ENABLE_VOTE_RUN); 1912 } 1913 1914 const struct clk_ops clk_alpha_pll_lucid_5lpe_ops = { 1915 .prepare = alpha_pll_lucid_5lpe_prepare, 1916 .enable = alpha_pll_lucid_5lpe_enable, 1917 .disable = alpha_pll_lucid_5lpe_disable, 1918 .is_enabled = clk_trion_pll_is_enabled, 1919 .recalc_rate = clk_trion_pll_recalc_rate, 1920 .round_rate = clk_alpha_pll_round_rate, 1921 .set_rate = alpha_pll_lucid_5lpe_set_rate, 1922 }; 1923 EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_5lpe_ops); 1924 1925 const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops = { 1926 .enable = alpha_pll_lucid_5lpe_enable, 1927 .disable = alpha_pll_lucid_5lpe_disable, 1928 .is_enabled = clk_trion_pll_is_enabled, 1929 .recalc_rate = clk_trion_pll_recalc_rate, 1930 .round_rate = clk_alpha_pll_round_rate, 1931 }; 1932 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_5lpe_ops); 1933 1934 const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops = { 1935 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate, 1936 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate, 1937 .set_rate = clk_lucid_5lpe_pll_postdiv_set_rate, 1938 }; 1939 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_5lpe_ops); 1940 1941 void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 1942 const struct alpha_pll_config *config) 1943 { 1944 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 1945 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 1946 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 1947 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); 1948 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); 1949 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); 1950 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); 1951 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), config->user_ctl_hi1_val); 1952 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 1953 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 1954 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); 1955 1956 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, 0); 1957 1958 /* Disable PLL output */ 1959 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1960 1961 /* Set operation mode to OFF */ 1962 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 1963 1964 /* Place the PLL in STANDBY mode */ 1965 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 1966 } 1967 EXPORT_SYMBOL_GPL(clk_zonda_pll_configure); 1968 1969 static int clk_zonda_pll_enable(struct clk_hw *hw) 1970 { 1971 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1972 struct regmap *regmap = pll->clkr.regmap; 1973 u32 val; 1974 int ret; 1975 1976 regmap_read(regmap, PLL_MODE(pll), &val); 1977 1978 /* If in FSM mode, just vote for it */ 1979 if (val & PLL_VOTE_FSM_ENA) { 1980 ret = clk_enable_regmap(hw); 1981 if (ret) 1982 return ret; 1983 return wait_for_pll_enable_active(pll); 1984 } 1985 1986 /* Get the PLL out of bypass mode */ 1987 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL); 1988 1989 /* 1990 * H/W requires a 1us delay between disabling the bypass and 1991 * de-asserting the reset. 1992 */ 1993 udelay(1); 1994 1995 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 1996 1997 /* Set operation mode to RUN */ 1998 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); 1999 2000 regmap_read(regmap, PLL_TEST_CTL(pll), &val); 2001 2002 /* If cfa mode then poll for freq lock */ 2003 if (val & ZONDA_STAY_IN_CFA) 2004 ret = wait_for_zonda_pll_freq_lock(pll); 2005 else 2006 ret = wait_for_pll_enable_lock(pll); 2007 if (ret) 2008 return ret; 2009 2010 /* Enable the PLL outputs */ 2011 regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, ZONDA_PLL_OUT_MASK); 2012 2013 /* Enable the global PLL outputs */ 2014 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); 2015 2016 return 0; 2017 } 2018 2019 static void clk_zonda_pll_disable(struct clk_hw *hw) 2020 { 2021 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2022 struct regmap *regmap = pll->clkr.regmap; 2023 u32 val; 2024 2025 regmap_read(regmap, PLL_MODE(pll), &val); 2026 2027 /* If in FSM mode, just unvote it */ 2028 if (val & PLL_VOTE_FSM_ENA) { 2029 clk_disable_regmap(hw); 2030 return; 2031 } 2032 2033 /* Disable the global PLL output */ 2034 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 2035 2036 /* Disable the PLL outputs */ 2037 regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, 0); 2038 2039 /* Put the PLL in bypass and reset */ 2040 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N | PLL_BYPASSNL, 0); 2041 2042 /* Place the PLL mode in OFF state */ 2043 regmap_write(regmap, PLL_OPMODE(pll), 0x0); 2044 } 2045 2046 static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate, 2047 unsigned long prate) 2048 { 2049 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2050 unsigned long rrate; 2051 u32 test_ctl_val; 2052 u32 l, alpha_width = pll_alpha_width(pll); 2053 u64 a; 2054 int ret; 2055 2056 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 2057 2058 ret = alpha_pll_check_rate_margin(hw, rrate, rate); 2059 if (ret < 0) 2060 return ret; 2061 2062 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 2063 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 2064 2065 /* Wait before polling for the frequency latch */ 2066 udelay(5); 2067 2068 /* Read stay in cfa mode */ 2069 regmap_read(pll->clkr.regmap, PLL_TEST_CTL(pll), &test_ctl_val); 2070 2071 /* If cfa mode then poll for freq lock */ 2072 if (test_ctl_val & ZONDA_STAY_IN_CFA) 2073 ret = wait_for_zonda_pll_freq_lock(pll); 2074 else 2075 ret = wait_for_pll_enable_lock(pll); 2076 if (ret) 2077 return ret; 2078 2079 /* Wait for PLL output to stabilize */ 2080 udelay(100); 2081 return 0; 2082 } 2083 2084 const struct clk_ops clk_alpha_pll_zonda_ops = { 2085 .enable = clk_zonda_pll_enable, 2086 .disable = clk_zonda_pll_disable, 2087 .is_enabled = clk_trion_pll_is_enabled, 2088 .recalc_rate = clk_trion_pll_recalc_rate, 2089 .round_rate = clk_alpha_pll_round_rate, 2090 .set_rate = clk_zonda_pll_set_rate, 2091 }; 2092 EXPORT_SYMBOL_GPL(clk_alpha_pll_zonda_ops); 2093 2094 void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 2095 const struct alpha_pll_config *config) 2096 { 2097 u32 lval = config->l; 2098 2099 lval |= TRION_PLL_CAL_VAL << LUCID_EVO_PLL_CAL_L_VAL_SHIFT; 2100 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval); 2101 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 2102 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 2103 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); 2104 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); 2105 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); 2106 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); 2107 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 2108 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 2109 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); 2110 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl_hi2_val); 2111 2112 /* Disable PLL output */ 2113 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 2114 2115 /* Set operation mode to STANDBY and de-assert the reset */ 2116 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 2117 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 2118 } 2119 EXPORT_SYMBOL_GPL(clk_lucid_evo_pll_configure); 2120 2121 static int alpha_pll_lucid_evo_enable(struct clk_hw *hw) 2122 { 2123 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2124 struct regmap *regmap = pll->clkr.regmap; 2125 u32 val; 2126 int ret; 2127 2128 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); 2129 if (ret) 2130 return ret; 2131 2132 /* If in FSM mode, just vote for it */ 2133 if (val & LUCID_EVO_ENABLE_VOTE_RUN) { 2134 ret = clk_enable_regmap(hw); 2135 if (ret) 2136 return ret; 2137 return wait_for_pll_enable_lock(pll); 2138 } 2139 2140 /* Check if PLL is already enabled */ 2141 ret = trion_pll_is_enabled(pll, regmap); 2142 if (ret < 0) { 2143 return ret; 2144 } else if (ret) { 2145 pr_warn("%s PLL is already enabled\n", clk_hw_get_name(&pll->clkr.hw)); 2146 return 0; 2147 } 2148 2149 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 2150 if (ret) 2151 return ret; 2152 2153 /* Set operation mode to RUN */ 2154 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); 2155 2156 ret = wait_for_pll_enable_lock(pll); 2157 if (ret) 2158 return ret; 2159 2160 /* Enable the PLL outputs */ 2161 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK); 2162 if (ret) 2163 return ret; 2164 2165 /* Enable the global PLL outputs */ 2166 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); 2167 if (ret) 2168 return ret; 2169 2170 /* Ensure that the write above goes through before returning. */ 2171 mb(); 2172 return ret; 2173 } 2174 2175 static void _alpha_pll_lucid_evo_disable(struct clk_hw *hw, bool reset) 2176 { 2177 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2178 struct regmap *regmap = pll->clkr.regmap; 2179 u32 val; 2180 int ret; 2181 2182 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); 2183 if (ret) 2184 return; 2185 2186 /* If in FSM mode, just unvote it */ 2187 if (val & LUCID_EVO_ENABLE_VOTE_RUN) { 2188 clk_disable_regmap(hw); 2189 return; 2190 } 2191 2192 /* Disable the global PLL output */ 2193 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 2194 if (ret) 2195 return; 2196 2197 /* Disable the PLL outputs */ 2198 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); 2199 if (ret) 2200 return; 2201 2202 /* Place the PLL mode in STANDBY */ 2203 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 2204 2205 if (reset) 2206 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, 0); 2207 } 2208 2209 static int _alpha_pll_lucid_evo_prepare(struct clk_hw *hw, bool reset) 2210 { 2211 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2212 struct clk_hw *p; 2213 u32 val = 0; 2214 int ret; 2215 2216 /* Return early if calibration is not needed. */ 2217 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 2218 if (!(val & LUCID_EVO_PCAL_NOT_DONE)) 2219 return 0; 2220 2221 p = clk_hw_get_parent(hw); 2222 if (!p) 2223 return -EINVAL; 2224 2225 ret = alpha_pll_lucid_evo_enable(hw); 2226 if (ret) 2227 return ret; 2228 2229 _alpha_pll_lucid_evo_disable(hw, reset); 2230 2231 return 0; 2232 } 2233 2234 static void alpha_pll_lucid_evo_disable(struct clk_hw *hw) 2235 { 2236 _alpha_pll_lucid_evo_disable(hw, false); 2237 } 2238 2239 static int alpha_pll_lucid_evo_prepare(struct clk_hw *hw) 2240 { 2241 return _alpha_pll_lucid_evo_prepare(hw, false); 2242 } 2243 2244 static void alpha_pll_reset_lucid_evo_disable(struct clk_hw *hw) 2245 { 2246 _alpha_pll_lucid_evo_disable(hw, true); 2247 } 2248 2249 static int alpha_pll_reset_lucid_evo_prepare(struct clk_hw *hw) 2250 { 2251 return _alpha_pll_lucid_evo_prepare(hw, true); 2252 } 2253 2254 static unsigned long alpha_pll_lucid_evo_recalc_rate(struct clk_hw *hw, 2255 unsigned long parent_rate) 2256 { 2257 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2258 struct regmap *regmap = pll->clkr.regmap; 2259 u32 l, frac; 2260 2261 regmap_read(regmap, PLL_L_VAL(pll), &l); 2262 l &= LUCID_EVO_PLL_L_VAL_MASK; 2263 regmap_read(regmap, PLL_ALPHA_VAL(pll), &frac); 2264 2265 return alpha_pll_calc_rate(parent_rate, l, frac, pll_alpha_width(pll)); 2266 } 2267 2268 static int clk_lucid_evo_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 2269 unsigned long parent_rate) 2270 { 2271 return __clk_lucid_pll_postdiv_set_rate(hw, rate, parent_rate, LUCID_EVO_ENABLE_VOTE_RUN); 2272 } 2273 2274 const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops = { 2275 .enable = alpha_pll_lucid_evo_enable, 2276 .disable = alpha_pll_lucid_evo_disable, 2277 .is_enabled = clk_trion_pll_is_enabled, 2278 .recalc_rate = alpha_pll_lucid_evo_recalc_rate, 2279 .round_rate = clk_alpha_pll_round_rate, 2280 }; 2281 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_evo_ops); 2282 2283 const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops = { 2284 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate, 2285 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate, 2286 .set_rate = clk_lucid_evo_pll_postdiv_set_rate, 2287 }; 2288 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_evo_ops); 2289 2290 const struct clk_ops clk_alpha_pll_lucid_evo_ops = { 2291 .prepare = alpha_pll_lucid_evo_prepare, 2292 .enable = alpha_pll_lucid_evo_enable, 2293 .disable = alpha_pll_lucid_evo_disable, 2294 .is_enabled = clk_trion_pll_is_enabled, 2295 .recalc_rate = alpha_pll_lucid_evo_recalc_rate, 2296 .round_rate = clk_alpha_pll_round_rate, 2297 .set_rate = alpha_pll_lucid_5lpe_set_rate, 2298 }; 2299 EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_evo_ops); 2300 2301 const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops = { 2302 .prepare = alpha_pll_reset_lucid_evo_prepare, 2303 .enable = alpha_pll_lucid_evo_enable, 2304 .disable = alpha_pll_reset_lucid_evo_disable, 2305 .is_enabled = clk_trion_pll_is_enabled, 2306 .recalc_rate = alpha_pll_lucid_evo_recalc_rate, 2307 .round_rate = clk_alpha_pll_round_rate, 2308 .set_rate = alpha_pll_lucid_5lpe_set_rate, 2309 }; 2310 EXPORT_SYMBOL_GPL(clk_alpha_pll_reset_lucid_evo_ops); 2311 2312 void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 2313 const struct alpha_pll_config *config) 2314 { 2315 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 2316 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); 2317 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); 2318 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 2319 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 2320 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 2321 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); 2322 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); 2323 2324 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 2325 2326 regmap_update_bits(regmap, PLL_MODE(pll), 2327 PLL_RESET_N | PLL_BYPASSNL | PLL_OUTCTRL, 2328 PLL_RESET_N | PLL_BYPASSNL); 2329 } 2330 EXPORT_SYMBOL_GPL(clk_rivian_evo_pll_configure); 2331 2332 static unsigned long clk_rivian_evo_pll_recalc_rate(struct clk_hw *hw, 2333 unsigned long parent_rate) 2334 { 2335 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2336 u32 l; 2337 2338 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); 2339 2340 return parent_rate * l; 2341 } 2342 2343 static long clk_rivian_evo_pll_round_rate(struct clk_hw *hw, unsigned long rate, 2344 unsigned long *prate) 2345 { 2346 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2347 unsigned long min_freq, max_freq; 2348 u32 l; 2349 u64 a; 2350 2351 rate = alpha_pll_round_rate(rate, *prate, &l, &a, 0); 2352 if (!pll->vco_table || alpha_pll_find_vco(pll, rate)) 2353 return rate; 2354 2355 min_freq = pll->vco_table[0].min_freq; 2356 max_freq = pll->vco_table[pll->num_vco - 1].max_freq; 2357 2358 return clamp(rate, min_freq, max_freq); 2359 } 2360 2361 const struct clk_ops clk_alpha_pll_rivian_evo_ops = { 2362 .enable = alpha_pll_lucid_5lpe_enable, 2363 .disable = alpha_pll_lucid_5lpe_disable, 2364 .is_enabled = clk_trion_pll_is_enabled, 2365 .recalc_rate = clk_rivian_evo_pll_recalc_rate, 2366 .round_rate = clk_rivian_evo_pll_round_rate, 2367 }; 2368 EXPORT_SYMBOL_GPL(clk_alpha_pll_rivian_evo_ops); 2369 2370 void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 2371 const struct alpha_pll_config *config) 2372 { 2373 u32 val, val_u, mask, mask_u; 2374 2375 regmap_write(regmap, PLL_L_VAL(pll), config->l); 2376 regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha); 2377 regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 2378 2379 if (pll_has_64bit_config(pll)) 2380 regmap_write(regmap, PLL_CONFIG_CTL_U(pll), 2381 config->config_ctl_hi_val); 2382 2383 if (pll_alpha_width(pll) > 32) 2384 regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi); 2385 2386 val = config->main_output_mask; 2387 val |= config->aux_output_mask; 2388 val |= config->aux2_output_mask; 2389 val |= config->early_output_mask; 2390 val |= config->pre_div_val; 2391 val |= config->post_div_val; 2392 val |= config->vco_val; 2393 val |= config->alpha_en_mask; 2394 val |= config->alpha_mode_mask; 2395 2396 mask = config->main_output_mask; 2397 mask |= config->aux_output_mask; 2398 mask |= config->aux2_output_mask; 2399 mask |= config->early_output_mask; 2400 mask |= config->pre_div_mask; 2401 mask |= config->post_div_mask; 2402 mask |= config->vco_mask; 2403 mask |= config->alpha_en_mask; 2404 mask |= config->alpha_mode_mask; 2405 2406 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); 2407 2408 /* Stromer APSS PLL does not enable LOCK_DET by default, so enable it */ 2409 val_u = config->status_val << ALPHA_PLL_STATUS_REG_SHIFT; 2410 val_u |= config->lock_det; 2411 2412 mask_u = config->status_mask; 2413 mask_u |= config->lock_det; 2414 2415 regmap_update_bits(regmap, PLL_USER_CTL_U(pll), mask_u, val_u); 2416 regmap_write(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 2417 regmap_write(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 2418 2419 if (pll->flags & SUPPORTS_FSM_MODE) 2420 qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0); 2421 } 2422 EXPORT_SYMBOL_GPL(clk_stromer_pll_configure); 2423 2424 static int clk_alpha_pll_stromer_determine_rate(struct clk_hw *hw, 2425 struct clk_rate_request *req) 2426 { 2427 u32 l; 2428 u64 a; 2429 2430 req->rate = alpha_pll_round_rate(req->rate, req->best_parent_rate, 2431 &l, &a, ALPHA_REG_BITWIDTH); 2432 2433 return 0; 2434 } 2435 2436 static int clk_alpha_pll_stromer_set_rate(struct clk_hw *hw, unsigned long rate, 2437 unsigned long prate) 2438 { 2439 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2440 int ret; 2441 u32 l; 2442 u64 a; 2443 2444 rate = alpha_pll_round_rate(rate, prate, &l, &a, ALPHA_REG_BITWIDTH); 2445 2446 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 2447 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 2448 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), 2449 a >> ALPHA_BITWIDTH); 2450 2451 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 2452 PLL_ALPHA_EN, PLL_ALPHA_EN); 2453 2454 if (!clk_hw_is_enabled(hw)) 2455 return 0; 2456 2457 /* 2458 * Stromer PLL supports Dynamic programming. 2459 * It allows the PLL frequency to be changed on-the-fly without first 2460 * execution of a shutdown procedure followed by a bring up procedure. 2461 */ 2462 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 2463 PLL_UPDATE); 2464 2465 ret = wait_for_pll_update(pll); 2466 if (ret) 2467 return ret; 2468 2469 return wait_for_pll_enable_lock(pll); 2470 } 2471 2472 const struct clk_ops clk_alpha_pll_stromer_ops = { 2473 .enable = clk_alpha_pll_enable, 2474 .disable = clk_alpha_pll_disable, 2475 .is_enabled = clk_alpha_pll_is_enabled, 2476 .recalc_rate = clk_alpha_pll_recalc_rate, 2477 .determine_rate = clk_alpha_pll_stromer_determine_rate, 2478 .set_rate = clk_alpha_pll_stromer_set_rate, 2479 }; 2480 EXPORT_SYMBOL_GPL(clk_alpha_pll_stromer_ops); 2481 2482 static int clk_alpha_pll_stromer_plus_set_rate(struct clk_hw *hw, 2483 unsigned long rate, 2484 unsigned long prate) 2485 { 2486 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2487 u32 l, alpha_width = pll_alpha_width(pll); 2488 int ret, pll_mode; 2489 u64 a; 2490 2491 rate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 2492 2493 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &pll_mode); 2494 if (ret) 2495 return ret; 2496 2497 regmap_write(pll->clkr.regmap, PLL_MODE(pll), 0); 2498 2499 /* Delay of 2 output clock ticks required until output is disabled */ 2500 udelay(1); 2501 2502 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 2503 2504 if (alpha_width > ALPHA_BITWIDTH) 2505 a <<= alpha_width - ALPHA_BITWIDTH; 2506 2507 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 2508 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), 2509 a >> ALPHA_BITWIDTH); 2510 2511 regmap_write(pll->clkr.regmap, PLL_MODE(pll), PLL_BYPASSNL); 2512 2513 /* Wait five micro seconds or more */ 2514 udelay(5); 2515 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N, 2516 PLL_RESET_N); 2517 2518 /* The lock time should be less than 50 micro seconds worst case */ 2519 usleep_range(50, 60); 2520 2521 ret = wait_for_pll_enable_lock(pll); 2522 if (ret) { 2523 pr_err("Wait for PLL enable lock failed [%s] %d\n", 2524 clk_hw_get_name(hw), ret); 2525 return ret; 2526 } 2527 2528 if (pll_mode & PLL_OUTCTRL) 2529 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, 2530 PLL_OUTCTRL); 2531 2532 return 0; 2533 } 2534 2535 const struct clk_ops clk_alpha_pll_stromer_plus_ops = { 2536 .prepare = clk_alpha_pll_enable, 2537 .unprepare = clk_alpha_pll_disable, 2538 .is_enabled = clk_alpha_pll_is_enabled, 2539 .recalc_rate = clk_alpha_pll_recalc_rate, 2540 .determine_rate = clk_alpha_pll_stromer_determine_rate, 2541 .set_rate = clk_alpha_pll_stromer_plus_set_rate, 2542 }; 2543 EXPORT_SYMBOL_GPL(clk_alpha_pll_stromer_plus_ops); 2544